Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel has a display area and a first frame area arranged on one side of the display area. The display panel comprises a first conductive layer, a cathode layer and a second conductive layer. The first conductive layer comprises fan-out wires located in the first frame area. The cathode layer is arranged on the first conductive layer. The second conductive layer is arranged on the cathode layer. The second conductive layer comprises touch control lead wires located in the first frame area. In the thickness direction of the display panel, the touch control lead wires partially overlap the fan-out wires. A shielding electrode is arranged in the first frame area and is different from the cathode layer. The shielding electrode is arranged between the fan-out wires and the touch control lead wires. The part of the touch control lead wires that overlaps the fan-out wires at least partially overlaps the shielding electrode. In this way, the shielding electrode can shield the interference of the signals transmitted by the fan-out wires on the signals transmitted by the touch control lead wires, thereby improving the touch control accuracy.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diode (OLED) display panels have advantages such as active light emission, wide viewing angle, wide color gamut, high brightness, fast response speed, low power consumption, and flexible structure, making them increasingly popular in the market.

[0003] At the bottom bezel of the display panel, there is an overlap between the upper-layer touch traces and the lower-layer display signal traces. Since both display and touch signals are driven simultaneously, the display signal traces below the touch traces cause significant interference to the touch signal. Currently, a cathode layer, covering the entire surface, is typically extended to the area between the touch traces and display signal traces at the bottom bezel to shield the touch signal from display signal interference. However, due to fluctuations in the manufacturing precision of the cathode layer, some areas of the display signal cannot be shielded by the cathode layer, causing the touch signal to still be affected by the display signal, thus impacting touch accuracy.

[0004] Therefore, it is necessary to provide a display panel and display device to improve this deficiency. Summary of the Invention

[0005] This application provides a display panel and display device that can improve touch accuracy.

[0006] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, having a display area and a first border area disposed on one side of the display area, the display panel comprising: The first conductive layer includes fan-out traces located in the first border area; A cathode layer is disposed on the first conductive layer; and A second conductive layer is disposed on the cathode layer and includes a touch lead located in the first bezel area. In the thickness direction of the display panel, the touch lead overlaps with the fan-out trace portion. The display panel further includes a shielding electrode located in the first frame area. The shielding electrode is disposed in a different layer from the cathode layer. In the thickness direction of the display panel, the shielding electrode is located between the fan-out trace and the touch lead. The overlapping portion of the touch lead and the fan-out trace at least partially overlaps with the shielding electrode.

[0007] Optionally, the display panel further includes: A third conductive layer is disposed between the first conductive layer and the shielding electrode, and includes at least two DC voltage lines. A portion of the fan-out trace is located between the orthographic projections of two adjacent DC voltage lines onto a reference plane, which is parallel to the light-emitting surface of the display panel. The orthographic projection of the shielding electrode on the reference plane covers the orthographic projection of the portion of the fan-out trace located between two adjacent DC voltage lines on the reference plane.

[0008] Optionally, at least two of the DC voltage lines are arranged at intervals along the direction from the display area toward the first frame area; The orthographic projection of the shielding electrode on the reference plane covers the orthographic projection of at least one of the DC voltage lines on the reference plane, and also covers the gap between the orthographic projections of two adjacent DC voltage lines on the reference plane.

[0009] Optionally, the orthographic projection of the shielding electrode on the reference plane is spaced apart from the orthographic projection of the DC voltage line closest to the display area on the reference plane; Alternatively, the orthogonal projection of the shielding electrode onto the reference plane overlaps with the orthogonal projection of the DC voltage line closest to the display area onto the reference plane.

[0010] Optionally, the shielding electrode has a first opening, the first opening being an orthographic projection on the reference plane, and the DC voltage line being an orthographic projection on the reference plane.

[0011] Optionally, at least two of the DC voltage lines include power lines, the orthographic projection of the power lines on the reference plane overlapping the orthographic projection of the shielding electrode on the reference plane; The power cord has a second opening, and the orthographic projection of the second opening on the reference plane is located within the orthographic projection of the shielding electrode on the reference plane.

[0012] Optionally, the orthographic projection of the first opening on the reference plane and the orthographic projection of the second opening on the reference plane are spaced apart from each other.

[0013] Optionally, the cathode layer is disposed in the display area and the first border area; The orthographic projection of the shielding electrode onto the reference plane partially overlaps with the orthographic projection of the cathode layer onto the reference plane, and the reference plane is parallel to the light-emitting surface of the display panel.

[0014] Optionally, the display panel includes: A third conductive layer is disposed between the first conductive layer and the cathode layer; and An anode layer is disposed between the third conductive layer and the cathode layer; The shielding electrode is disposed in the same layer as the anode layer and is made of the same material; or, the shielding electrode is disposed between the third conductive layer and the anode layer.

[0015] According to a second aspect of this application, a display device is provided, including a display panel as described above.

[0016] In the display panel of this application embodiment, by providing a shielding electrode in the first frame area that is disposed in a different layer from the cathode layer, and by placing the shielding electrode between the fan-out trace and the touch lead, the overlapping portion of the touch lead and the fan-out trace overlaps at least partially with the shielding electrode. In this way, the shielding electrode can be used to shield the interference of the signal transmitted by the fan-out trace on the signal transmitted by the touch lead, thereby improving the touch accuracy.

[0017] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0019] Figure 1 A top view of a display panel provided for an embodiment of this application; Figure 2 A top view of the first border area of ​​a display panel provided for an embodiment of this application; Figure 3 A cross-sectional view of the display panel provided in an embodiment of this application along the A-A' direction; Figure 4 A schematic diagram of the film layer structure of a display panel provided for an embodiment of this application; Figure 5 A schematic diagram of the pixel driving circuit of a display panel provided for an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0021] An embodiment of this application provides a display panel having a display area and a first border area disposed on one side of the display area. The display panel includes a first conductive layer, a cathode layer, and a second conductive layer. The first conductive layer includes fan-out traces located in the first border area. The cathode layer is disposed on the first conductive layer, and the second conductive layer is disposed on the cathode layer. The second conductive layer includes touch leads located in the first border area. In the thickness direction of the display panel, the touch leads and the fan-out traces partially overlap. The display panel also includes a shielding electrode located in the first border area. The shielding electrode is disposed in a different layer from the cathode layer. In the thickness direction of the display panel, the shielding electrode is located between the fan-out traces and the touch leads. The overlapping portion of the touch leads and the fan-out traces at least partially overlaps with the shielding electrode.

[0022] In the embodiments of this application, by setting a shielding electrode in the first frame area that is disposed in a different layer from the cathode layer, and placing the shielding electrode between the fan-out trace and the touch lead, the overlapping part of the touch lead and the fan-out trace overlaps with the shielding electrode at least partially. In this way, the shielding electrode can be used to shield the interference of the signal transmitted by the fan-out trace on the signal transmitted by the touch lead, thereby improving the touch accuracy.

[0023] like Figure 1 As shown, Figure 1 This is a top view of a display panel provided in an embodiment of this application. The display panel 100 has a display area AA and a first border area NA1 disposed on one side of the display area AA. The display area AA is an area for displaying an image, and the display panel may include multiple light-emitting devices located within the display area AA and pixel driving circuits for driving the light-emitting devices. The first border area NA1 is an area for placing fan-out traces and bonding driver chips, printed circuit boards, or flexible circuit boards.

[0024] In some embodiments, such as Figure 1As shown, the display panel 100 has a display area AA and a bezel area NA. The bezel area NA surrounds the display area AA and includes multiple bezel areas. For example, the bezel area NA includes a first bezel area NA1 and a second bezel area NA2 located on both sides of the display area AA in the second direction Y, and a third bezel area NA3 and a fourth bezel area NA4 located on both sides of the display area AA in the first direction X. The first bezel area NA1 is the lower bezel area of ​​the display panel, the second bezel area NA1 is the upper bezel area, and the third bezel area NA3 and the fourth bezel area NA4 are the left bezel area and the right bezel area, respectively. The display panel includes a gate driving circuit located in at least one of the third bezel area NA3 and the fourth bezel area NA4.

[0025] In some embodiments, such as Figures 1 to 3 As shown, Figure 2 A top view of the first border area of ​​a display panel provided for an embodiment of this application. Figure 3 The cross-sectional view of the display panel provided in the embodiment of this application along the A-A' direction shows that the display panel 100 includes a first conductive layer 1, a cathode layer 704, and a second conductive layer 2. The first conductive layer 1 includes a fan-out trace 11 located in the first border area NA1. The cathode layer 704 is disposed on the first conductive layer 1, and the second conductive layer 2 is disposed on the cathode layer 704. The second conductive layer 2 includes a touch lead 21 located in the first border area NA1. In the thickness direction of the display panel, the touch lead 21 and the fan-out trace 11 partially overlap.

[0026] In some embodiments, such as Figure 2 As shown, the first conductive layer 1 includes multiple fan-out traces 11, which extend in a direction different from the first direction X. For example, the fan-out traces 11 can extend in the second direction Y, or they can extend in a direction that is in the same plane as the first direction X and the second direction Y and forms an angle with the first direction X and the second direction Y. The second conductive layer 2 includes multiple touch leads 21, which extend in the first direction X and are spaced apart in the second direction Y.

[0027] In some embodiments, such as Figure 1 and Figure 2 As shown, the first frame area NA1 includes a fan-out sub-area NA11, where both the fan-out trace 11 and the touch lead 21 are located. In the thickness direction of the display panel, the touch lead 21 partially overlaps with the fan-out trace 11. One touch lead 21 can overlap with multiple fan-out traces 11, and one fan-out trace 11 can also overlap with multiple touch leads 21.

[0028] In some embodiments, the first bezel area NA1 may further include a bonding sub-area (not shown in the figure). The bonding sub-area is located on the side of the fan-out sub-area away from the display area. The bonding sub-area has multiple terminals, and the driver chip and circuit board can be bonded to the display panel through the terminals. The fan-out trace 11 is connected between the display signal lines of the display area and the terminals of the bonding sub-area for transmitting display-related signals. For example, the fan-out trace 11 may include, but is not limited to, source signal lines, gate signal lines, clock signal lines, etc.

[0029] In some embodiments, the second conductive layer 2 may include a plurality of touch electrodes and touch signal lines located in the display area. The touch electrodes are electrically connected between the touch electrodes and the touch leads, and the touch leads are electrically connected between the touch signal lines and the driver chip for transmitting touch signals.

[0030] In some embodiments, such as Figure 2 and Figure 3 As shown, the display panel also includes a shielding electrode 3, which is located in the first frame area NA1. Specifically, the shielding electrode 3 is at least partially located in the fan-out sub-area NA11. For example, the shielding electrode 3 may be disposed only in the fan-out sub-area NA11, or it may be disposed in other areas of the first frame area NA1 other than the fan-out sub-area NA11.

[0031] like Figure 2 and Figure 3 As shown, the shielding electrode 3 and the cathode layer 704 are disposed in different layers. In the thickness direction of the display panel, the shielding electrode 3 is located between the fan-out trace 11 and the touch lead 21. The overlapping part of the touch lead 21 and the fan-out trace 11 overlaps with the shielding electrode 3 at least partially.

[0032] In some embodiments, the fan-out trace 11 is connected to an alternating voltage signal, the touch lead 21 is connected to an alternating voltage signal, and the shielding electrode 3 is connected to a DC voltage signal. The constant electric field formed by the DC voltage signal of the shielding electrode 3 is used to shield the signal transmitted by the fan-out trace from interfering with the signal transmitted by the touch lead, thereby reducing the interference of touch signals and improving the touch accuracy of the display panel.

[0033] In some embodiments, the overlapping portion of the touch lead 21 and the fan-out trace 11 may partially overlap with the shielding electrode 3, or it may completely overlap with the shielding electrode 3.

[0034] In some embodiments, a portion of the overlap between the touch lead 21 and the fan-out trace 11 at least partially overlaps with the cathode layer 704, a portion of the overlap between the touch lead 21 and the fan-out trace 11 at least partially overlaps with the shielding electrode 3, and a portion of the overlap between the shielding electrode 3 and the touch lead 21 and the fan-out trace 11 does not overlap with the cathode layer 704. In this way, the interference of the signal transmitted by the touch lead can be achieved by using the shared shielding of the cathode layer 704 and the shielding electrode 3 on the signal transmitted by the fan-out trace.

[0035] In some embodiments, a portion of the overlap between the touch lead 21 and the fan-out trace 11 at least partially overlaps with the cathode layer 704, a portion of the overlap between the touch lead 21 and the fan-out trace 11 at least partially overlaps with the shielding electrode 3, and a portion of the overlap between the shielding electrode 3 and the touch lead 21 and the fan-out trace 11 at least partially overlaps with the cathode layer 704. In this way, the cathode layer 704 and the shielding electrode 3 can share the shielding to prevent interference from the signal transmitted by the fan-out trace to the signal transmitted by the touch lead, and can avoid the situation where the process accuracy fluctuation of the cathode layer 704 cannot effectively shield the interference of the fan-out trace to the touch signal.

[0036] In some embodiments, such as Figure 4 As shown, Figure 4 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. The display panel includes a substrate 10, a driving circuit layer 6 disposed on the substrate 10, a light-emitting device layer 7 disposed on the driving circuit layer 6, an encapsulation layer 8 disposed on the light-emitting device layer 7, and a touch layer 9 disposed on the encapsulation layer 8. The driving circuit layer 6 includes an active layer 601, a first gate insulating layer 602, a first gate layer 603, a second gate insulating layer 604, a second gate layer 605, an interlayer dielectric layer 606, a first source-drain layer 607, a first planarization layer 608, a second source-drain layer 609, and a second planarization layer 610, which are sequentially stacked on the substrate 10. The light-emitting device layer 7 includes an anode layer 701, a pixel definition layer 702, a light-emitting layer 703, and a cathode layer 704, which are sequentially stacked on the driving circuit layer 6. The encapsulation layer 8 is a thin-film encapsulation structure, including a first inorganic encapsulation layer 801, an organic encapsulation layer 802, and a second inorganic encapsulation layer 803, which are sequentially stacked on the light-emitting device layer 7. The touch layer 9 includes a first touch conductive layer 901, a first touch insulating layer 902, a second touch conductive layer 903, and a second touch insulating layer 904, which are stacked sequentially on the encapsulation layer 8.

[0037] It should be noted that, Figure 4 This illustration only shows one type of display panel's film layer structure and does not represent the film layer structure of display panels in actual applications. In practical applications, the display panel can be replaced with the film layer structure of an existing display panel to achieve the same or similar functions.

[0038] In some embodiments, such as Figure 3and Figure 4 As shown, the display panel includes at least one first conductive layer 1, which is disposed in the driving circuit layer 6, i.e., the driving circuit layer 6 includes at least one first conductive layer 1. For example, the driving circuit layer 6 includes one first conductive layer 1, which can be a first gate layer 603 or a second gate layer 605 in the driving circuit layer 6, and fan-out traces are provided in the first gate layer 603 or the second gate layer 605; or, the driving circuit layer 6 includes two first conductive layers 1, one of which is a first gate layer 603 and the other is a second gate layer 605, and fan-out traces are provided in both the first gate layer 603 and the second gate layer 605. The orthogonal projections of the fan-out traces in the first gate layer 603 and the fan-out traces in the second gate layer 605 on the substrate are arranged at intervals, which can reduce signal crosstalk between the fan-out traces in the first gate layer 603 and the fan-out traces in the second gate layer 605.

[0039] In some embodiments, such as Figure 3 and Figure 4 As shown, the display panel includes at least one second conductive layer 2, which is disposed in the touch layer 9, i.e., the touch layer 9 includes at least one second conductive layer 2. For example, the touch layer 9 includes one second conductive layer 2, which is either a first touch conductive layer 901 or a second touch conductive layer 903, and touch leads 21 are provided in either the first touch conductive layer 901 or the second touch conductive layer 903; or, the touch layer 9 includes two second conductive layers 2, wherein one second conductive layer 2 is a first touch conductive layer 901, and the other second conductive layer 2 is a second touch conductive layer 903, and touch leads 21 are provided in both the first touch conductive layer 901 and the second touch conductive layer 903.

[0040] In some embodiments, such as Figure 2 and Figure 3 As shown, the display panel also includes a third conductive layer 4, which is disposed between the first conductive layer 1 and the shielding electrode 3. The third conductive layer 4 includes at least two DC voltage lines 40 located in the first frame area NA1. A portion of the fan-out trace 11 is located between the orthographic projections of two adjacent DC voltage lines 40 on a reference plane. The reference plane is parallel to the light-emitting surface of the display panel. The orthographic projection of a portion of the fan-out trace 11 on the reference plane overlaps with the orthographic projections of the DC voltage lines 40 and the touch lead 21 on the reference plane. The DC voltage lines 40 are connected to DC voltage signals, and the constant electric field formed by the DC voltage signals of the DC voltage lines 40 shields the interference of the signals transmitted by the fan-out traces on the signals transmitted by the touch leads.

[0041] In some embodiments, such as Figure 2 and Figure 3As shown, the orthographic projection of the touch lead 21 on the reference plane is at least partially located between the orthographic projections of the two adjacent DC voltage lines 40 on the reference plane. The orthographic projection of the shielding electrode 3 on the reference plane covers the orthographic projection of the fan-out trace 11 located between the two adjacent DC voltage lines 40 on the reference plane. In this way, the shielding electrode 3 can be used to shield the interference of the alternating voltage signal transmitted by the fan-out trace 11 exposed in the gap between the two adjacent DC voltage lines 40 on the touch signal of the touch lead 21 above the gap between the two adjacent DC voltage lines 40.

[0042] In some embodiments, such as Figure 5 As shown, Figure 5 This is a schematic diagram of a pixel driving circuit for a display panel provided in an embodiment of this application. The display panel includes multiple pixel driving circuits and multiple light-emitting devices located in the display area. The pixel driving circuit includes a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, a third reset transistor T8, and a storage capacitor Cst. The display panel includes multiple DC voltage lines 40, including a first reset signal line Vi1, a second reset signal line Vi2, a third reset signal line Vi3, and multiple power lines 41, including a first power line VDD and a second power line VSS.

[0043] The first electrode of driving transistor T1 is electrically connected to the first node A, the second electrode of driving transistor T1 is electrically connected to the second node B, and the gate of driving transistor T1 is electrically connected to the third node Q; the first electrode of switching transistor T2 is electrically connected to the data line Data, the second electrode of switching transistor T2 is electrically connected to the first node A, and the gate of switching transistor T2 is electrically connected to the first scan line Scan1; the first electrode of compensation transistor T3 is electrically connected to the third node Q, the second electrode of compensation transistor T3 is electrically connected to the second node B, and the gate of compensation transistor T3 is electrically connected to the first scan line Scan1; the first electrode of the first reset transistor T4 is electrically connected to the first reset signal line Vi1, the second electrode of the first reset transistor T4 is electrically connected to the third node Q, and the gate of the first reset transistor T4 is electrically connected to the second scan line Scan2; the first electrode of the first light-emitting control transistor T5 is electrically connected to the first power supply line VDD, the second electrode of the first light-emitting control transistor T5 is electrically connected to the first node A, the second… The first electrode of the light-emitting control transistor T6 is electrically connected to the second node B, and the second electrode of the second light-emitting control transistor T6 is electrically connected to the fourth node C. The gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are electrically connected to the light-emitting control signal line EM. The first electrode of the second reset transistor T7 is electrically connected to the second reset signal line Vi2, the second electrode of the second reset transistor T7 is electrically connected to the fourth node C, and the gate of the second reset transistor T7 is electrically connected to the third scan line Scan3. The first electrode of the third reset transistor T8 is electrically connected to the third reset signal line Vi3, the second electrode of the third reset transistor T8 is electrically connected to the first node A, and the gate of the third reset transistor T8 is electrically connected to the third scan line Scan3. The upper storage plate of the storage capacitor Cst is electrically connected to the first power supply line VDD, and the lower storage plate of the storage capacitor Cst is electrically connected to the third node Q. The anode of the light-emitting device E is electrically connected to the fourth node C, and the cathode of the light-emitting device E is electrically connected to the second power supply line VSS.

[0044] In this embodiment, the first reset signal line Vi1, the second reset signal line Vi2, the third reset signal line Vi3, the first power line VDD, and the second power line VSS are all simultaneously located in the display area and the non-display area. Taking the first reset signal line Vi1 as an example, the portion of the first reset signal line Vi1 located in the display area extends along the second direction Y, and the portion of the first reset signal line Vi1 located in the fan-out sub-area NA11 extends along the first direction X. The other signal lines are similarly arranged and will not be described in detail here.

[0045] In some embodiments, at least one of the first source-drain layer 607 and the second source-drain layer 609 is provided with a DC voltage line 40. For example, portions of the first reset signal line Vi1, the second reset signal line Vi2, the third reset signal line Vi3, the first power line VDD, and the second power line VSS located in the fan-out sub-region NA11 are disposed on the same layer of the first source-drain layer 607 or the second source-drain layer 609; or, portions of at least one of the first reset signal line Vi1, the second reset signal line Vi2, the third reset signal line Vi3, the first power line VDD, and the second power line VSS located in the fan-out sub-region NA11 are disposed on the first source-drain layer 607, and portions of at least another power line located in the fan-out sub-region NA11 are disposed on the second source-drain layer 609.

[0046] In some embodiments, such as Figure 2 As shown, portions of the first reset signal line Vi1, the second reset signal line Vi2, the third reset signal line Vi3, the first power line VDD, and the second power line (not shown) located in the fan-out sub-region NA11 are arranged sequentially at intervals in the fan-out sub-region NA11 in a direction opposite to the second direction Y. The portions of the first reset signal line Vi1, the second reset signal line Vi2, the third reset signal line Vi3, the first power line VDD, and the second power line VSS located in the fan-out sub-region NA11 are disposed in the same layer on the second source-drain layer 609. The first reset signal line Vi1, the second reset signal line Vi2, the third reset signal line Vi3, the first power line VDD, and the second power line VSS extend in the first direction X. The fan-out trace 11 extends in a direction opposite to the first direction X and overlaps with the aforementioned reset signal lines in the thickness direction. A portion of the fan-out trace 11 is disposed between two adjacent reset signal lines.

[0047] Taking the first reset signal line Vi1 and the second reset signal line Vi2 as examples, the orthographic projection of the shielding electrode 3 on the reference plane covers the orthographic projection of the portion of the fan-out trace 11 located between adjacent first reset signal lines Vi1 and Vi2 on the reference plane. In this way, the shielding electrode 3 can be used to shield the alternating voltage signal transmitted by the portion of the fan-out trace 11 exposed in the gap between the first reset signal lines Vi1 and Vi2 from interference with the touch signal of the touch lead 21 above the gap between the first reset signal lines Vi1 and Vi2. Similarly, the shielding electrode 3 can also cover the fan-out trace 11 exposed in the gaps between adjacent second reset signal lines Vi2 and third reset signal lines Vi3, between third reset signal lines Vi3 and the first power line VDD, and between the first power line VDD and the second power line VSS.

[0048] In some embodiments, such as Figure 2As shown, at least two DC voltage lines 40 are arranged at intervals along the direction from the display area AA to the first frame area NA1. The orthographic projection of the shielding electrode 3 on the reference plane covers the orthographic projection of at least one DC voltage line 40 on the reference plane, and also covers the gap between the orthographic projections of two adjacent DC voltage lines 40 on the reference plane.

[0049] In some embodiments, the orthogonal projection of the shielding electrode 3 on the reference plane may only cover the orthogonal projection of the second reset signal line Vi2 on the reference plane, and cover the gap between the orthogonal projections of the second reset signal line Vi2 and the adjacent first reset signal line Vi1 or third reset signal line Vi3 on the reference plane; or, the orthogonal projection of the shielding electrode 3 on the reference plane may only cover the orthogonal projection of the third reset signal line Vi3 on the reference plane, and cover the gap between the third reset signal line Vi3 and the adjacent second reset signal line Vi2 or the first power line VDD on the reference plane; or, the orthogonal projection of the shielding electrode 3 on the reference plane may only cover the orthogonal projection of the first power line VDD on the reference plane, and cover the gap between the first power line VDD and the adjacent third reset signal line Vi3 or the second power line VSS on the reference plane.

[0050] In some embodiments, the orthographic projection of the shielding electrode 3 on the reference plane can cover the orthographic projections of at least two of the first reset signal line Vi1, the second reset signal line Vi2, the third reset signal line Vi3, the first power line VDD, and the second power line on the reference plane, as well as the gap between the orthographic projections.

[0051] In some embodiments, the orthographic projection of the shielding electrode 3 on the reference plane can simultaneously cover the orthographic projections of the first reset signal line Vi1, the second reset signal line Vi2, the third reset signal line Vi3, the first power line VDD, and the second power line on the reference plane, as well as the gap between the orthographic projections.

[0052] In some embodiments, the orthographic projection of the shielding electrode 3 onto the reference plane is spaced apart from the orthographic projection of the DC voltage line 40 closest to the display area AA onto the reference plane.

[0053] like Figure 2 As shown, the orthographic projection of the shielding electrode 3 on the reference plane covers the orthographic projections of the second reset signal line Vi2, the third reset signal line Vi3, the first power line VDD, and the second power line on the reference plane, as well as the gap between the orthographic projections, and also covers the first reset signal line Vi1 and the second reset signal line Vi2. Among the multiple DC voltage lines 40, the first reset signal line Vi1 is closest to the display area AA, and the orthographic projection of the shielding electrode 3 on the reference plane and the orthographic projection of the first reset signal line Vi1 on the reference plane are spaced apart from each other.

[0054] It should be noted that, since the first reset signal line Vi1 is relatively close to the display area, and the shielding electrode 3 is made of a conductive metallic material, if the shielding electrode 3 is too close to the display area AA, it will reflect the light emitted by the light-emitting devices at the edge of the display area, affecting the display effect of the display panel. This embodiment prevents reflections caused by the shielding electrode 3 being too close to the display area by spacing the orthographic projection of the shielding electrode 3 on the reference plane from the orthographic projection of the first reset signal line Vi1, which is closest to the display area AA, thus ensuring the display effect of the display area.

[0055] In some embodiments, the edge of the orthographic projection of the shielding electrode 3 on the reference plane can be aligned with the edge of the orthographic projection of the first reset signal line Vi1 on the reference plane, but they do not overlap. This also prevents the shielding electrode 3 from being too close to the display area and causing reflection, thus ensuring the display effect of the display area.

[0056] It should be noted that, Figure 2 This illustration only shows one arrangement of the first reset signal line Vi1, the second reset signal line Vi2, the third reset signal line Vi3, the first power line VDD, and the second power line VSS, and does not represent the actual number and arrangement of DC voltage lines in practical applications. In practical applications, the number and arrangement of DC voltage lines can be adjusted according to requirements, only ensuring that the orthographic projection of the shielding electrode 3 on the reference plane does not overlap with the orthographic projection of the DC voltage line 40 closest to the display area AA on the reference plane.

[0057] In some embodiments, the orthographic projection of the shielding electrode 3 onto the reference plane overlaps with the orthographic projection of the DC voltage line 40 closest to the display area AA onto the reference plane. For example, the orthographic projection of the shielding electrode 3 onto the reference plane overlaps with the orthographic projection of the portion of the first reset signal line Vi1 away from the display area AA onto the reference plane. This also prevents the shielding electrode 3 from being too close to the display area, thus preventing reflections and ensuring the display effect of the display area.

[0058] In some embodiments, the shielding electrode 3 is provided with a first opening 31, and the orthographic projection of the first opening 31 on the reference plane is located within the orthographic projection of the DC voltage line 40 on the reference plane.

[0059] like Figure 2As shown, the shielding electrode 3 has multiple first openings 31. The orthographic projection of each first opening 31 onto the reference plane is rectangular. The multiple first openings 31 are arranged at intervals along the first direction X and the second direction Y. The orthographic projections of the multiple first openings 31 onto the reference plane are located within the orthographic projection of the second reset signal line Vi2 onto the reference plane, the orthographic projections of the multiple first openings 31 onto the reference plane are located within the orthographic projection of the third reset signal line Vi3 onto the reference plane, and the orthographic projections of the multiple first openings 31 onto the reference plane are located within the orthographic projection of the first power line VDD onto the reference plane.

[0060] In this embodiment, by providing multiple first openings 31 on the shielding electrode 3, moisture in the organic film layers such as the first and second planarization layers can be discharged. This not only prevents moisture from corroding the luminescent material but also avoids bulging and film peeling caused by the inability to release moisture. Furthermore, by positioning the orthographic projection of the first opening 31 onto the reference plane within the orthographic projection of the DC voltage line 40 onto the reference plane, the fan-out traces in the area where the first opening 31 is located can be shielded by the DC voltage line 40. This prevents the fan-out traces below the first opening 31 from being exposed, ensuring that the shielding electrode 3 and the DC voltage line 40 can shield the signal transmitted by the fan-out traces from interfering with the signal transmitted by the touch lead.

[0061] In some embodiments, the orthographic projection of the power line 41 on the reference plane overlaps with the orthographic projection of the shielding electrode 3 on the reference plane. The power line 41 has a second opening 411, and the orthographic projection of the second opening 411 on the reference plane is located within the orthographic projection of the shielding electrode 3 on the reference plane. This allows moisture to escape from the organic film layers such as the first and second planarization layers, preventing corrosion of the luminescent material by moisture and avoiding bulging and film peeling due to moisture retention. Furthermore, this embodiment ensures that the orthographic projection of the second opening 411 on the reference plane is located within the orthographic projection of the shielding electrode 3 on the reference plane. The fan-out traces in the area where the second opening 411 is located can be shielded by the shielding electrode 3. This prevents the second opening 411 from exposing the fan-out traces below, ensuring that the shielding electrode 3 and the DC voltage line 40 can shield the signal transmitted by the fan-out traces from interfering with the signal transmitted by the touch lead.

[0062] In some embodiments, such as Figure 2 As shown, the first power line VDD is provided with a plurality of second openings 411. The second openings 411 penetrate the first power line VDD in the thickness direction. The orthographic projection of the second openings 411 on the reference plane is located within the orthographic projection of the shielding electrode 3 on the reference plane.

[0063] In some embodiments, the second power line VSS is provided with a plurality of second openings 411, the second openings 411 extending through the second power line VSS in the thickness direction, and the orthographic projection of the second openings 411 on the reference plane is located within the orthographic projection of the shielding electrode 3 on the reference plane.

[0064] In some embodiments, the first power line VDD and the second power line VSS can each be provided with a plurality of second openings 411, and the orthographic projection of the second openings 411 on the reference plane is located within the orthographic projection of the shielding electrode 3 on the reference plane.

[0065] In some embodiments, the orthographic projection of the first opening 31 on the reference plane and the orthographic projection of the second opening 411 on the reference plane are spaced apart from each other. At least one orthographic projection of the first opening 31 on the reference plane may be located between the orthographic projections of two adjacent second openings 411 on the reference plane, and at least one orthographic projection of the second opening 411 on the reference plane may be located between the orthographic projections of two adjacent first openings 31 on the reference plane, so as to avoid the first opening 31 and the second opening 411 overlapping. This not only allows water vapor in the organic film layers such as the first planarization layer and the second planarization layer to be discharged, preventing water vapor from corroding the light-emitting material and avoiding bulging and film peeling due to the inability to release water vapor, but also prevents the first opening 31 and the second opening 411 from exposing the fan-out traces below, so as to ensure that the shielding electrode 3 and the DC voltage line 40 can shield the interference of the signal transmitted by the fan-out traces to the signal transmitted by the touch lead.

[0066] In some embodiments, such as Figure 2 and Figure 3 As shown, the cathode layer 704 is disposed in the display area AA and the first border area NA1. The orthographic projection of the shielding electrode 3 on the reference plane overlaps with the orthographic projection of the cathode layer 704 on the reference plane.

[0067] It should be noted that due to fluctuations in the manufacturing precision of the cathode layer, the display signal in some areas cannot be shielded by the cathode layer, causing the touch signal to still be interfered with by the display signal, thus affecting the accuracy of touch control. This embodiment addresses this by ensuring that the orthogonal projection of the shielding electrode 3 onto the reference plane partially overlaps with the orthogonal projection of the cathode layer 704 onto the reference plane. Even if the boundary of the cathode layer shrinks due to fluctuations in manufacturing precision, the shielding electrode 3 can still cover the fan-out traces not covered by the cathode layer, thus shielding the signals transmitted through the fan-out traces from interfering with the signals transmitted through the touch leads, thereby improving touch accuracy.

[0068] In some embodiments, such as Figure 2 and Figure 3As shown, the third conductive layer 4 is disposed between the first conductive layer 1 and the anode layer 701, the anode layer 701 is disposed between the third conductive layer 4 and the cathode layer 704, and the shielding electrode 3 is disposed in the same layer as the anode layer 701 and is made of the same material.

[0069] In the actual manufacturing process, the shielding electrode 3 can be fabricated simultaneously with the anode layer 701 using the same film-forming process. By using the process of the anode layer 701 to fabricate the shielding electrode 3, the interference of the signal transmitted by the fan-out traces on the signal transmitted by the touch lead can be reduced without increasing the film structure and related process of the display panel, thereby improving the touch accuracy.

[0070] In some embodiments, the shielding electrode 3 is electrically connected to the second power line VSS to receive the DC voltage signal transmitted by the second power line VSS and form a constant electric field, thereby shielding the signal transmitted by the fan-out trace from interfering with the signal transmitted by the touch lead. In other embodiments, the shielding electrode 3 may also be electrically connected to other DC voltage lines besides the second power line VSS. For example, the shielding electrode 3 may be electrically connected to any one of the first power line VDD, the first reset signal line Vi1, the second reset signal line Vi2, and the third reset signal line Vi3.

[0071] In some embodiments, the shielding electrode 3 may be disposed between the third conductive layer 4 and the anode layer 701. For example, the display panel includes a third source-drain layer disposed between the driving circuit layer and the light-emitting device layer, and the third source-drain layer includes a shielding electrode. By adding a third source-drain layer between the driving circuit layer and the light-emitting device layer, and using the third source-drain layer to place the shielding electrode 3, interference of signals transmitted by fan-out traces to signals transmitted by touch leads can also be shielded, thereby improving touch accuracy.

[0072] Based on the display panel provided in the above embodiments of this application, embodiments of this application also provide a display device, in conjunction with... Figure 6 As shown, Figure 6 The diagram below shows the structure of a display device provided in an embodiment of this application. The display device includes a display panel 100 and a housing 200. The display panel 100 is disposed on the housing 200. The display panel 100 can be any of the display panels provided in the above embodiments. The display device provided in the embodiments of this application can achieve the same technical effects as the display panels described above, which will not be elaborated here.

[0073] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a display panel and a display device. The display panel has a display area and a first frame area disposed on one side of the display area. The display panel includes a first conductive layer, a cathode layer and a second conductive layer. The first conductive layer includes fan-out traces located in the first frame area. The cathode layer is disposed on the first conductive layer, and the second conductive layer is disposed on the cathode layer. The second conductive layer includes touch leads located in the first frame area. In the thickness direction of the display panel, the touch leads and the fan-out traces partially overlap. By providing a shielding electrode disposed in the first frame area that is dissimilar to the cathode layer, and placing the shielding electrode between the fan-out traces and the touch leads, the overlapping portion of the touch leads and the fan-out traces at least partially overlaps with the shielding electrode. In this way, the shielding electrode can be used to shield the interference of the signal transmitted by the fan-out traces on the signal transmitted by the touch leads, thereby improving the touch accuracy.

[0074] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0075] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0076] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0077] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a first border area disposed on one side of the display area. The first conductive layer includes fan-out traces located in the first border area; A cathode layer is disposed on the first conductive layer; and A second conductive layer is disposed on the cathode layer and includes a touch lead located in the first bezel area. In the thickness direction of the display panel, the touch lead overlaps with the fan-out trace portion. The display panel further includes a shielding electrode located in the first frame area. The shielding electrode is disposed in a different layer from the cathode layer. In the thickness direction of the display panel, the shielding electrode is located between the fan-out trace and the touch lead. The overlapping portion of the touch lead and the fan-out trace at least partially overlaps with the shielding electrode.

2. The display panel as described in claim 1, characterized in that, The display panel also includes: A third conductive layer is disposed between the first conductive layer and the shielding electrode, and includes at least two DC voltage lines. A portion of the fan-out trace is located between the orthographic projections of two adjacent DC voltage lines onto a reference plane, which is parallel to the light-emitting surface of the display panel. The orthographic projection of the shielding electrode on the reference plane covers the orthographic projection of the portion of the fan-out trace located between two adjacent DC voltage lines on the reference plane.

3. The display panel as described in claim 2, characterized in that, At least two of the DC voltage lines are arranged at intervals along the direction from the display area toward the first border area; The orthographic projection of the shielding electrode on the reference plane covers the orthographic projection of at least one of the DC voltage lines on the reference plane, and also covers the gap between the orthographic projections of two adjacent DC voltage lines on the reference plane.

4. The display panel as described in claim 3, characterized in that, The orthographic projection of the shielding electrode on the reference plane is spaced apart from the orthographic projection of the DC voltage line closest to the display area on the reference plane; Alternatively, the orthogonal projection of the shielding electrode onto the reference plane overlaps with the orthogonal projection of the DC voltage line closest to the display area onto the reference plane.

5. The display panel as described in claim 3, characterized in that, The shielding electrode has a first opening, the first opening being an orthographic projection on the reference plane, and the DC voltage line being an orthographic projection on the reference plane.

6. The display panel as described in claim 5, characterized in that, At least two of the DC voltage lines include power lines, the orthographic projection of the power lines onto the reference plane overlapping the orthographic projection of the shielding electrode onto the reference plane; The power cord has a second opening, and the orthographic projection of the second opening on the reference plane is located within the orthographic projection of the shielding electrode on the reference plane.

7. The display panel as described in claim 6, characterized in that, The orthographic projection of the first opening on the reference plane and the orthographic projection of the second opening on the reference plane are spaced apart from each other.

8. The display panel as claimed in any one of claims 1 to 7, characterized in that, The cathode layer is disposed in the display area and the first border area; The orthographic projection of the shielding electrode onto the reference plane partially overlaps with the orthographic projection of the cathode layer onto the reference plane, and the reference plane is parallel to the light-emitting surface of the display panel.

9. The display panel as described in any one of claims 1 to 7, characterized in that, The display panel includes: A third conductive layer is disposed between the first conductive layer and the cathode layer; and An anode layer is disposed between the third conductive layer and the cathode layer; The shielding electrode is disposed in the same layer as the anode layer and is made of the same material; or, the shielding electrode is disposed between the third conductive layer and the anode layer.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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