Integrated power management unit for full surround gate technology

Abstract

At least one integrated power management unit (702) of the IC (700) includes a first unit (700) that is a 4-high unit, the first unit including a first contiguous n-well (704), a first power interconnect (792) coupled to a first voltage source (Vdd1) associated with a first voltage domain and the first contiguous n-well (704), a second contiguous n-well (706), a second power interconnect (796) coupled to a second voltage source (Vdd2) associated with a second voltage domain and the second contiguous n-well (706), a first subset (710a) of first voltage level shifters (710) associated with the first voltage domain and coupled to the first power interconnect, and a second subset (710b) of first voltage level shifters (710) associated with the second voltage domain and coupled to the second power interconnect.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Non-Provisional Patent Application Serial No. 18 / 504,062, filed November 7, 2023, entitled “INTEGRATED POWER MANAGEMENT CELLS FOR GATE ALLAROUND TECHNOLOGIES”, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to the layout structure of integrated circuits (ICs), and more specifically to integrated power management units for gate all around (GAA) technology. Background Technology

[0004] Gate all-around (GAA) technology is a transistor design in which the gate material surrounds the conductive channel from all sides. GAA technology provides a better effective transistor width (…). W eff It also offers superior electrostatic control compared to other types of transistors, such as field-effect transistors (FETs) and / or fin FETs (FinFETs), where the gate material only partially surrounds the conductive channel.

[0005] However, GAA technology exhibits an undesirable parasitic bottom transistor (PBT) beneath the bottom nanosheet channel, increasing junction leakage. Junction leakage progressively worsens when n-wells (n-wells) are incorporated into GAA technology, leading to transistor performance degradation. While separating the n-wells can reduce junction leakage, it results in a larger footprint for each transistor. Therefore, a solution to the junction leakage problem is needed without significantly increasing the footprint of GAA transistors. Summary of the Invention

[0006] In one aspect of this disclosure, at least one integrated power management unit of an integrated circuit (IC) includes a first unit. The first unit is a 4-height unit including a first row, a second row, a third row, and a fourth row. The first unit also includes a first consecutive n-well (n-well), a first power interconnect, a second consecutive n-well, a second power interconnect, and a first voltage level shifter including a first subset and a second subset. The first consecutive n-well extends in a first direction across portions of the first and second rows of the first unit to the edge of the first unit. The first power interconnect extends in a first direction along the edges of both the first and second rows of the first unit and is coupled to a first voltage source associated with a first voltage domain and the first consecutive n-well. The second consecutive n-well extends in a first direction across portions of the third and fourth rows of the first unit to the edge of the first unit. The second power interconnect extends in a first direction along the edges of both the third and fourth rows of the first unit and is coupled to a second voltage source associated with a second voltage domain and the second consecutive n-well. A first subset of the first voltage level shifter is located in one of the first or second rows of the first unit, and the first subset of the first voltage level shifter is associated with the first voltage domain and coupled to the first power interconnect. The second subset of the first voltage level shifter is in one of the third or fourth rows of the first cell, and the second subset of the first voltage level shifter is associated with the second voltage domain and coupled to the second power interconnect. Attached Figure Description

[0007] Figure 1 This is the first illustration showing a side view of the various layers within an integrated circuit (IC).

[0008] Figure 2 This is the second illustration, showing a side view of each layer within the IC.

[0009] Figure 3A This is an illustration of an example of a FinFET (Fin Field-Effect Transistor).

[0010] Figure 3B This is an illustration of an example of a gate-all-around (GAA) field-effect transistor (FET).

[0011] Figure 4A This is a schematic diagram illustrating an example of a split n-well.

[0012] Figure 4B This is a diagram illustrating the layout of an example of a split n-well.

[0013] Figure 5A This is a schematic diagram illustrating an example of merging n traps.

[0014] Figure 5B This is a diagram illustrating the layout of an example of merging n traps.

[0015] Figure 6A This is a diagram illustrating an example of a cell with merged n-wells.

[0016] Figure 6B This is a diagram illustrating an example of a cell with a split n-well.

[0017] Figure 6C This is an illustration of another example of a cell with a split n-well.

[0018] Figure 7 This is a diagram illustrating examples of a set of integrated power management units according to various aspects of this disclosure.

[0019] Figure 8A is an illustration illustrating examples of integrated power management units according to various aspects of this disclosure.

[0020] Figure 8B is an illustration illustrating examples of integrated power management units according to various aspects of this disclosure.

[0021] Figure 8C is an illustration illustrating examples of integrated power management units according to various aspects of this disclosure.

[0022] Figure 9 This is a diagram illustrating examples of a set of integrated power management units and additional units according to various aspects of this disclosure.

[0023] Figure 10 This is a diagram illustrating examples of a set of integrated power management units according to various aspects of this disclosure.

[0024] Figure 11A This is a diagram illustrating examples of integrated power management units according to various aspects of this disclosure.

[0025] Figure 11B This is a diagram illustrating examples of integrated power management units according to various aspects of this disclosure. Detailed Implementation

[0026] Gate-all-around (GAA) technology has an undesirable parasitic bottom transistor (PBT) beneath the bottom nanosheet channel, leading to increased junction leakage. Junction leakage becomes progressively more severe when n-wells (n-wells) are incorporated into GAA technology, resulting in transistor performance degradation. While separating the n-wells can reduce junction leakage, it results in a larger footprint per transistor. The example aspect presented in this paper provides a set of integrated power management units for GAA technology, allowing for continuous n-wells without significantly increasing leakage current.

[0027] Various aspects generally relate to the layout structure of integrated circuits (ICs). Some aspects more specifically relate to integrated power management units for GAA (Power Assignment) technology. In some examples, at least one integrated power management unit of an integrated circuit (IC) includes a first cell. The first cell is a 4-height cell including a first row, a second row, a third row, and a fourth row. The first cell also includes a first consecutive n-well (n-well), a first power interconnect, a second consecutive n-well, a second power interconnect, and a first voltage level shifter including a first subset and a second subset. The first consecutive n-well extends in a first direction across portions of the first and second rows of the first cell to the edge of the first cell. The first power interconnect extends in a first direction along the edges of both the first and second rows of the first cell and is coupled to a first voltage source associated with a first voltage domain and the first consecutive n-well. The second consecutive n-well extends in a first direction across portions of the third and fourth rows of the first cell to the edge of the first cell. The second power interconnect extends in a first direction along the edges of both the third and fourth rows of the first cell and is coupled to a second voltage source associated with a second voltage domain and the second consecutive n-well. A first subset of the first voltage level shifter is located in one of the first or second rows of the first cell, and the first subset of the first voltage level shifter is associated with a first voltage domain and coupled to a first power interconnect. A second subset of the first voltage level shifter is located in one of the third or fourth rows of the first cell, and the second subset of the first voltage level shifter is associated with a second voltage domain and coupled to a second power interconnect.

[0028] Specific aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. In some examples, by employing the integrated power management unit given in the example aspects, the area occupied by the GAA transistor can be reduced without significantly increasing its leakage current. Therefore, the overall size of the IC can be reduced. Furthermore, the proposed integrated power management units are scalable. They facilitate the combination of multi-bit voltage level shifters without congestion and allow for toggling signal transmissions, thus providing greater versatility in designing layout architectures.

[0029] The detailed description following, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and not as representing only the configurations in which the concepts described herein can be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form. Apparatus and methods will be described in the following detailed description and can be illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, elements, etc.

[0030] Figure 1 This is the first illustration 100, showing a side view of a unit device and the various layers within an IC. Each layer varies in the z-direction (labeled the third direction). For example... Figure 1 As illustrated, the transistor has a gate 102 (which may be referred to as POLY in some cases, even though the gate may be formed of metal, polysilicon, or a combination of polysilicon and metal), a source 104, and a drain 106. The source 104 and drain 106 may be formed of fins (for FinFETs) or one or more nanosheet channels (for GAA field-effect transistors (GAAFETs)). In a GAAFET (as illustrated), the gate 102 may extend in a second direction (e.g., a vertical direction outward from the page along the y-axis), and one or more nanosheet channels may extend in a first direction orthogonal to the second direction (e.g., a horizontal direction along the x-axis), and the gate 102 may surround one or more nanosheet channels from all sides. In a FinFET, the gate 102 may extend in the second direction, and the fins may extend in a first direction orthogonal to the second direction (e.g., a horizontal direction along the x-axis). Contact layer interconnect 108 (also referred to as a metal POLY (MP) layer interconnect or contact B (CB) layer interconnect) may contact gate 102. Contact layer interconnects 140 and 150 (each may also be referred to as a metal diffused (MD) layer interconnect or contact A (CA) layer interconnect) may contact source 104 and / or drain 106, respectively. Via 112 (also referred to as via A (VA)) may contact contact layer interconnect 150. Metal O (M0) layer interconnect 114 may contact via 112. M0 layer interconnect 114 is illustrated as extending unidirectionally in a first direction, but may also extend in a second direction. Via V0 116 may contact M0 layer interconnect 114. Metal I (M1) layer interconnect 118 may contact via V0 116. M1 layer interconnect 118 is illustrated as extending unidirectionally in the second direction, but may alternatively extend unidirectionally in the first direction. The higher layers include a via layer with via V1, a metal 2 (M2) layer with M2 layer interconnects, and a higher via / metal layer. The M2 layer and the higher layer interconnects may extend in a first direction or a second direction. Metal q (M q The metal layers (1 and above) can extend in both the first and second directions. The cell device can be implemented using FinFET, GAAFET (as illustrated), or other multi-gate FETs. For continuous oxide diffusion (OD) regions spanning multiple devices, the fins / nanofabrications are continuous across multiple devices (in the first direction). For discontinuous OD regions spanning multiple devices, the fins / nanofabrications are separated at diffusion interruptions (e.g., single / double diffusion interruptions extending in the second direction) between multiple devices in different groups.

[0031] Figure 2This is a second illustration 200, illustrating a standard cell and the various layers within an IC. Each layer varies in the z-direction (labeled the third direction). For example... Figure 2 As illustrated, the transistor has a gate 202, a source 204, and a drain 206. The source 204 and drain 206 can be formed by fins (for FinFETs) or one or more nanosheet channels (for GAAFETs). In a GAAFET (as illustrated), the gate 202 may extend in a second direction (e.g., a vertical direction outward from the page along the y-axis), and one or more nanosheet channels may extend in a first direction orthogonal to the second direction (e.g., a horizontal direction along the x-axis), and the gate 202 may surround one or more nanosheet channels from all sides. In a FinFET, the gate 202 may extend in the second direction, and the fins may extend in a first direction orthogonal to the second direction (e.g., a horizontal direction along the x-axis). Contact layer interconnects 208 (also referred to as MP layer interconnects or CB layer interconnects) may contact the gate 202. Contact layer interconnects 240 and 250 (each may also be referred to as MD layer interconnects or CA layer interconnects) may contact the source 204 and / or the drain 206, respectively. Via 212 (also referred to as via B (VB)) can access contact layer interconnect 208. M0 layer interconnect 214 can access via 212. M0 layer interconnect 214 is illustrated as extending unidirectionally in a first direction, but may also extend in a second direction. Via V0 216 can access M0 layer interconnect 214. M1 layer interconnect 218 can access via V0 216. M1 layer interconnect 218 is illustrated as extending unidirectionally in the second direction, but may alternatively extend unidirectionally in the first direction. Higher layers include a via layer having via V1, an M2 layer having M2 layer interconnects, and higher via / metal layers. The M2 layer and higher layer interconnects may extend in either the first or second direction. q The metal layers and above can extend in both the first and second directions. The cell device can be implemented using FinFETs, GAAFETs (as illustrated), or other multi-gate FETs. For continuous OD regions spanning multiple devices, the fins / nanofabrications are continuous across multiple devices (in the first direction). For discontinuous OD regions spanning multiple devices, the fins / nanofabrications are separated at diffusion interruptions (e.g., single / double diffusion interruptions extending in the second direction) between multiple devices in different groups.

[0032] Refer again Figure 1 and Figure 2 The bottommost metal layer is exemplified as layer 0, but alternatively, it may be designated as layer 1. The bottommost metal layer may extend unidirectionally in the horizontal direction. Layers above the bottommost metal layer may extend unidirectionally in the vertical direction. Layers two layers above the bottommost metal layer may extend unidirectionally in the horizontal direction.

[0033] The example aspect given in this paper provides vertically stacked power domains, in which metal programmable normally open cells are integrated as part of a voltage level shifter cell between power domains.

[0034] GAA technology is a transistor design in which gate material surrounds the channel region from all sides, thus enabling better control of the current flowing through the channel than other types of transistors, such as planar or field-effect transistors (FETs) and / or FinFETs. Figure 3A The illustration 300 is an example of a FinFET, in which gate material 302 surrounds the fin transistor body 304 from three sides (i.e., except for the bottom side). Figure 3B The illustration 350 is an example of a GAAFET, where gate material 352 surrounds multiple nanosheet channels 362, 364, 366 of the GAAFET from all sides. This is in contrast to FinFETs (such as...). Figure 3A Compared to FinFET, GAAFET (such as FinFET) Figure 3B The GAAFET shown provides a better effective transistor width ( W eff And better static electricity control.

[0035] Cells fabricated using FinFET technology can exhibit negligible body effects. Therefore, FinFETs can incorporate their n-wells without significantly impacting their performance (e.g., without significantly increasing junction leakage). As used herein, "body effect" refers to the change in threshold voltage due to source-body voltage (or substrate bias). Threshold voltage considering body effect. It can be described by the following equation: (1) in It is the threshold voltage without volume effect. It is the source-body voltage (or substrate bias). It is the Fermi potential (negative for nMOS, positive for pMOS), and It is the body effect coefficient.

[0036] On the other hand, GAAFETs have channels located on the bottom nanosheets (such as...) Figure 3B Undesirable parasitic bottom transistors beneath the nanosheet channel (366) in a GAAFET can lead to increased junction leakage. Junction leakage progressively worsens when multiple n-wells of a GAAFET are combined, degrading transistor performance. In some examples, combined n-wells can increase junction leakage by approximately two times. To reduce junction leakage in a GAAFET, the n-wells of the transistor can be split (e.g., separated). However, splitting the n-wells increases the footprint of each transistor.

[0037] Figure 4A and Figure 4B An example of a cell with a split n-well is shown. Figure 4A This is a schematic diagram 400 illustrating an example of two split n-wells. Figure 4A A power switch 410 and an underlying logic unit 420 served by the power switch 410 are shown. The underlying logic unit 420 may include a first set of transistors 422 and a second set of transistors 424. The power switch 410 may include a normally open power supply 412 and a clamping power supply 414. Figure 4A In this configuration, if the transistors are planar transistors, n-wells 402 and 404 can be isolated (e.g., by a 0.8µm n-well spacing) to reduce junction leakage. For example, the first group of transistors 422 may occupy most of the logic cell 420 (compared to the second group of transistors 424). When the power switch 410 is de-energized (clamping power supply 414 is at 0), the first group of transistors 422 can be de-energized, and all logic in that group of transistors 422 can be floating (meaning the logic can drift to indeterminate voltage levels). Therefore, n-well 402 can be connected to the floating power supply to reduce junction leakage, and n-well 402 can be isolated from n-well 404. Figure 4B Illustration 450 shows a layout diagram illustrating an example of a split n-well. Figure 4B In this configuration, two separate n-wells (e.g., n-wells 402 and 404) can be separated by an n-well spacing of, for example, 0.8 μm. Figure 4B The third separate n-well 406 is also shown, which is positioned 0.8 μm (n-well spacing) away from n-well 404.

[0038] Figure 5A and Figure 5B An example of a cell with an fused n-well is shown. Figure 5A Illustration 500 is a schematic diagram illustrating an example of merging n traps. Figure 5A In this configuration, if the transistor is a FinFET, the negligible bulk effect of the FinFET allows the FinFET to be connected to a single normally open power supply 512, and the n-wells of the FinFET can be combined to form a continuous (i.e., combined) n-well 502, thereby reducing the footprint occupied by the FinFET. Figure 5B Illustration 550 shows a layout diagram of an example of merging n-well 502.

[0039] GAAFETs can use split n-wells to avoid large junction leakage. However, as Figure 4A , Figure 4B , Figure 5A and Figure 5BAs shown, compared to merged n-wells, split n-wells increase the transistor footprint due to, for example, the n-well spacing between them. In some examples, split n-wells can increase the footprint of all power management units, such as Global Distributed Head Switch (GDHS) units, 0-pin hold-up flip-flops, and normally open buffers. In some cases, split n-wells can increase the footprint by 1.5% to 2% compared to using merged n-wells.

[0040] Figure 6A This is illustration 600, illustrating an example of merging n traps. Figure 6A In this configuration, a cell may share a merged n-well with adjacent cells (e.g., n-well 602). Cells sharing a merged n-well may be referred to as type 1 cells. Figure 6A In addition to the positive power supply (e.g., vddx 606) and ground reference (e.g., vsssx 608), a cell with a combined n-well (n-well 602) may have secondary power supplies for each part of the driving logic (e.g., vdd_ext 604), but may not have any n-well taps (e.g., a structure that connects the n-well to a voltage source). Figure 6B Illustration 620 illustrates an example of a cell with a split n-well. Figure 6B In this configuration, the split n-wells of the cell (e.g., n-wells 622a, 622b, 622c) may have built-in taps for n-wells 622a and 622c. One or more of the built-in taps at 622a and 622c may be connected to a voltage source Vdd_aon 634. This cell may be referred to as a type 2 cell. Figure 6C Illustration 640 is another example illustrating a cell with a split n-well. Figure 6C In this configuration, the split n-wells of the cell (e.g., n-wells 642a, 642b, 642c) may have built-in taps for n-wells 642a and 642c. One or more of the built-in taps at 642a and 642c may be connected to a voltage source VDDX 656. This cell may be referred to as a type 3 cell. Figure 6B and Figure 6C As shown, the spacing between the built-in taps in the split n-well and the split n-well (e.g., spacings 630, 632, 650, 652) can increase the occupied area of ​​the IC.

[0041] like Figure 6A , Figure 6B and Figure 6C As shown, the choice between split n-wells and merged n-wells is of great significance for semiconductor structures. For example, when merging n-wells ( Figure 6A ) is divided into multiple split n-wells ( Figure 6B or Figure 6C When ), type 1 unit ( Figure 6A ) can be transformed into a type 1 unit ( Figure 6A Type 2 units occupying a larger horizontal area Figure 6B ) or type 3 unit ( Figure 6C Additionally, type 2 unit ( Figure 6B ) and Type 3 unit ( Figure 6C This might require a double-height cell (to allow for proper stacking with other cell types), which further increases the space occupied by the cell compared to a Type 1 cell (which can be a single-height cell). For some cell types, such as 0-pin hold-down flip-flops and GDHS cells, this shift from Type 1 to Type 2 or Type 3 cells could result in an estimated increase of 1.5% to 2% in the overall chip-scale area cell distribution (based on...). KailuaR2 data).

[0042] The example aspects presented in this paper provide integrated power management units (or cell islands) for ICs. The layout of the integrated power management units (or cell islands) reduces horizontal space through vertical stacking and is suitable for GAA transistors. The integrated power management units (or cell islands) include vertically stacked (rather than horizontally stacked) voltage domains. This allows for the use of merged n-wells on GAA transistors without significantly increasing leakage current, thereby reducing the area occupied by the GAA transistors. Therefore, the overall size of the IC can be reduced. Furthermore, the proposed integrated power management units are scalable. They facilitate the integration of multi-bit voltage level shifters without congestion and allow for toggling signal transmission, thus providing greater versatility in designing layout architectures.

[0043] Figure 7 This is a diagram 700 illustrating an example of a set of integrated power management units according to various aspects of this disclosure. The set of integrated power management units includes unit 702. Unit 702 is a 4-height multi-domain unit comprising four rows in a second direction of transistor logic. Unit 702 has a first n-well 704 coupled to a power interconnect 792, thereby providing a voltage V associated with a first voltage domain (e.g., 0.435 V to 1.155 V). dd1 Unit 702 has a second n-well 706 coupled to power interconnect 796, thereby providing a voltage V associated with a second voltage domain (e.g., 2.515 V or 2.565 V). dd2 Both n-wells 704 and 706 extend to the edge of cell 702 in the first direction. Figure 7 The right and left edges in the first direction of the n-wells 704 and 706 are continuous with the n-wells of the adjacent positioned cells 732 and 762. Therefore, there is no isolation (e.g., deep trench isolation (DTI) or shallow trench isolation (STI)) between cells 702, 732 and 762.

[0044] The first line 782 includes transistor logic, which includes coupling to provide voltage V. ss The power interconnect 790 is an n-type metal-oxide-semiconductor (MOS) (nMOS) transistor (e.g., ground voltage), and includes a connection to a voltage V. dd1 The power interconnect 792 contains a p-type MOS (pMOS) transistor. The second line 784 includes transistor logic, which includes coupling to provide a voltage V. dd1 The power interconnect 792 includes a pMOS transistor and includes a connection to provide a voltage V. ss The power interconnect 794 is an nMOS transistor. The third line 786 includes transistor logic, which includes coupling to provide a voltage V. ss The power interconnect 794 is an nMOS transistor, and includes a coupling to provide a voltage V. dd2 The power interconnect 796 is a pMOS transistor. The fourth line 788 includes transistor logic, which includes coupling to provide a voltage V. dd2 The power interconnect 796 is a pMOS transistor, and includes a coupling to provide a voltage V. ss The power interconnect is an nMOS transistor of 798.

[0045] Voltage level shifter 710 is located in rows 784, 788 of cell 702. Voltage level shifter 710 includes a first subset 710a coupled to a first power domain via power interconnect 796, thereby providing voltage V. dd1 And includes a second subset 710b coupled to the second power domain via power interconnect 792, thereby providing voltage V dd2 The voltage level shifter 710 is further coupled to power interconnects 794, 798, thereby providing voltage V. ss .

[0046] Unit 702 may include a clamping subunit 712 within the first row 782. The clamping subunit 712 is coupled to a first subset 710a of the voltage level shifter 710 and power interconnects 790, 792. Unit 702 may also include an Engineering Change Order (ECO) subunit 714. The ECO subunit may be replaced with a logic unit prior to manufacturing.

[0047] Unit 702 may include a clamping subunit 718 within the third row 786. The clamping subunit 718 is coupled to a second subset 710b of the voltage level shifter 710 and power interconnects 794, 796. Unit 702 may also include a metal programmable normally open subunit 720. The clamping subunit 718 may also be a normally open subunit. Figure 7An example implementation of subunits 712, 714, 718, and 720 is shown. In some examples, one or more of subunits 712, 714, 718, and 720 may be metal programmable units and may be programmed into various types of units, such as hold-on flip-flops, normally open buffers, or inverters.

[0048] Power interconnects 790, 792, 794, 796 and 798 extend across cell 702 in a first direction and may be located on the lowest metal layer (e.g., M0 or M1 layer) of the horizontal interconnects extending in the first direction.

[0049] The integrated power management unit set may also include a unit 732 adjacent to unit 702. An n-well 704 extends in a first direction to the edges of units 702 and 732, such that the n-well 704 is continuous across units 702 and 732. Unit 732 is also a 4-height multi-domain unit, which includes a voltage level shifter 740 (including subsets 740a and 740b), clamping sub-units 742 and 748 resembling clamping sub-units 712 and 718 respectively, a logic unit 744, and a metal programmable normally-on sub-unit 750.

[0050] The integrated power management unit set may also include a unit 762 adjacent to unit 732. An n-well 704 extends in a first direction to the edges of units 702 and 762, such that the n-well 704 is continuous across units 702, 732, and 762. Unit 762 is also a 4-height multi-domain unit, which includes a voltage level shifter 770 (including subsets 770a and 770b), clamping sub-units 772 and 778 resembling clamping sub-units 712 and 718 respectively, a logic sub-unit 774, and a metal programmable normally-on sub-unit 780.

[0051] Figure 8A is a diagram 800 illustrating an example of an integrated power management unit according to various aspects of the present disclosure. Figure 8B is a diagram 850 illustrating another example of an integrated power management unit according to various aspects of the present disclosure. Figure 8C is a diagram 880 illustrating another example of an integrated power management unit according to various aspects of the present disclosure. Figure 7The voltage level shifters in the second row 784 and the fourth row 788 are illustrated. Alternatively, the voltage level shifter 710 may be in rows 784 and 786, as illustrated in Figure 8A; in rows 782 and 786, as illustrated in Figure 8B; or in rows 782 and 788, as illustrated in Figure 8C. As illustrated in Figure 8A, clamping subunits 712 and 718 are in rows 782 and 788, respectively. Logic subunit 714 is in row 782, and metal-programmable normally-open subunit 720 is in row 788. As illustrated in Figure 8B, clamping subunits 712 and 718 are in rows 784 and 788, respectively. Logic subunit 714 is in row 784, and metal-programmable normally-open subunit 720 is in row 788. As illustrated in Figure 8C, clamping subunits 712 and 718 are in rows 784 and 786, respectively. Logic subunit 714 is in row 784, and metal programmable normally open subunit 720 is in row 786.

[0052] Refer again Figure 7 Figures 8A to 8C show that at least one integrated power management unit of the IC includes a first cell 702. The first cell 702 is a 4-height cell. The first cell 702 includes a first row 782, a second row 784, a third row 786, and a fourth row 788. The first cell 702 includes a first continuous n-well 704 extending in a first direction across portions of the first row 782 and the second row 784 of the first cell 702 to the edge of the first cell 702. The first cell 702 also includes a first power interconnect 792 extending in a first direction along both the edges of the first row 782 and the second row 784 of the first cell 702. The first power interconnect 792 is coupled to a first voltage source V associated with a first voltage domain. dd1 And coupled to a first continuous n-well 704. The first unit also includes a second continuous n-well 706 extending in a first direction across portions of the third row 786 and the fourth row 788 of the first unit 702 to the edge of the first unit 702. The first unit 702 also includes a second power interconnect 796 extending in a first direction along both the edges of the third row 786 and the fourth row 788 of the first unit 702. The second power interconnect 796 is coupled to a second voltage source V associated with a second voltage domain. dd2 And coupled to the second consecutive n-well 706. The first unit 702 also includes the first row 782 (Figures 8B and 8C) or the second row 784 ( Figure 7 A first subset 710a of the first voltage level shifter 710 in one of Figures 8A and 8B. The first subset 710a of the first voltage level shifter 710 is associated with a first voltage domain and coupled to a first power interconnect 792. The first unit 702 also includes a third row 786 (Figures 8A and 8B) or a fourth row 788 (Figures 8B and 8B) of the first unit 702. Figure 7The second subset 710b of the first voltage level shifter 710 in one of Figures 8C. The second subset 710b of the first voltage level shifter 710 is associated with the second voltage domain and coupled to the second power interconnect 796.

[0053] In some respects, the first unit 702 also includes the first row 782 of the first unit 702 ( Figure 7 A first clamping subunit 712 is associated with a first voltage domain in either the first row 782 (Figure 8A) or the second row 784 (Figures 8B and 8C). The first clamping subunit 712 is coupled to a first power interconnect 792, and a first subset 710a of the first voltage level shifter 710 is located in the other of the first row 782 or the second row 784 of the first unit 702. The first unit 702 also includes a third row 786 (Figure 8B and 8C) of the first unit 702. Figure 7 A second clamping subunit 718 is associated with the second voltage domain in one of Figure 8C (or the fourth row 788 in Figures 8A and 8B). The second clamping subunit 718 is coupled to the second power interconnect 796, and the second subset 710b of the first voltage level shifter 710 is in the other of the third row 786 or the fourth row 788 of the first unit 702.

[0054] In some respects, the first voltage source V dd1 It is an input voltage drain-to-drain (VDD) voltage source, and a second voltage source V dd2 It is the output VDD voltage source.

[0055] In some aspects, the first unit 702 also includes a third power interconnect 790, a fourth power interconnect 794, and a fifth power interconnect 798. The third power interconnect 790 extends along the edge of the first row 782 of the first unit 702 in a first direction, and the third power interconnect 790 is coupled to a third voltage source V. ss The fourth power interconnect 794 extends along the edges of both the second row 784 and the third row 786 of the first unit 702 in a first direction, and the fourth power interconnect 794 is coupled to the third voltage source V. ss The fifth power interconnect 798 extends along the edge of the fourth row 788 of the first unit 702 in a first direction, and the fifth power interconnect 798 is coupled to the third voltage source V. ss The first clamping subunit 712 is coupled to the third power interconnect 790. Figure 7 The first voltage level shifter 710 is coupled to one of the third power interconnect 790 or the fourth power interconnect 794 (Figures 8B and 8C), and the first subset 710a of the first voltage level shifter 710 is coupled to the other of the third power interconnect 790 or the fourth power interconnect 794. The second clamping subunit 718 is coupled to the fourth power interconnect 794 (Figures 8B and 8C). Figure 7The first voltage level shifter 710 is coupled to one of the fourth power interconnect 794 or the fifth power interconnect 798 (Figures 8A and 8B), and the second subset 710b of the first voltage level shifter 710 is coupled to the other of the fourth power interconnect 794 or the fifth power interconnect 798.

[0056] In some respects, the third voltage source V ss It is a voltage source powered by a voltage source (VSS).

[0057] In some aspects, the first unit 702 also includes a first row 782 associated with and connected to the first voltage domain. Figure 7 The logic sub-unit 714 is adjacent to the first clamping sub-unit 712 in either Figure 8A or the second row 784 (Figures 8B and 8C). The logic sub-unit 714 is coupled to the first power interconnect 792 and the third power interconnect 790. Figure 7 One of the following: (and Figure 8A) or the fourth power interconnect 794 (Figures 8B and 8C).

[0058] In some respects, the second clamping subunit 718 is a normally open subunit.

[0059] In some aspects, the first unit 702 also includes a third row 786 associated with the second voltage domain and connected to the first unit 702. Figure 7 The normally open sub-unit 720 is adjacent to the second clamping sub-unit 718 in either Figure 8C or the fourth row 788 (Figures 8A and 8B). The normally open sub-unit 720 is coupled to the second power interconnect 796 and the fourth power interconnect 794. Figure 7 One of the following: (and Figure 8C) or the fifth power interconnect 798 (Figures 8A and 8B).

[0060] In some aspects, such as Figure 7 As shown, the first clamping subunit 712 is located in the first row 782 of the first unit 702 and is coupled to the third power interconnect 790. A first subset 710a of the first voltage level shifter 710 is located in the second row 784 of the first unit 702 and is coupled to the fourth power interconnect 794. A second clamping subunit 718 is located in the third row 786 of the first unit 702 and is coupled to the fourth power interconnect 794. A second subset 710b of the first voltage level shifter 710 is located in the fourth row 788 of the first unit 702 and is coupled to the fifth power interconnect 798.

[0061] In some aspects, such as Figure 7As shown, the first unit 702 further includes a logic subunit 714 and a normally open subunit 720. The logic subunit 714 is associated with a first voltage domain and is adjacent to a first clamping subunit 712 in the first row 782 of the first unit 702, and is coupled to a first power interconnect 792 and a third power interconnect 790. The normally open subunit 720 is associated with a second voltage domain and is adjacent to a second clamping subunit 718 in the third row 786 of the first unit 702, and is coupled to a second power interconnect 796 and a fourth power interconnect 794.

[0062] In some aspects, as shown in FIG8C, a first subset 710a of the first voltage level shifter 710 is located in the first row 782 of the first unit 702c, and is coupled to the third power interconnect 790. A first clamping subunit 712 is located in the second row 784 of the first unit 702c, and is coupled to the fourth power interconnect 794. A second clamping subunit 718 is located in the third row 786 of the first unit 702c, and is coupled to the fourth power interconnect 794. A second subset 710b of the first voltage level shifter 710 is located in the fourth row 788 of the first unit 702c, and is coupled to the fifth power interconnect 798.

[0063] In some aspects, as shown in Figure 8C, the first unit 702c further includes a logic subunit 714 and a normally open subunit 720. The logic subunit 714 is associated with a first voltage domain and is adjacent to a first clamping subunit 712 in the second row 784 of the first unit 702c. The logic subunit 714 is coupled to a first power interconnect 792 and a fourth power interconnect 794. The normally open subunit 720 is associated with a second voltage domain and is adjacent to a second clamping subunit 718 in the third row 786 of the first unit 702c. The normally open subunit 720 is coupled to a second power interconnect 796 and a fourth power interconnect 794.

[0064] In some aspects, as shown in FIG8A, a first clamping subunit 712 is located in the first row 782 of the first unit 702a and is coupled to a third power interconnect 790. A first subset 710a of a first voltage level shifter 710 is located in the second row 784 of the first unit 702a and is coupled to a fourth power interconnect 794. A second subset 710b of the first voltage level shifter 710 is located in the third row 786 of the first unit 702a and is coupled to the fourth power interconnect 794. A second clamping subunit 718 is located in the fourth row 788 of the first unit 702a and is coupled to a fifth power interconnect 798.

[0065] In some aspects, as shown in Figure 8A, the first unit 702a further includes a logic subunit 714 and a normally open subunit 720. The logic subunit 714 is associated with a first voltage domain and is adjacent to a first clamping subunit 712 in the first row 782 of the first unit 702a. The logic subunit 714 is coupled to a first power interconnect 792 and a third power interconnect 790. The normally open subunit 720 is associated with a second voltage domain and is adjacent to a second clamping subunit 718 in the fourth row 788 of the first unit 702a. The normally open subunit 720 is coupled to a second power interconnect 796 and a fifth power interconnect 798.

[0066] In some aspects, as shown in FIG8B, a first subset 710a of the first voltage level shifter 710 is located in the first row 782 of the first unit 702b. The first subset 710a of the first voltage level shifter 710 is coupled to a third power interconnect 790. A first clamping subunit 712 is located in the second row 784 of the first unit 702b and is coupled to a fourth power interconnect 794. A second subset 710b of the first voltage level shifter 710 is located in the third row 786 of the first unit 702b and is coupled to the fourth power interconnect 794. A second clamping subunit 718 is located in the fourth row 788 of the first unit 702b and is coupled to a fifth power interconnect 798.

[0067] In some aspects, as shown in Figure 8B, the first unit 702b further includes a logic subunit 714 and a normally open subunit 720. The logic subunit 714 is associated with a first voltage domain and is adjacent to a first clamping subunit 712 in the second row 784 of the first unit 702b. The logic subunit 714 is coupled to a first power interconnect 792 and a fourth power interconnect 794. The normally open subunit 720 is associated with a second voltage domain and is adjacent to a second clamping subunit 718 in the fourth row 788 of the first unit 702b. The normally open subunit 720 is coupled to a second power interconnect 796 and a fifth power interconnect 798.

[0068] In some aspects, such as Figure 7 As shown, at least one integrated power management unit of the IC also includes a second unit 732 adjacent to the first unit 702. The second unit 732 is a 4-height unit and includes a first row 782, a second row 784, a third row 786, and a fourth row 788. A first continuous n-well 704 extends in a first direction across portions of the first row 782 and the second row 784 of the first unit 702 and the second unit 732. A first power interconnect 792 extends in a first direction along the edges of both the first row 782 and the second row 784 of the first unit and the second unit (702 and 732). A second continuous n-well 706 extends in a first direction across portions of the third row 786 and the fourth row 788 of the first unit 702 and the second unit 732. The second power interconnect 796 extends in a first direction along the edges of both the third row 786 and the fourth row 788 of the first unit and the second unit (702 and 732).

[0069] In some aspects, such as Figure 7 As shown, the second unit 732 also includes a first subset 740a of the second voltage level shifter 740 and a second subset 740b of the second voltage level shifter 740. The first subset 740a of the second voltage level shifter 740 is located in either the first row 782 or the second row 784 of the second unit 732. The first subset 740a of the second voltage level shifter 740 is associated with a first voltage domain and coupled to a first power interconnect 792. The second subset 740b of the second voltage level shifter 740 is located in either the third row 786 or the fourth row 788 of the second unit 732. The second subset 740b of the second voltage level shifter 740 is associated with a second voltage domain and coupled to a second power interconnect 796.

[0070] In some aspects, such as Figure 7As shown, at least one integrated power management unit of the IC also includes a plurality of cells (732 and 762) adjacent to the first cell 702. Each of the plurality of cells (732 and 762) is a 4-height cell, and the plurality of cells (732 and 762) includes a first row 782, a second row 784, a third row 786, and a fourth row 788. The first cell 702 and the plurality of cells (732 and 762) form a cell set. A first consecutive n-well 704 extends in a first direction across the portion of the cell set (702, 732, and 762) between the edges of the cell set (702, 732, and 762) between the first row 782 and the second row 784. A first power interconnect 792 extends in the first direction along both the edges of the first row 782 and the second row 784 of the cell set (702, 732, and 762). A second continuous n-well 706 extends in a first direction across the portion of the cell sets (702, 732, and 762) between the edges of the cell sets (702, 732, and 762). A second power interconnect 796 extends in the first direction along both the edges of the third row 786 and the fourth row 788 of the cell sets (702, 732, 762). Each of the plurality of cells (732 and 762) includes a voltage level shifter (e.g., voltage level shifters 740, 770).

[0071] Figure 9 This is a diagram 900 illustrating an IC comprising a set of integrated power management units and additional units according to various aspects of this disclosure. Figure 9 As illustrated, the reorganized integrated power management unit can be located adjacent, in the second direction, to additional logic cells 904 having consecutive n-wells coupled to normally open power domains. The additional logic cells can be single-height (e.g., 950) or dual-height (e.g., 960). The additional logic cells may include clamping sub-units 912, 916, 942, 946, 972, and 976, and additional logic sub-units 914, 918, 944, 948, 974, and 978. Therefore, the 4-height multi-domain integrated power management unit can be adjacent single-domain single-height or dual-height logic cells, or multi-domain logic cells, and the additional logic cells do not result in a significant increase in horizontal space.

[0072] In some respects, the design of the integrated power management unit is scalable, and multiple units can be arranged along a first direction (e.g., the x-direction). Figure 10 This is a diagram 1000 illustrating examples of a set of integrated power management units according to various aspects of this disclosure. Figure 10In this design, multiple integrated power management units (such as unit 1 1002, unit 2 1004, unit 3 1006, and unit 4 1008) may be adjacent to each other along a first direction (e.g., the x-direction). Each of the units (unit 1 1002, unit 2 1004, unit 3 1006, and unit 4 1008) may be one of the integrated power management units of this disclosure (e.g., units 702, 702a, 702b, 702c, 732, 762) and may include a voltage level shifter (e.g., voltage level shifter 710, 740, or 770). Therefore, this design can provide a multi-bit voltage level shifter without congestion.

[0073] In some respects, the integrated power management units of this disclosure (e.g., units 702, 702a, 702b, 702c, 732, 762) can be vertically flipped (or inverted) to accommodate various voltage domain signal transmission methods. Figure 11A The illustration 1100 is an example of an integrated power management unit 1112 according to various aspects of the present disclosure. Figure 11B Illustration 1150 is another example illustrating the integrated power management unit 1162 according to various aspects of this disclosure. Unit 1112 may be a vertically flipped version of unit 1162. Figure 11A An integrated power management unit 1112 is shown, wherein signals enter from the VDDCX side 1102 and exit via the VDDMX side 1104. In another configuration, Figure 11B Another variation of unit 1162 is shown, which allows signals to enter from the VDDMX side 1152 and exit via the VDDCX side 1154.

[0074] The aforementioned unit design allows for the use of merged n-wells without significantly increasing leakage current, thereby reducing the area occupied by the GAA transistors. This results in a reduction in the overall IC size. Furthermore, the proposed integrated power management units are scalable. They facilitate the integration of multi-bit voltage level shifters without congestion and allow for toggling signal transmission, thus providing greater versatility in designing layout architectures.

[0075] It should be understood that the specific order or hierarchy of the steps in the disclosed process is an example of the exemplary method. It should be understood that the specific order or hierarchy of the steps in these processes can be rearranged according to design preferences. Furthermore, some steps can be combined or omitted. The appended method claims present elements of multiple steps in a sample order, but are not intended to limit one to the specific order or hierarchy presented.

[0076] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language of the claims, wherein references to elements in the singular form, unless specifically stated otherwise, are not intended to mean “one and only one” but rather “one or more”. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects. Unless specifically stated otherwise, the term “some” refers to one or more. Combinations such as “at least one of A, B, or C,” “at least one of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and / or C, and may include multiple A, multiple B, or multiple C. Specifically, combinations such as "at least one of A, B, or C," "at least one of A, B, and C," and "A, B, C, or any combination thereof" can be A only, B only, C only, A and B, A and C, B and C, or A and B and C, wherein any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the various aspects described throughout this disclosure, whether currently or hereafter known to those skilled in the art, are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is explicitly recited in the claims. No claim element should be construed as a component plus a function unless the element is explicitly stated using the phrase "a component for...".

[0077] The following examples are merely illustrative and can be combined with other specific implementations or aspects of the teachings described herein without limitation.

[0078] Aspect 1 is at least one integrated power management unit of an integrated circuit (IC), the at least one integrated power management unit of the integrated circuit (IC) including a first unit, the first unit being a 4-height unit, the first unit including a first row, a second row, a third row, and a fourth row. The first unit includes: a first continuous n-well (n-well) extending in a first direction across portions of the first row and the second row of the first unit to the edge of the first unit; a first power interconnect extending in the first direction along the edges of both the first row and the second row of the first unit, the first power interconnect being coupled to a first voltage source associated with a first voltage domain and coupled to the first continuous n-well; a second continuous n-well extending in the first direction across portions of the third row and the fourth row of the first unit to the edge of the first unit; and a second power interconnect extending along the third row and the fourth row of the first unit. The edges of both in the fourth row extend in the first direction, the second power interconnect is coupled to a second voltage source associated with the second voltage domain and coupled to the second consecutive n-well; a first subset of the first voltage level shifter, the first subset of the first voltage level shifter being in one of the first row or the second row of the first cell, the first subset of the first voltage level shifter being associated with the first voltage domain and coupled to the first power interconnect; and a second subset of the first voltage level shifter, the second subset of the first voltage level shifter being in one of the third row or the fourth row of the first cell, the second subset of the first voltage level shifter being associated with the second voltage domain and coupled to the second power interconnect.

[0079] Aspect 2 is at least one integrated power management unit of an IC according to aspect 1, wherein the first unit further includes a first clamping subunit associated with a first voltage domain in one of the first row or the second row of the first unit, the first clamping subunit being coupled to the first power interconnect, wherein the first subset of the first voltage level shifter is in the other of the first row or the second row of the first unit; and a second clamping subunit associated with a second voltage domain in one of the third row or the fourth row of the first unit, the second clamping subunit being coupled to the second power interconnect, wherein the second subset of the first voltage level shifter is in the other of the third row or the fourth row of the first unit.

[0080] Aspect 3 is at least one integrated power management unit of an IC according to any one of Aspects 1 and 2, wherein the first voltage source is an input voltage drain-to-drain (VDD) voltage source and the second voltage source is an output VDD voltage source.

[0081] Aspect 4 is at least one integrated power management unit of an IC according to any one of Aspects 1 to 2, wherein the first unit further comprises: a third power interconnect extending in a first direction along the edge of the first row of the first unit, the third power interconnect being coupled to a third voltage source; a fourth power interconnect extending in the first direction along the edges of both the second row and the third row of the first unit, the fourth power interconnect being coupled to the third voltage source; and a fifth power interconnect extending in the first direction along the edge of the fourth row of the first unit, the fifth power interconnect being coupled to the third voltage source, wherein a first clamping subunit is coupled to one of the third power interconnect or the fourth power interconnect, and a first subset of the first voltage level shifter is coupled to the other of the third power interconnect or the fourth power interconnect, and wherein a second clamping subunit is coupled to one of the fourth power interconnect or the fifth power interconnect, and a second subset of the first voltage level shifter is coupled to the other of the fourth power interconnect or the fifth power interconnect.

[0082] Aspect 5 is at least one integrated power management unit of the IC according to aspect 4, wherein the third voltage source is a voltage source powered (VSS) voltage source.

[0083] Aspect 6 is at least one integrated power management unit of an IC according to aspect 4, wherein the first unit further includes a logic sub-unit associated with the first voltage domain, the logic sub-unit being adjacent to a first clamping sub-unit in one of the first row or the second row of the first unit, the logic sub-unit being coupled to the first power interconnect and one of the third power interconnect or the fourth power interconnect.

[0084] Aspect 7 is at least one integrated power management unit of the IC according to aspect 4, wherein the second clamping subunit is a normally open subunit.

[0085] Aspect 8 is at least one integrated power management unit of an IC according to aspect 4, wherein the first unit further includes a normally open sub-unit associated with the second voltage domain, the normally open sub-unit being adjacent to a second clamping sub-unit in one of the third or fourth rows of the first unit, the normally open sub-unit being coupled to a second power interconnect and one of the fourth or fifth power interconnect.

[0086] Aspect 9 is at least one integrated power management unit of an IC according to aspect 4, wherein a first clamping subunit is in the first row of the first unit, the first clamping subunit being coupled to the third power interconnect; a first subset of the first voltage level shifter is in the second row of the first unit, the first subset of the first voltage level shifter being coupled to the fourth power interconnect; a second clamping subunit is in the third row of the first unit, the second clamping subunit being coupled to the fourth power interconnect; and a second subset of the first voltage level shifter is in the fourth row of the first unit, the second subset of the first voltage level shifter being coupled to the fifth power interconnect.

[0087] Aspect 10 is at least one integrated power management unit of an IC according to aspect 9, wherein the first unit further includes a logic sub-unit associated with the first voltage domain, the logic sub-unit being adjacent to the first clamping sub-unit in the first row of the first unit, the logic sub-unit being coupled to the first power interconnect and the third power interconnect; and a normally open sub-unit associated with the second voltage domain, the normally open sub-unit being adjacent to the second clamping sub-unit in the third row of the first unit, the normally open sub-unit being coupled to the second power interconnect and the fourth power interconnect.

[0088] Aspect 11 is at least one integrated power management unit of an IC according to aspect 4, wherein a first subset of a first voltage level shifter is in the first row of the first unit, the first subset of the first voltage level shifter being coupled to the third power interconnect; a first clamping subunit is in the second row of the first unit, the first clamping subunit being coupled to the fourth power interconnect; a second clamping subunit is in the third row of the first unit, the second clamping subunit being coupled to the fourth power interconnect; and a second subset of the first voltage level shifter is in the fourth row of the first unit, the second subset of the first voltage level shifter being coupled to the fifth power interconnect.

[0089] Aspect 12 is at least one integrated power management unit of an IC according to aspect 12, wherein the first unit further includes a logic sub-unit associated with the first voltage domain, the logic sub-unit being adjacent to the first clamping sub-unit in the second row of the first unit, the logic sub-unit being coupled to the first power interconnect and the fourth power interconnect; and a normally open sub-unit associated with the second voltage domain, the normally open sub-unit being adjacent to the second clamping sub-unit in the third row of the first unit, the normally open sub-unit being coupled to the second power interconnect and the fourth power interconnect.

[0090] Aspect 13 is at least one integrated power management unit of an IC according to aspect 4, wherein a first clamping subunit is in the first row of the first unit, the first clamping subunit being coupled to the third power interconnect; a first subset of the first voltage level shifter is in the second row of the first unit, the first subset of the first voltage level shifter being coupled to the fourth power interconnect; a second subset of the first voltage level shifter is in the third row of the first unit, the second subset of the first voltage level shifter being coupled to the fourth power interconnect; and a second clamping subunit is in the fourth row of the first unit, the second clamping subunit being coupled to the fifth power interconnect.

[0091] Aspect 14 is at least one integrated power management unit of an IC according to aspect 13, wherein the first unit further includes a logic sub-unit associated with the first voltage domain, the logic sub-unit being adjacent to the first clamping sub-unit in the first row of the first unit, the logic sub-unit being coupled to the first power interconnect and the third power interconnect; and a normally open sub-unit associated with the second voltage domain, the normally open sub-unit being adjacent to the second clamping sub-unit in the fourth row of the first unit, the normally open sub-unit being coupled to the second power interconnect and the fifth power interconnect.

[0092] Aspect 15 is at least one integrated power management unit of an IC according to aspect 4, wherein a first subset of a first voltage level shifter is in the first row of the first unit, the first subset of the first voltage level shifter being coupled to the third power interconnect; a first clamping subunit is in the second row of the first unit, the first clamping subunit being coupled to the fourth power interconnect; a second subset of the first voltage level shifter is in the third row of the first unit, the second subset of the first voltage level shifter being coupled to the fourth power interconnect; and a second clamping subunit is in the fourth row of the first unit, the second clamping subunit being coupled to the fifth power interconnect.

[0093] Aspect 16 is at least one integrated power management unit according to aspect 15, wherein the first unit further includes a logic sub-unit associated with the first voltage domain, the logic sub-unit being adjacent to the first clamping sub-unit in the second row of the first unit, the logic sub-unit being coupled to the first power interconnect and the fourth power interconnect; and a normally open sub-unit associated with the second voltage domain, the normally open sub-unit being adjacent to the second clamping sub-unit in the fourth row of the first unit, the normally open sub-unit being coupled to the second power interconnect and the fifth power interconnect.

[0094] Aspect 17 is at least one integrated power management unit of an IC according to any one of Aspects 1 to 16, wherein the at least one integrated power management unit of the IC further includes a second unit adjacent to the first unit, the second unit being a 4-height unit, the second unit including a first row, a second row, a third row, and a fourth row, wherein a first continuous n-well extends in the first direction across portions of the first unit and the first row and the second row of the second unit between the edge of the first unit and the edge of the second unit; a first power interconnect extends in the first direction along the edges of both the first unit and the first row and the second row of the second unit; a second continuous n-well extends in the first direction across portions of the first unit and the third row and the fourth row of the second unit between the edge of the first unit and the edge of the second unit; and a second power interconnect extends in the first direction along the edges of both the first unit and the third row and the fourth row of the second unit.

[0095] Aspect 18 is at least one integrated power management unit of an IC according to aspect 17, wherein the second unit further includes a first subset of a second voltage level shifter in one of the first or second rows of the second unit, the first subset of the second voltage level shifter being associated with the first voltage domain and coupled to the first power interconnect; and a second subset of the second voltage level shifter in one of the third or fourth rows of the second unit, the second subset of the second voltage level shifter being associated with the second voltage domain and coupled to the second power interconnect.

[0096] Aspect 19 is at least one integrated power management unit of an IC according to any one of Aspects 1 to 16, wherein the at least one integrated power management unit of the IC further includes a plurality of units adjacent to the first unit, each of the plurality of units being a 4-height unit, the plurality of units including a first row, a second row, a third row, and a fourth row, the first unit and the plurality of units being a unit set, wherein a first consecutive n-well extends in a first direction across portions of the first row and the second row of the unit set between the edges of the unit set; a first power interconnect extends in the first direction along the edges of both the first row and the second row of the unit set; a second consecutive n-well extends in the first direction across portions of the third row and the fourth row of the unit set between the edges of the unit set; a second power interconnect extends in the first direction along the edges of both the third row and the fourth row of the unit set; wherein each of the plurality of units includes a voltage level shifter.

Claims

1. At least one integrated power management unit of an integrated circuit (IC), the at least one integrated power management unit of the integrated circuit (IC) comprising: The first unit is a 4-height unit, comprising a first row, a second row, a third row, and a fourth row. The first unit includes: A first continuous n-type well (n-well) extends in a first direction across portions of the first row and the second row of the first cell to the edge of the first cell; A first power interconnect extends in the first direction along the edges of both the first row and the second row of the first cell, the first power interconnect being coupled to a first voltage source associated with a first voltage domain and coupled to the first consecutive n-wells; The second continuous n-well extends in the first direction across portions of the third and fourth rows of the first cell to the edge of the first cell; The second power interconnect extends in the first direction along the edges of both the third and fourth rows of the first cell, and the second power interconnect is coupled to a second voltage source associated with a second voltage domain and coupled to the second consecutive n-well. A first subset of the first voltage level shifter, the first subset of the first voltage level shifter being in one of the first row or the second row of the first cell, the first subset of the first voltage level shifter being associated with the first voltage domain and coupled to the first power interconnect; and A second subset of the first voltage level shifter, which is located in one of the third or fourth rows of the first unit, is associated with the second voltage domain and coupled to the second power interconnect.

2. At least one integrated power management unit of the IC according to claim 1, wherein the first unit further comprises: A first clamping sub-unit associated with the first voltage domain in one of the first row or the second row of the first unit, the first clamping sub-unit being coupled to the first power interconnect, wherein the first subset of the first voltage level shifter is in the other of the first row or the second row of the first unit; and A second clamping subunit associated with the second voltage domain in one of the third or fourth rows of the first unit, the second clamping subunit being coupled to the second power interconnect, wherein the second subset of the first voltage level shifter is in the other of the third or fourth rows of the first unit.

3. At least one integrated power management unit of the IC according to claim 1, wherein the first voltage source is an input voltage drain-to-drain (VDD) voltage source, and the second voltage source is an output VDD voltage source.

4. At least one integrated power management unit of the IC according to claim 2, wherein the first unit further comprises: A third power interconnect extends along the edge of the first row of the first cell in the first direction, and the third power interconnect is coupled to a third voltage source; A fourth power interconnect extends in the first direction along the edges of both the second and third rows of the first cell, and the fourth power interconnect is coupled to the third voltage source; and A fifth power interconnect, extending along the edge of the fourth row of the first cell in the first direction, is coupled to the third voltage source. The first clamping subunit is coupled to one of the third power interconnect or the fourth power interconnect, and the first subset of the first voltage level shifter is coupled to the other of the third power interconnect or the fourth power interconnect. The second clamping subunit is coupled to one of the fourth power interconnect or the fifth power interconnect, and the second subset of the first voltage level shifter is coupled to the other of the fourth power interconnect or the fifth power interconnect.

5. At least one integrated power management unit of the IC according to claim 4, wherein the third voltage source is a voltage source powered (VSS) voltage source.

6. At least one integrated power management unit of the IC according to claim 4, wherein the first unit further comprises: A logic sub-unit associated with the first voltage domain, the logic sub-unit being adjacent to the first clamping sub-unit in one of the first row or the second row of the first unit, the logic sub-unit being coupled to the first power interconnect and one of the third power interconnect or the fourth power interconnect.

7. At least one integrated power management unit of the IC according to claim 4, wherein the second clamping subunit is a normally open subunit.

8. At least one integrated power management unit of the IC according to claim 4, wherein the first unit further comprises: A normally open sub-cell associated with the second voltage domain, the normally open sub-cell being adjacent to the second clamping sub-cell in one of the third or fourth rows of the first cell, the normally open sub-cell being coupled to the second power interconnect and one of the fourth or fifth power interconnect.

9. At least one integrated power management unit of the IC according to claim 4, wherein: The first clamping subunit is located in the first row of the first unit, and the first clamping subunit is coupled to the third power interconnect. The first subset of the first voltage level shifter is located in the second row of the first cell, and the first subset of the first voltage level shifter is coupled to the fourth power interconnect. The second clamping subunit is located in the third row of the first unit, and the second clamping subunit is coupled to the fourth power interconnect; and The second subset of the first voltage level shifter is located in the fourth row of the first unit, and the second subset of the first voltage level shifter is coupled to the fifth power interconnect.

10. At least one integrated power management unit of the IC according to claim 9, wherein the first unit further comprises: A logic sub-unit associated with the first voltage domain, the logic sub-unit being adjacent to the first clamping sub-unit in the first row of the first unit, the logic sub-unit being coupled to the first power interconnect and the third power interconnect; and A normally open sub-cell associated with the second voltage domain, the normally open sub-cell being adjacent to the second clamping sub-cell in the third row of the first cell, the normally open sub-cell being coupled to the second power interconnect and the fourth power interconnect.

11. At least one integrated power management unit of the IC according to claim 4, wherein: The first subset of the first voltage level shifter is in the first row of the first cell, and the first subset of the first voltage level shifter is coupled to the third power interconnect. The first clamping subunit is located in the second row of the first unit, and the first clamping subunit is coupled to the fourth power interconnect. The second clamping subunit is located in the third row of the first unit, and the second clamping subunit is coupled to the fourth power interconnect; and The second subset of the first voltage level shifter is located in the fourth row of the first unit, and the second subset of the first voltage level shifter is coupled to the fifth power interconnect.

12. At least one integrated power management unit of the IC according to claim 11, wherein the first unit further comprises: A logic sub-unit associated with the first voltage domain, the logic sub-unit being adjacent to the first clamping sub-unit in the second row of the first unit, the logic sub-unit being coupled to the first power interconnect and the fourth power interconnect; and A normally open sub-cell associated with the second voltage domain, the normally open sub-cell being adjacent to the second clamping sub-cell in the third row of the first cell, the normally open sub-cell being coupled to the second power interconnect and the fourth power interconnect.

13. At least one integrated power management unit of the IC according to claim 4, wherein: The first clamping subunit is located in the first row of the first unit, and the first clamping subunit is coupled to the third power interconnect. The first subset of the first voltage level shifter is located in the second row of the first cell, and the first subset of the first voltage level shifter is coupled to the fourth power interconnect. The second subset of the first voltage level shifter is located in the third row of the first unit, and the second subset of the first voltage level shifter is coupled to the fourth power interconnect. and The second clamping subunit is located in the fourth row of the first unit, and the second clamping subunit is coupled to the fifth power interconnect.

14. At least one integrated power management unit of the IC according to claim 13, wherein the first unit further comprises: A logic sub-unit associated with the first voltage domain, the logic sub-unit being adjacent to the first clamping sub-unit in the first row of the first unit, the logic sub-unit being coupled to the first power interconnect and the third power interconnect; and A normally open sub-cell associated with the second voltage domain, the normally open sub-cell being adjacent to the second clamping sub-cell in the fourth row of the first cell, the normally open sub-cell being coupled to the second power interconnect and the fifth power interconnect.

15. At least one integrated power management unit of the IC according to claim 4, wherein: The first subset of the first voltage level shifter is in the first row of the first cell, and the first subset of the first voltage level shifter is coupled to the third power interconnect. The first clamping subunit is located in the second row of the first unit, and the first clamping subunit is coupled to the fourth power interconnect. The second subset of the first voltage level shifter is located in the third row of the first unit, and the second subset of the first voltage level shifter is coupled to the fourth power interconnect. and The second clamping subunit is located in the fourth row of the first unit, and the second clamping subunit is coupled to the fifth power interconnect.

16. At least one integrated power management unit of the IC according to claim 15, wherein the first unit further comprises: A logic sub-unit associated with the first voltage domain, the logic sub-unit being adjacent to the first clamping sub-unit in the second row of the first unit, the logic sub-unit being coupled to the first power interconnect and the fourth power interconnect; and A normally open sub-cell associated with the second voltage domain, the normally open sub-cell being adjacent to the second clamping sub-cell in the fourth row of the first cell, the normally open sub-cell being coupled to the second power interconnect and the fifth power interconnect.

17. At least one integrated power management unit of the IC according to claim 1, wherein the at least one integrated power management unit of the IC further comprises: The second unit, adjacent to the first unit, is a 4-height unit and includes the first row, the second row, the third row, and the fourth row, wherein: The first consecutive n-well extends in the first direction across portions of the first and second rows of the first and second cells between the edges of the first and second cells; The first power interconnect extends in the first direction along the edges of both the first row and the second row of the first unit and the second unit; The second consecutive n-well extends in the first direction across portions of the third and fourth rows of the first and second cells between the edge of the first cell and the edge of the second cell; The second power interconnect extends in the first direction along the edges of both the third and fourth rows of the first and second units.

18. At least one integrated power management unit of the IC according to claim 17, wherein the second unit further comprises: A first subset of the second voltage level shifter, the first subset of the second voltage level shifter being in one of the first row or the second row of the second cell, the first subset of the second voltage level shifter being associated with the first voltage domain and coupled to the first power interconnect; and A second subset of the second voltage level shifter, which is located in one of the third or fourth rows of the second unit, is associated with the second voltage domain and coupled to the second power interconnect.

19. At least one integrated power management unit of the IC according to claim 1, wherein the at least one integrated power management unit of the IC further comprises: Multiple units adjacent to the first unit, each of which is a 4-height unit, including the first row, the second row, the third row, and the fourth row, wherein the first unit and the multiple units form a unit set: The first consecutive n-well extends in the first direction across portions of the first row and the second row of the cell set between the edges of the cell set; The first power interconnect extends in the first direction along the edges of both the first row and the second row of the cell assembly; The second consecutive n-well extends in the first direction across portions of the third and fourth rows of the cell set between the edges of the cell set; The second power interconnect extends in the first direction along the edges of both the third and fourth rows of the cell assembly; Each of the plurality of units includes a voltage level shifter.

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