Integrated power management unit for gate all-around technology

By employing an integrated power management unit in GAA technology and utilizing a vertically stacked design of consecutive n-wells and voltage level shifters, the problems of junction leakage and increased area in GAA technology are solved, achieving a smaller area and more flexible circuit design.

CN122162520APending Publication Date: 2026-06-05QUALCOMM INC
0 Cites 0 Cited by

Patent Information

Application Number
CN202480068665.8
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Priority Date
2023-11-07
Filing Date
2024-10-24
Publication Date
2026-06-05

AI Technical Summary

Technical Problem

Gate all around (GAA) technology has an unwanted parasitic bottom transistor beneath the bottom nanosheet channel, which leads to increased junction leakage. When the n-well is merged, the junction leakage is severe, affecting transistor performance. At the same time, separating the n-well increases the transistor footprint.

Method used

It employs an integrated power management unit, including a 4-height cell structure, utilizing consecutive n-wells and power interconnects, combined with voltage level shifters, and through a vertically stacked voltage domain design, allows for the merging of n-wells without significantly increasing leakage current and reducing transistor footprint.

Benefits of technology

Without increasing leakage current, the footprint of GAA transistors is reduced, providing greater design flexibility and versatility for integrated circuit layouts of multi-bit voltage level shifters.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

At least one integrated power management unit (702) of the IC (700) comprises a first unit (700), the first unit (700) being a 4 height unit, the first cell includes a first continuous n-well (704), a first power interconnect (792) coupled to a first voltage source (Vdd1) associated with a first voltage domain and the first continuous n-well (704), a second continuous n-well (706), a second power interconnect (796) coupled to a second voltage source (Vdd2) associated with a second voltage domain and the second continuous n-well (706), a first subset (710a) of first voltage level shifters (710) associated with the first voltage domain and coupled to the first power interconnect, and a second subset (710b) of first voltage level shifters (710) associated with the second voltage domain and coupled to the second power interconnect.
Need to check novelty before this filing date? Find Prior Art