A multi-stage variable step adaptive zero-crossing detection circuit
By using a multi-stage variable-step adaptive zero-crossing detection circuit, the step value and offset regulation are dynamically adjusted, solving the trade-off problem between convergence speed and steady-state accuracy in high-efficiency switching power supply design. This improves the system's response speed and steady-state performance, while reducing energy loss and EMI interference.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2026-03-27
- Publication Date
- 2026-06-09
AI Technical Summary
Existing adaptive detection circuits in high-efficiency switching power supply design face challenges in balancing convergence speed and steady-state accuracy, as well as poor adaptability to operating conditions and insufficient anti-interference capabilities, resulting in low efficiency and severe EMI interference.
A multi-stage variable-step adaptive zero-crossing detection circuit is adopted. Through a time-domain quantization sampling array and a state logic discrimination and locking module, the step value and offset adjustment are dynamically adjusted to achieve fast convergence and steady-state locking, thereby enhancing anti-interference capability.
It achieves a balance between fast response and steady-state accuracy, reduces energy loss, improves EMI performance, and enhances system robustness and adaptability.
Smart Images
Figure CN122171872A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit design, specifically relating to a multi-stage variable step adaptive zero-crossing detection circuit. Background Technology
[0002] In high-efficiency switching power supply design, to improve energy conversion efficiency under light loads, the converter typically operates in discontinuous conduction mode (DCM). Ideally, in DCM mode, the low-side power transistor turns off precisely the instant the inductor current decreases to zero. Deviating from this ideal point will have the following significant negative impacts:
[0003] If the low-side power transistor turns off prematurely before the inductor current drops to zero, the system will enter the "body diode freewheeling phase". The forward voltage drop of the body diode is usually much higher than the voltage drop when the power transistor is on. This surge in voltage drop will lead to severe conduction losses and directly reduce the converter's conversion efficiency.
[0004] If the low-side power transistor remains on after the inductor current drops to zero, a "current backflow" phenomenon will occur in the system, meaning that energy flows back to ground from the output capacitor through the inductor. This means that the energy already transferred to the output is drawn back and wasted on the loop resistance, resulting in a significant decrease in efficiency.
[0005] Increased Electromagnetic Interference (EMI): When the low-side power transistor suddenly turns off under conditions of large reverse current, the parasitic inductance and capacitance of the switching node (SW) undergo violent energy exchange, generating high-frequency ringing noise. This high-frequency interference not only increases the difficulty of zero-crossing determination but also affects surrounding electronic equipment through conduction and radiation, increasing the design complexity of EMI filters.
[0006] Existing adaptive detection circuits have the following significant drawbacks in practical industrial applications:
[0007] The trade-off between convergence speed and steady-state accuracy: Traditional adaptive circuits typically use a fixed calibration step. If the step current is set too large, although it can quickly pull back the deviated turn-off point during startup or load transients, it will cause the control potential to fluctuate wildly around the equilibrium point after entering steady state, resulting in deterioration of the output ripple. If the step current is set too small, although the steady-state performance is improved, the system's convergence speed is extremely slow, making it impossible to track changes in operating conditions in real time.
[0008] Poor adaptability to operating conditions: Existing adaptive zero-crossing detection circuits often exhibit 'static operating condition dependence'. Even if the system completes adaptive adjustment and reaches steady state under a specific operating condition (such as a specific input voltage, output voltage, and load current), when the operating condition changes abruptly or drifts slowly (e.g., output voltage fluctuations caused by load transients, or on-resistance drift of the power transistor due to temperature changes), the originally 'adjusted' adaptive threshold or control voltage will no longer correspond to the current ideal zero-crossing point.
[0009] Insufficient anti-interference capability: The switching noise and ringing signal generated when the power transistor is turned off can easily cause the sampling trigger to produce an illegal logic state. Traditional simple logic judgment circuits cannot identify and filter such interference, which can easily lead to erroneous actions in the control loop.
[0010] Therefore, developing an intelligent multi-stage zero-crossing detection circuit that can achieve both fast convergence and steady-state locking, as well as adaptive output voltage changes, has become an urgent technical problem to be solved in the field of power management chips. Summary of the Invention
[0011] This invention provides a multi-stage variable-step adaptive zero-crossing detection circuit, aiming to solve the following technical problems:
[0012] The contradiction caused by the single adjustment step size: the existing technology uses fixed step calibration, which cannot balance the transient response speed (convergence time) and the steady-state turn-off accuracy (inductor current when turned off).
[0013] Lack of steady-state dead-zone control: Traditional feedback loops continuously fine-tune around the ideal point, causing the control voltage to generate limit loop oscillations in steady state, which deteriorates the output ripple and EMI performance;
[0014] Drift caused by output voltage variation: Since the zero-crossing slope of the inductor current is affected by the output voltage, the fixed-duration sampling window cannot maintain consistent detection accuracy under all operating conditions;
[0015] Logic misjudgment under noise interference: Parasitic ringing of switching nodes can easily induce logic malfunctions.
[0016] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:
[0017] A multi-stage variable-step adaptive zero-crossing detection circuit includes:
[0018] A time-domain quantization sampling array, comprising at least three cascaded delay units for generating at least three sequentially delayed sampling times; a trigger is set at the output of each delay unit, and when the trigger is triggered, the characteristic signal of the switch node (SW) is time-domain quantized and sampled to output a multi-bit hot code logic value reflecting the zero-crossing position of the current;
[0019] The state logic discrimination and locking module obtains the state corresponding to the input hot code logic value from a preset correspondence table between hot code logic values and states; then, it adjusts the step value according to the state, accumulates the adjustment step value with the current digital control word, and outputs the updated digital control word.
[0020] The zero-crossing detection comparator module is connected to the output of the state logic discrimination and locking module. The resistance value of the offset adjustment R_DAC module inside the zero-crossing detection comparator module is adjusted according to the output digital control word, thereby adjusting the electrical symmetry of the comparator input stage and thus accurately controlling the offset voltage of the comparator.
[0021] Furthermore, the time-domain quantization sampling method includes:
[0022] Method 1: Delay the zero-crossing detection output (ZCD_OUT) sequentially by using at least 3 cascaded delay units, detect the rising edge of the switch node (SW) by using the rising edge detection module, and collect multiple delayed zero-crossing detection outputs at the rising edge of the switch node (SW) to obtain a multi-bit hot code logic value.
[0023] Method 2: Delay the zero-crossing detection output (ZCD_OUT) sequentially using at least three cascaded delay units. Sample the switch node (SW) characteristic signal at the rising edge of each delayed ZCD_OUT to obtain the logic value. Use a comparator to determine whether the switch node (SW) characteristic signal value (voltage value) is greater than GND (ground). If it is greater than GND, obtain the logic value 1; otherwise, obtain the logic value 0.
[0024] Furthermore, the states include near-ideal state, slightly deviating from ideal state, severely deviating from ideal state, and current backflow.
[0025] Furthermore, the state logic discrimination and locking module adjusts the step value according to the state setting, specifically including the following situations:
[0026] Target range (dead zone locking mode): When the current state is close to the ideal state according to the hot code logic value, the step value is set to 0, the current digital control word remains unchanged, and the step update is stopped to eliminate steady-state limit cycle oscillation.
[0027] Fine-tuning range (small step mode): When the current state is slightly deviated from the ideal state according to the hot code logic value, the step value is set to a small step 'a', and small step adjustment is performed to prevent steady-state overshoot;
[0028] Coarse adjustment interval (large step mode): When the current state is determined to be seriously deviating from the ideal state based on the hot code logic value, the step value is set to a large step b, where the large step b ≥ 2 times the small step a (b ≥ 2a), and large step adjustment is performed to achieve rapid convergence of the system loop;
[0029] Backoff interval (high-gain anti-backflow mode): When the current state is determined to be in a current backflow state based on the hot code logic value, the step value is set to -b to force the system to quickly get out of the backflow state and minimize energy loss.
[0030] Furthermore, the zero-crossing detection comparator module compares the switch node (SW) characteristic signal with GND (ground) to obtain the zero-crossing detection output (ZCD_OUT), which serves as the input to the first delay unit.
[0031] Furthermore, the offset adjustment R_DAC module is a digitally controlled resistor-to-analog converter network (R_DAC), whose equivalent resistance value changes linearly or non-linearly with the size of the input digital control word.
[0032] Furthermore, by narrowing the time difference between time-domain quantization sampling moments, the detection offset caused by the steepening slope of the inductor current due to the rise in the output voltage of the switching power supply is offset, so that the time-domain quantization detection error of the inductor current remains constant under different output voltage conditions.
[0033] Furthermore, a logic validity verification module can be set up in the state logic discrimination and locking module to prevent false state judgments. The validity verification module performs the following operations:
[0034] The input hot code logic value is verified. If an illegal logic value other than the hot code rule is detected, it is determined to be switch noise interference, and the step value "0" is output, while the current digital control word remains unchanged.
[0035] When a sudden jump in the input hot code logic value to a non-adjacent state is detected, the output step value is "0", and the current digital control word remains unchanged. The state logic discrimination and locking module works normally only when the same jump occurs multiple times (≥3 times), thereby effectively filtering out transient disturbances and significantly improving the robustness of steady-state control.
[0036] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0037] Achieving both dynamic response and steady-state quality: By distinguishing multiple states through time-domain quantization and making corresponding adjustments according to different states, a control strategy of "running fast when turning off too early, moving slowly when turning off too late, and locking in place when turning off in time" is realized. This significantly shortens the loop convergence time while also taking into account the accuracy in steady state, making the inductor current closer to 0.
[0038] Establishing a steady-state lockout dead zone: Introducing dead zone discrimination logic enables the system to stop unnecessary feedback operations after entering the ideal state, which greatly smooths the control voltage, reduces output voltage ripple, and improves the system's EMI performance.
[0039] Asymmetric protection mechanism: Since the energy loss due to current backflow is the highest among all situations, a large step-by-step rapid correction is activated when current backflow is detected to avoid a large amount of energy loss.
[0040] Error detection shielding: It does not execute the function for any cases other than hot code values, and it also checks whether the status changes continuously to filter out error triggers.
[0041] High versatility: The multi-level control strategy proposed in this invention can be widely adapted to various zero-crossing detection architectures and has great industrial application value. Attached Figure Description
[0042] Figure 1 This is a schematic diagram of time-domain quantization sampling method 1;
[0043] Figure 2 This is a schematic diagram of time-domain quantization sampling method 2;
[0044] Figure 3 The circuit diagram for multi-stage step adaptive zero-crossing detection using time-domain quantization sampling method 1 is shown.
[0045] Figure 4 This is a circuit diagram for a multi-stage step adaptive zero-crossing detection circuit using time-domain quantization sampling method 2. Detailed Implementation
[0046] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.
[0047] A multi-stage variable-step adaptive zero-crossing detection circuit includes:
[0048] 1. Time-domain quantization sampling array:
[0049] The time-domain quantization sampling array includes at least three cascaded delay units to generate at least three sequentially delayed sampling times; a trigger is set at the output of each delay unit, and when the trigger is triggered, the characteristic signal of the switch node (SW) is sampled in the time domain and a multi-bit hot code logic value reflecting the position of the current zero crossing is output.
[0050] Temporal quantization sampling methods include:
[0051] Method 1: Delay the zero-crossing detection output (ZCD_OUT) sequentially by using at least 3 cascaded delay units, detect the rising edge of the switch node (SW) by using the rising edge detection module, and collect multiple delayed zero-crossing detection outputs at the rising edge of the switch node (SW) to obtain a multi-bit hot code logic value.
[0052] like Figure 1 As shown in the figure, the four dashed lines of ZCD_OUT are generated by ZCD_OUT after four sequential delays. At the rising edge of the switch node (SW), the four zero-crossing detection outputs (ZCD_OUT) after the current time delay are collected by the flip-flop, and then the logic values of ZCD_OUT at four different times can be obtained.
[0053] Figure 1 The four situations shown are: (1) The figure is close to the ideal state, and the four-bit logic signal is “1000”; (2) The figure is slightly deviated from the ideal state, and the four-bit logic signal is “1100”; (3) The figure is seriously deviated from the ideal state, and the four-bit logic signal is “1111”; (4) The figure is current backflow, and the four-bit logic signal is “0000”.
[0054] Method 2: Delay the zero-crossing detection output (ZCD_OUT) sequentially using at least three cascaded delay units. Sample the switch node (SW) characteristic signal at the rising edge of each delayed ZCD_OUT to obtain the logic value. Use a comparator to determine whether the switch node (SW) characteristic signal value (voltage value) is greater than GND (ground). If it is greater than GND, obtain the logic value 1; otherwise, obtain the logic value 0.
[0055] like Figure 2 As shown in the figure, the four dashed lines of ZCD_OUT are generated by ZCD_OUT after four sequential delays. The voltage value of SW signal is collected at their rising edge and it is determined whether it is greater than GND (ground). If it is greater than GND, the logic value is 1; otherwise, the logic value is 0.
[0056] Figure 2 The four situations shown are: (1) The figure is close to the ideal state, and the four-bit logic signal collected is “0111”; (2) The figure is slightly deviated from the ideal state, and the four-bit logic signal collected is “0011”; (3) The figure is seriously deviated from the ideal state, and the four-bit logic signal collected is “0000”; (4) The figure is the case of current backflow, and the four-bit logic signal collected is “1111”.
[0057] 2. State logic judgment and locking module:
[0058] It is connected to the output of the time-domain quantization sampling array and is used to receive the multi-bit hot code logic value output by the time-domain quantization sampling array.
[0059] The state logic discrimination and locking module obtains the state corresponding to the input hot code logic value from the preset correspondence table between hot code logic values and states based on the input hot code logic value; then, it adjusts the step value according to the state setting, accumulates the adjustment step value with the current digital control word, and outputs the updated digital control word (such as Q[6:0]).
[0060] The states include near-ideal state, slightly deviating from ideal state, severely deviating from ideal state, and current backflow.
[0061] The adjustment of the step value based on the status setting includes the following specific situations:
[0062] Target range (dead zone locking mode): When the current state is close to the ideal state according to the hot code logic value, the step value is set to 0, the current digital control word remains unchanged, and the step update is stopped to eliminate steady-state limit cycle oscillation.
[0063] Fine-tuning range (small step mode): When the current state is slightly deviated from the ideal state according to the hot code logic value, the step value is set to a small step 'a', and small step adjustment is performed to prevent steady-state overshoot;
[0064] Coarse adjustment interval (large step mode): When the current state is determined to be seriously deviating from the ideal state based on the hot code logic value, the step value is set to a large step b, where the large step b ≥ 2 times the small step a (b ≥ 2a), and large step adjustment is performed to achieve rapid convergence of the system loop;
[0065] Backoff interval (high-gain anti-backflow mode): When the current state is determined to be in a current backflow state based on the hot code logic value, the step value is set to -b to force the system to quickly get out of the backflow state and minimize energy loss.
[0066] 3. Zero-crossing detection comparator module:
[0067] The characteristic signal of the switching node (SW) is compared with GND (ground) to obtain the zero-crossing detection output (ZCD_OUT), which serves as the input to the first delay unit. The zero-crossing detection comparator module is connected to the output of the state logic discrimination and locking module. Based on the output digital control word, the resistance value of the offset adjustment R_DAC module inside the zero-crossing detection comparator module is adjusted, thereby adjusting the electrical symmetry of the comparator input stage and thus precisely controlling the comparator's offset voltage. The system closed loop continuously adjusts this offset voltage, gradually bringing the comparator's actual switching point closer to and eventually locking it at a near-ideal inductor current zero-crossing point.
[0068] The offset adjustment R_DAC module is a digitally controlled resistor-to-analog converter (R_DAC), whose equivalent resistance changes linearly or non-linearly with the size of the input digital control word.
[0069] Furthermore, by narrowing the time difference between time-domain quantization sampling moments, the detection offset caused by the steepening slope of the inductor current due to the rise in the output voltage of the switching power supply is offset, so that the time-domain quantization detection error of the inductor current remains constant under different output voltage conditions.
[0070] Furthermore, a logic validity verification module can be set up in the state logic discrimination and locking module to prevent false state judgments. The validity verification module performs the following operations:
[0071] The input hot code logic value is verified. If an illegal logic value other than the hot code rule is detected, it is determined to be switch noise interference, and the step value "0" is output, while the current digital control word remains unchanged.
[0072] When a sudden jump in the input hot code logic value to a non-adjacent state is detected, the output step value is "0", and the current digital control word remains unchanged. The state logic discrimination and locking module works normally only when the same jump occurs multiple times (≥3 times), thereby effectively filtering out transient disturbances and significantly improving the robustness of steady-state control.
[0073] Example
[0074] The example uses a synchronous rectified Buck converter operating in discontinuous conduction mode (DCM) or burst mode.
[0075] like Figure 3 As shown, for time-domain quantization sampling method 1, the connection relationship of this multi-stage variable-step adaptive zero-crossing detection circuit is as follows: switching node voltage The rising edge detection module performs rising edge detection to obtain... The signal is delayed four times using four delay units to obtain ZCD_OUT_d1, ZCD_OUT_d2, ZCD_OUT_d3, and ZCD_OUT_d4; The signal serves as the clock signal for the four D flip-flops. ZCD_OUT_d1, ZCD_OUT_d2, ZCD_OUT_d3, and ZCD_OUT_d4 are used as the D inputs of the four flip-flops, resulting in the outputs Q0, Q1, Q2, and Q3, which are then transmitted to the state logic discrimination and locking module. The logic discrimination and locking module generates an updated digital control word (such as Q[6:0]) to control the resistance value of the R_DAC module. The resistance value of the R_DAC module affects the symmetry of the input stage of the ZCD comparator unit, thereby changing the offset voltage detected by the ZCD to adjust the system to the ideal state.
[0076] like Figure 4 As shown, for time-domain quantization sampling method 2, the connection relationship of the multi-stage variable-step adaptive zero-crossing detection circuit is as follows: The output ZCD_OUT signal generated by the ZCD module is delayed four times using four delay units to obtain ZCD_OUT_d1, ZCD_OUT_d2, ZCD_OUT_d3, and ZCD_OUT_d4; rising edge detection is performed on these four signals, which are then used as the clock signals for the four D flip-flops. Switch node voltage. After processing by the comparator COMP module, the outputs of the four flip-flops, Q0, Q1, Q2, and Q3, are sent to the state logic discrimination and locking module. The logic discrimination and locking module generates an updated digital control word (such as Q[6:0]) to control the resistance value of the R_DAC module. The resistance value of the R_DAC module affects the symmetry of the input stage of the ZCD comparator unit, thereby changing the offset voltage detected by the ZCD to adjust the system to the ideal state.
[0077] Based on the logic values of the above circuit, the following logical method for state logic judgment is given:
[0078] Current collected logical value The last updated logical value was 1111. The last updated logical value was 0111 The last updated logical value was 0011 The last updated logical value was 0001 The last updated logical value was 0000 1111 Output value -4 Output value -4 Keep Keep Keep 0111 Keep Keep Keep Keep Keep 0011 Keep Output value +1 Output value +1 Output value +1 Keep 0001 Keep Keep Output value +2 Output value +2 Output value +2 0000 Keep Keep Keep Keep Output value +8
Claims
1. A multi-stage variable-step adaptive zero-crossing detection circuit, characterized in that, include: A time-domain quantization sampling array, comprising at least three cascaded delay units for generating at least three sequentially delayed sampling times; a trigger is set at the output of each delay unit, and when the trigger is triggered, the characteristic signal of the switching node is sampled in the time domain and a hot code logic value is output. The state logic discrimination and locking module obtains the state corresponding to the input hot code logic value from a preset correspondence table between hot code logic values and states; then, it sets a step value according to the state, accumulates the step value with the current digital control word, and outputs the updated digital control word. The zero-crossing detection comparator module is connected to the output of the state logic discrimination and locking module. The resistance value of the offset adjustment R_DAC module inside the zero-crossing detection comparator module is adjusted according to the output digital control word, thereby adjusting the electrical symmetry of the comparator input stage.
2. The multi-stage variable-step adaptive zero-crossing detection circuit according to claim 1, characterized in that, The time-domain quantization sampling is accomplished through one of the following methods: Method 1: Delay the zero-crossing detection output sequentially by using at least 3 cascaded delay units, detect the rising edge of the switch node according to the rising edge detection module, and collect multiple delayed zero-crossing detection outputs at the rising edge of the switch node to obtain the hot code logic value. Method 2: Delay the zero-crossing detection output sequentially by using at least 3 cascaded delay units, and sample the switch node characteristic signal at the rising edge of each delayed zero-crossing detection output to obtain the hot code logic value.
3. The multi-stage variable-step adaptive zero-crossing detection circuit according to claim 2, characterized in that, In Method 2, it is determined whether the characteristic signal value of the switch node is greater than GND. If it is greater than GND, the logic value is 1; otherwise, the logic value is 0.
4. The multi-stage variable-step adaptive zero-crossing detection circuit according to claim 1, characterized in that, The states include near-ideal state, slightly deviating from ideal state, severely deviating from ideal state, and current backflow.
5. The multi-stage variable-step adaptive zero-crossing detection circuit according to claim 1, characterized in that, The state logic discrimination and locking module sets the step value according to the state: When the current state is determined to be close to the ideal state based on the hot code logic value, the step value is set to 0, and the current digital control word remains unchanged. When the current state is determined to be slightly deviating from the ideal state based on the hot code logic value, the step value is set to a small step 'a'. When the current state is determined to be seriously deviating from the ideal state based on the hot code logic value, the step value is set to a large step b, and b≥2a; When the current state is determined to be in a current reverse flow state based on the hot code logic value, the step value is set to -b.
6. The multi-stage variable-step adaptive zero-crossing detection circuit according to claim 1, characterized in that, The zero-crossing detection comparator module compares the switch node characteristic signal with GND to obtain the zero-crossing detection output, which serves as the input to the first delay unit.
7. The multi-stage variable-step adaptive zero-crossing detection circuit according to claim 1, characterized in that, The offset adjustment R_DAC module is a digitally controlled resistor-to-analog converter network, and its equivalent resistance value changes linearly or non-linearly with the size of the input digital control word.
8. The multi-stage variable-step adaptive zero-crossing detection circuit according to claim 1, characterized in that, By shrinking the time difference between sampling moments in the time domain quantization, the detection offset caused by the steepening slope of the inductor current due to the rise in the output voltage of the switching power supply is offset.
9. The multi-stage variable-step adaptive zero-crossing detection circuit according to claim 1, characterized in that, A logic validity verification module is set up in the state logic discrimination and locking module to prevent false judgments of the state.
10. The multi-stage variable-step adaptive zero-crossing detection circuit according to claim 9, characterized in that, The validity verification module performs the following operations: The input hot code logic value is verified. If an illegal logic value other than the hot code rule is detected, it is determined to be switch noise interference, and the step value "0" is output, while the current digital control word remains unchanged. When a sudden jump in the input hot code logic value to a non-adjacent state is detected, the output step value is "0", and the current digital control word remains unchanged; When the same sudden jump occurs multiple times, the state logic judgment and locking module works normally, effectively filtering out transient disturbances.