Aging prediction method and device, computer device and storage medium
By acquiring multi-dimensional operational data of microprocessor chips and training them using deep neural network models, the problem of low efficiency in existing aging prediction methods is solved, achieving more efficient and accurate aging state quantification, especially considering the cumulative effect of aging and chip process deviations.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHANGSHA AVIATION VOCATIONAL & TECH COLLEGE (AIR FORCE AVIATION MAINTENANCE TECH COLLEGE)
- Filing Date
- 2026-02-07
- Publication Date
- 2026-06-09
AI Technical Summary
Existing microprocessor aging prediction methods are inefficient or have low accuracy, and fail to effectively consider the cumulative effect of aging.
By acquiring multi-dimensional operational data of the microprocessor chip's computing unit, including the cumulative values of temperature, voltage, path input signal probability, and flip rate, and training it using a deep neural network model, a second neural network model is generated to output the path delay increment caused by aging effects.
It improves the efficiency and accuracy of aging prediction, can accurately quantify the aging state of computing units, solves the prediction bias caused by missing data dimensions, and takes into account chip process deviations, thus improving the reliability of prediction.
Smart Images
Figure CN122173375A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit technology, and in particular to an aging prediction method, apparatus, computer equipment, aging prediction system, and storage medium. Background Technology
[0002] Microprocessors are core components of modern information technology, possessing powerful computing capabilities and are indispensable parts of electronic devices. During use, microprocessors inevitably experience aging due to phenomena such as electron migration and time-related breakdown. To prevent malfunctions caused by microprocessor aging from damaging equipment, it is necessary to detect the degree of aging. The primary method for microprocessor detection is by monitoring the processor's output voltage.
[0003] However, traditional aging prediction methods suffer from problems such as low efficiency or low accuracy. Summary of the Invention
[0004] Therefore, it is necessary to provide an aging prediction method, apparatus, computer equipment, and storage medium that can improve efficiency and accuracy in addressing the aforementioned technical problems.
[0005] In a first aspect, an aging prediction method is provided, the method comprising: Acquire operational data pairs from the arithmetic units in the microprocessor chip; wherein, the operational data pairs include temperature data pairs, voltage data pairs, path input signal probability data pairs, and path input signal flip rate data pairs; the temperature data pairs include the temperature at a first moment and the cumulative temperature value within a target time period; the voltage data pairs include the voltage at a first moment and the cumulative voltage value within a target time period; the path input signal probability data pairs include the path input signal probability at a first moment and the cumulative path input signal probability value within a target time period; the path input signal flip rate data pairs include the path input signal flip rate at a first moment and the cumulative path input signal flip rate value within a target time period; the target time period is from a second moment to a first moment; the first moment is greater than the second moment; The running data is input into the first neural network model to train the second neural network model, and the path delay increment caused by the aging effect of the output computing unit is based on the second neural network model.
[0006] In this embodiment, the aging prediction method described above acquires the operating data pairs of the computing units in the microprocessor chip. It uses accumulated temperature, accumulated voltage, accumulated path input signal probability, and accumulated path input signal reversal rate to characterize the long-term cumulative effects of different aging factors, enriching the data dimensions used for aging prediction and avoiding prediction bias caused by missing data dimensions. This accurately quantifies the aging state of the computing units. Then, the operating data pairs are input into a first neural network model for training, resulting in a trained second neural network model. This model outputs the path delay increment caused by the aging effect of the computing units, improving the efficiency, reliability, and accuracy of aging prediction.
[0007] In one embodiment, the method further includes obtaining the nanometer-scale manufacturing process of the microprocessor chip; wherein, inputting the running data pair into a first neural network model to train a trained second neural network model includes: inputting the running data pair and the nanometer-scale manufacturing process into the first neural network model to train a second neural network model.
[0008] In this embodiment, the input data considers temperature, voltage, path input signal probability, and path input signal flipping probability at a certain moment, and also takes into account the cumulative effect of aging. Furthermore, it incorporates the process variation effect between chips, resolving the unreliability issues caused by simulation experimental data and further improving the efficiency, reliability, and accuracy of aging prediction.
[0009] In one embodiment, the method further includes: determining the current frequency degradation rate of the microprocessor chip based on the path delay increment; in response to the frequency degradation rate being greater than a preset threshold, determining a target compensation voltage corresponding to the current frequency degradation rate based on the mapping relationship between the current frequency degradation rate and the compensation voltage, so as to control voltage compensation of the microprocessor chip based on the target compensation voltage; wherein the target compensation voltage is the compensation voltage required for the microprocessor chip to recover to its initial frequency state.
[0010] In this embodiment, the current frequency degradation rate of the microprocessor chip is determined based on the path delay increment; then, in response to the frequency degradation rate being greater than a preset threshold, a target compensation voltage corresponding to the current frequency degradation rate is determined based on the mapping relationship between the current frequency degradation rate and the compensation voltage, so as to control the voltage compensation of the microprocessor chip according to the target compensation voltage, thereby improving the performance and frequency of the microprocessor chip.
[0011] In one embodiment, the cumulative path input signal probability value includes the aging assessment value under the negative bias temperature instability (NBTI) mechanism; the cumulative path input signal reversal rate value includes the aging assessment value under the hot carrier injection (HCI) mechanism.
[0012] In this embodiment, the aging evaluation value under the negative bias temperature instability (NBTI) mechanism is used as the main content of the cumulative probability value of the path input signal, and the aging evaluation value under the hot carrier injection (HCI) mechanism is used as the main content of the cumulative reversal rate value of the path input signal. The main characteristics of the NBTI aging machine mechanism are reflected in the running data pair, and the cumulative nature of the aging effect is further reflected in the aging prediction process.
[0013] In one embodiment, the first neural network model is a deep neural network model; the deep neural network model includes N layers of deep neural networks; where N is an integer greater than or equal to 5; each layer of the deep neural network includes a fully connected operation layer, an activation operation layer, and a batch normalization operation layer; the number of neurons included in each layer of the deep neural network is arranged in descending order from the input direction of the deep neural network model to the output direction of the deep neural network model, the output of the previous layer of the deep neural network is the input of the next layer of the deep neural network, and the number of neurons included in the Nth layer of the deep neural network is 1. In this embodiment, the first neural network model is configured as a deep neural network model, which includes N layers of deep neural networks, where N is an integer greater than or equal to 5. Each layer of the deep neural network includes a fully connected layer, an activation layer, and a batch normalization layer. The number of neurons in each layer is arranged in descending order from the input direction to the output direction of the deep neural network model. The output of the previous layer serves as the input to the next layer, and the Nth layer contains only 1 neuron. This configuration allows the first neural network model, after training, to effectively fit the complex nonlinear relationship between the aging effect and multi-dimensional operational data, solving the problem of weak generalization ability in traditional prediction models and improving the accuracy, efficiency, and reliability of aging prediction.
[0014] In one embodiment, the deep neural network is a convolutional neural network; the dropout rate of the deep neural network is 0.2; the dropout rate is used to characterize the deep neural network randomly dropping 20% of the neuron connections during forward propagation.
[0015] In this embodiment, the deep neural network is configured as a convolutional neural network, and the dropout rate of the deep neural network is set to 0.2. By randomly dropping 20% of the neuron connections in the forward propagation of the deep neural network through the dropout rate, the generalization performance of the first neural network model is effectively improved, overfitting is prevented, and the training efficiency of the first neural network model is maintained.
[0016] In one embodiment, the running data is input to train a first neural network model to obtain a trained second neural network model, including: The running data is randomly divided to generate training, validation and test sets; The first neural network model is trained using the training and validation sets, and tested using the test set. The model parameters of the first neural network model are adjusted based on the prediction accuracy values obtained from training and testing, until the prediction accuracy value is greater than a preset threshold, thus generating the second neural network model.
[0017] In this embodiment, the data is randomly divided according to the running data to generate a training set, a validation set, and a test set. Then, the first neural network model is trained according to the training set and the validation set, and the first neural network model is tested according to the test set. The model parameters of the first neural network model are adjusted based on the prediction accuracy value obtained from training and testing until the prediction accuracy value is greater than a preset threshold, and a second neural network model is generated, which improves the efficiency and accuracy of model training.
[0018] Secondly, an aging prediction device is provided, the device including a data acquisition module and a model training module.
[0019] The data acquisition module is used to acquire operational data pairs of the arithmetic units in the microprocessor chip. These operational data pairs include temperature data pairs, voltage data pairs, path input signal probability data pairs, and path input signal flip rate data pairs. The temperature data pairs include the temperature at a first moment and the cumulative temperature value within a target time period. The voltage data pairs include the voltage at a first moment and the cumulative voltage value within a target time period. The path input signal probability data pairs include the path input signal probability at a first moment and the cumulative path input signal probability within a target time period. The path input signal flip rate data pairs include the path input signal flip rate at a first moment and the cumulative path input signal flip rate within a target time period. The target time period is from a second moment to a first moment, and the first moment is greater than the second moment. The model training module is used to input the operational data pairs into a first neural network model for training, obtaining a trained second neural network model, and outputting the path delay increment caused by the aging effect of the arithmetic units based on the second neural network model.
[0020] In this embodiment, the aforementioned aging prediction device acquires operational data pairs from the computing units in the microprocessor chip through a data acquisition module. It characterizes the long-term cumulative effects of different aging factors using accumulated temperature, accumulated voltage, accumulated path input signal probability, and accumulated path input signal reversal rate, enriching the data dimensions used for aging prediction and avoiding prediction bias caused by missing data dimensions, thus accurately quantifying the aging state of the computing units. Then, the operational data pairs are input into a first neural network model through a model training module to train a trained second neural network model. This allows the second neural network model to output the path delay increment caused by the aging effect of the computing units, improving the efficiency, reliability, and accuracy of aging prediction.
[0021] Thirdly, a computer device is provided, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of any of the methods described in the above method embodiments.
[0022] Fourthly, an aging prediction system is provided, comprising any of the computer devices and detection circuits described in the above-described computer device embodiments. The computer device and the detection circuit are electrically connected. The detection circuit is disposed within a microprocessor chip; the detection circuit is used to detect operating data pairs.
[0023] Fifthly, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of any of the methods described in the above method embodiments.
[0024] The aforementioned aging prediction method, apparatus, computer equipment, and storage medium acquire operational data pairs from the computing units in a microprocessor chip. They characterize the long-term cumulative effects of different aging factors through accumulated temperature, accumulated voltage, accumulated path input signal probability, and accumulated path input signal reversal rate, enriching the data dimensions used for aging prediction and avoiding prediction bias caused by missing data dimensions, thus accurately quantifying the aging state of the computing units. Subsequently, the operational data pairs are input into a first neural network model for training, resulting in a trained second neural network model. This model outputs the path delay increment caused by aging effects in the computing units, improving the efficiency, reliability, and accuracy of aging prediction. Attached Figure Description
[0025] Figure 1 This is a diagram illustrating the application environment of the aging prediction method in one embodiment; Figure 2 This is a schematic diagram of the first process of an aging prediction method in one embodiment; Figure 3 This is a schematic diagram of the structure of a deep neural network in one embodiment; Figure 4 This is a schematic diagram of the second process of the aging prediction method in another embodiment; Figure 5 This is a schematic diagram of the third process of the aging prediction method in another embodiment; Figure 6 This is a structural block diagram of an aging prediction device in one embodiment; Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0026] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0027] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0029] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
[0030] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.
[0031] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.
[0032] First, the technical terms used in this application will be explained.
[0033] Aging effects refer to the changes in certain characteristic parameters of hardware circuits in complex System-on-Chips (SoCs) over time due to physical damage during operation. The cumulative effect of this physical damage leads to device failure and ultimately the failure of the entire SoC. In transistors, aging effects mainly include three aspects: hot carrier injection (HCI), negative bias temperature instability (NBTI), and time-dependent dielectric breakdown (TDDB). In metal interconnects, aging effects are primarily characterized by electromigration. In operational circuits composed of logic gates, aging effects manifest primarily as increased circuit delay due to threshold voltage degradation and increased line delay due to increased interconnect resistance.
[0034] From the perspective of the manifestation of circuit aging effects, aging causes physical defects in transistors to accumulate continuously, eventually leading to transistor failure and causing irreversible damage to the entire complex SoC. However, on a real time scale, the physical lifespan of a complex SoC caused by aging is indeed far greater than the functional lifespan due to its product positioning and functional evolution. Aging-induced failure of complex SoCs is almost unobservable on a real time scale. Even in a 2000-hour accelerated life test, the tested circuit only experienced a 10% increase in delay rather than failure.
[0035] The applicant found in their research that existing aging prediction methods mainly focus on the main causes of aging effects, that is, only considering temperature, voltage, path input signal probability, and path input signal flipping probability at a certain moment, without deeply considering the cumulative nature of aging effects. Therefore, there is an urgent need for a new aging prediction method that can better predict the path delay increment caused by aging effects in SoCs.
[0036] This application provides an aging prediction method that can be applied to, for example... Figure 1 The aging prediction system shown includes a computer device 100 and a detection circuit 200. The computer device 100 and the detection circuit 200 are electrically connected. The detection circuit 200 is located within a microprocessor chip and is used to detect operating data pairs.
[0037] In one embodiment, such as Figure 2 As shown, an aging prediction method is provided, which can be applied to... Figure 1 The following steps are used as an example to illustrate the process, which includes steps 201 to 202.
[0038] Step 201: Obtain the operation data pairs of the arithmetic units in the microprocessor chip.
[0039] The operational data pairs include temperature data pairs, voltage data pairs, path input signal probability data pairs, and path input signal reversal rate data pairs. The temperature data pairs include the temperature at the first moment and the cumulative temperature value within the target time period. The voltage data pairs include the voltage at the first moment and the cumulative voltage value within the target time period. The path input signal probability data pairs include the path input signal probability at the first moment and the cumulative path input signal probability value within the target time period. The path input signal reversal rate data pairs include the path input signal reversal rate at the first moment and the cumulative path input signal reversal rate value within the target time period. The target time period is from the second moment to the first moment; the first moment is greater than the second moment. Specifically, the computer device 100 acquires operational data pairs from the arithmetic unit in the microprocessor chip. It uses the cumulative temperature value, cumulative voltage value, cumulative path input signal probability value, and cumulative path input signal reversal rate value to characterize the long-term cumulative impact of different aging factors, enriching the data dimensions used for aging prediction (e.g., changing from 4-dimensional data to 8-dimensional data), avoiding prediction bias caused by missing data dimensions, and accurately quantifying the aging state of the arithmetic unit.
[0040] Understandably, the cumulative temperature value is used to characterize the cumulative aging effect of the arithmetic unit due to temperature. The cumulative voltage value is used to characterize the cumulative aging effect of the arithmetic unit due to voltage. The cumulative path input signal value is used to characterize the cumulative aging effect of the arithmetic unit due to signal probability. The cumulative path input signal flip rate value is used to characterize the cumulative aging effect of the arithmetic unit due to signal flip rate.
[0041] In a specific example, the cumulative temperature value is obtained based on the following expression: in, This is the cumulative temperature value; for t Temperature at any moment;P For the second moment; Q For the first moment.
[0042] The cumulative voltage value is obtained based on the following expression: in, This is the cumulative voltage value; for t Voltage at any given moment; P For the second moment; Q For the first moment.
[0043] The cumulative probability value of the path input signal is obtained based on the following expression: in, The cumulative probability value of the path input signal; for t The probability of the path input signal at time t; P For the second moment; Q For the first moment.
[0044] The cumulative value of the path input signal toggle rate is obtained based on the following expression: in, The cumulative value of the path input signal flip rate; for t The path input signal flip rate at any given time; P For the second moment; Q This is for immediate action. The above is just a specific example; in actual applications, it should be flexibly set according to user needs, and no restrictions are imposed here.
[0045] In this embodiment, the temperature data pair may include the temperature at a first moment and the maximum value of the cumulative temperature value within the target time period; it may also include the temperature at a first moment and the minimum value of the cumulative temperature value within the target time period; or it may include the temperature at a first moment and the average value of the cumulative temperature value within the target time period.
[0046] In the embodiments of this application, the voltage data pair may include the voltage at a first moment and the maximum value of the cumulative voltage value within a target time period; it may also include the voltage at a first moment and the minimum value of the cumulative voltage value within a target time period; or it may include the voltage at a first moment and the average value of the cumulative voltage value within a target time period.
[0047] In this embodiment of the application, the path input signal probability data includes the path input signal probability at the first moment and the maximum value of the cumulative path input signal probability within the target time period; it may also include the path input signal probability at the first moment and the minimum value of the cumulative path input signal probability within the target time period; or it may include the average value of the path input signal probability at the first moment and the cumulative path input signal probability within the target time period.
[0048] In this embodiment, the path input signal flip rate data includes the path input signal flip rate at the first moment and the maximum value of the cumulative path input signal flip rate within the target time period; it may also include the minimum value of the path input signal flip rate at the first moment and the cumulative path input signal flip rate within the target time period; or it may include the average value of the path input signal flip rate at the first moment and the cumulative path input signal flip rate within the target time period.
[0049] In one embodiment, the cumulative path input signal probability value includes the aging assessment value under the negative bias temperature instability (NBTI) mechanism; the cumulative path input signal reversal rate value includes the aging assessment value under the hot carrier injection (HCI) mechanism.
[0050] In this embodiment, the aging evaluation value under the negative bias temperature instability (NBTI) mechanism is used as the main content of the cumulative probability value of the path input signal, and the aging evaluation value under the hot carrier injection (HCI) mechanism is used as the main content of the cumulative reversal rate value of the path input signal. The main characteristics of the NBTI aging machine mechanism are reflected in the running data pair, and the cumulative nature of the aging effect is further reflected in the aging prediction process.
[0051] Step 202: Input the running data into the first neural network model to train it, and obtain the trained second neural network model. Then, output the path delay increment of the operation unit caused by the aging effect based on the second neural network model.
[0052] In this embodiment, the process of training a first neural network with running data to obtain a trained second neural network may include: first, randomly partitioning the running data to generate a training set, a validation set, and a test set. The training set is used to train the first neural network; the validation set is used to determine the network structure of the first neural network or parameters controlling the model complexity; and the test set is used to evaluate the quality and accuracy of the trained second neural network. If the prediction accuracy is greater than a preset threshold, the training of the first neural network converges, and the second neural network is generated.
[0053] In this embodiment, the process of training a first neural network with running data to obtain a trained second neural network may include: randomly partitioning the running data to generate a training set, a validation set, and a test set; training the first neural network model using the training set and the validation set; testing the first neural network model using the test set; and adjusting the model parameters of the first neural network model based on the prediction accuracy values obtained from training and testing until the prediction accuracy value is greater than a preset threshold, thereby generating the second neural network model. In this way, the generalization ability of the trained second neural network can be improved.
[0054] In this embodiment of the application, the process of training the first neural network with running data to obtain a trained second neural network may include: randomly dividing the running data pair to generate a training set and a validation set; training the first neural network model according to the training set and validating the first neural network model according to the validation set; adjusting the model parameters of the first neural network model based on the prediction accuracy value obtained from training and validation until the prediction accuracy value is greater than a preset threshold, and generating the second neural network model.
[0055] Understandably, the random data partitioning ratio can be flexibly set according to user needs. For example, the running data pairs can be randomly partitioned in a 7:2:1 ratio, so that the training set accounts for 70% of the running data pairs, the validation set accounts for 20% of the running data pairs, and the test set accounts for 10% of the running data pairs.
[0056] In a specific example, the prediction accuracy is calculated based on the loss function of the first neural network model. A higher output value (loss) of the loss function indicates a greater difference between the predicted value and the target value, i.e., a smaller prediction accuracy. Therefore, during the training and testing of deep neural networks, it is necessary to minimize the output value (loss) of the loss function.
[0057] Understandably, during the training of the first neural network model, because it is desired that the output of the first neural network model be as close as possible to the actual predicted value, i.e., the path delay increment, the weight vector of each layer of the neural network can be updated by comparing the predicted value obtained from the current training of the first neural network model with the actual target value, and then updating the weight vector of each layer of the neural network according to the difference between the two (of course, there is usually a process before the first update, i.e., pre-configuring the parameters of each layer in the deep neural network). For example, if the predicted value is too high, the weight vector is adjusted to make it predict lower, and this adjustment is continued until the first neural network model can predict the actual target value or a value very close to the actual target value, i.e., the prediction accuracy value is greater than a preset threshold. In one embodiment, the first neural network model is a deep neural network model; the deep neural network model includes N layers of deep neural networks.
[0058] Where N is an integer greater than or equal to 5; each layer of the deep neural network includes a fully connected operation layer, an activation operation layer, and a batch normalization operation layer; the number of neurons in each layer of the deep neural network is arranged in descending order from the input direction of the deep neural network model to the output direction of the deep neural network model, the output of the previous layer of the deep neural network is the input of the next layer of the deep neural network, and the number of neurons in the Nth layer of the deep neural network is 1.
[0059] like Figure 3 The diagram shown is a schematic representation of a deep neural network according to an embodiment of this application. The deep neural network has 5 layers. Each layer consists of fully connected operations, activation operations, and batch normalization operations.
[0060] In this embodiment, the first neural network model is configured as a deep neural network model, which includes N layers of deep neural networks, where N is an integer greater than or equal to 5. Each layer of the deep neural network includes a fully connected layer, an activation layer, and a batch normalization layer. The number of neurons in each layer is arranged in descending order from the input direction to the output direction of the deep neural network model. The output of the previous layer serves as the input to the next layer, and the Nth layer contains only 1 neuron. This configuration allows the first neural network model, after training, to effectively fit the complex nonlinear relationship between the aging effect and multi-dimensional operational data, solving the problem of weak generalization ability in traditional prediction models and improving the accuracy, efficiency, and reliability of aging prediction.
[0061] In one embodiment, the deep neural network is a convolutional neural network; the dropout rate of the deep neural network is 0.2; the dropout rate is used to characterize the deep neural network randomly dropping 20% of the neuron connections during forward propagation.
[0062] In this embodiment, the deep neural network is configured as a convolutional neural network, and the dropout rate of the deep neural network is set to 0.2. By randomly dropping 20% of the neuron connections in the forward propagation of the deep neural network through the dropout rate, the generalization performance of the first neural network model is effectively improved, overfitting is prevented, and the training efficiency of the first neural network model is maintained.
[0063] Implementing the embodiments of this application, since deep neural networks are non-memory-based neural networks, the prediction result under the current input has no relation to previous inputs. Therefore, this cumulative effect cannot be expressed from the deep neural network itself, but can only be reflected from the input data. Specifically, the aging prediction method proposed in this application not only considers the temperature, voltage, path input signal probability, and path input signal reversal probability at a certain moment in the input data, but also further considers the cumulative nature of the aging effect. In this way, the accuracy of aging prediction can be improved.
[0064] The applicant discovered in their research that existing training data all come from simulation analysis. The ideal data obtained from simulation analysis cannot amplify circuit process deviations, resulting in predictions with only a low prediction error, making them unsuitable for application to real chips. Based on this, such as... Figure 4 The diagram shown is a flowchart of an aging prediction method provided in an embodiment of this application, which may include, but is not limited to, the following steps: Step 401: Obtain the running data pairs of the computing units in the microprocessor chip and the nanometer scale of the microprocessor chip's manufacturing process; Step 402: Input the running data and the nanometer-scale manufacturing process into the first neural network model for training to obtain the second neural network model.
[0065] Specifically, computer equipment 100 acquires the nanometer-scale manufacturing process details of the microprocessor chip; then, it inputs the running data and the nanometer-scale manufacturing process details into a first neural network model for training, resulting in a second neural network model. Traditional aging prediction techniques ignore process deviations caused by the manufacturing process, leading to significant discrepancies between the acquired simulation data and real data, thus causing the simulation data to be unreliable. Therefore, this method not only considers temperature, voltage, path input signal probability, and path input signal flipping probability at a specific moment, but also fully takes into account the process deviation effects between chips, solving the unreliability problem caused by simulation data and further improving the efficiency, reliability, and accuracy of aging prediction.
[0066] Implementing the embodiments of this application, since deep neural networks are non-memory-based neural networks, the prediction result under the current input has no relation to the previous input. Therefore, this cumulative effect cannot be expressed from the deep neural network itself, but can only be reflected from the input data. Specifically, the aging prediction method proposed in this application considers the temperature, voltage, path input signal probability, and path input signal flipping probability at a certain moment in the input data, and also takes into account the cumulative nature of the aging effect. Furthermore, it incorporates the process variation effect between chips, solving the problem of unreliability caused by simulation experimental data, and further improving the efficiency, reliability, and accuracy of aging prediction.
[0067] Based on this, the aforementioned aging prediction method acquires operational data pairs of the computing units in the microprocessor chip. It characterizes the long-term cumulative effects of different aging factors through cumulative temperature, cumulative voltage, cumulative path input signal probability, and cumulative path input signal reversal rate, enriching the data dimensions used for aging prediction and avoiding prediction bias caused by missing data dimensions, thus accurately quantifying the aging state of the computing units. Then, the operational data pairs are input into a first neural network model for training, resulting in a trained second neural network model. This model outputs the path delay increment caused by the aging effect of the computing units, improving the efficiency, reliability, and accuracy of aging prediction.
[0068] In one embodiment, such as Figure 5 As shown, the method further includes steps 501 to 502.
[0069] Step 501: Determine the current frequency degradation rate of the microprocessor chip based on the path delay increment; Step 502: In response to the frequency degradation rate being greater than a preset threshold, a target compensation voltage corresponding to the current frequency degradation rate is determined based on the mapping relationship between the current frequency degradation rate and the compensation voltage, so as to control the voltage compensation of the microprocessor chip according to the target compensation voltage.
[0070] The target compensation voltage is the compensation voltage required for the microprocessor chip to recover to its initial frequency state. Specifically, the computer device 100 determines the current frequency degradation rate of the microprocessor chip based on the path delay increment; then, in response to the frequency degradation rate being greater than a preset threshold, it determines the target compensation voltage corresponding to the current frequency degradation rate based on the mapping relationship between the current frequency degradation rate and the compensation voltage, so as to control the voltage compensation of the microprocessor chip according to the target compensation voltage, thereby improving the performance and frequency of the microprocessor chip.
[0071] In a specific example, the mapping relationship between the current frequency degradation rate and the compensation voltage is determined by performing voltage compensation tests on the microprocessor chip after the frequency of the microprocessor chip has degraded.
[0072] In the voltage compensation test described above, by increasing the supply voltage to the microprocessor chip, the chip's frequency degradation is restored to its initial frequency state, meaning the chip's frequency is brought back to its initial frequency. Through this voltage compensation test, for any frequency degradation rate of the chip, the compensation voltage required to restore the chip from that degradation rate to its initial frequency state can be determined, thus establishing the correspondence between the chip's frequency degradation rate and the compensation voltage.
[0073] The above are just specific examples. In actual applications, the settings should be flexibly adjusted according to user needs, and no restrictions are imposed here.
[0074] In this embodiment, the current frequency degradation rate of the microprocessor chip is determined based on the path delay increment; then, in response to the frequency degradation rate being greater than a preset threshold, a target compensation voltage corresponding to the current frequency degradation rate is determined based on the mapping relationship between the current frequency degradation rate and the compensation voltage, so as to control the voltage compensation of the microprocessor chip according to the target compensation voltage, thereby improving the performance and frequency of the microprocessor chip.
[0075] It should be understood that, although Figures 2-5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be performed in other orders. Furthermore, Figures 2-5 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0076] Secondly, such as Figure 6 As shown, an aging prediction device is provided, the device including a data acquisition module 610 and a model training module 620.
[0077] The data acquisition module 610 is used to acquire operational data pairs from the arithmetic units in the microprocessor chip. These operational data pairs include temperature data pairs, voltage data pairs, path input signal probability data pairs, and path input signal flip rate data pairs. The temperature data pairs include the temperature at a first moment and the cumulative temperature value within a target time period. The voltage data pairs include the voltage at a first moment and the cumulative voltage value within a target time period. The path input signal probability data pairs include the path input signal probability at a first moment and the cumulative path input signal probability value within a target time period. The path input signal flip rate data pairs include the path input signal flip rate at a first moment and the cumulative path input signal flip rate value within a target time period. The target time period is from a second moment to a first moment; the first moment is greater than the second moment. The model training module 620 is used to train the first neural network model by inputting the running data, and obtain the trained second neural network model, so as to output the path delay increment of the operation unit caused by the aging effect based on the second neural network model.
[0078] In one embodiment, the data acquisition module 610 is further configured to acquire the nanometer-scale manufacturing process of the microprocessor chip; the model training module 620 is further configured to input the running data pair and the nanometer-scale manufacturing process into the first neural network model for training, thereby obtaining the second neural network model.
[0079] In one embodiment, the device further includes a voltage compensation module.
[0080] The voltage compensation module is used to determine the current frequency degradation rate of the microprocessor chip based on the path delay increment. In response to the frequency degradation rate being greater than a preset threshold, the voltage compensation module determines the target compensation voltage corresponding to the current frequency degradation rate based on the mapping relationship between the current frequency degradation rate and the compensation voltage, so as to control the voltage compensation of the microprocessor chip according to the target compensation voltage. The target compensation voltage is the compensation voltage required for the microprocessor chip to recover to the initial frequency state.
[0081] In one embodiment, the cumulative path input signal probability value includes the aging assessment value under the negative bias temperature instability (NBTI) mechanism; the cumulative path input signal reversal rate value includes the aging assessment value under the hot carrier injection (HCI) mechanism.
[0082] In one embodiment, the first neural network model is a deep neural network model; the deep neural network model includes N layers of deep neural networks; where N is an integer greater than or equal to 5; each layer of the deep neural network includes a fully connected operation layer, an activation operation layer, and a batch normalization operation layer; the number of neurons included in each layer of the deep neural network is arranged in descending order from the input direction of the deep neural network model to the output direction of the deep neural network model, the output of the previous layer of the deep neural network is the input of the next layer of the deep neural network, and the number of neurons included in the Nth layer of the deep neural network is 1.
[0083] In one embodiment, the deep neural network is a convolutional neural network; the dropout rate of the deep neural network is 0.2; the dropout rate is used to characterize the deep neural network randomly dropping 20% of the neuron connections during forward propagation.
[0084] In one embodiment, the model training module 620 includes a model training unit.
[0085] The model training unit is used to randomly divide the running data pairs to generate training sets, validation sets, and test sets. The model training unit is used to train the first neural network model based on the training set and validation set, and to test the first neural network model based on the test set. The model parameters of the first neural network model are adjusted based on the prediction accuracy values obtained from training and testing until the prediction accuracy value is greater than a preset threshold, thereby generating the second neural network model.
[0086] Specific limitations regarding the aging prediction device can be found in the limitations of the aging prediction method described above, and will not be repeated here. Each module in the aforementioned aging prediction device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.
[0087] In one embodiment, a computer device 100 is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 7As shown. The computer device 100 includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor of the computer device 100 provides computing and control capabilities. The memory of the computer device 100 includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface of the computer device 100 is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements an aging prediction method. The display screen of the computer device 100 can be a liquid crystal display (LCD) or an e-ink display. The input devices of the computer device 100 can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse, etc.
[0088] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device 100 to which the present application is applied. The specific computer device 100 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0089] Thirdly, a computer device 100 is provided, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of any of the methods described in the above method embodiments.
[0090] Fourthly, such as Figure 1 As shown, an aging prediction system is provided, which includes any of the computer devices 100 in the above-described embodiments and a detection circuit 200. The computer device 100 and the detection circuit 200 are electrically connected. The detection circuit is disposed within a microprocessor chip; the detection circuit 200 is used to detect operating data pairs.
[0091] Fifthly, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of any of the methods described in the above method embodiments.
[0092] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
[0093] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0094] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. An aging prediction method, the method comprising: The system acquires operational data pairs from the arithmetic units in a microprocessor chip. These operational data pairs include temperature data pairs, voltage data pairs, path input signal probability data pairs, and path input signal flip rate data pairs. The temperature data pairs include the temperature at a first moment and the cumulative temperature value over a target time period. The voltage data pairs include the voltage at the first moment and the cumulative voltage value over the target time period. The path input signal probability data pairs include the path input signal probability at the first moment and the cumulative path input signal probability over the target time period. The path input signal flip rate data pairs include the path input signal flip rate at the first moment and the cumulative path input signal flip rate over the target time period. The target time period is from a second moment to the first moment; the first moment is greater than the second moment. The running data is input into the first neural network model to train a trained second neural network model, and the path delay increment of the computing unit due to aging effect is output based on the second neural network model.
2. The method according to claim 1, characterized in that, The method further includes obtaining the nanometer-scale manufacturing process of the microprocessor chip; wherein, the step of inputting the running data into a first neural network model to train a trained second neural network model includes: The operating data and the nanometer-scale manufacturing process are input into the first neural network model for training, thereby obtaining the second neural network model.
3. The method according to claim 1 or 2, characterized in that, The method further includes: The current frequency degradation rate of the microprocessor chip is determined based on the path delay increment; In response to the frequency degradation rate being greater than a preset threshold, a target compensation voltage corresponding to the current frequency degradation rate is determined according to the mapping relationship between the current frequency degradation rate and the compensation voltage, so as to control the voltage compensation of the microprocessor chip according to the target compensation voltage; wherein, the target compensation voltage is the compensation voltage required for the microprocessor chip to recover to the initial frequency state.
4. The method according to claim 1, characterized in that, The cumulative probability value of the path input signal includes the aging evaluation value under the negative bias temperature instability (NBTI) mechanism; the cumulative flip rate value of the path input signal includes the aging evaluation value under the hot carrier injection (HCI) mechanism.
5. The method according to any one of claims 1 to 4, characterized in that, The first neural network model is a deep neural network model; the deep neural network model includes N layers of deep neural networks; where N is an integer greater than or equal to 5; each layer of the deep neural network includes a fully connected operation layer, an activation operation layer, and a batch normalization operation layer; the number of neurons included in each layer of the deep neural network is arranged in descending order from the input direction of the deep neural network model to the output direction of the deep neural network model, the output of the previous layer of the deep neural network is the input of the next layer of the deep neural network, and the number of neurons included in the Nth layer of the deep neural network is 1.
6. The method according to claim 5, characterized in that, The deep neural network is a convolutional neural network; the dropout rate of the deep neural network is 0.2; the dropout rate is used to characterize the deep neural network randomly dropping 20% of the neuron connections during forward propagation.
7. The method according to claim 1, characterized in that, The step of inputting the running data into the first neural network model to train the trained second neural network model includes: The running data pairs are randomly divided to generate training, validation, and test sets; The first neural network model is trained using the training set and the validation set, and tested using the test set. The model parameters of the first neural network model are adjusted based on the prediction accuracy values obtained from training and testing, until the prediction accuracy value is greater than a preset threshold, thereby generating the second neural network model.
8. An aging prediction device, characterized in that, The device includes: A data acquisition module is used to acquire operational data pairs from the arithmetic units in a microprocessor chip; wherein, the operational data pairs include temperature data pairs, voltage data pairs, path input signal probability data pairs, and path input signal flip rate data pairs; the temperature data pairs include the temperature at a first moment and the cumulative temperature value within a target time period; the voltage data pairs include the voltage at the first moment and the cumulative voltage value within the target time period; the path input signal probability data pairs include the path input signal probability at the first moment and the cumulative path input signal probability value within the target time period; the path input signal flip rate data pairs include the path input signal flip rate at the first moment and the cumulative path input signal flip rate value within the target time period; the target time period is from a second moment to the first moment; the first moment is greater than the second moment; The model training module is used to train the first neural network model by inputting the running data to obtain a trained second neural network model, and to output the path delay increment of the computing unit caused by the aging effect based on the second neural network model.
9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.
10. An aging prediction system, characterized in that, The aging prediction system includes the computer device and the detection circuit as described in claim 9; the computer device and the detection circuit are electrically connected; the detection circuit is disposed within the microprocessor chip; the detection circuit is used to detect the operating data pair.
11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.