Host device and method of operating a host device

Abstract

A host device and a method of operating a host device are provided. The host device includes a cache configured to temporarily store data copied from a main memory, and a processor configured to process data read from the cache. The cache includes a plurality of ways, wherein each of the plurality of ways has an area distinguished by a plurality of indexes, the data includes first data, and the plurality of indexes includes a first index. The processor includes a cache management circuit configured to generate the first index by using a first adaptive matrix and a first vector, wherein the first adaptive matrix is based on upper bits of a first address corresponding to the first data, and the first vector is based on lower bits of the first address, and manage the first data to be temporarily stored in an empty area among areas corresponding to the first index in the plurality of ways.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0180229, filed on December 6, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to storage devices and host devices, and more specifically, to storage devices and host devices that perform operations by using buffer memory or cache. Background Technology

[0003] Devices that perform memory operations or data processing operations (such as storage devices and host devices) may utilize specific memories (such as buffer memories or caches) to improve operating speed or performance.

[0004] To access a specific memory location, a device can generate an index by applying a hash algorithm (or hash function) to an address received externally or generated internally. However, because the relevant hash algorithms are based on linear methods, specific indexes supported only by that specific memory location are used in concentrated quantities. Therefore, the utilization efficiency of that specific memory location may be low, leading to degraded device performance. Summary of the Invention

[0005] One or more embodiments provide a storage device that efficiently utilizes buffer memory or a host device that efficiently utilizes cache by generating an index based on a hash algorithm (or hash function) with added non-linear elements.

[0006] According to one aspect of an embodiment, a host device includes: a cache configured to temporarily store a plurality of data copied from main memory; and a processor configured to process the plurality of data read from the cache. The cache includes a plurality of paths, each of the plurality of paths having a region distinguished by a plurality of indices, the plurality of data including first data, and the plurality of indices including a first index. The processor includes cache management circuitry configured to: generate the first index using a first adaptive matrix and a first vector, wherein the first adaptive matrix is ​​based on the higher bits of a first address corresponding to the first data, and the first vector is based on the lower bits of the first address; and manage the first data as stored in an empty region within the region corresponding to the first index in the plurality of paths.

[0007] According to another aspect of an embodiment, a host device includes: a cache configured to temporarily store a plurality of data copied from main memory; and a processor configured to process the plurality of data read from the cache. The cache includes a plurality of paths, each of the plurality of paths having a region distinguished by a plurality of indices, the plurality of data including first data, and the plurality of indices including a first index. The processor includes cache management circuitry configured to: generate a first index by performing a hash operation on a first address corresponding to the first data using a first adaptive matrix based on a first thread corresponding to the first data; and manage the first data as temporarily stored in an empty region within the region corresponding to the first index in the plurality of paths.

[0008] According to another aspect of the embodiments, a method of operating a host device is provided. The host device includes a cache. The cache includes a plurality of paths. Each of the plurality of paths has a region distinguished by a plurality of indices. The method includes: generating an adaptive matrix based on the higher bits of an address corresponding to data; generating a vector based on the lower bits of the address; performing a hash operation based on the adaptive matrix and the vector; and storing the data in an empty region within the region corresponding to the index generated from the hash operation in the plurality of paths.

[0009] According to another aspect of the embodiments, a storage device includes: a memory device including non-volatile memory; a memory controller configured to: control a first memory operation of the memory device based on a first address and a first memory command received from an external device; and a buffer memory allocated to the memory controller and including a plurality of paths, wherein each of the plurality of paths has a region distinguished by a plurality of indices. The memory controller includes memory management circuitry configured to: generate a first index among the plurality of indices using a first adaptive matrix and a vector, wherein the first adaptive matrix is ​​based on the higher bits of the first address and the vector is based on the lower bits of the first address; and control the first memory operation based on the state of the region in the plurality of paths corresponding to the first index and the first memory command.

[0010] The memory management circuitry can also be configured to postpone the start of the first memory operation based on the state of a region indicating that a first address was previously stored in the region and a second memory operation for the first address is being performed by the memory device. Attached Figure Description

[0011] The above and other aspects and features will become clearer from the following description of embodiments in conjunction with the accompanying drawings.

[0012] Figure 1 This is a schematic block diagram of a computing system according to an embodiment.

[0013] Figure 2 This is a diagram illustrating the operation of a cache management circuit according to an embodiment.

[0014] Figure 3 This is a diagram illustrating the operation method of an index generator according to an embodiment.

[0015] Figure 4 This is a diagram illustrating the operation method of an index generator according to an embodiment.

[0016] Figure 5 This is a flowchart of the operation method of the host device according to an embodiment.

[0017] Figure 6A This is a diagram illustrating a fixed matrix in an environment where processing is performed by the first to third threads, according to a comparative example. Figure 6B This is a diagram illustrating the first adaptive matrix to the third adaptive matrix in an environment where processing is performed by the first thread to the third thread according to an embodiment.

[0018] Figure 7A It is shown Figure 6A A diagram illustrating the operation of the cache management circuitry in the diagram, and Figure 7B It is shown Figure 6B A diagram illustrating the operation of the cache management circuit in the image.

[0019] Figure 8 This is a diagram illustrating the operation of a cache management circuit according to an embodiment.

[0020] Figure 9A , Figure 9B and Figure 9C This is a flowchart of a method for generating an adaptive matrix according to an embodiment.

[0021] Figure 10 This is a flowchart of a method for updating an adaptive matrix according to an embodiment.

[0022] Figure 11 This is a diagram of a host device according to an embodiment.

[0023] Figure 12 This is a diagram illustrating the operation of a storage device according to an embodiment.

[0024] Figure 13 This is a diagram illustrating the operation of a memory management circuit according to an embodiment.

[0025] Figure 14 This is a diagram illustrating the operation of a memory management circuit in an environment where processing is performed by a first thread and a second thread, according to an embodiment.

[0026] Figure 15 This is a block diagram of a system-on-a-chip according to an embodiment.

[0027] Figure 16 This is a block diagram of an electronic device according to an embodiment. Detailed Implementation

[0028] In the following detailed description, embodiments are given with reference to the accompanying drawings. The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto, and may be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of other examples or other embodiments also provided herein or not provided herein but consistent with this disclosure.

[0029] Figure 1 This is a schematic block diagram of computing system 1 according to an embodiment.

[0030] Reference Figure 1 The computing system 1 may include a host device 10, a storage device 20, a system memory 30, and a bus interface 40.

[0031] According to embodiments, computing system 1 may correspond to any of a smartphone, tablet PC, smart TV, mobile phone, laptop computer, media player, digital camera, home appliance, wearable device, computing device, etc. However, these are provided as examples, and embodiments are not limited thereto. Computing system 1 may be implemented as various devices.

[0032] According to an embodiment, the host device 10, storage device 20, and system memory 30 can communicate with each other via a bus interface 40. As an example, the bus interface 40 may support any of the following protocols: Peripheral Component Interconnect (PCI), PCIe, Universal Serial Bus (USB), Serial Advanced Technology Attachment (SATA), and Compute Fast Link (CXL).

[0033] According to an embodiment, when the processor 11 performs data processing operations, the system memory 30, which is a memory allocated to the host device 10, can be used by the processor 11 to store necessary data or processed data. In this specification, the system memory 30 may be referred to as main memory. As an example, the system memory 30 may include a volatile memory implemented as one of static random access memory (SRAM) and dynamic random access memory (DRAM). However, these are provided as examples, and the embodiments are not limited thereto. The system memory 30 may include a non-volatile memory implemented as one of phase-change random access memory (PRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FeRAM).

[0034] According to an embodiment, the host device 10 may include a processor 11 and a cache 13. The processor 11 may include cache management circuitry 12. As an example, according to an embodiment, the cache management circuitry 12 may be configured to perform necessary operations such that the processor 11 can efficiently utilize the cache 13. The cache management circuitry 12 may be implemented in dedicated hardware for performing operations, or it may be implemented by the processor 11 operating according to software instructions. In this specification, the operation of the cache management circuitry 12 may be understood as the operation of the host device 10 or the processor 11.

[0035] According to an embodiment, cache 13 may cache frequently used data from the host device 10 within the data stored in system memory 30. In this specification, caching may be defined as the process of temporarily storing a copy of data stored in a particular memory in cache 13, allowing the processor 11 to access the data more quickly. As an example, cache 13 may include multiple paths. A path of cache 13 may include regions distinguished by multiple indices. A region of a path of cache 13 may include memory space in which data copied from system memory 30 is stored, and the index indicating the region may correspond to a specific address. As an example, a cache line including a valid bit, a tag, and data may be stored in a region of a path of cache 13. The valid bit is a bit indicating whether the corresponding cache line is valid, and the tag is information indicating the cache address of the corresponding region of cache 13. The valid bit and tag may be combined with the index to search for the address in system memory 30 where the data of the corresponding cache line is stored.

[0036] According to an embodiment, in order to temporarily store frequently used data stored in system memory 30 by processor 11 in cache 13, cache management circuit 12 can generate an index corresponding to the data using a hash function. As a specific example, cache management circuit 12 can input the address used to read data stored in system memory 30 into the hash function, and can use the value output from the hash function as the index. In this specification, operations using the hash function are performed according to a hash algorithm matched with the hash function. Operations may include generating an adaptive matrix and a vector, which will be described below, and performing specific operations between the adaptive matrix and the vector. Furthermore, in this specification, operations using the hash function may be referred to as hash operations.

[0037] As an example, cache management circuit 12 can generate an index corresponding to data using an adaptive matrix based on the higher bits of the address corresponding to the data and a vector based on the lower bits of the address corresponding to the data. As another example, cache management circuit 12 can generate an index corresponding to data using an adaptive matrix based on the thread corresponding to the data and a vector based on the lower bits of the address. In this specification, a thread is the main entity performing the task of processing data, wherein processor 11 can perform processing through multiple threads.

[0038] According to an embodiment, in order to temporarily store data in the cache 13 of the system memory 30, the cache management circuit 12 can generate indexes via a nonlinear operation method that generates adaptive matrices and vectors based on information about the data and uses the generated adaptive matrices and vectors for specific operations. Therefore, the regions corresponding to multiple indices of the cache 13 can be used evenly, allowing the cache 13 to be used efficiently. Thus, the performance of the host device 10 can be improved.

[0039] According to an embodiment, the storage device 20 may include a memory controller 21 and a memory device 23. The memory controller 21 may include memory management circuitry 22. As an example, according to an embodiment, the memory management circuitry 22 is configured to perform necessary operations such that the memory controller 21 can efficiently control the memory operations of the memory device 23. The memory management circuitry 22 may be implemented in hardware dedicated to performing the operations, or it may be implemented by the memory controller 21, which operates according to software instructions. In this specification, the operation of the memory management circuitry 22 can be understood as the operation of the storage device 20 or the memory controller 21.

[0040] According to an embodiment, memory controller 21 can control memory operations of memory device 23 based on memory commands received from host device 10. Memory controller 21 can centrally receive multiple memory commands from multiple threads of host device 10. When memory controller 21 controls memory operations of memory device 23 according to multiple memory commands, management may be required to prevent conflicts between memory operations. Memory management circuitry 22 can perform operations to prevent conflicts between memory operations of memory device 23, wherein memory management circuitry 22 may utilize buffer memory allocated to memory device 20 of memory controller 21. As an example, buffer memory may include multiple paths. Paths of buffer memory may include regions distinguished by multiple indices. A region of a path of buffer memory is a memory space in which a specific address corresponding to a memory region that is the target of a memory operation frequently performed by memory device 23 is stored, and an index indicating the region may correspond to a specific address. As an example, status information indicating the status of a region may also be stored in a region of a path of buffer memory. In this specification, status information may include information indicating the type of memory operation and whether a memory operation is being performed on a memory region of memory device 23 corresponding to a region.

[0041] According to an embodiment, in order to temporarily store the addresses corresponding to memory regions of the memory device 23 that are frequently requested for memory operations by the host device 10 in a buffer memory, the memory management circuit 22 can generate an index corresponding to the address using a hash function. As a specific example, the memory management circuit 22 can input the address received from the host device 10 into the hash function and use the value output from the hash function as the index.

[0042] As an example, memory management circuit 22 can use an adaptive matrix based on the higher bits of the address and a vector based on the lower bits of the address to generate an index corresponding to the address. As another example, memory management circuit 22 can use an adaptive matrix based on the thread corresponding to the address and a vector based on the lower bits of the address to generate an index corresponding to the data.

[0043] According to an embodiment, in order to manage memory operations by storing frequently used addresses in a buffer memory, the memory management circuit 22 can generate indexes via a non-linear operation method that generates adaptive matrices and vectors based on information about the corresponding addresses and uses the generated adaptive matrices and vectors for specific operations. Therefore, the regions of the buffer memory corresponding to multiple indices can be used evenly, allowing the buffer memory to be used efficiently. Thus, the performance of the memory controller 21 can be improved.

[0044] exist Figure 1In this example, both cache management circuit 12 and memory management circuit 22 are provided. The computing system 1 may include only one of the cache management circuit 12 and memory management circuit 22.

[0045] Figure 2 This is a diagram illustrating the operation of a cache management circuit 100 according to an embodiment.

[0046] Reference Figure 2 The cache management circuit 100 may include an index generator (e.g., an index generation circuit) 102. According to an embodiment, the index generator 102 may input the address corresponding to data into a hash function 112, and provide the resulting value output from the hash function 112 based on the input address as an index to the cache management circuit 100. For example, the index generator 102 may input a first address ADDR#00 corresponding to first data into the hash function 112, and provide the first result value RV#00 output from the hash function 112 based on the first address ADDR#00 as an index to the cache management circuit 100. The first result value RV#00 may correspond to the first index INDEX#00 among the first index INDEX#00 to the (L-1)th index INDEX#(L-1)0 (where L is an integer greater than 1). Figure 2 In the cache 110, the area corresponding to the shaded part represents the area of ​​multiple paths that is in a full state, and the area corresponding to the unshaded part represents the area of ​​multiple paths that is in an empty state.

[0047] According to an embodiment, hash function 112 is a function with non-linear characteristics between its input and output. Hash function 112 may include functions that define methods for generating and computing adaptive matrices and vectors.

[0048] According to an embodiment, the cache management circuit 100 may store a first cache line CL#00 including first data in a region indicated by a first index INDEX#00 among a plurality of regions with the highest priority of the first WAY#00 from the first WAY#00 to the (K-1)WAY#(K-1)0 (where K is an integer greater than 1).

[0049] Figure 3 This is a diagram illustrating an operational method according to an embodiment, and may be performed, for example, by an index generator 102.

[0050] Reference Figure 3The address ADDR can include higher-order bits and lower-order bits. The address ADDR can include N bits (where N is an integer greater than M), the higher-order bits can include NM bits, and the lower-order bits can include M bits (where M is an integer of 1 or greater than 1). Furthermore, the number of lower-order bits in the address ADDR can correspond to the number of bits in the index. Therefore, the number of bits in the index can be "M".

[0051] According to an embodiment, the index generator 102 can generate an adaptive matrix of size "M×M" based on at least one of the higher bits of the address ADDR and can generate a vector of size "M×1" based on the lower bits of the address ADDR. In one embodiment, the inverse matrix of the adaptive matrix exists. As a specific example, the index generator 102 can generate an adaptive matrix in which at least one of the higher bits of the address ADDR is arranged in a specific pattern. Furthermore, the index generator 102 can generate an adaptive matrix in which all (i.e., each of the NM higher bits) of the address ADDR are arranged in a specific pattern.

[0052] Index generator 102 can perform multiplication and XOR operations between adaptive matrices and vectors to generate an output vector of size "M×1". Therefore, index generator 102 can identify the index corresponding to the output vector.

[0053] Figure 4 The diagram specifically illustrates the operation method according to the embodiment, and, for example, can be derived from... Figure 2 The index generator 102 in the middle is executed.

[0054] Reference Figure 4 The address ADDR' may include higher bits [9] to

[31] and lower bits [0] to [8]. The address ADDR' may include 32 bits, wherein the higher bits [9] to

[31] may include 23 bits and the lower bits [0] to [8] may include 9 bits. The number of bits in the index may be 9, which corresponds to the number of lower bits [0] to [8].

[0055] According to an embodiment, index generator 102 can generate an adaptive matrix in which the higher bits [9] to

[31] of address ADDR' are arranged in a specific pattern. As a specific example, index generator 102 can generate an adaptive matrix in which the higher bits [9] to

[31] are arranged in a specific pattern in the elements above the main diagonal of an upper triangular matrix. Index generator 102 can generate a vector based on the lower bits [0] to [8] of address ADDR'.

[0056] Index generator 102 can perform multiplication and XOR operations between adaptive matrices and vectors to generate an output vector of size "9×1". Therefore, index generator 102 can identify the index corresponding to the output vector.

[0057] However, Figure 4 The examples of generating adaptive matrices in the examples are merely illustrative, and the embodiments are not limited thereto. The higher bits [9] through

[31] can be arranged in various patterns in the adaptive matrix.

[0058] Figure 5 This is a flowchart of the operation method of the host device according to an embodiment. Figure 5 The operating method of the host device can correspond to the operating method of the processor included in the host device or the cache management circuit included in the processor.

[0059] Reference Figure 5 In operation S100, the host device can generate an adaptive matrix corresponding to the higher-order bits of the address. According to an embodiment, the host device can generate the adaptive matrix based on the higher-order bits of the address. As a specific example, in the adaptive matrix generated by the host device, at least one of the higher-order bits of the address can be arranged in a specific pattern.

[0060] In operation S110, the host device can generate a vector corresponding to the lower bits of the address.

[0061] In operation S120, the host device can perform multiplication and XOR operations between the adaptive matrix generated in operation S100 and the vector generated in operation S110.

[0062] In operation S130, the host device may temporarily store the data corresponding to the address in the cache based on the matching of the index with the operation result in operation S120. As a specific example, the host device may temporarily store the data in an empty area within the area corresponding to the index in one of multiple paths of the cache. As an example, the data may be stored in the corresponding area of ​​the cache as part of a cache line.

[0063] Figure 6A This is a diagram illustrating a fixed matrix FMT in an environment where processing is performed by threads THR#00, THR#10, and THR#20 from the first to the third thread, according to a comparative example. Figure 6B This is a diagram illustrating the first adaptive matrix to the third adaptive matrix AMT#0, AMT#1, and AMT#2 in an environment where processing is performed by the first to third threads THR#00, THR#10, and THR#20 according to an embodiment. Figure 6A and Figure 6BIn this example, we assume that the number of higher-order bits in the address is 23 and the number of lower-order bits is 9. However, this is merely an example. Implementations are not limited to this.

[0064] Reference Figure 6A In the comparison example, the first address ADDR#00 corresponding to the first thread THR#00 may include a higher bit with a first fixed value and a lower bit with an arbitrary value; the second address ADDR#10 corresponding to the second thread THR#10 may include a higher bit with a second fixed value and a lower bit with an arbitrary value; and the third address ADDR#20 corresponding to the third thread THR#20 may include a higher bit with a third fixed value and a lower bit with an arbitrary value. The first to third fixed values ​​may be different from each other. That is, the first fixed value may correspond to a unique first value corresponding to the first thread THR#00, the second fixed value may correspond to a unique second value corresponding to the second thread THR#10, and the third fixed value may correspond to a unique third value corresponding to the third thread THR#20.

[0065] According to the comparison example, a fixed matrix FMT of size "32×32" can be used to generate indices corresponding to the first to third addresses ADDR#00, ADDR#10, and ADDR#20. Therefore, in the comparison example, because the indices are determined in a relatively linear manner based on the lower bits of addresses ADDR#00, ADDR#10, and ADDR#20, specific indices can be used in a concentrated manner. See below. Figure 7A Specific examples to describe them.

[0066] Further reference Figure 6B In one embodiment, a first adaptive matrix AMT#0 of size "9×9" can be used to generate an index corresponding to the first address ADDR#00, a second adaptive matrix AMT#1 of size "9×9" can be used to generate an index corresponding to the second address ADDR#10, and a third adaptive matrix AMT#2 of size "9×9" can be used to generate an index corresponding to the third address ADDR#20.

[0067] According to an embodiment, the first adaptive matrix AMT#0 may be based on the higher bits of a first address ADDR#00 having a first fixed value, the second adaptive matrix AMT#1 may be based on the higher bits of a second address ADDR#10 having a second fixed value, and the third adaptive matrix AMT#2 may be based on the higher bits of a third address ADDR#20 having a third fixed value. The first to third adaptive matrices AMT#0, AMT#1, and AMT#2 corresponding to the first to third threads THR#00, THR#10, and THR#20 may be different from each other. In one embodiment, based on the correspondence between the first and second fixed values, the first adaptive matrix AMT#0 and the second adaptive matrix AMT#1 are the same.

[0068] Figure 7A It is shown Figure 6A A diagram illustrating the operation of the cache management circuitry in the diagram, and Figure 7B It is shown Figure 6B A diagram illustrating the operation of the cache management circuitry. Figure 7A and Figure 7B In this case, it is assumed that the first address to the third address ADDR#00, ADDR#10 and ADDR#20 are received sequentially by the cache management circuit.

[0069] Reference Figure 7A In the comparative example, the cache management circuit can generate the first index INDEX#00 using a fixed matrix FMT and a first vector based on the lower bits of the first address ADDR#00. Because the region of the first WAY#00 in the region corresponding to the first index INDEX#00 is filled, the cache management circuit can temporarily store the first cache line CL#00, which includes the first data, in the empty region of the next path (second path WAY#10) of the index. The cache management circuit can also generate the first index INDEX#00 using a fixed matrix FMT and a second vector based on the lower bits of the second address ADDR#10. Because the regions of the first WAY#00 and second WAY#10 in the region corresponding to the first index INDEX#00 are filled, the cache management circuit can temporarily store the second cache line CL#10, which includes the second data, in the empty region of the next path (third path WAY#20) of the index. Furthermore, the cache management circuit can generate the first index INDEX#00 using a fixed matrix FMT and a third vector based on the lower bits of the third address ADDR#20. Because the regions of the first to third paths WAY#00, WAY#10 and WAY#20 in the region corresponding to the first index INDEX#00 are filled, the cache management circuit can temporarily store the third cache line CL#20, which includes the third data, in the empty region of the next path (fourth path WAY#30) of the index.

[0070] In the comparison example, because a linear method is used to generate the index, the first index INDEX#00 can be used in a concentrated manner, which reduces the utilization of a portion of the region of cache 110. Therefore, in the comparison example, the utilization of cache 110 can be reduced.

[0071] Reference Figure 7B The cache management circuit can generate a first index INDEX#00 using a first adaptive matrix AMT#0 based on the higher bits of the first address ADDR#00 and a first vector based on the lower bits of the first address ADDR#00. Because the region of the first path WAY#00 in the region corresponding to the first index INDEX#00 is filled, the cache management circuit can temporarily store the first cache line CL#00, which includes the first data, in the empty region of the next path (second path WAY#10) of the index. The cache management circuit can generate a second index INDEX#10 using a second adaptive matrix AMT#1 based on the higher bits of the second address and a second vector based on the lower bits of the first address ADDR#10. Because the region of the first path WAY#00 in the region corresponding to the second index INDEX#10 is filled, the cache management circuit can temporarily store the second cache line CL#10, which includes the second data, in the empty region of the next path (second path WAY#10) of the index. Furthermore, the cache management circuitry can generate the third index INDEX#20 using the third adaptive matrix AMT#2 based on the higher bits of the third address and the third vector based on the lower bits of the third address ADDR#20. Because the region of the first path WAY#00 in the region corresponding to the third index INDEX#20 is filled, the cache management circuitry can temporarily store the third cache line CL#20, which includes the third data, in the empty region of the next path (second path WAY#10) of the index.

[0072] In one embodiment, because a non-linear method is used to generate the indexes, the first index INDEX#00 to the fourth index INDEX#30 can be used evenly, thereby improving the utilization of cache 110. Therefore, the operational performance of the host device using cache 110 can be improved.

[0073] Figure 8 This is a diagram illustrating the operation of the cache management circuit 200 according to an embodiment.

[0074] Reference Figure 8 The cache management circuit 200 may include an index generator (e.g., an index generation circuit) 210. The index generator 210 can generate cache indexes corresponding to addresses by referring to the management table 212.

[0075] According to an embodiment, management table 212 may indicate multiple adaptive matrices AMT#00 to AMT#(Q-1)0 respectively mapped to multiple threads THR#00 to THR#(Q-1)0 (where Q is an integer of 2 or greater than 2). As a specific example, a first adaptive matrix AMT#00 may be mapped to a first thread THR#00, a second adaptive matrix AMT#10 may be mapped to a second thread THR#10, and a Qth adaptive matrix AMT#(Q-1)0 may be mapped to a Qth thread THR#(Q-1)0. Furthermore, the multiple adaptive matrices AMT#00 to AMT#(Q-1)0 may be different from each other. In some embodiments, some of the multiple adaptive matrices AMT#00 to AMT#(Q-1)0 may be the same. This is because, to improve cache utilization, it is not necessary for all adaptive matrices AMT#00 to AMT#(Q-1)0 to be different.

[0076] According to an embodiment, cache management circuit 200 can identify the thread corresponding to a received address, refer to management table 212 based on the identified thread, and identify an adaptive matrix mapped to the identified thread. In one embodiment, cache management circuit 200 can identify the adaptive matrix mapped to the higher bits of the received address based on management table 212. Cache management circuit 200 can generate an index corresponding to the received address by using the identified adaptive matrix.

[0077] Figures 9A to 9C This is a flowchart of a method for generating an adaptive matrix according to an embodiment. The operation of the host device described below can be understood as the operation of a processor included in the host device or cache management circuitry included in the processor.

[0078] Reference Figure 9A In operation S200A, the host device can obtain first information about the higher bits of the address of each thread. The fixed value of the higher bits of the address can be different for each thread, and the first information can include the higher bits of the address of each thread.

[0079] In operation S210A, the host device can determine the placement pattern of the higher bits of the address in the adaptive matrix for each thread based on the first information obtained in operation S200A.

[0080] In operation S220A, the host device can generate an adaptive matrix for each thread based on the placement pattern determined in operation S210A.

[0081] The host device can be accessed by using a table (such as, Figure 8 The management table 212 in the table is used to manage the adaptive matrix for each thread.

[0082] Reference Figure 9B In operation S200B, the host device can generate a seed for each thread. As an example, the host device can generate a first seed corresponding to the first thread and a second seed corresponding to the second thread, wherein the first seed and the second seed have different values.

[0083] In operation S210B, the host device can generate an adaptive matrix for each thread based on a seed for each thread. As an example, the host device can generate a first adaptive matrix corresponding to the first thread based on a first reference bit or a first method corresponding to the first seed. Furthermore, the host device can generate a second adaptive matrix corresponding to the second thread based on a second reference bit or a second method corresponding to the second seed.

[0084] The host device can be accessed by using a table (such as, Figure 8 The management table 212 in the table is used to manage the adaptive matrix for each thread.

[0085] Further reference Figure 9C During operation S200C, the host device can obtain second information about at least one of the following: the number of cache paths, the number of cache indices, and the number of threads.

[0086] In operation S210C, the host device may generate multiple adaptive matrices based on the second information obtained in operation S200C. As an example, the host device may generate multiple adaptive matrices based on at least one of the number of cache paths, the number of cache indices, and the number of threads, thereby maximizing cache utilization. In some embodiments, the host device may obtain multiple adaptive matrices from a neural network model by inputting the second information into a neural network model trained to generate the optimal adaptive matrices.

[0087] In operation S220C, the host device can perform a one-to-one mapping between threads and multiple adaptive matrices generated in operation S210C.

[0088] The host device can be accessed by using a table (such as, Figure 8 The management table 212 in the table is used to manage the adaptive matrix for each thread.

[0089] Figure 10 This is a flowchart of a method for updating an adaptive matrix according to an embodiment. The operation of the host device described below can be understood as the operation of a processor included in the host device or cache management circuitry included in the processor.

[0090] Reference Figure 10In operation S300, the host device can monitor the pattern (or state) of cache path filling. As an example, the host device can monitor the pattern formed by filled or empty regions within the cache path regions.

[0091] In operation S310, the host device can determine whether the monitoring result of operation S300 meets the update condition. As an example, the host device can confirm the cache utilization based on the monitoring pattern, wherein a utilization rate below a threshold can be set as meeting the update condition.

[0092] When operation S310 is true (i.e., when the monitoring result of operation S300 meets the update condition), operation S320 can be followed to update the adaptive matrix used for each thread by the host device. In other words, the host device can generate a new adaptive matrix corresponding to the thread or adjust the placement of the components of the existing adaptive matrix.

[0093] If operation S310 is not successful (i.e., when the monitoring result of operation S300 does not meet the update conditions), operation S300 can be repeated. In this respect, operation S300 can be repeated until the monitoring result meets the update conditions.

[0094] Figure 11 This is a diagram of the host device 300 according to an embodiment.

[0095] Reference Figure 11 The host device 300 may include a processor 310, an L1 cache 321, an L2 cache 322, and an L3 cache 323.

[0096] As an example, L1 cache 321, L2 cache 322, and L3 cache 323 can be hierarchically connected to each other. L1 cache 321 can cache frequently used data stored in L2 cache 322 that is frequently used by the processor 310. L2 cache 322 can cache frequently used data stored in L3 cache 323 that is frequently used by the processor 310. Furthermore, L3 cache 323 can cache data stored in system memory (…). Figure 1 The data in 30) is the data that is frequently used by the processor 310.

[0097] According to an embodiment, the processor 310 may include an L1 cache management circuit 311, an L2 cache management circuit 312, and an L3 cache management circuit 313. The L1 cache management circuit 311 can generate an index matching the structure of the L1 cache 321 in a manner consistent with the embodiments described above. The L2 cache management circuit 312 can generate an index matching the structure of the L2 cache 322 in a manner consistent with the embodiments described above. Furthermore, the L3 cache management circuit 313 can generate an index matching the structure of the L3 cache 323 in a manner consistent with the embodiments described above.

[0098] However, Figure 11 The structure of the host device 300 described herein is merely an example, and the embodiments are not limited thereto. These embodiments can be applied to various implementations of the host device 300.

[0099] Figure 12 This is a diagram illustrating the operation of the storage device 400 according to an embodiment.

[0100] Reference Figure 12 The storage device 400 may include a memory management circuit 410 and a buffer memory 420. The memory management circuit 410 may include an index generator (i.e., an index generation circuit) 412.

[0101] According to an embodiment, the index generator 412 can input the first address ADDR#01 received with the memory command into the hash function 414, and can provide the first result value RV#01 output from the hash function 414 as an index to the memory management circuit 410. The first result value RV#01 can correspond to the first index INDEX#01 among the first index INDEX#01 to the (L-1)th index INDEX#(L-1)1.

[0102] According to an embodiment, hash function 414 is a function with non-linear characteristics between its input and output. Hash function 414 may include functions that define methods for generating and computing adaptive matrices and vectors.

[0103] According to an embodiment, the memory management circuit 410 can store the first address ADDR#01 in the region indicated by the first index INDEX#01 among a plurality of regions of the first WAY#01 with the highest priority among the first WAY#01 to the (K-1)th WAY#(K-1)1.

[0104] Figure 13 This is a diagram illustrating the operation of the memory management circuit 410 according to an embodiment.

[0105] Reference Figure 13The memory management circuit 410 may include an index generator 412. The index generator 412 can generate an index of the buffer memory corresponding to an address by referring to the management table 416.

[0106] According to an embodiment, management table 416 may indicate multiple adaptive matrices AMT#01 to AMT#(Q-1)1 respectively mapped to multiple threads THR#01 to THR#(Q-1)1. As a specific example, a first adaptive matrix AMT#01 may be mapped to a first thread THR#01, a second adaptive matrix AMT#11 may be mapped to a second thread THR#11, and a Qth adaptive matrix AMT#(Q-1)1 may be mapped to a Qth thread THR#(Q-1)1. Furthermore, the multiple adaptive matrices AMT#01 to AMT#(Q-1)1 may be different from each other. In some embodiments, some of the multiple adaptive matrices AMT#01 to AMT#(Q-1)1 may be the same.

[0107] According to an embodiment, the memory management circuit 410 can identify the thread corresponding to the received address, refer to the management table 416 based on the identified thread, and identify an adaptive matrix mapped to the identified thread. The memory management circuit 410 can generate an index corresponding to the received address by using the identified adaptive matrix.

[0108] Furthermore, as described above, the embodiment for generating the index of the cache management circuit can be applied to the method for generating the index of the memory management circuit 410.

[0109] Figure 14 This is a diagram illustrating the operation of a memory management circuit 410 in an environment where processing is performed by a first thread THR#01 and a second thread THR#11, according to an embodiment.

[0110] Reference Figure 14 The memory management circuit 410 can generate a first index INDEX#01 using a first adaptive matrix based on the higher bits of the first address ADDR#01 corresponding to the first thread THR#01 and a first vector based on the lower bits of the first address ADDR#01, and can identify the region of the second path WAY#11 storing the first address ADDR#01 based on the first index INDEX#01. The memory management circuit 410 can confirm the status information R indicating that a read operation is being performed on the memory region corresponding to the first address ADDR#01 in the region, and can postpone the start of the write operation according to the write command W_CMD. Thereafter, the memory management circuit 410 can start the write operation after confirming the status information RD indicating that the read operation is complete and in a ready state, and can modify the status information W to indicate that a write operation according to the write command W_CMD is being performed.

[0111] Furthermore, the memory management circuit 410 can generate a second index INDEX#11 using a second adaptive matrix based on the higher bits of the second address ADDR#11 corresponding to the second thread THR#11 and a second vector based on the lower bits of the second address ADDR#11, and can identify the region storing the second address ADDR#11 of the second path WAY#11 based on the second index INDEX#11. The memory management circuit 410 can confirm the status information W indicating that a write operation is being performed on the memory region corresponding to the second address ADDR#11 in the corresponding region of the memory device, and can postpone the start of the read operation according to the read command R_CMD. Thereafter, the memory management circuit 410 can start the read operation after confirming the status information RD indicating that the write operation is complete and in a ready state, and can modify the status information R to indicate that a read operation according to the read command R_CMD is being performed.

[0112] Figure 15 This is a block diagram of a system-on-chip 1000 according to an embodiment.

[0113] Reference Figure 15 The system-on-a-chip 1000 may include a central processing unit (CPU) 1010, a graphics processing unit (GPU) 1020, a neural network processor (NPU) 1030, internal memory 1040, a memory interface 1050, a display controller 1060, and a bus interface 1070. The internal components of the system-on-a-chip 1000 can communicate via the bus interface 1070.

[0114] According to an embodiment, the CPU 1010 may include cache management circuitry consistent with the embodiments described above. Through the cache management circuitry, data stored in internal memory 1040 or external memory 1051 can be efficiently cached in the cache of the CPU 1010, and the cached data can be processed or executed.

[0115] According to an embodiment, GPU 1020 may include cache management circuitry consistent with the embodiments described above. Through the cache management circuitry, data stored in internal memory 1040 or external memory 1051 can be efficiently cached in the cache of GPU 1020. The cached data for deep learning can be used to perform synchronization matrix operations, or the cached data can be converted into signals suitable for display device 1061.

[0116] According to an embodiment, the NPU 1030 may include cache management circuitry consistent with the embodiments described above. Through the cache management circuitry, data stored in internal memory 1040 or external memory 1051 can be efficiently cached in the cache of the NPU 1030, and large-scale operations on the cached data can be performed using neural networks.

[0117] Display device 1061 can display image signals output from display controller 1060. For example, display device 1061 can be implemented as a liquid crystal display (LCD), a light-emitting diode (LED) display, an organic LED (OLED) display, an active-matrix OLED (AMOLED) display, or a flexible display. Display controller 1060 can control the operation of display device 1061.

[0118] Internal memory 1040 may include random access memory (RAM) for temporary storage of programs (or applications), data, or commands.

[0119] The memory interface 1050 can communicate with the external memory 1051 via an interface. The memory interface 1050 can control the overall operation of the external memory 1051 and can control the data exchange between the external memory 1051 and any of the CPU 1010, GPU 1020 and NPU 1030.

[0120] Figure 16 This is a block diagram of an electronic device according to an embodiment.

[0121] Reference Figure 16 The electronic device may include a system-on-a-chip (SOC) 2000, a camera module 2100, a display 2200, a power supply 2300, an input / output (I / O) port 2400, a memory 2500, a storage device 2600, an external memory 2700, and a network device 2800.

[0122] According to an embodiment, in order to improve the utilization of the cache of the processor included in the system-on-chip 2000, the system-on-chip 2000 may generate an adaptive matrix based on the higher bits of the address, and may use the generated adaptive matrix to generate an index for using the cache according to a non-linear method.

[0123] Camera module 2100 represents a module capable of converting an optical image into an electrical image. Therefore, the electrical image output from the camera module can be stored in storage device 2600, memory 2500, or external memory 2700. Furthermore, the electrical image output from the camera module can be displayed on display 2200.

[0124] The display 2200 can display data output from storage device 2600, memory 2500, I / O port 2400, external memory 2700 or network device 2800.

[0125] The power supply 2300 can supply operating voltage to at least one of the components.

[0126] I / O port 2400 represents a port configured to transmit data to an electronic device or to transmit data output from an electronic device to an external device. For example, I / O port 2400 may include a port for connecting to a pointing device (such as a computer mouse), a port for connecting to a printer, or a port for connecting to a USB drive.

[0127] The memory 2500 can be implemented as volatile or non-volatile memory. According to an embodiment, a memory interface configured to control data access operations (e.g., read operations, write operations (or programming operations), or erase operations) targeting the memory 2500 can be integrated or built into the system-on-chip 2000. According to another embodiment, the memory interface can be implemented between the system-on-chip 2000 and the memory 2500.

[0128] The storage device 2600 can be implemented as a hard disk drive or a solid-state drive (SSD).

[0129] The external memory 2700 may be implemented as a Secure Digital (SD) card or a Multimedia Card (MMC). According to an embodiment, the external memory 2700 may include a Subscriber Identity Module (SIM) card or a Universal Subscriber Identity Module (USIM) card.

[0130] Network device 2800 refers to a device configured to connect electronic devices to a wired or wireless network.

[0131] While aspects of the embodiments have been specifically shown and described, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A host device, comprising: The cache is configured to temporarily store multiple data copied from main memory; as well as The processor is configured to process the plurality of data read from the cache. The cache includes multiple paths, each of which has a region distinguished by multiple indices. The multiple data includes first data, and the multiple indices include the first index. The processor includes a cache management circuit, which is configured as follows: A first index is generated using a first adaptive matrix and a first vector, wherein the first adaptive matrix is ​​based on the higher bits of a first address corresponding to the first data, and the first vector is based on the lower bits of the first address; and The first data is managed as a temporary storage in an empty region within the region corresponding to the first index in the plurality of paths.

2. The host device as claimed in claim 1, wherein, In the first adaptive matrix, at least one bit of the higher bits of the first address is arranged in a specific pattern.

3. The host device as claimed in claim 1, wherein, In the first adaptive matrix, the higher bits of the first address are arranged in a specific pattern.

4. The host device as claimed in claim 1, wherein, The inverse of the first adaptive matrix exists.

5. The host device as claimed in claim 1, wherein, The first adaptive matrix includes an upper triangular matrix in which the higher bits of the first address are arranged in a specific pattern among the elements above the main diagonal of the upper triangular matrix.

6. The host device according to any one of claims 1 to 5, wherein, The cache management circuit is also configured to determine the first adaptive matrix by using a first method corresponding to the higher bit of the first address.

7. The host device according to any one of claims 1 to 5, wherein, The cache management circuit is also configured to: identify the first adaptive matrix that maps to the higher bits of the first address based on the management table.

8. The host device according to any one of claims 1 to 5, wherein, The cache management circuit is configured to generate a first index by performing multiplication and XOR operations on a first adaptive matrix and a first vector.

9. The host device according to any one of claims 1 to 5, wherein, The number of lower bits in the first address matches the number of bits in the first index.

10. The host device according to any one of claims 1 to 5, wherein, The plurality of data also includes second data, and the plurality of indexes also includes a second index, and The cache management circuit is also configured as follows: A second index is generated using a second adaptive matrix and a second vector, wherein the second adaptive matrix is ​​based on the higher bits of the second address corresponding to the second data, and the second vector is based on the lower bits of the second address; and The second data is managed as a temporary storage in an empty region within the region corresponding to the second index in the plurality of paths.

11. The host device as claimed in claim 10, wherein, Because the higher-order bits of the first address are different from the higher-order bits of the second address, the first adaptive matrix and the second adaptive matrix are different.

12. The host device as claimed in claim 10, wherein, Based on the correspondence between the higher-order bits of the first address and the higher-order bits of the second address, the first adaptive matrix and the second adaptive matrix are the same.

13. A host device, comprising: The cache is configured to temporarily store multiple data copied from main memory; as well as The processor is configured to process the plurality of data read from the cache. The cache includes multiple paths, each of which has a region distinguished by multiple indices. The multiple data includes first data, and the multiple indices include the first index. The processor includes a cache management circuit, which is configured as follows: A first index is generated by performing a hash operation on the first address corresponding to the first data using a first adaptive matrix based on the first thread corresponding to the first data; and The first data is managed as a temporary storage in an empty region within the region corresponding to the first index in the plurality of paths.

14. The host device as claimed in claim 13, wherein, The plurality of data also includes second data, and the plurality of indexes also includes a second index, and The cache management circuit is also configured as follows: A second index is generated by performing a hash operation on the second address corresponding to the second data using a second adaptive matrix based on the second thread corresponding to the second data; and The second data management is temporarily stored in an empty area within the region corresponding to the second index in the plurality of paths.

15. The host device as claimed in claim 14, wherein, Since the first thread and the second thread are different from each other, the first adaptive matrix and the second adaptive matrix are different.

16. The host device as claimed in claim 14, wherein, Based on the correspondence between the first thread and the second thread, the first adaptive matrix is ​​the same as the second adaptive matrix.

17. The host device as claimed in claim 13, wherein, The cache management circuitry is also configured to identify a first adaptive matrix mapped to the first thread from a management table that indicates multiple adaptive matrices mapped to multiple threads respectively.

18. The host device as claimed in claim 17, wherein, The cache management circuit is also configured to monitor the filling patterns of the plurality of paths and update the management table based on the monitoring results.

19. The host device according to any one of claims 13 to 18, wherein, The host device includes any one of a central processing unit, a graphics processing unit, and a neural network processor.

20. A method of operating a host device, the host device including a cache, wherein, The cache includes multiple paths, each of which has a region distinguished by multiple indices, and the method includes: An adaptive matrix is ​​generated based on the higher bits of the address corresponding to the data; Generate a vector based on the lower bits of the address; Perform a hash operation based on the adaptive matrix and the vector; and The data is stored in an empty region within the region corresponding to the index generated from the hash operation in the plurality of paths.

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