Hierarchical compression interconnection method, device and equipment
By using a hierarchical compression interconnection method, nodes in a PCIe switch are divided into hardware groups and software groups, generating compression results within groups and between subgroups. This solves the problems of wiring complexity and signal quality, achieves lightweight interconnection and real-time requirements, and adapts to the global and local interconnection needs of PCIe switches.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JINAN MAIWEI INTELLIGENT TECHNOLOGY CO LTD
- Filing Date
- 2026-01-20
- Publication Date
- 2026-06-09
AI Technical Summary
As the number of ports increases in PCIe switches, the fully interconnected structure leads to an exponential increase in cabling channels, resulting in cabling complexity, signal quality, and power consumption issues. Existing solutions cannot flexibly achieve lightweight design and channel reduction, and time-division multiplexing schemes cannot guarantee real-time requirements.
A hierarchical compression interconnection method is adopted, which divides nodes into hardware groups and software groups. By generating compression results within groups and between subgroups, the number and complexity of wiring are reduced, global and local interconnection is achieved, signal quality is ensured and power consumption is reduced.
It effectively reduces wiring complexity and power consumption, improves signal quality, ensures real-time performance, enables global and local interconnection, adapts to the lightweight interconnection of various PORT states of PCIe Switch, and reduces design difficulty.
Smart Images
Figure CN122173423A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data processing technology, and in particular to a hierarchical compression interconnection method, apparatus and equipment. Background Technology
[0002] High-speed serial computer expansion bus (Peripheral Component Interconnect Express, or PCIe) switch devices use ports for external communication. More powerful PCIe switches have more ports and simultaneously support multiple USPs and virtual switch functionality where each USP port is bound to different DSP port groups. PCIe switches are required to be compatible with both handling one USP bound to all other DSPs and virtual switch functionality configured with multiple USPs. In terms of interconnect structure, they must be compatible with both full interconnection of all ports and partial full interconnection of ports within a virtual switch group. In PCIe switches, as the number of ports increases, a full interconnection structure leads to an exponential increase in wiring channels, causing wiring and timing issues.
[0003] To overcome the above problems as much as possible, some solutions exist, but these solutions have the following drawbacks: Crossbar switch solutions typically involve accessing the entire bus, making it difficult to flexibly design for lightweight status signals or reduce the number of channels. Furthermore, abstracting the master and slave devices on a crossbar switch as nodes only provides pathways between master and slave nodes, not pathways between slave nodes. Abstracting the PORT as a node also fails to meet the requirements for full interconnection between all nodes and partial full interconnection.
[0004] Time-division multiplexing scheme: cannot guarantee real-time requirements. Summary of the Invention
[0005] This application provides a layered compression interconnection method, apparatus, and device to at least solve the aforementioned technical problems in the related art.
[0006] This application provides a hierarchical compressed interconnection method applied to a hierarchical compressed interconnection system. The system includes multiple nodes, which are divided into multiple hardware groups. Each node is configured into at least one software group, and any node is in only one software group. Each node corresponds to one port. The method includes: Receive a request from the first node to obtain the node status. The request is used to determine the port status information of the preset nodes in the target software group to which the first node belongs. Based on the request, obtain the node identification information and port status information of all nodes in each hardware group; Based on the node identifier information of all target nodes in the Nth hardware group that match the preset node, the pre-configured initial mask is updated to obtain the Nth updated mask, where N is a positive integer; Based on the port status information of all nodes in the first hardware group to which the first node belongs, the pre-configured exclusion code corresponding to the first node, and the first update mask corresponding to the first hardware group, the intra-group compression result is generated. The first hardware group is one of multiple hardware groups. Based on the port status information of all nodes in the second hardware group other than the first hardware group and the second update mask corresponding to the second hardware group, the inter-subgroup compression result is generated. The second hardware group is any hardware group other than the first hardware group among multiple hardware groups. After generating the inter-subgroup compression results for each hardware group other than the first hardware group, the port status information of the preset node in the target software group to which the first node belongs is determined based on all the inter-subgroup compression results and the intra-group compression results. The port status information of the preset nodes in the target software group to which the first node belongs is fed back to the first node.
[0007] This application also provides a hierarchical compression interconnection device applied to a hierarchical compression interconnection system. The system includes multiple nodes, which are divided into multiple hardware groups. Each node is configured to at least one software group, and any node is in only one software group. Each node corresponds to one port. The device includes: The receiving module is used to receive a request from the first node to obtain the node status. The request is used to determine the port status information of a preset node in the target software group to which the first node belongs. The acquisition module is used to obtain the node identification information and port status information of all nodes in each hardware group according to the request. The mask update module is used to update the pre-configured initial mask based on the node identification information of all target nodes that match the preset node in the Nth hardware group, and obtain the Nth updated mask, where N is a positive integer; The processing module is used to generate intra-group compression results based on the port status information of all nodes in the first hardware group to which the first node belongs, the pre-configured exclusion code corresponding to the first node, and the first update mask corresponding to the first hardware group. The first hardware group is one of multiple hardware groups. Based on the port status information of all nodes in the second hardware group other than the first hardware group and the second update mask corresponding to the second hardware group, the module generates inter-subgroup compression results based on the port status information of all nodes in the second hardware group other than the first hardware group. The second hardware group is any hardware group other than the first hardware group. After generating the inter-subgroup compression results for each hardware group other than the first hardware group, the module determines the port status information of the preset nodes in the target software group to which the first node belongs based on all inter-subgroup compression results and intra-group compression results. The sending module is used to send back the port status information of preset nodes in the target software group to which the first node belongs to the first node.
[0008] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described layered compression interconnection methods.
[0009] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described layered compression interconnection methods.
[0010] According to this application, when the software group consists of only one software group, the above method performs global interconnection, while when the number of software groups includes multiple software groups, it performs local interconnection.
[0011] In global interconnection, for N hardware groups, each hardware group will generate a subgroup compression result corresponding to a software group, so N wiring is required. The generation of each intergroup compression result requires N-1 wiring, and the final result requires one wiring. Therefore, the final requirement is N(N-1) wiring.
[0012] In partial interconnection, since it needs to be divided into K software groups, the final required cabling is KN(N-1) cabling.
[0013] In either case, this approach significantly reduces the complexity compared to the O(N²M²) wiring complexity of related technologies, including the number of wirings and channels. This naturally reduces wiring complexity, improves signal quality, and lowers power consumption. Furthermore, this method allows for flexible implementation of both global and local interconnects, ensuring that the PCIe Switch is compatible with both full interconnection of all ports and local full interconnection of ports within a VirtualSwitch group. This interconnection method is a lightweight interconnection oriented towards the state of each port on the PCIe Switch, not an interconnection of communication lines within the PCIe Switch, and does not affect the original enumeration and communication processes of the PCIe Switch. The structure is easily expandable, reducing design complexity. Attached Figure Description
[0014] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0015] Figure 1 This is a schematic flowchart of a layered compression interconnection method provided in an embodiment of this application; Figure 2 This is a schematic diagram illustrating the principle structure of a layered compression interconnection method provided in an embodiment of this application. Figure 3 A schematic diagram of another layered compression interconnection method provided in this application embodiment; Figure 4 The Nth hardware group provided in the embodiments of this application may include K inter-subgroup compression and a maximum of M intra-group compression. Figure 5 A simplified schematic diagram illustrating the principle of a specific application example of a hierarchical compression interconnection method provided in this application embodiment; Figure 6 A schematic diagram of a layered compression interconnection device structure provided in an embodiment of this application; Figure 7 This is a schematic diagram of an electronic device structure provided in an embodiment of this application. Detailed Implementation
[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.
[0017] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.
[0018] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0019] PCIe switch devices use ports for external communication. Ports can be USPs or DSPs, depending on functional requirements. Each PCIe switch device supports one USP bound to all other DSPs. More powerful PCIe switches have more ports and simultaneously support multiple USPs and different DSPs bound to each USP port, forming a virtual switch group. Within the virtual switch functional division, the USPs and their bound DSPs are considered a virtual switch group. PCIe switches are hardware-required to be compatible with both handling one USP bound to all other DSPs and virtual switching when configured with multiple USPs.
[0020] PCIe has functions requiring real-time processing, such as flow control and power management. Each port on a PCIe switch needs to obtain the output status of other ports as a basis for decision-making. This necessitates a lightweight, fully interconnected structure for the output status signals between each related port to obtain the required input. Furthermore, these functions have real-time requirements, making time-division multiplexing an incompatible solution. If Virtual Switch functionality is supported, lightweight, localized, fully interconnected status signals for ports within a Virtual Switch group must also be implemented. Therefore, the interconnection structure must simultaneously support both full interconnection of all ports and localized full interconnection of ports within a Virtual Switch group. This interconnection is a lightweight interconnection oriented towards the status of each port on the PCIe switch, not an interconnection of communication lines within the PCIe switch, and does not affect the original enumeration and communication processes of the PCIe switch.
[0021] In PCIe switches, as the number of ports increases, the fully interconnected architecture leads to an exponential increase in cabling channels, causing cabling and timing issues. Assuming a PCIe switch has a total of N*M ports, divided into N groups, with M ports in each group, the number of interconnecting channels in a traditional fully interconnected architecture follows an O(N²M²) growth pattern. When N=9 and M=8, the number of channels reaches as high as 5112. A large number of cabling channels leads to the following problems: 1. Exponential cabling complexity: The number of interconnect channels in traditional fully interconnected architectures follows an O(N²M²) growth pattern. When N=9 and M=8, the number of channels reaches as high as 5112. Too much cabling leads to increased design complexity and physical implementation difficulties due to cabling congestion.
[0022] 2. Signal quality issues: Too many cabling channels may lead to cabling congestion and tangling, resulting in a decrease in the channel's frequency. At high frequencies, the signal quality of the channel will be reduced due to excessively dense cabling channels and interference from noise.
[0023] 3. Power consumption issues: Too many wiring channels may cause wiring to become tangled, thus increasing the wiring distance and leading to uncontrolled dynamic power consumption due to capacitor charging and discharging caused by a large number of wirings.
[0024] The current full and partial interconnection structures between ports within a PCIe switch have the following drawbacks: - Crossbar switch solutions typically involve accessing the entire bus, making it difficult to flexibly design lightweight solutions and reduce channels for status signals. Furthermore, abstracting the master and slave devices on a crossbar switch as nodes only provides pathways between master and slave nodes, not pathways between slave nodes. Abstracting the PORT as a node also fails to meet the requirements of full interconnection and partial full interconnection between all nodes mentioned in this patent.
[0025] - Time-division multiplexing scheme: cannot guarantee real-time requirements.
[0026] To address the aforementioned problems, embodiments of this application provide a hierarchical compressed interconnection method. This method is applied to a hierarchical compressed interconnection system, which includes multiple nodes. These nodes are divided into multiple hardware groups, and each node is configured into at least one software group. Any node resides in only one software group, and each node corresponds to one port. See details... Figure 1 As shown, the method includes the following steps: Step S101: Receive a request from the first node to obtain the node status.
[0027] Specifically, this request is used to determine the port status information of preset nodes in the target software group to which the first node belongs.
[0028] See details Figure 2 As shown, Figure 2 The diagram illustrates a proposed structure for a hierarchical compressed interconnect system. Figure 2 The example only shows one hardware group, which includes M nodes ( Figure 2 (Not shown in the image), each node corresponds to a port. For example... Figure 2 The diagram shows PORT1 to PORTM.
[0029] Suppose the request sent by the first node to obtain the node status corresponds to the hardware group to which the first node belongs, for example, the first hardware group. Figure 2 The diagram illustrates the first hardware group corresponding to compression 1 within the group. Correspondingly, the target software group to which the first node belongs is the first software group. Figure 2 The diagram illustrates the structure of the first inter-subgroup compression in the first software group (e.g., the inter-subgroup compression operation performed by the first hardware group is inter-subgroup compression 1_1). This diagram mainly shows the process of performing corresponding operations on the port status information of all nodes included in the first hardware group to generate the first inter-subgroup compression result.
[0030] Step S102: Based on the request, obtain the node identification information and port status information of all nodes in each hardware group.
[0031] Specifically, according to the request, it is necessary to obtain not only the node identification information and port information of all nodes in the hardware group to which the first node belongs, but also the node identification information and port status information of all nodes in other hardware groups. This is because other hardware groups may also include nodes belonging to the same software group as the first node. These parameters are needed when performing corresponding inter-group compression operations based on the port status information of nodes in each hardware group; therefore, it is necessary to obtain the node identification information and port status information corresponding to each node. It should also be noted that obtaining the port status information of nodes in each hardware group, as described above, is primarily used when performing inter-subgroup compression operations and intra-group compression operations. The difference from related technologies is that these wirings only need to be laid out to the components performing the corresponding operations, such as the CPU, and do not require interconnection between all nodes.
[0032] Step S103: Update the pre-configured initial mask based on the node identifier information of all target nodes that match the preset node in the Nth hardware group, and obtain the Nth updated mask.
[0033] Specifically, N is a positive integer. Updating the pre-configured initial mask aims to select port status information from nodes within the target software group for calculation, while masking port status information from nodes not belonging to the target software group. This avoids interference with the calculation. The principle is that the first node only cares about the port status information of other nodes within the same software group. The port status information of other nodes is not within its scope of interest and therefore is not calculated.
[0034] Step S104: Generate intra-group compression results based on the port status information of all nodes in the first hardware group to which the first node belongs, the pre-configured exclusion code corresponding to the first node, and the first update mask corresponding to the first hardware group.
[0035] Specifically, the first hardware group is one of multiple hardware groups. The exclusion code is used to indicate whether the current calculation includes the first node. For example, if the position number corresponding to the first node in the exclusion code is 0, it means it is not included; if it is 1, it means it is included. Whether the first node is included is determined based on the actual situation, which will not be elaborated here.
[0036] Therefore, in a specific example, based on the port status information of all nodes in the first hardware group to which the first node belongs, the pre-configured exclusion code corresponding to the first node, and the first update mask corresponding to the first hardware group, the intra-group compression result is generated, which specifically includes the following steps: Step a1: Based on the exclusion code, determine whether the port status information of the first node is effective, and generate the first group of internal compression sub-results.
[0037] Step a2: Generate the intra-group compression result based on the first intra-group compression sub-result and the first update mask.
[0038] For specific examples, see, for instance. Figure 2 As shown, Figure 2 The diagram illustrates a simplified process of intra-group compression in the first hardware group. For example, the port status of the first node is determined to be invalid based on the exclusion code, while the first update mask is used to indicate that port 1 and port 2 are valid. That is, port 1 and port 2 both belong to the target software group. Other ports in the first hardware group other than port 1 and port 2 are invalid. Then, the mask value of the position corresponding to other ports in the first update mask will represent invalidity, for example, 0. The first update mask as a whole is 11000000 (assuming 1 is the valid bit).
[0039] After processing based on the first group's compression sub-result and the first update mask, the generated group's compression result shows that ports 1 and 2 are valid, while the status of other ports is invalid, represented as 01000000. It should be noted that the 1 in 01000000 represents that only the port status of port 2 is obtained during this calculation process.
[0040] Then, based on 01000000, further compression can be performed to obtain the intra-group compression result. In an optional example, the intra-group compression result is a 1-bit signal.
[0041] In an optional example, each port status is represented, for example, as a 1-bit wide digital electrical signal. For instance, if the statistics are for the "flow control" status of port 2, suppose a port status of 1 means "congested, data transmission needs to stop" and a port status of 0 means "unimpeded, data can be received".
[0042] During the compression process, it is necessary to determine whether the port status of any port in the hardware group is congested, for example, port 2 in this application file is congested. In this case, the compression result for the group is "congested". Otherwise, the compression result for the group is "unimpeded".
[0043] Step S105: Generate inter-subgroup compression results based on the port status information of all nodes in the second hardware group (excluding the first hardware group) and the second update mask corresponding to the second hardware group.
[0044] The second hardware group is any hardware group other than the first hardware group among multiple hardware groups.
[0045] For details, please refer to [link / reference]. Figure 2 As shown, Figure 2 The diagram illustrates, for example, the inter-subgroup compression process. Based on the port status information of the M PORT ports in the first hardware group and the first update mask corresponding to the first hardware group (i.e., 11000000), a first set of computation results is generated. Then, a logical operation is performed on the first set of computation results to obtain a 1-bit signal, which serves as the final inter-subgroup compression result. In other words, similar to the intra-group compression result, the inter-group compression result is a 1-bit signal.
[0046] The reason for adjusting both intra-group and inter-group compression results to 1-bit signals is that signals can be transmitted through a single channel, reducing the number of channels and wiring, lowering wiring complexity, improving signal quality, and reducing power consumption.
[0047] In an optional example, Figure 2 All operations in the code, such as operation S, operation T, operation X, operation Z, etc., are logical AND operations or logical OR operations.
[0048] The specific operation method to be used depends on whether the valid bit of the port status is high or low in the actual situation, and whether 0 or 1 is valid in the update mask. In other words, it is determined according to the actual situation, so no restrictions are imposed here.
[0049] Step S106: After generating the inter-subgroup compression results for each hardware group other than the first hardware group, determine the port status information of the preset node in the target software group to which the first node belongs based on all the inter-subgroup compression results and intra-group compression results.
[0050] Step S107: Feed back the port status information of the preset nodes in the target software group to which the first node belongs to the first node.
[0051] Specifically, the preset node essentially determines whether the first node is included. When the exclusion code determines that the first node is valid, the preset node will include all nodes in the target software group, meaning that the port status information of all nodes will be fed back to the first node. Otherwise, the port status information of all nodes in the target software group except the first node will be fed back to the first node.
[0052] However, it should be noted that during the process of obtaining the port status of each preset node in the target software group to which the first node belongs, it is not necessary to perform the compression operation between the first subgroups. This description is only for the purpose of fully illustrating the technical solution of this application. As mentioned above, when determining the port status information of the preset nodes in the target software group, the method used is to exclude... Figure 2 The inter-group compression results determined in the hardware groups other than neutron group compression 1_1, and the intra-group compression results corresponding to the first hardware group, are used to determine this. The reason for this is... Figure 2 The illustration of inter-subgroup compression 1_1 is merely symbolically intended to illustrate the specific implementation process of each inter-subgroup compression operation. That is, the implementation process of other inter-subgroup compression operations is similar to that of inter-subgroup compression 1_1, and will not be elaborated further here. See also... Figure 2 As shown, Figure 2 The diagram illustrates that MUX is used to select the inter-subgroup compression operation results corresponding to the target software group for subsequent calculations. The selection here is actually to exclude inter-subgroup compression 1_1.
[0053] The hierarchical compression interconnection method provided in this application embodiment performs global interconnection when the software group includes only one software group, and local interconnection when the number of software groups includes multiple software groups.
[0054] In global interconnection, for N hardware groups, each hardware group will generate a subgroup compression result corresponding to a software group, so N wiring is required. The generation of each intergroup compression result requires N-1 wiring, and the final result requires one wiring. Therefore, the final requirement is N(N-1) wiring.
[0055] In partial interconnection, since it needs to be divided into K software groups, the final required cabling is KN(N-1) cabling.
[0056] In either case, this approach significantly reduces the complexity compared to the O(N²M²) wiring complexity of related technologies, including the number of wirings and channels. This naturally reduces wiring complexity, improves signal quality, and lowers power consumption. Furthermore, this method allows for flexible implementation of both global and local interconnects, ensuring that the PCIe Switch is compatible with both full interconnection of all ports and local full interconnection of ports within a VirtualSwitch group. This interconnection method is a lightweight interconnection oriented towards the state of each port on the PCIe Switch, not an interconnection of communication lines within the PCIe Switch, and does not affect the original enumeration and communication processes of the PCIe Switch. The structure is easily expandable, reducing design complexity.
[0057] In an optional example, based on the foregoing embodiments, the port status information of preset nodes in the target software group to which the first node belongs is determined according to the compression results between all subgroups and the compression results within the group. See details... Figure 3 As shown, it includes: Step S301: Perform a merging logic operation on the compression results between subgroups to obtain the compression results between subgroups corresponding to the target software group.
[0058] Step S302: Merge the inter-group compression results and the intra-group compression results to obtain the port status information of the preset nodes in the target software group to which the first node belongs.
[0059] For details, see Figure 2 As shown, the process involves performing logical operations on all inter-group compression results to obtain the final inter-group compression result. For example, the first inter-group compression result is concatenated with the second, ..., Nth inter-group compression result. Each inter-group compression result is a 1-bit result, such as 0 or 1. The N-1 inter-group compression results then constitute N-1 1-bit data units. These 1-bit data units are then subjected to AND or OR operations to obtain a single 1-bit data unit.
[0060] Then, see Figure 2 As shown, the obtained inter-group compression results and intra-group compression results are then merged and compressed again. In fact, the merging and compression operation is also a kind of "AND" or "OR" operation. The specific operation is determined according to the actual situation, and the specific selection principle is similar to that introduced above, so it will not be repeated here.
[0061] See details Figure 2 As shown, Figure 2 The diagram illustrates that for each node that issues a request, the port status information of the final preset node will be fed back to the corresponding node (the arrow in the diagram indicates the corresponding port, which is used to express that the information is fed back to the corresponding node).
[0062] In this way, the entire decision-making process is completed within one or a very few clock cycles using hardware logic gates. The latency from state perception to response is extremely low and constant, meeting the most demanding real-time control requirements. Any port can obtain a global state view based on a software-defined logic group, transcending its physical location. It can understand the status of preset nodes within its target software group within the PCIe Switch's range, thus making more intelligent decisions. It relies on pre-compressed 1-bit signals, rather than massive raw states, greatly saving cabling resources. It transforms a complex "who is where and what happened" question into a simple "yes / no" question, making port control logic very simple and fast. This is the foundation for achieving "Virtual Switch" performance isolation and Quality of Service (QoS). It ensures that flow control and power management within a virtual group are self-consistent and efficient, unaffected by physical dispersion. It achieves a perfect closed loop from complex perception to efficient execution.
[0063] Further, see Figure 4 As shown, Figure 4 This illustrates that the Nth hardware group can include K inter-group compressions and at most M intra-group compressions. This is because, for each hardware group, its nodes can be assigned to at most K software groups, and for each software group, the following process needs to be executed: Figure 2 The process corresponding to one inter-subgroup compression shown in the diagram generates one inter-subgroup compression result, so it includes a total of K inter-subgroup compressions (N_K1 to N_KK). However, assuming that M nodes in the hardware group all issue requests to obtain node status, then at most M intra-group compression operations are required, so it includes M intra-group compressions (N_M1 to N_MM).
[0064] In an optional embodiment, when the i-th node is not determined to be assigned to a fixed software compression group, the method further includes the following method steps, as detailed below: Step b1: Obtain the compression results between all groups.
[0065] Step b2: After determining the software group to which the i-th node belongs, select the inter-group compression result corresponding to the software group to which the i-th node belongs from all inter-group compression results; Step b3: Based on the inter-group compression result corresponding to the software group of the i-th node and the intra-group compression result corresponding to the hardware group to which the i-th node belongs, determine the port status information of the preset nodes in the software group of the i-th node and feed it back to the i-th node.
[0066] Specifically, the process of obtaining the compression results between all groups is described above and will not be repeated here. Then, after determining the software group to which the i-th node belongs, the port status information of the preset nodes in the software group of the i-th node, which is finally determined according to the aforementioned steps, is fed back to the i-th node.
[0067] In an optional example, considering that in practical applications, in addition to knowing the status information of which ports, it is also necessary to know the corresponding responsiveness of the port status information and the urgency of the inflow to flow control, the embodiments of this application may also include the following: Obtain the influencing factors corresponding to the port status information, as well as the weight information corresponding to the port; Based on the impact factors and the mapping relationship corresponding to the impact factors, the impact level corresponding to the urgency is determined; Based on the impact level and weight information, determine the weighted urgency information corresponding to the port status.
[0068] A specific expression is, for example, weighted urgency information.
[0069] Among them, Weight is the weight information corresponding to the port information, and its impact is basically the impact level corresponding to the urgency of the port status information.
[0070] Then, after obtaining the weighted urgency information for each port, it also includes using an exclusion code to determine whether the weighted urgency information corresponding to the port that sent the request is included. Regardless of whether it is included, the maximum value is selected from the weighted urgency information corresponding to each port in the hardware group and output, thereby informing the port that sent the request which port has the most urgent current port status in the same target software group.
[0071] In a specific example, taking flow control calculation as an example, a local weighted congestion level (WCL) value is calculated in real time.
[0072] The congestion level CL value has a bit width of 3 bits, which can represent 8 levels (0-7).
[0073] Computational logic (example): CL=0: Buffer occupancy <25% (fully unobstructed) CL=1: 25% <= occupancy rate < 40% CL=2: 40% <= occupancy rate < 55% CL=3: 55% <= Occupancy rate < 70% (mild congestion) CL=4: 70% <= occupancy rate < 80% CL=5: 80% <= occupancy rate < 90% (moderate congestion) CL=6: 90% <= occupancy rate < 98% (severe congestion) CL=7: Occupancy rate >= 98% (about to overflow, extreme congestion) Each port has a pre-configured static weight value that reflects its importance in the system.
[0074] Weight bit width: Assuming it is 2 bits, it can represent 4 priorities (0-3).
[0075] Assignment example: Weight=3: High-performance GPU port Weight=2: High-speed network card port, NVMe controller port Weight=1: General purpose I / O port Weight=0: Management port (or can be ignored) Before reporting its status to the outside world, the port first combines its local CL with its own weight to obtain a "weighted flow control level".
[0076] Calculation formula: .
[0077] 1. Weighted flow control level (WCL) for each of the M ports in the group (assuming it is 6 bits wide, because 3 bits CL * maximum weight 4 = maximum value of 20, which requires 5 bits, rounded to 6 bits).
[0078] Masking: Similar to before, use an "exclusion code" to mask the WCL of its own port to 0.
[0079] Compression operation: Instead of a multi-input OR gate, it is a multi-input maximum value comparator (MaxFinder).
[0080] The circuit compares all unmasked WCL values in parallel and outputs the largest WCL value.
[0081] Output: A 6-bit value representing "the most congestion level among all Group_A members except myself within this group".
[0082] 2. When performing inter-group compression, the following may also be included: Input: WCL of M ports in this hardware group.
[0083] Masking: Filtering is performed using the "update mask" generated by DMMU. Ports not belonging to the target software group have their WCL set to 0.
[0084] Compression operation: Also uses a multi-input maximum value comparator.
[0085] Output: A 6-bit value representing "the most significant congestion level among all Group_A members in this hardware group".
[0086] 3. When performing a merge and compression operation, the following may also be included: Input: 1 6-bit result from the ICU, and (N-1) 6-bit results from other groups of GCU.
[0087] Merge operation: Perform the maximum value comparison again on these (N) 6-bit inputs.
[0088] Final output: a 6-bit "Global Maximum Weighted Flow Control Level" (GlobalMaxWCL).
[0089] 4. After the first node receives this 6-bit "global maximum weighted flow control level" value, its flow control strategy can become very precise and intelligent.
[0090] Predefined response strategy table (example): ifGlobal_Max_WCL==0: Normal transmission, no flow control.
[0091] if1<=Global_Max_WCL<10: Slight rate limiting, reducing the sending window by 20%.
[0092] f10<=Global_Max_WCL<20: Moderate rate limiting, reducing the sending window by 50%.
[0093] ifGlobal_Max_WCL>=20: Aggressive rate limiting / pause, reducing the sending window by 80% or temporarily pausing sending.
[0094] This method represents a leap from "one-size-fits-all" flow control to "gradient rate limiting," significantly optimizing system throughput and latency. The system automatically distinguishes between critical and non-critical traffic congestion, prioritizing the quality of high-priority services. Even with low flow limit (CL) values, slight preventative rate limiting is triggered if the congestion originates from a high-weight port, preventing further congestion and improving system stability. The response is gradual, avoiding the "ping-pong effect" (oscillations caused by frequent flow control switching) of Boolean flow control. Without significantly increasing hardware complexity, intelligent, priority-based differential flow control is achieved, significantly improving the efficiency and robustness of large-scale heterogeneous computing systems.
[0095] In an optional example, see [link to example]. Figure 5 As shown, Figure 5To illustrate a specific example, in a PCIe Switch device, each port needs to obtain the cred_valid output status of other ports via a fully interconnected approach to generate its own required masknp signals. In a PCIe Switch scenario without Virtual Switches, there will be one USP and the rest will be DSPs. In a PCIe Switch scenario using Virtual Switches, for example, with two groups of Virtual Switches, each Virtual Switch group will have one USP and several DSPs; and the ports of the two Virtual Switch groups will not overlap.
[0096] In this application scenario, the masknp signals for the full interconnection structure between PORTs and the full interconnection structure between software-grouped PORTs are generated using the methods described in any of the foregoing embodiments. In this specific example, N*M=9*8, meaning the PCIe Switch has 72 PORTs, divided into 9 groups of 8 PORTs each.
[0097] 1) Each hardware group is numbered from 1 to N, where N=9; within each group, the PORTs are numbered from 1 to M, where M=8. The output status cred_valid of each PORT within a group is recorded sequentially in an M-bit array ARR. Assume that cred_valid = 1 represents non-blocking, and 0 represents blocking. In the diagram above, PORT1 and PORT8 are examples to illustrate the hardware groups to which each node belongs. PORT1 to PORT8, for example, belong to the first hardware group mentioned earlier. PORT1 is, for example, a node in the target software group corresponding to inter-group compression 1, while PORT8 belongs to a node in another software group.
[0098] 2) Inter-group compression is a bitwise OR operation between ARR[8:1] and the mask. For example, 1 in the mask indicates masking, and 0 indicates no masking. After performing the necessary logic such as bitwise AND on all bits in the array, each group outputs a single-bit signal st_sig_g*_k*. 3) Intra-group compression means that when processing the state of a PORT within a group, only the states of other PORTs are considered, without considering the state output of the PORT itself. For the state of the i-th PORT in the group, an 8-bit shift logic shifts 1 to the left by i bits. The output of the shift logic is in the form of a one-hot code (where 1 indicates a valid state (i.e., excluded), and the valid bits in the one-hot code are 1 and the other bits are 0; or, assuming 0 indicates a valid state (i.e., excluded), the valid bits in the one-hot code are 0 and the other bits are 1). The state of the i-th PORT in the group is obtained by performing a bitwise OR operation between the one-hot code and the M-bit array ARR. If we consider the software dynamic configuration grouping Virtual Switch Group 1 and Virtual Switch Group 2. For all PORTs in Virtual Switch Group 1, set the corresponding maskA in "Group Compression Unit 1" to 0, and set the mask bits of those not in Virtual Switch Group 1 to 1; OR the result of ARR with the one-hot code, and OR it with the mask to mask the PORTs not in this Virtual Switch group, and obtain the st_inside_g*_p* of each PORT (here, 1 in each bit signal represents non-blocking, and 0 represents blocking). The figure shows the 8 PORTs of Group 1, corresponding to st_inside_g1_p1~p8[8:1]; perform a bitwise AND operation on the bits of st_inside_g1_p1~p8[8:1] to output st_inside_p*.
[0099] In an optional example, if the signal frequency is high, the result of performing a bitwise AND operation on each bit of st_inside_g1_p1~p8[8:1] is scalded through a register to form st_inside_p*; 4) Merge compression interconnects to introduce inter-group compression output st_other_tot_g*_k*, and introduce intra-group compression output st_inside_p*; first select the specific signal st_other_tot_g*_k* in the same software group as the PORT corresponding to the combined compression in operation Z, and then perform the operation. The final output is the state input required by the PORT.
[0100] 5) If you want to be compatible with both full interconnection and partial full interconnection, that is, when both full interconnection and Virtual Switch scenarios are applicable, for example, if there are 2 Virtual Switches, the compression component in the group needs to use 2.
[0101] For example, software dynamically configures PORT1~PORT4 and PORT9~PORT12 in Virtual Switch group 1; software dynamically configures PORT5~PORT8 and PORT13~PORT16 in Virtual Switch group 2. In Virtual Switch group 1, within the hardware group's compression 1, the mask should be set to 0xf0 to disable unused PORT5~PORT8. In Group 2 of the hardware group, within Compressor 1, the mask should be set to 0xf0 to block PORTs 13-16, which are not used by the Virtual Switch. For Virtual Switch Group 2, in Group 1 of the hardware group, within Compressor 2, the mask should be set to 0x0f to block PORTs 1-4, which are not used; in Group 2 of the hardware group, within Compressor 2, the mask should be set to 0x0f to block PORTs 9-12, which are not used by the Virtual Switch. In this specific example, the mask and exclusion code are illustrated using hexadecimal, but they can also be in binary. The specific representation can be set according to the actual situation; no restrictions are placed here.
[0102] All other ports not included in these two software groups are blocked.
[0103] 6) Mask out the ports that do not need to be involved in the calculation, and then let all ports participate in the calculation.
[0104] It should be noted that, Figure 5 The diagram also illustrates that for each hardware group, a maximum of k inter-subgroup compression operations will be performed. That is, for each software group, if a node belonging to that software group exists within the hardware group, an inter-subgroup compression operation will be performed once. Therefore, as... Figure 5 As shown, Figure 5 Assuming each hardware group contains nodes from k software groups, for each hardware group, k inter-subgroup compression operations are performed, i.e. Figure 5 The diagram illustrates the inter-group operation results for subgroups such as 1×k and 2×k. Then, for each software group, the corresponding inter-group operation results are selected and communicated to generate the inter-group operation result, which is essentially performing a MUX operation to obtain the inter-group compression result. Furthermore, when determining the inter-group compression corresponding to a specific port, the MUX method can be used to select the inter-group compression result corresponding to the software group where the port belongs and the intra-group compression result corresponding to the hardware group where the port belongs, and combine them to generate the final result. The specific implementation process has been detailed above, so it will not be elaborated further here.
[0105] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.
[0106] Embodiments of this application also provide a hierarchical compression interconnection device. The device is applied to a hierarchical compression interconnection system, which includes multiple nodes. These nodes are divided into multiple hardware groups, and each node is configured into at least one software group. Any node resides in only one software group, and each node corresponds to one port. See details [link to specific documentation]. Figure 6 As shown, the device includes: a receiving module 601, an acquisition module 602, a mask update module 603, a processing module 604, and a sending module 605.
[0107] The receiving module 601 is used to receive a request from the first node to obtain the node status. The request is used to determine the port status information of a preset node in the target software group to which the first node belongs. The acquisition module 602 is used to acquire the node identification information and port status information of all nodes in each hardware group according to the request. The mask update module 603 is used to update the pre-configured initial mask based on the node identification information of all target nodes that match the preset node in the Nth hardware group, and obtain the Nth updated mask, where N is a positive integer; The processing module 604 is used to generate intra-group compression results based on the port status information of all nodes in the first hardware group to which the first node belongs, the pre-configured exclusion code corresponding to the first node, and the first update mask corresponding to the first hardware group. The first hardware group is one of multiple hardware groups. The module is used to generate inter-subgroup compression results based on the port status information of all nodes in the second hardware group other than the first hardware group and the second update mask corresponding to the second hardware group. The second hardware group is any hardware group other than the first hardware group. After generating the inter-subgroup compression results corresponding to each hardware group other than the first hardware group, the module determines the port status information of the preset nodes in the target software group to which the first node belongs based on all inter-subgroup compression results and intra-group compression results. The sending module 605 is used to send back the port status information of preset nodes in the target software group to which the first node belongs to the first node.
[0108] In an optional example, processing module 604 is specifically used to perform merging logic operations on the inter-group compression results to obtain the inter-group compression results corresponding to the target software group. The inter-group compression results and intra-group compression results are merged to obtain the port status information of the preset nodes in the target software group to which the first node belongs.
[0109] In an optional example, the mask update module 603 is specifically used to determine the sorting order of the target nodes in the Nth hardware group based on the node identification information of all target nodes that match the preset node in the Nth hardware group. Based on the sorting order, the mask positions in the initial mask that correspond to the sorting order are designated as valid bits.
[0110] In an optional example, processing module 604 is specifically used to determine whether the port status information of the first node is effective based on the exclusion code, and generate the first group of internal compression sub-results; Based on the first group's compression sub-results and the first update mask, generate the group's compression results.
[0111] In an optional example, the combined logical operations include logical AND or logical OR operations.
[0112] In one optional example, the in-group compression result is a 1-bit signal.
[0113] In one optional example, the inter-group compression result is a 1-bit signal.
[0114] The description of the features of the hierarchical compression interconnection device provided in this application can be found in the relevant description of the hierarchical compression interconnection method, which will not be repeated here.
[0115] The hierarchical compression interconnection device provided in this application performs global interconnection when the software group includes only one software group, and local interconnection when the number of software groups includes multiple software groups.
[0116] In global interconnection, for N hardware groups, each hardware group will generate a subgroup compression result corresponding to a software group, so N wiring is required. The generation of each intergroup compression result requires N-1 wiring, and the final result requires one wiring. Therefore, the final requirement is N(N-1) wiring.
[0117] In partial interconnection, since it needs to be divided into K software groups, the final required cabling is KN(N-1) cabling.
[0118] In either case, this approach significantly reduces the complexity compared to the O(N²M²) wiring complexity of related technologies, including the number of wirings and channels. This naturally reduces wiring complexity, improves signal quality, and lowers power consumption. Furthermore, this method allows for flexible implementation of both global and local interconnects, ensuring that the PCIe Switch is compatible with both full interconnection of all ports and local full interconnection of ports within a VirtualSwitch group. This interconnection method is a lightweight interconnection oriented towards the state of each port on the PCIe Switch, not an interconnection of communication lines within the PCIe Switch, and does not affect the original enumeration and communication processes of the PCIe Switch. The structure is easily expandable, reducing design complexity.
[0119] Embodiments of this application also provide an electronic device, such as... Figure 7 As shown, it includes a memory 10 and a processor 20, the memory 10 storing a computer program, and the processor 20 being configured to run the computer program to perform the steps in any of the above-described hierarchical compressed interconnection method embodiments.
[0120] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described hierarchical compression interconnection method embodiments at runtime.
[0121] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.
[0122] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described hierarchical compression interconnection method embodiments.
[0123] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0124] The foregoing has provided a detailed description of a layered compression interconnection method, apparatus, and device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to aid in understanding the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. A hierarchical compression interconnection method, characterized by, The method is applied to a hierarchical compression interconnection system, the system comprising multiple nodes, the multiple nodes being divided into multiple hardware groups, and each of the multiple nodes being configured into at least one software group, with any node residing in only one software group, and each node corresponding to one port. The method includes: Receive a request from the first node to obtain the node status, the request being used to determine the port status information of a preset node in the target software group to which the first node belongs; According to the request, obtain the node identification information and port status information of all nodes in each hardware group; Based on the node identifier information of all target nodes in the Nth hardware group that match the preset node, the pre-configured initial mask is updated to obtain the Nth updated mask, where N is a positive integer; Based on the port status information of all nodes in the first hardware group to which the first node belongs, the pre-configured exclusion code corresponding to the first node, and the first update mask corresponding to the first hardware group, an intra-group compression result is generated. The first hardware group is one of the multiple hardware groups. Based on the port status information of all nodes in the second hardware group other than the first hardware group and the second update mask corresponding to the second hardware group, an inter-subgroup compression result is generated. The second hardware group is any hardware group other than the first hardware group among the multiple hardware groups. After generating the inter-subgroup compression results for each hardware group other than the first hardware group, the port status information of the preset node in the target software group to which the first node belongs is determined based on all the inter-subgroup compression results and the intra-group compression results. The port status information of the preset nodes in the target software group to which the first node belongs is fed back to the first node.
2. The method according to claim 1, characterized in that, The step of determining the port status information of the preset node in the target software group to which the first node belongs, based on all the inter-subgroup compression results and the intra-group compression results, specifically includes: The inter-group compression results are merged logically to obtain the inter-group compression result corresponding to the target software group; The inter-group compression results and the intra-group compression results are merged to obtain the port status information of the preset nodes in the target software group to which the first node belongs.
3. The method according to claim 1 or 2, characterized in that, The step of updating the pre-configured initial mask based on the node identifier information of all target nodes in the Nth hardware group that match the preset node specifically includes: Based on the node identifier information of all target nodes in the Nth hardware group that match the preset node, determine the sorting order of the target node in the Nth hardware group; According to the sorting order, the mask positions in the initial mask that correspond to the sorting order are designated as valid bits.
4. The method according to claim 1 or 2, characterized in that, The step of generating an intra-group compression result based on the port status information of all nodes in the first hardware group to which the first node belongs, the pre-configured exclusion code corresponding to the first node, and the first update mask corresponding to the first hardware group specifically includes: Based on the exclusion code, determine whether the port status information of the first node is effective, and generate the first group of internal compression sub-results; The intra-group compression result is generated based on the first intra-group compression sub-result and the first update mask.
5. The method according to claim 2, characterized in that, The combined logical operation includes logical AND or logical OR operations.
6. The method according to claim 1 or 2, characterized in that, The compression result within the group is a 1-bit signal.
7. The method according to claim 5, characterized in that, The inter-group compression result is a 1-bit signal.
8. A hierarchical compression interconnection device, characterized in that, The device is applied to a hierarchical compression interconnection system, the system comprising multiple nodes, the multiple nodes being divided into multiple hardware groups, and each of the multiple nodes being configured into at least one software group, with any node residing in only one software group, and each node corresponding to one port. The device includes: The receiving module is used to receive a request from the first node to obtain the node status, the request being used to determine the port status information of a preset node in the target software group to which the first node belongs; The acquisition module is used to acquire, according to the request, the node identification information and port status information of all nodes in each hardware group; The mask update module is used to update the pre-configured initial mask based on the node identification information of all target nodes that match the preset node in the Nth hardware group, and obtain the Nth updated mask, where N is a positive integer; The processing module is configured to generate intra-group compression results based on the port status information of all nodes in a first hardware group to which the first node belongs, a pre-configured exclusion code corresponding to the first node, and a first update mask corresponding to the first hardware group, wherein the first hardware group is one of a plurality of hardware groups; generate inter-subgroup compression results based on the port status information of all nodes in a second hardware group other than the first hardware group and a second update mask corresponding to the second hardware group, wherein the second hardware group is any hardware group other than the first hardware group; after generating inter-subgroup compression results for each hardware group other than the first hardware group, the module determines the port status information of preset nodes in the target software group to which the first node belongs based on all the inter-subgroup compression results and the intra-group compression results; The sending module is used to send back the port status information of preset nodes in the target software group to which the first node belongs to the first node.
9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the hierarchical compressed interconnect method as described in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the steps of the hierarchical compression interconnection method according to any one of claims 1 to 7.