Interface conversion device, chip debugging system, system on chip and electronic equipment
By using an interface conversion device and a custom debugging interface protocol, the problems of low SPI interface speed and difficulty in timing convergence during chip debugging are solved, achieving efficient and reliable chip debugging.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING TSINGMICRO INTELLIGENT TECH CO LTD
- Filing Date
- 2026-02-13
- Publication Date
- 2026-06-09
AI Technical Summary
Existing chip debugging technologies suffer from low SPI interface speed, excessive number of internal subsystem ports, and difficulty in timing convergence, resulting in low debugging efficiency and high complexity.
An interface conversion device is used to convert external SPI signals into a custom debugging interface protocol. Communication is achieved through two global signal lines, and an asynchronous clock design and parity check retransmission mechanism are used to realize full-duplex communication.
Significantly increases the SPI interface rate to 30Mb, reduces the number of internal subsystem ports, reduces timing convergence difficulty, improves transmission reliability, and simplifies chip design.
Smart Images
Figure CN122173426A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip debugging technology, specifically to an interface conversion device, a chip debugging system, a system-on-a-chip, and electronic equipment. Background Technology
[0002] With the rapid development of integrated circuit technology, the complexity of System-on-Chip (SoC) chips is constantly increasing, especially in the field of artificial intelligence chips, where multi-subsystem architecture has become the mainstream design scheme. To ensure the correctness of chip functionality and the optimization of performance, chip debugging systems play a crucial role throughout the entire design process. Traditional chip debugging schemes mainly rely on standard debugging protocols such as JTAG and SPI interfaces, which enable communication between external debugging equipment and the chip's internal debugging resources.
[0003] However, existing chip debugging technologies still face numerous technical challenges and limitations in practical applications. First, traditional debugging interfaces have low data transmission rates, especially the SPI interface used as an external debugging interface, which can only reach speeds below 10Mb. In complex chips with multi-die packages, it may even only reach around 5Mb, failing to fully utilize the maximum 30Mb support of the external microcontroller's SPI interface and severely restricting debugging efficiency. Second, internal subsystems consume excessive port resources. Traditional debugging solutions use an APB bus architecture, with each APB bus requiring at least 100 ports. In complex systems such as AI chips, the port resources of each subsystem are already limited. Numerous global traces occupy valuable routing channels, compressing the chip area available for implementing internal subsystem functions. Finally, the difficulty of timing convergence is increasingly prominent. Current debugging paths use SPI or JTAG interfaces for global routing, making signal timing difficult to converge and hindering further improvements in internal data transmission rates. This requires backend design teams to invest significant effort in timing optimization, increasing design complexity and development time. Summary of the Invention
[0004] To address the technical challenges of existing debug path design and debugging schemes, such as low SPI interface speed, excessive number of internal subsystem ports, and difficulty in timing convergence, this paper proposes an interface conversion device, a chip debugging system, a system-on-a-chip (SoC), and electronic devices. The goal is to achieve significant improvements in SPI interface speed, a substantial reduction in the number of internal subsystem ports, a significant reduction in timing convergence difficulty, full-duplex communication, and enhanced transmission reliability.
[0005] To achieve the above objectives, in some embodiments of this application, an interface conversion device is provided for a chip debugging system. The device is disposed on the top layer of the chip and adjacent to the SPI input / output pads. It is used to convert externally input SPI signals into internal signals of a custom debugging interface protocol and output them via a preset number of global signal lines. The device includes a data buffer module for matching the data transmission rate between the SPI interface and the custom debug interface.
[0006] Optionally, the device further includes: An SPI slave interface unit is used to receive the externally input SPI signal; The debugging interface host unit is connected to the data buffer module and is used to drive the internal signals.
[0007] Optionally, the debug interface host unit is configured to generate and send communication frames that conform to a custom debug interface protocol; The communication frame format includes multiple valid data bits and one parity bit.
[0008] Optionally, the debug interface host unit is further configured to perform parity checks on the received data, and to initiate a retransmission process via the two global signal lines when a check error is detected.
[0009] Optionally, the device further includes a data flow management unit connected between the SPI slave interface unit and the debug interface master unit, which manages the data flowing through the data buffer module.
[0010] Optionally, the data flow management unit includes: A buffer control unit, connected to the SPI slave interface unit, is used to control the writing of data from the SPI slave interface unit to the data buffer module; The scheduling unit is connected to the data buffer module and the debug interface host unit, respectively, and is used to read data from the data buffer module, perform protocol scheduling, and then send it to the debug interface host unit.
[0011] Optionally, the scheduling unit is further configured to encapsulate the data from the data buffer module according to the frame format of the custom debugging interface protocol.
[0012] In some embodiments of this application, a chip debugging system including the aforementioned interface conversion device is also provided, the system further comprising: One or more debug interface slave units are located within a subsystem of the chip; and One or more synchronous bridge modules are connected between the debug interface host unit and the debug interface slave unit of the interface conversion device; The debug interface host unit and the debug interface slave unit are configured to communicate in full-duplex mode through a preset number of global signal lines based on mutually asynchronous clocks; the preset number is less than the number of debug interface slave units.
[0013] Optionally, the signal timing between the debug interface host unit and the debug interface slave unit is configured as follows: In the idle state, keep the data output signal line high; When a falling edge is detected on the data input signal line, data reception begins; Receive a predetermined number of valid data bits and one parity bit in sequence; When the data input signal line is detected to return to a high level, it is determined that the current frame data transmission is complete.
[0014] Optionally, the debug interface host unit and the debug interface slave unit are further configured to perform the following retransmission mechanism: When the receiving end detects a parity error in a communication frame, it sends a retransmission request command to the sending end via a signal line. The sending end determines the position of the data frame to be retransmitted according to the retransmission request instruction, and after sending a retransmission start instruction, it retransmits data from the corresponding data frame position. When a retransmission request command or retransmission start command itself is detected to have a check error, an interrupt is triggered and the data input signal line is restored to a high level.
[0015] In some embodiments of this application, a system-on-a-chip (SoC) is also provided, comprising: The chip debugging system described above; One or more subsystems; The debug interface slave unit of each subsystem is used to convert the received internal signals into signals conforming to the APB bus protocol or the AXI bus protocol in order to access the debug resources inside the subsystem.
[0016] In some embodiments of this application, an electronic device is also provided, including the aforementioned system-on-a-chip.
[0017] The beneficial technical effects of this application are as follows: It significantly improves the SPI interface rate by placing the SPI at the chip pad, minimizing the impact of half-cycle sampling. The interface rate is 6 times higher than the current solution, reaching 30Mb. It significantly reduces the number of internal subsystem ports by using two lines for global routing through a custom debug interface, reducing the number of subsystem ports by 52 times compared to traditional methods, thus reducing area usage and congestion risk. It significantly reduces timing convergence difficulty by using an asynchronous method to greatly improve internal routing speed while ensuring data path timing. In timing-critical areas, timing convergence is achieved directly through timing, significantly reducing the difficulty of clock access, selection, and clock tree generation. It achieves full-duplex communication, requiring only two lines internally. The master and SLV use asynchronous clock sampling, minimizing the number of lines and reducing synchronous clock tree branches. It improves transmission reliability by supporting parity checking and retransmission mechanisms, ensuring better transmission correctness. Attached Figure Description
[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the application structure of a system-on-a-chip provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of the SPI slave interface unit and the debug interface master unit provided in an embodiment of this application; Figure 3 This is a schematic diagram of the connection relationship of a data flow management unit provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a data flow management unit provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a chip debugging system provided in an embodiment of this application; Figure 6 This is a timing diagram illustrating the implementation of the interface protocol according to an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a system-on-a-chip provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0019] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.
[0020] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.
[0021] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.
[0022] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed description. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.
[0023] It should be noted that, please refer to Figure 1 As shown in the following embodiments, the SPI input / output pads refer to the SPI signal pins on the chip's physical package that connect to an external host device (such as an MCU), typically located within the top-level input / output ring (IO ring) of the chip. Placing the relevant functional modules here minimizes the transmission path of high-speed SPI signals (especially half-cycle sampling signals) within the chip.
[0024] The SPI slave interface unit corresponds to Figure 1 The SPI SLV module is driven by an external MCU / SPI4 signal. As an SPI protocol slave device, it is responsible for receiving and parsing the clock (SCLK), chip select (CS), master-out-slave-in (MOSI) signals from the external host, and generating master-in-slave-out (MISO) signals.
[0025] The data buffer module corresponds to Figure 1 The data_buf module is typically a first-in, first-out (FIFO) memory used to temporarily store data. This addresses the data throughput differences caused by clock domain and rate mismatches between external SPI interfaces (e.g., 30Mb / s) and internal custom debug interfaces (e.g., 100Mb / s), ensuring a continuous and unlost data stream.
[0026] The debug interface master unit corresponds to Figure 1The debug_if_mst part within the spi2debug module is the master controller of the custom debugging interface protocol. It is responsible for organizing data frames according to the protocol and driving the td0 (data output) and sampling td1 (data input) signal lines.
[0027] The two global signal lines refer to the TD1 (debug data input) and TD0 (debug data output) signal lines that run throughout the entire chip. They form the basis for implementing the physical connections of the entire chip's debug network, and compared to the traditional APB bus (which requires dozens of lines), they greatly save wiring resources and the number of subsystem ports.
[0028] The debug interface slave unit corresponds to Figure 1 The debug_if_slv module is located at the entry point of each subsystem. As a slave device of a custom debug interface protocol, it receives protocol frames from global signal lines and converts them into standard bus transactions.
[0029] The synchronous bridge module (Pipe) corresponds to Figure 1 The pipe module in the chip is a pipelined bridge circuit composed of multi-level registers. It is inserted into long-distance global signal line paths to "beat" high-speed signals (insert registers) in order to decompose the critical path. It is a key component for realizing reliable long-distance transmission of high-speed signals within the chip and easy timing convergence.
[0030] The data flow management unit is Figure 1 This is manifested in the collaboration between spi_buf_ctrl (buffer control unit) and scheduler (scheduler unit), which is responsible for managing the conversion of data flow and control flow from the SPI side to the debug interface side.
[0031] In some embodiments of this application, an interface conversion device is provided for a chip debugging system. The device is disposed on the top layer of the chip and adjacent to the SPI input / output pads. It is used to convert externally input SPI signals into internal signals of a custom debugging interface protocol and output them via a preset number of global signal lines. The device may include a data buffer module for matching the data transmission rate between the SPI interface and the custom debugging interface. The preset number of global signal lines can be set according to actual needs, such as configuring two, three, or four global signal lines, which reduces the number of traditional APB buses, greatly saving wiring resources and the number of subsystem ports. The term "adjacent SPI input / output pads" refers to a distance of less than 3 nanometers between the interface conversion device and the SPI input / output pads; specific details can be found in [reference needed]. Figure 1As shown, the SPI (4-wire) is set below 3 nanometers, thereby minimizing the transmission path of high-speed SPI signals inside the chip.
[0032] In practice, this interface conversion device is a hardware module (which can be called spi2debug) located on the top layer of the chip and adjacent to the SPI input / output pads. The core function of this device is to convert debugging commands and data from an external debugger (via the SPI interface) into signals that conform to the internal custom debugging interface protocol, and send them to the inside of the chip through a preset number of global signal lines, such as two global signal lines (td1, td0).
[0033] For details, please refer to Figure 2 As shown, the device further includes: An SPI slave interface unit is used to receive the externally input SPI signal; The SPI slave interface unit (SPI SLV) is directly connected to the chip's SPI physical pads and receives standard 4-wire SPI signals. By placing the interface conversion device at the top level near the I / O, the path of the SPI signal (especially SCLK) from the pads to the sampling register is significantly shortened. This reduces the difficulty of meeting the stringent setup / hold time requirements of the SPI protocol (especially the half-cycle sampling requirement), making it possible to increase the SPI interface rate to over 30Mb / s.
[0034] The debugging interface host unit is connected to the data buffer module and is used to drive the internal signals.
[0035] Furthermore, the debug interface host unit is configured to generate and send communication frames conforming to a custom debug interface protocol; wherein the format of the communication frame includes multiple valid data bits and one parity bit. Moreover, the debug interface host unit is also configured to perform parity checking on received data, and to initiate a retransmission process via the two global signal lines when a parity error is detected.
[0036] The debug interface host unit (debug_if_mst) is the output interface of the interface conversion device, and its internal logic is configured to perform the following functions: Protocol frame generation: Receive data from the scheduler and encapsulate it into a specific communication frame. This frame format contains 32 bits (or other predetermined bit lengths, such as 16 bits or 64 bits) of effective data (payload), followed by a parity bit. This design significantly increases the amount of effective data transmitted in a single transmission and improves bandwidth utilization.
[0037] Signal driving and sampling: According to the custom timing, the encapsulated frame is driven serially to the td0 signal line for output. At the same time, it samples the td1 signal line to receive response data from the subsystem.
[0038] Checksum and Retransmission Control: This unit contains checksum logic. When it receives a data frame from the TD1 line, it calculates its parity bit; if the checksum fails, its retransmission control logic is triggered, initiating a retransmission process through the TD0 line, for example, by sending a retransmission request command.
[0039] Please refer to Figure 3 As shown, in some embodiments of this application, the device further includes a data flow management unit connected between the SPI slave interface unit and the debug interface master unit, and manages the data flowing through the data buffer module.
[0040] For further details, please refer to... Figure 4 As shown, the data flow management unit includes: A buffer control unit, connected to the SPI slave interface unit, is used to control the writing of data from the SPI slave interface unit to the data buffer module; A scheduling unit, connected to both the data buffer module and the debug interface host unit, is used to read data from the data buffer module, perform protocol scheduling, and then send it to the debug interface host unit. The scheduling unit also encapsulates data from the data buffer module according to the frame format of the custom debug interface protocol.
[0041] Specifically, in practical operation, the data buffer module can be integrated into the data flow management unit; thus, the data flow management unit consists of three parts: a buffer control unit, a data buffer module, and a scheduling unit, and the execution actions of each part are as follows: The buffer control unit (spi_buf_ctrl) is connected after the SPI SLV and is responsible for writing the parsed valid SPI data into the data buffer module (data_buf). It manages the write pointer and status to ensure that data does not overflow.
[0042] The data buffer module (data_buf) acts as an asynchronous FIFO or a dual-clock-domain FIFO, with its write side controlled by the SPI clock domain and its read side controlled by the debug interface clock domain. It effectively isolates the two asynchronous clock domains and buffers data to match the instantaneous rate differences between them, which is crucial for ensuring efficient data transmission.
[0043] The scheduler reads data from the data_buf and schedules and encapsulates it according to the rules of the custom debug interface protocol. Its output is connected to the debug interface host unit (debug_if_mst).
[0044] Those skilled in the art can choose the arrangement of the data buffer module according to actual needs, such as integrating it into the data flow management unit or setting it up separately; this application does not make any further restrictions here.
[0045] Therefore, the interface conversion device provided in this application solves the bridging problem between the external low-speed SPI interface and the high-speed debugging requirements inside the chip through top-level layout, protocol conversion, rate buffering and custom high-speed interface driver, laying the foundation for efficient debugging of the entire chip.
[0046] To facilitate a clearer understanding of the specific implementation logic of the interface conversion device provided in this application, the above embodiments will be described in an overall exemplary manner below. Those skilled in the art will understand that this description does not limit the specific implementation of this application.
[0047] The interface conversion device provided in this application is mainly used in chip debugging systems. It is cleverly placed on the top layer of the chip and adjacent to the SPI input / output pads. It converts externally input SPI signals into internal signals of a custom debugging interface protocol and outputs them through two global signal lines. The device adopts an asynchronous clock design, which can effectively match the rate differences between different interfaces and significantly reduce the number of global traces, thereby reducing the difficulty of timing convergence.
[0048] This interface conversion device mainly consists of four core components: an SPI slave interface unit, a data flow management unit, a data buffer module, and a debug interface master unit. These modules are connected via a data bus and control signal lines, forming a complete signal conversion path.
[0049] The SPI slave interface unit serves as the device's input, responsible for receiving external SPI signals. Implemented according to the standard SPI protocol specification, this unit can identify and parse clock signals, data input signals, and chip select signals from the external host. The SPI slave interface unit parallelizes the received serial data and transmits the parsed data to the data flow management unit. Because this SPI slave interface unit is located on the top layer of the chip and adjacent to the SPI input / output pads, it effectively reduces the timing convergence difficulty caused by the half-cycle sampling requirement stipulated by the SPI protocol, thereby supporting higher interface speeds.
[0050] The data flow management unit connects between the SPI slave interface unit and the debug interface master unit, and is responsible for managing the data flow direction and timing control through the data buffer module. This data flow management unit comprises two sub-modules: a buffer control unit and a scheduling unit. The buffer control unit, connected to the SPI slave interface unit, is responsible for controlling the write operations of data from the SPI slave interface unit to the data buffer module, including write timing control, data validity checks, and buffer status monitoring. The scheduling unit, connected to both the data buffer module and the debug interface master unit, is responsible for reading data from the data buffer module, performing protocol scheduling, and then sending it to the debug interface master unit. The scheduling unit is also responsible for encapsulating data from the data buffer module according to the frame format of the custom debug interface protocol, ensuring that data can be transmitted internally in the correct format.
[0051] The data buffer module is one of the core components of the device, specifically designed to match the data transfer rates between the SPI interface and the custom debug interface. This module employs a FIFO structure design, which mitigates the rate mismatch caused by different clock domains between the two interfaces. When there is a difference between the SPI interface data input rate and the internal debug interface output rate, the data buffer module temporarily stores data to balance the rate difference, ensuring the continuity and integrity of data transmission and maximizing the utilization of the SPI interface's transmission capacity.
[0052] The debug interface host unit, acting as the device's output, connects to the data buffer module and is responsible for driving internal signals and controlling the output of the two global signal lines. This unit is configured to generate and send communication frames conforming to the custom debug interface protocol. The communication frame format includes 32 valid data bits and 1 parity bit, significantly increasing the effective data volume per transmission compared to the standard UART protocol's 8 data bits, improving the effective transmission efficiency from 8 / 11 to 32 / 35. The debug interface host unit is also configured to perform parity verification on the received data. When a parity error is detected, a retransmission process can be initiated through the two global signal lines to ensure the reliability of data transmission.
[0053] The interface conversion device uses a custom debugging interface protocol based on the standard UART protocol with four key improvements: First, the transmission rate is increased to 100Mbps, with the host and slave sides using clocks of 200MHz or higher for sampling, and the host and slave sides operating asynchronously at their sampling clock frequencies, eliminating the need for a global synchronization clock; second, the data bit width is expanded from 8 bits to 32 bits, significantly improving single-transmission efficiency; third, a parity check bit is forcibly added to improve transmission reliability; and fourth, a complete retransmission mechanism is added to ensure the accuracy of data transmission.
[0054] Please refer to Figure 5As shown, in some embodiments of this application, a chip debugging system including the aforementioned interface conversion device is also provided, the system further comprising: One or more debug interface slave units are located within a subsystem of the chip; and One or more synchronous bridge modules are connected between the debug interface host unit and the debug interface slave unit of the interface conversion device; The debug interface host unit and the debug interface slave unit are configured to communicate in full-duplex mode through a preset number of global signal lines based on mutually asynchronous clocks; the preset number is less than the number of debug interface slave units.
[0055] In this embodiment, the number of global signal lines can be configured according to actual needs, with the aim of reducing the number of buses. Therefore, the preset number must be less than the number of debug interface slave units. In practice, the chip debugging system constructs a chip-level debug network with a custom debug interface protocol over two global signal lines as its backbone. This system integrates the aforementioned interface conversion device and expands the access capabilities of the subsystems. The relationship between the components in its structure is as follows: As described in the previous embodiments, the interface conversion device acts as the system's "gateway," connecting the external SPI world with the internal debugging network.
[0056] The synchronous bridge module (pipe) connects the debug_if_mst output of the interface conversion device to the global signal lines leading to each subsystem. Due to the long global traces and heavy loads, timing violations are easily generated under high-speed (e.g., 100Mb / s) signal transmission. The pipe module uses register-level pacing to divide a long combinational logic path into multiple shorter segments that are easier to converge in timing, thereby ensuring the stability and reliability of signal transmission over long distances within the chip.
[0057] One or more debug interface slave units (debug_if_slv) are distributed on the boundaries of various subsystems that require debug access (such as CPU clusters, AI accelerators, storage controllers, etc.).
[0058] In some embodiments of this application, the signal timing between the debug interface host unit and the debug interface slave unit is configured as follows: In the idle state, keep the data output signal line high; When a falling edge is detected on the data input signal line, data reception begins; Receive a predetermined number of valid data bits and one parity bit in sequence; When the data input signal line is detected to return to a high level, it is determined that the current frame data transmission is complete.
[0059] For details, please refer to Figure 6 As shown, the debug interface master unit and debug interface slave unit adopt a specific signal timing protocol: in the idle state, the data output signal line is kept high; when a falling edge is detected on the data input signal line, data reception begins; 32 valid data bits and 1 parity bit are received sequentially; when the data input signal line returns to high, the current frame data transmission is considered complete. This timing design simplifies the handshake protocol and improves transmission efficiency.
[0060] To ensure reliable data transmission, the system implements a complete retransmission mechanism. Please refer to [further details]. Figure 6 As shown, in one embodiment of this application, the debug interface host unit and the debug interface slave unit can also be configured to perform the following retransmission mechanism: When the receiving end detects a parity error in a communication frame, it sends a retransmission request command to the sending end via a signal line. The sending end determines the position of the data frame to be retransmitted according to the retransmission request instruction, and after sending a retransmission start instruction, it retransmits data from the corresponding data frame position. When a retransmission request command or retransmission start command itself is detected to have a check error, an interrupt is triggered and the data input signal line is restored to a high level.
[0061] Specifically, when the receiving end detects a parity check error in a communication frame, it sends a retransmission request command to the sending end via a signal line. The retransmission request command is an 8-bit valid data set, 0xab, where bit 0 is 1 to indicate a retransmission request, and bits 1-7 form a receive count value representing the number of frames currently received. The sending end determines the position of the data frame to be retransmitted based on the retransmission request command. It calculates the retransmission position by comparing the transmit counter with the receive count value carried in the retransmission command: if the 7 bits are the same, the retransmission position is the transmit count value minus the receive count value; if the 7 bits are not equal, the retransmission position is 128 minus the receive count value plus the transmit count value. Before starting retransmission, the sending end first sends a retransmission start command, 0xaa, where bit 0 represents the start of retransmission and bits 1-7 represent the retransmission position, then retransmits data starting from the corresponding data frame position. When a parity check error is detected in the retransmission request command or the retransmission start command itself, the system triggers an interrupt and restores the data input signal line to a high level to prevent error propagation. This retransmission mechanism does not support nested retransmissions. If an error occurs during retransmission, the local end will directly report an interrupt and pull the transmission signal high.
[0062] This interface conversion device reduces the number of traces by 52 times compared to the traditional APB interface by converting the SPI interface into a custom debugging interface requiring only two global signal lines, significantly reducing chip area usage and the risk of wiring congestion. Simultaneously, the asynchronous clock design greatly simplifies clock access selection and clock tree generation, improving the overall system feasibility and reliability.
[0063] In practical work, each debug interface slave unit module can perform the following actions: Protocol processing: Receive the conditioned TD1 / TD0 signals via the pipe and decode them according to the same protocol agreed upon with debug_if_mst. Its sampling clock is provided by the subsystem's own clock domain and is asynchronous with the clock domain of debug_if_mst. This asynchronous design eliminates the need for a complex global synchronization clock tree distribution, reducing implementation difficulty.
[0064] Signal timing: The protocol specifies that td0 remains high during idle periods. A data frame begins with a falling edge on td1, followed by continuous sampling of a predetermined number of bits (e.g., 32 bits) of data and a 1-bit parity bit. The frame ends with a rising edge on td1. The logic within debug_if_slv is configured to strictly adhere to this sampling sequence.
[0065] Retransmission mechanism involvement: When debug_if_slv acts as a receiver (e.g., receiving a write command) and detects a frame check error, its internal retransmission control logic is activated. A specific retransmission request instruction (e.g., 0xAB format, where the least significant bit 1 indicates a request and the high 7 bits are the local receive counter value) is sent to debug_if_mst via the td0 line. Correspondingly, when it acts as a sender (e.g., returning read data) and receives a retransmission request from debug_if_mst, it calculates the frame position requiring retransmission based on the counter value carried in the instruction, first sending a retransmission start instruction (e.g., 0xAA format), and then retransmitting data from that position. If the retransmission instruction itself malfunctions during transmission, the relevant logic triggers a debug interrupt and forcibly pulls its transmit signal line high to notify the host computer of a serious link error.
[0066] Therefore, the chip debugging system provided in this application constructs a high-bandwidth, low-wiring-overhead, and easy-to-implement global chip debugging infrastructure through asynchronous clock design, a simplified 2-wire physical layer, distributed protocol slaves, and a synchronous bridge for timing guarantees. The retransmission mechanism further ensures the reliability of data transmission.
[0067] Please refer to Figure 7 As shown, in some embodiments of this application, a system-on-a-chip (SoC) is also provided, comprising: The chip debugging system described above; One or more subsystems; The debug interface slave unit of each subsystem is used to convert the received internal signals into signals conforming to the APB bus protocol or the AXI bus protocol in order to access the debug resources inside the subsystem.
[0068] In practice, after receiving the 32-bit internal signals from the debug interface master unit, the debug interface slave unit within each subsystem first parses the signals, extracting the address, control, and data fields. Depending on the subsystem's internal bus protocol, the debug interface slave unit converts these fields into corresponding bus signals. When the subsystem uses the APB bus protocol, the debug interface slave unit generates the PADDR address signal, PWRITE read / write control signal, PSEL select signal, PENABLE enable signal, and PWDATA write data signal or PRDATA read data signal. When the subsystem uses the AXI bus protocol, the debug interface slave unit generates corresponding AXI address channel, data channel, and control channel signals, including AWADDR, AWVALID, AWREADY write address signals, WDATA, WVALID, WREADY write data signals, ARADDR, ARVALID, ARREADY read address signals, and RDATA, RVALID, RREADY read data signals.
[0069] This design enables a highly efficient debug communication architecture for the system-on-a-chip (SoC). An external debug host can access the debug resources of various subsystems within the chip via a standard SPI interface. Internally, only two global signal lines are needed for full-duplex communication, reducing the number of global traces by 52 times compared to the traditional APB interface scheme. Furthermore, the asynchronous clock operation of the debug interface master and slave units significantly reduces the complexity of clock tree design and timing convergence difficulties. The 100Mbps transmission rate of the custom debug protocol matches well with the external SPI interface rate, ensuring maximum efficiency in debug data acquisition, while the combination of a 32-bit data width and parity check with retransmission mechanisms guarantees high reliability for on-chip debug communication.
[0070] In some embodiments of this application, an electronic device is also provided, including the aforementioned system-on-a-chip.
[0071] Specifically, the electronic device can adopt a modular design architecture, with a system-on-a-chip (SoC) integrated as the core processing unit on the main circuit board. The SoC connects to other functional modules of the electronic device through standard interfaces, including power management modules, storage modules, input / output interface modules, and communication modules.
[0072] The debugging function of the system-on-a-chip (SoC) establishes a connection with an external debugging host via the SPI interface. The external debugging interface of the electronic device uses a standard SPI connector, which provides four signal lines: clock signal SCLK, master output / slave input signal MOSI, master input / slave output signal MISO, and chip select signal CS. The external debugging host can access the debugging resources of various subsystems within the SoC through these signal lines, enabling monitoring and debugging of the electronic device's operating status.
[0073] The on-chip debugging system communicates with each subsystem via a custom debugging interface protocol, as described in detail in Embodiment 2. This protocol is based on an improved UART protocol to achieve high-speed transmission of 100Mbps. The debugging interface slave unit of each subsystem converts the received internal signals into a signal format conforming to the APB bus protocol or the AXI bus protocol in order to access the registers, memory and other debugging resources inside the subsystem.
[0074] During the operation of electronic devices, when system debugging or fault diagnosis is required, the external debugging host first sends debugging commands and data to the system-on-a-chip (SoC) via the SPI interface. The SoC's internal interface conversion device converts the SPI protocol to an internal custom debugging interface protocol, and then transmits the debugging information to the target subsystem via two global signal lines. The target subsystem's debugging interface slave unit receives the debugging information, converts it to the corresponding bus protocol format, accesses the subsystem's internal debugging resources, and obtains the necessary debugging data. The debugging data is then returned to the external debugging host along the reverse path, completing the entire debugging process.
[0075] This design enables the electronic device to achieve a highly efficient debugging architecture. An external debugging host can easily access the debugging functions of various subsystems within the electronic device via a standard SPI interface. Internally, only a small number of global traces are needed to achieve comprehensive debugging coverage, greatly simplifying the design complexity of the debugging interface and improving debugging efficiency and reliability. This design not only simplifies hardware connections but also provides significant flexibility and convenience during debugging, making the process more efficient and reliable. Through this modular and standardized design, the electronic device can provide comprehensive debugging functionality without adding extra complexity, ensuring the stability and reliability of the device under various operating conditions.
[0076] Figure 8 This is a block diagram illustrating an electronic device 900 including the aforementioned system-on-a-chip according to an exemplary embodiment. For example, the electronic device 900 may be an AI server, a training and push integrated machine, etc.
[0077] Reference Figure 8The electronic device 900 may include one or more of the following components: an AI-accelerated computing module, a CPU module, a power supply module, a hard drive module, and a fan module. Each module works in conjunction with the bus system through a standardized hardware interface, with the specific architecture as follows: The AI-accelerated computing module comprises multiple AI accelerator cards deployed in parallel. Each AI accelerator card integrates at least one AI accelerator chip (such as an RPU chip, GPU chip, or CGRA chip). The AI accelerator cards communicate with each other via a high-speed chip-to-chip (C2C) interconnect structure, supporting low-latency, high-bandwidth horizontal scaling. The AI accelerator chip is dedicated to performing AI computing tasks such as high-density matrix operations, neural network model training, and / or inference, providing the main computing power support.
[0078] The CPU module includes at least one CPU board, which houses a central processing unit (CPU) chip and associated CPU memory (such as DDR4 / DDR5, RAM). The CPU chip serves as the system control center, responsible for task scheduling, resource allocation, I / O management, and coordinating the parallel computing of the AI acceleration computing module, while also handling non-accelerated general-purpose computing tasks.
[0079] The power module is equipped with redundant power supply units to provide stable power distribution and management for the AI acceleration computing module, CPU module and other modules.
[0080] The hard drive module integrates a high-speed solid-state drive (SSD) and / or a large-capacity hard disk drive (HDD), connected to the system bus via a backplane. The hard drive stores the operating system, AI training datasets, model parameters, and computation results, providing high-throughput data read / write channels and supporting data preprocessing and persistence.
[0081] The fan module uses a multi-zone independent speed-controlled fan array, which is configured in key heat source areas (such as AI accelerator cards and CPU heat dissipation areas) to achieve system heat dissipation through forced air cooling and ensure the stable operation of high-efficiency computing components.
[0082] The CPU module is connected to the AI acceleration computing module via the PCIe bus to enable task distribution, result collection, and memory coordination.
[0083] The CPU module manages the data access of the hard drive module through SATA / SAS / NVMe interfaces.
[0084] The power module provides tiered power to all functional modules through the power distribution backplane.
[0085] The fan module adjusts the fan speed based on temperature monitoring signals from the CPU board and AI accelerator card.
[0086] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.
[0087] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.
[0088] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. An interface conversion device for a chip debugging system, characterized in that, The device is located on the top layer of the chip and adjacent to the SPI input / output pads. It is used to convert externally input SPI signals into internal signals of a custom debug interface protocol and output them via a preset number of global signal lines. The device includes a data buffer module for matching the data transmission rate between the SPI interface and the custom debug interface.
2. The interface conversion device according to claim 1, characterized in that, The device further includes: An SPI slave interface unit is used to receive the externally input SPI signal; The debugging interface host unit is connected to the data buffer module and is used to drive the internal signals.
3. The interface conversion device according to claim 2, characterized in that, The debug interface host unit is configured to generate and send communication frames that conform to the custom debug interface protocol; The communication frame format includes multiple valid data bits and one parity bit.
4. The interface conversion device according to claim 3, characterized in that, The debug interface host unit is also configured to perform parity checks on the received data, and to initiate a retransmission process through the two global signal lines when a check error is detected.
5. The interface conversion device according to claim 2, characterized in that, The device further includes a data flow management unit connected between the SPI slave interface unit and the debug interface master unit, which is used to manage the data flowing through the data buffer module.
6. The interface conversion device according to claim 5, characterized in that, The data flow management unit includes: A buffer control unit, connected to the SPI slave interface unit, is used to control the writing of data from the SPI slave interface unit to the data buffer module; The scheduling unit is connected to the data buffer module and the debug interface host unit, respectively, and is used to read data from the data buffer module, perform protocol scheduling, and then send it to the debug interface host unit.
7. The interface conversion device according to claim 6, characterized in that, The scheduling unit is also used to encapsulate the data from the data buffer module according to the frame format of the custom debugging interface protocol.
8. A chip debugging system comprising the interface conversion device according to any one of claims 1 to 7, characterized in that, The system also includes: One or more debug interface slave units are located within a subsystem of the chip; and One or more synchronous bridge modules are connected between the debug interface host unit and the debug interface slave unit of the interface conversion device; The debug interface host unit and the debug interface slave unit are configured to communicate in full-duplex mode through a preset number of global signal lines based on mutually asynchronous clocks; the preset number is less than the number of debug interface slave units.
9. The chip debugging system according to claim 8, characterized in that, The signal timing between the debug interface host unit and the debug interface slave unit is configured as follows: In the idle state, keep the data output signal line high; When a falling edge is detected on the data input signal line, data reception begins; Receive a predetermined number of valid data bits and one parity bit in sequence; When the data input signal line is detected to return to a high level, it is determined that the current frame data transmission is complete.
10. The chip debugging system according to claim 9, characterized in that, The debug interface host unit and the debug interface slave unit are further configured to perform the following retransmission mechanism: When the receiving end detects a parity error in a communication frame, it sends a retransmission request command to the sending end via a signal line. The sending end determines the position of the data frame to be retransmitted according to the retransmission request instruction, and after sending a retransmission start instruction, it retransmits data from the corresponding data frame position. When a retransmission request command or retransmission start command itself is detected to have a check error, an interrupt is triggered and the data input signal line is restored to a high level.
11. A system-on-a-chip (SoC), characterized in that, include: The chip debugging system as described in any one of claims 8 to 10; One or more subsystems; The debug interface slave unit of each subsystem is used to convert the received internal signals into signals conforming to the APB bus protocol or the AXI bus protocol in order to access the debug resources inside the subsystem.
12. An electronic device, characterized in that, Including the system-on-a-chip as described in claim 11.