Cascadeable single-bit spi slave module, serial-parallel conversion system and design method thereof
The serial-to-parallel conversion system using cascaded single-bit SPI slave modules solves the area and scalability issues in SPI slave interface design, achieving efficient serial data conversion and flexible process adaptability, supporting higher clock frequencies and shorter design cycles.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGDONG UNIV OF TECH
- Filing Date
- 2026-03-05
- Publication Date
- 2026-06-09
AI Technical Summary
Existing SPI slave interface designs suffer from large chip area overhead, poor scalability, and limited operating speed, especially when facing process migration, requiring extensive redesign and optimization.
Employing a cascadeable single-bit SPI slave module, the system uses a data latching unit composed of flip-flops and delay buffers to achieve serial data latching and parallel output. Combined with modular design and transistor-level optimization, it avoids complex clock tree networks and long-distance traces, supporting flexible layout and process migration.
It achieves efficient serial-to-parallel conversion, reduces chip area, supports higher clock frequencies, shortens design cycles, improves design efficiency and flexibility, and adapts to changes in different process nodes.
Smart Images
Figure CN122173430A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the technical field of digital-to-analog integrated circuit design, and in particular to a cascadeable single-bit SPI slave module, a serial-to-parallel conversion system, and a design method thereof. Background Technology
[0002] Complex mixed-signal integrated circuits typically contain numerous functional modules that require initialization upon power-up, reset, or mode switching. These include bias current sources, bias voltage sources, programmable gain amplifiers (PGAs), multiplexers (MUXs), and digital phase-locked loop (DPLL) configuration registers. The initialization control of these modules is usually achieved by writing configuration data to the corresponding control registers via a serial interface, thus completing the module's initialization configuration.
[0003] SPI (Serial Peripheral Interface) is a synchronous, full-duplex serial communication protocol first proposed by Motorola, designed for short-distance, high-speed data exchange. An SPI interface typically uses four signal lines: Serial Clock (SCK), Master Output / Slave Input (MOSI), Master Input / Slave Output (MISO), and a low-level active Slave Select (CS / SS) line. Because data is transmitted bit by bit through dedicated lines, SPI is characterized by high speed, high efficiency, and simple hardware implementation, and is currently widely used in the initialization control of devices such as EEPROMs, Flash memories, real-time clocks, A / D converters, and digital signal processors.
[0004] Traditional SPI slave interface designs primarily employ a digital synthesis-based approach, designing an SPI slave interface that includes a shift register set, with the number of registers equal to the output bit width. The SPI slave interface receives and latches one bit of data per clock cycle, continuing until a complete frame of serial data is received before outputting the latched data in parallel to the respective initialization modules.
[0005] However, this SPI slave design based on digital synthesis methods has the following technical drawbacks:
[0006] 1. Large chip area overhead: When the output bit width is large (such as 32-bit, 64-bit or higher), the clock tree driving the long shift register needs to insert a large number of buffers to reduce clock skew. In addition, digital synthesis methods usually need to reserve a lot of space for long traces and various buffers during the placement and routing stage, resulting in low area utilization.
[0007] 2. Poor scalability: Changes in output bit width, clock frequency, or process node require redesigning the entire RTL code and re-engineering the entire back-end design process, including synthesis, placement, and routing. This results in a long design cycle and a lack of flexibility. Especially when facing process migration, significant manpower is required for redesign and optimization.
[0008] 3. Limited operating speed: As the clock frequency increases, the requirements for data setup time and hold time become more stringent, limiting the maximum operating frequency. Furthermore, the large clock network introduces significant clock skew, increasing the difficulty of system timing convergence and further restricting the improvement of operating speed.
[0009] Therefore, there is an urgent need for a new SPI slave design that can overcome the above-mentioned defects, and achieve serial-to-parallel conversion function with small area and high scalability while ensuring high-speed performance. Summary of the Invention
[0010] The purpose of this invention is to overcome the shortcomings of the prior art and provide a cascadeable single-bit SPI slave module, a serial-to-parallel conversion system, and its design method.
[0011] To achieve the above objectives, the technical solution provided by this invention is as follows:
[0012] A cascadeable single-bit SPI slave module includes flip-flops D1, D2, and D3, delay buffers T1, T2, and T3, and a serial data input port D. I Serial data output port D O Clock input port CLK I Clock output port CLK O Parallel output control signal input port CS I Parallel output control signal output port CS O And the module's parallel output port Q;
[0013] The data latch unit consists of flip-flops D1 and D2 and delay buffer T1; at the clock input port CLK... I On the rising edge of the input signal, flip-flop D1 turns on, turning on the serial data input port D. I Data latched to internal node D C ; at the clock input port CLK I The falling edge of the input signal turns on flip-flop D2, causing D to turn on. C The data is buffered by delay buffer T1 and then output to the serial data output port D. O ; at the parallel output control signal input port CS IAt the rising edge of the input signal, flip-flop D3 turns on, turning on D... C Data is output to the module's parallel output port Q;
[0014] Delay buffer T2 is connected to the clock input port CLK I and clock output port CLK O Between these points, delay buffer T3 is connected to the parallel output control signal input port CS. I and parallel output control signal output port CS O between.
[0015] In this technical solution,
[0016] Serial data input port D I Used to receive serial data from the preceding module or an external host;
[0017] Serial data output port D O Used to output latched data to the next level module;
[0018] Clock input port CLK I Used to receive clock signals from the preceding module or an external host;
[0019] Clock output port CLK O Used to output the buffered clock signal to the next stage module;
[0020] Parallel output control signal input port CS I Used to receive chip select / control signals from the preceding module or an external host;
[0021] Parallel output control signal output port CS O Used to output the buffered control signal to the next level module;
[0022] Module parallel output port Q: Used to output latched data in parallel when the control signal is valid.
[0023] The working principle of the cascaded single-bit SPI slave module is as follows:
[0024] 1) Data sampling phase: Initially, the parallel output control signal is input to port CS. I When the signal is low, the module is in serial data reception mode. At the clock input port CLK... I On the rising edge, flip-flop D1 is turned on, and flip-flop D2 is turned off, allowing external serial data to flow from the serial data input port D. I Input and lock the internal node D C superior.
[0025] 2) Data transmission phase: at the clock input port CLKI On the falling edge, trigger D1 is turned off, trigger D2 is turned on, and the lock exists in internal node D. C The serial data is buffered by delay buffer T1 and then output to the serial data output port D. O This is used for sampling by the next level module.
[0026] 3) Data output stage: After a complete frame of external serial data has been received, the parallel output control signal input port CS is used. I On the rising edge, trigger D3 turns on, locking the internal node D. C The data is output to the module's parallel output port Q to achieve parallel data output.
[0027] Furthermore, the delay amounts of the delay buffers T1, T2, and T3 are adjusted through transistor-level design, so that the clock output port CLK... O The rising edge of the output signal is aligned with the serial data output port D. O The output signal is located at the center of the effective window of the output signal, and the parallel output control signal output port CS is used for output. O The rising edge of the output signal is aligned with the serial data output port D. O The effective window of the output signal is in the center.
[0028] Furthermore, to achieve the above objectives, the present invention also provides a serial-to-parallel conversion system based on modular single-bit SPI slave cascading, which includes N of the above-mentioned cascadable single-bit SPI slave modules, wherein the N cascadable single-bit SPI slave modules are cascaded sequentially.
[0029] The first-level module's serial data input port DI is connected to an external serial data MOSI, and the clock input port CLK... I Connect to an external clock CLK, and input the parallel output control signal CS to the port. I Connect to an external parallel output control signal CS;
[0030] The serial data output port D of the i-th level module O Clock output port CLK O Parallel output control signal output port CS O Connect the serial data input port D of the (i+1)th level module respectively. I Clock input port CLK I Parallel output control signal input port CS I , where 1≤i <N;
[0031] The parallel output ports Q of all modules form an N-bit parallel output bus.
[0032] The system works as follows:
[0033] 1) Serial data shift latch stage: While the external parallel output control signal CS is low, each module performs two operations in each cycle of the external clock CLK: sampling the current serial data input port D on the rising edge. I The data is then latched into internal node D. C ; Lock at node D on the falling edge C Data output to serial data output port D O This process allows serial data to be passed one level to the next and latched in each clock cycle.
[0034] 2) Data frame completion stage: After N clock cycles, the first serial data is locked in node D of the Nth level module. C,N The last data lock is stored in node D within the first-level module. C,1 This completes the latching of an N-bit external serial data stream MOSI in this system.
[0035] 3) Parallel Output Stage: When the external parallel output control signal CS generates a rising edge, all modules simultaneously or sequentially output their latched data to their respective parallel output ports Q1, Q2, ..., Q3. N-1 Q N This enables the conversion of N-bit serial data MOSI into parallel data output.
[0036] Furthermore, the N modules adopt a centralized layout, with all modules arranged consecutively and the corresponding ports of adjacent modules directly connected.
[0037] Furthermore, the N modules adopt a distributed layout, with the modules scattered near the functional modules that need to be configured, and the modules are connected by wires.
[0038] Furthermore, to achieve the above objectives, the present invention also includes a design method for the above-mentioned serial-to-parallel conversion system, comprising the following steps:
[0039] S1. Design and optimize the circuit schematic of the cascaded single-bit SPI slave module at the transistor level, design the flip-flop topology and the delay amount of the delay buffer, and verify the timing characteristics through simulation.
[0040] S2. Perform a full-custom layout design on the cascadeable single-bit SPI slave module, optimize transistor placement and port layout, and solidify it into a reusable standard unit to minimize area.
[0041] S3. Based on the required serial data bit width N, instantiate N cascaded single-bit SPI slave modules in the top-level layout of the chip, select a centralized or distributed layout scheme, and connect the modules serially in sequence.
[0042] Furthermore, the timing characteristics include setup time, hold time, and propagation delay. Timing optimization is achieved by adjusting the transistor sizes of buffers T1, T2, and T3 to ensure that the setup time, hold time, and propagation delay requirements are met.
[0043] Furthermore, the port layout optimization includes optimizing the serial data input port D. I Clock input port CLK I Parallel output control signal input port CS I Located on one side of the cascadeable single-bit SPI slave module, the serial data output port D... O Clock output port CLK O Parallel output control signal output port CS O It is placed on the other side of the cascadeable single-bit SPI slave module, so that the ports of adjacent modules can be directly connected when cascaded.
[0044] Furthermore, when the serial data bit width N changes, only the number of instantiated modules needs to be adjusted, without modifying the circuit structure of a single module.
[0045] Furthermore, when the clock frequency or manufacturing process changes, only the timing optimization or process migration of a single cascaded single-bit SPI slave module is required, without the need to resynthesize the entire system.
[0046] Compared with existing technologies, the principles and advantages of this technical solution are as follows:
[0047] 1. Employing a transistor-level full-custom design approach, this modular design avoids the problem of reserving large amounts of space for long-distance traces, a common issue in traditional digital synthesis solutions. Simultaneously, the clock signal buffering function is distributed across the delay buffers T2 of each module, resulting in minimal clock load for each module. This eliminates the need for complex clock tree synthesis (CTS) networks, reducing the area overhead of clock buffers and saving over 50% of chip area compared to traditional digital synthesis solutions.
[0048] 2. By optimizing the clock path at the transistor level and employing an asynchronous cascading approach, the system can adapt to higher clock frequencies. Optimizing the clock path delay of each module at the transistor level ensures that the setup and hold times of individual modules meet requirements, thus ensuring the timing of the cascaded system meets the requirements and avoiding the problem of clock skew accumulation in long shift registers. Simulation experiments achieved an operating frequency of 10GHz, far exceeding traditional solutions.
[0049] 3. Modular design methods offer high reusability, significantly shortening the design cycle and improving design efficiency.
[0050] 1) When the serial data bit width changes, only the number of module instances needs to be increased or decreased on the layout, without modifying any circuit design;
[0051] 2) When the clock frequency requirement changes, only the timing characteristics of a single module need to be re-optimized, rather than the entire circuit system;
[0052] 3) When the process nodes change, only a single module needs to be migrated and re-optimized to quickly complete the process migration of the entire system, avoiding strong dependence on specific processes.
[0053] 4. The module adopts a standardized port layout scheme, which supports centralized or distributed layout. It can be flexibly arranged according to the overall floor plan of the chip, which is conducive to optimizing the overall physical implementation of the chip. Attached Figure Description
[0054] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0055] Figure 1 This is a circuit schematic diagram of the cascaded single-bit SPI slave module of the present invention;
[0056] Figure 2 This is a schematic diagram illustrating the principle of the cascadeable single-bit SPI slave module of the present invention during the data sampling stage.
[0057] Figure 3 This is a schematic diagram illustrating the principle of the cascaded single-bit SPI slave module of the present invention during the data transmission phase.
[0058] Figure 4 This is a schematic diagram illustrating the principle of the cascadeable single-bit SPI slave module of the present invention during the data output stage.
[0059] Figure 5 This is a schematic diagram of the serial-to-parallel conversion system based on modular single-bit SPI slave cascading of the present invention;
[0060] Figure 6 This is a timing diagram of the excitation signal in the simulation experiment of this invention;
[0061] Figure 7 This is the ideal timing diagram of the module in the simulation experiment of this invention;
[0062] Figure 8 This is a schematic diagram of the module port layout in the simulation experiment of this invention;
[0063] Figure 9 This is a schematic diagram of the system layout in the simulation experiment of this invention. Detailed Implementation
[0064] The present invention will be further described below with reference to specific embodiments:
[0065] like Figure 1 As shown, the cascadeable single-bit SPI slave module described in this embodiment includes flip-flops D1, D2, and D3, delay buffers T1, T2, and T3, and a serial data input port D. I Serial data output port D O Clock input port CLK I Clock output port CLK O Parallel output control signal input port CS I Parallel output control signal output port CS O And the module's parallel output port Q;
[0066] The data latch unit consists of flip-flops D1 and D2 and delay buffer T1; at the clock input port CLK... I On the rising edge of the input signal, flip-flop D1 turns on, turning on the serial data input port D. I Data latched to internal node D C ; at the clock input port CLK I The falling edge of the input signal turns on flip-flop D2, causing D to turn on. C The data is buffered by delay buffer T1 and then output to the serial data output port D. O ; at the parallel output control signal input port CS I At the rising edge of the input signal, flip-flop D3 turns on, turning on D... C Data is output to the module's parallel output port Q;
[0067] Delay buffer T2 is connected to the clock input port CLK I and clock output port CLK O Between these points, delay buffer T3 is connected to the parallel output control signal input port CS. I and parallel output control signal output port CS O between.
[0068] In this embodiment,
[0069] Serial data input port D I Used to receive serial data from the preceding module or an external host;
[0070] Serial data output port D OUsed to output latched data to the next level module;
[0071] Clock input port CLK I Used to receive clock signals from the preceding module or an external host;
[0072] Clock output port CLK O Used to output the buffered clock signal to the next stage module;
[0073] Parallel output control signal input port CS I Used to receive chip select / control signals from the preceding module or an external host;
[0074] Parallel output control signal output port CS O Used to output the buffered control signal to the next level module;
[0075] Module parallel output port Q: Used to output latched data in parallel when the control signal is valid.
[0076] Specifically, the delay amounts of delay buffers T1, T2, and T3 are adjusted through transistor-level design to ensure that the clock output port CLK... O The rising edge of the output signal is aligned with the serial data output port D. O The output signal is located at the center of the effective window of the output signal, and the parallel output control signal output port CS is used for output. O The rising edge of the output signal is aligned with the serial data output port D. O The effective window of the output signal is in the center.
[0077] like Figures 2 to 4 As shown, the working principle of the cascaded single-bit SPI slave module is as follows:
[0078] 1) Data sampling phase: Initially, the parallel output control signal is input to port CS. I When the signal is low, the module is in serial data reception mode. At the clock input port CLK... I On the rising edge, flip-flop D1 is turned on, and flip-flop D2 is turned off, allowing external serial data to flow from the serial data input port D. I Input and lock the internal node D C superior.
[0079] 2) Data transmission phase: at the clock input port CLK I On the falling edge, trigger D1 is turned off, trigger D2 is turned on, and the lock exists in internal node D. C The serial data is buffered by delay buffer T1 and then output to the serial data output port D. O This is used for sampling by the next level module.
[0080] 3) Data output stage: After a complete frame of external serial data has been received, the parallel output control signal input port CS is used. I On the rising edge, trigger D3 turns on, locking the internal node D. C The data is output to the module's parallel output port Q to achieve parallel data output.
[0081] This embodiment also includes a serial-to-parallel conversion system based on modular single-bit SPI slave cascading, such as... Figure 5 As shown, it includes N cascaded single-bit SPI slave modules as described above, which are cascaded sequentially.
[0082] Among them, the serial data input port D of the first-level module I Connect to external serial data MOSI, clock input port CLK I Connect to an external clock CLK, and input the parallel output control signal CS to the port. I Connect to an external parallel output control signal CS;
[0083] The serial data output port D of the i-th level module O Clock output port CLK O Parallel output control signal output port CS O Connect the serial data input port D of the (i+1)th level module respectively. I Clock input port CLK I Parallel output control signal input port CS I , where 1≤i <N;
[0084] The parallel output ports Q of all modules form an N-bit parallel output bus.
[0085] The system works as follows:
[0086] 1) Serial data shift latch stage: While the external parallel output control signal CS is low, each module performs two operations in each cycle of the external clock CLK: sampling the current serial data input port D on the rising edge. I The data is then latched into internal node D. C ; Lock at node D on the falling edge C Data output to serial data output port D O This process allows serial data to be passed one level to the next and latched in each clock cycle.
[0087] 2) Data frame completion stage: After N clock cycles, the first serial data is locked in node D of the Nth level module. C,N The last data lock is stored in node D within the first-level module. C,1This completes the latching of an N-bit external serial data stream MOSI in this system.
[0088] 3) Parallel Output Stage: When the external parallel output control signal CS generates a rising edge, all modules simultaneously or sequentially output their latched data to their respective parallel output ports Q1, Q2, ..., Q3. N-1 Q N This enables the conversion of N-bit serial data MOSI into parallel data output.
[0089] N modules can be arranged in a centralized layout, with all modules arranged consecutively and corresponding ports of adjacent modules directly connected. In addition to a centralized layout, N modules can also be arranged in a distributed layout, with modules placed near the functional modules that need to be configured and connected to each other by wires.
[0090] This embodiment also includes a design method for the above-mentioned serial-to-parallel conversion system, comprising the following steps:
[0091] S1. Design and optimize the circuit schematic of the cascaded single-bit SPI slave module at the transistor level, design the flip-flop topology and the delay amount of the delay buffer, and verify the timing characteristics through simulation.
[0092] S2. Perform a full-custom layout design on the cascadeable single-bit SPI slave module, optimize transistor placement and port layout, and solidify it into a reusable standard unit to minimize area.
[0093] S3. Based on the required serial data bit width N, instantiate N cascaded single-bit SPI slave modules in the top-level layout of the chip, select a centralized or distributed layout scheme, and connect the modules serially in sequence.
[0094] In this embodiment, the timing characteristics include setup time, hold time, and propagation delay. Timing optimization is achieved by adjusting the transistor sizes of buffers T1, T2, and T3 to ensure that the setup time, hold time, and propagation delay requirements are met.
[0095] The port layout optimization includes optimizing the serial data input port D. I Clock input port CLK I Parallel output control signal input port CS I Located on one side of the cascadeable single-bit SPI slave module, the serial data output port D... O Clock output port CLK O Parallel output control signal output port CS O It is placed on the other side of the cascadeable single-bit SPI slave module, so that the ports of adjacent modules can be directly connected when cascaded.
[0096] When the serial data bit width N changes, only the number of instantiated modules needs to be adjusted, without modifying the circuit structure of individual modules.
[0097] When the clock frequency or manufacturing process changes, only the timing optimization or process migration of a single cascaded single-bit SPI slave module is required, without the need to resynthesize the entire system.
[0098] To demonstrate the effectiveness and superiority of the solution described in this invention, a supporting experiment was conducted, taking the construction of a 32-bit serial-to-parallel conversion system as an example:
[0099] I. External test excitation signal settings:
[0100] 1. Clock input signal CLK: A square wave signal with a frequency of 10GHz and a voltage amplitude of 0V to 1V, with a rise time and fall time of 10ps.
[0101] 2. External serial data stream MOSI: 10GHz 01 binary code stream signal with a voltage amplitude of 0V to 1V, which stops after 32 clock cycles.
[0102] 3. External parallel output control signal CS: Initially at a low level (0V), it is pulled high to a high level (1V) at the 66th clock cycle (i.e., after the 32-bit data input is completed and after an appropriate delay).
[0103] Among them, serial data input port D I The serial input signal DI leads the clock input signal CLK in phase, meaning it changes before CLK by 0.3 clock cycles (30 ps). The timing diagram of the excitation signal in one frame of input data is as follows: Figure 6 As shown.
[0104] II. Optimized Design of Cascadeable Single-Bit SPI Slave Module
[0105] The main circuit of the module consists of three flip-flops (D1, D2, D3) for data latching and output, and two inverters.
[0106] Basic working principle:
[0107] On the rising edge of the clock, flip-flop D1 latches the serial data into the internal node D. C ;
[0108] On the falling edge of the clock, flip-flop D2 locks the internal node D. C The serial data at this stage is output to the next stage;
[0109] On the rising edge of the parallel output control signal CS, flip-flop D3 locks the internal node D. CThe serial data is output to the external parallel port Q of the system.
[0110] Based on the speed requirements, a transmission gate or current-mode logic (CML) positive edge flip-flop is selected as the flip-flop for the main circuit to meet the high-speed operation requirements of 10GHz.
[0111] Timing compensation design:
[0112] To meet strict timing requirements, three delay buffers T1, T2, and T3 were added to the module as timing compensation for the main circuit. Each of the three delay buffers consists of a buffer and an inverter cascaded together.
[0113] Delay buffer T1: Clock signal CLK through delay flip-flop D2 C This makes CLK C The rising edge is precisely aligned with the center of the valid signal window at the data input terminal of flip-flop D2, ensuring reliable data transmission.
[0114] Delay buffer T2: Through the clock output port CLK of the delay module O The output signal is such that its rising edge is precisely aligned with the serial data output port D. O The output signal is positioned at the center of the effective window to ensure that the next-level module can sample it correctly.
[0115] Delay buffer T3: Control signal input port CS is used to delay the parallel output control signal. I The input signal ensures that the rising edge of the input signal to the parallel output control signal output port is precisely aligned with the serial data output port D. O The output signal is positioned in the center of the effective window to ensure the correct transmission of the control signal.
[0116] The ideal timing of the module is as follows Figure 7 As shown.
[0117] III. Implementation Plan for Territorial Layout
[0118] Module-level layout:
[0119] The internal port layout scheme of the module is as follows Figure 8 As shown, the ports are optimized and arranged according to cascading requirements: D I CLK I CS I Located on one side of the module, D O CLK O CS O Located on the other side of the module, the Q port is arranged according to actual connection requirements.
[0120] When cascading and centralized placement are required, seamless connection can be achieved simply by overlapping the output ports of the previous module layout with the input ports of the next module layout. For example, the CS of the previous module can be overlapped. O Port and CS of the next module I Overlap, D O With D I Overlap, CLK O With CLK I Overlapping. This layout eliminates the wiring resource consumption associated with cascading, further reducing the footprint.
[0121] System-level layout:
[0122] This supporting experiment uses a layout scheme that divides 32 modules into 4 groups, with 8 modules cascaded in each group. Modules within a group are placed together, and the groups are connected by short wires, such as... Figure 9 As shown. This hierarchical layout scheme ensures short-distance connections between modules while also providing layout flexibility.
[0123] The specific layout parameters are as follows:
[0124] 1) Each group consists of 8 modules stacked vertically, with direct port connections between modules;
[0125] 2) CLK in Group 1 O D O CS O Connect to CLK in group 2 via a short wire. I D I CS I ;
[0126] 3) Group 2 connects to Group 3, and Group 3 connects to Group 4;
[0127] 4) The Q ports of all modules are connected to the corresponding configuration modules via metal wires.
[0128] IV. Performance Verification Results
[0129] SPICE simulation verified that the 32-bit serial-to-parallel conversion system in this embodiment works normally at a 10GHz clock frequency. The key performance indicators are as follows:
[0130] 1) Maximum operating frequency: 10GHz (superior to the typical level of traditional digital integrated solutions);
[0131] 2) Setup time: < 20ps;
[0132] 3) Holding time: < 15ps;
[0133] 4) Power consumption: reduced by approximately 30% compared to traditional solutions (due to the elimination of the clock tree buffer);
[0134] 5) Area: Saves approximately 55% compared to traditional digital integrated solutions.
[0135] The above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Therefore, any changes made in accordance with the shape and principle of the present invention should be covered within the protection scope of the present invention.
Claims
1. A cascadeable single-bit SPI slave module, characterized in that, Includes flip-flops D1, D2, and D3; delay buffers T1, T2, and T3; and a serial data input port D. I Serial data output port D O Clock input port CLK I Clock output port CLK O Parallel output control signal input port CS I Parallel output control signal output port CS O And the module's parallel output port Q; The data latch unit consists of flip-flops D1 and D2 and delay buffer T1; at the clock input port CLK... I On the rising edge of the input signal, flip-flop D1 turns on, turning on the serial data input port D. I Data latched to internal node D C ; at the clock input port CLK I The falling edge of the input signal turns on flip-flop D2, causing D to turn on. C The data is buffered by delay buffer T1 and then output to the serial data output port D. O ; at the parallel output control signal input port CS I At the rising edge of the input signal, flip-flop D3 turns on, turning on D... C Data is output to the module's parallel output port Q; Delay buffer T2 is connected to the clock input port CLK I and clock output port CLK O Between these points, delay buffer T3 is connected to the parallel output control signal input port CS. I and parallel output control signal output port CS O between.
2. The cascadeable single-bit SPI slave module according to claim 1, characterized in that, The delay amounts of the delay buffers T1, T2, and T3 are adjusted through transistor-level design, so that the clock output port CLK... O The rising edge of the output signal is aligned with the serial data output port D. O The output control signal output port CS is located in the center of the effective window of the output signal. O The rising edge of the output signal is aligned with the serial data output port D. O The effective window of the output signal is in the center.
3. A serial-to-parallel conversion system based on modular single-bit SPI slave cascading, characterized in that, It includes N cascaded single-bit SPI slave modules as described in claim 1 or 2, wherein the N cascaded single-bit SPI slave modules are cascaded sequentially; Among them, the serial data input port D of the first-level module I Connect to external serial data MOSI, clock input port CLK I Connect to an external clock CLK, and input the parallel output control signal CS to the port. I Connect to an external parallel output control signal CS; The serial data output port D of the i-th level module O Clock output port CLK O Parallel output control signal output port CS O Connect the serial data input port D of the (i+1)th level module respectively. I Clock input port CLK I Parallel output control signal input port CS I , where 1≤i <N; The parallel output ports Q of all modules form an N-bit parallel output bus.
4. The serial-to-parallel conversion system based on modular single-bit SPI slave cascading as described in claim 3, characterized in that, The N modules are arranged in a centralized layout, with all modules arranged consecutively and the corresponding ports of adjacent modules directly connected.
5. The serial-to-parallel conversion system based on modular single-bit SPI slave cascading according to claim 3, characterized in that, The N modules are arranged in a distributed layout, with the modules scattered around the functional modules that need to be configured, and the modules are connected by wires.
6. A design method for the serial-to-parallel conversion system as described in claim 3, characterized in that, Includes the following steps: S1. Design and optimize the circuit schematic of the cascaded single-bit SPI slave module at the transistor level, design the flip-flop topology and the delay amount of the delay buffer, and verify the timing characteristics through simulation. S2. Perform fully custom hand-designed layout of the cascadeable single-bit SPI slave module, optimize transistor placement and port layout, and solidify it into a reusable standard unit. S3. Based on the required serial data bit width N, instantiate N cascaded single-bit SPI slave modules in the top-level layout of the chip, select a centralized or distributed layout scheme, and connect the modules serially in sequence.
7. The design method according to claim 6, characterized in that, The timing characteristics include setup time, hold time, and propagation delay. Timing optimization is achieved by adjusting the transistor sizes of buffers T1, T2, and T3 to ensure that setup time, hold time, and propagation delay requirements are met.
8. The design method according to claim 6, characterized in that, The port layout optimization includes optimizing the serial data input port D. I Clock input port CLK I Parallel output control signal input port CS I Located on one side of the cascaded single-bit SPI slave module, the serial data output port D O Clock output port CLK O Parallel output control signal output port CS O It is placed on the other side of the cascadeable single-bit SPI slave module, so that the ports of adjacent modules can be directly connected when cascaded.
9. The design method according to claim 6, characterized in that, When the serial data bit width N changes, only the number of instantiated modules needs to be adjusted.
10. The design method according to claim 6, characterized in that, When the clock frequency or manufacturing process changes, only timing optimization or process migration is required for a single cascaded single-bit SPI slave module.