Display panel and display device

Abstract

This invention provides a display panel and display device, relating to the field of display technology, for reducing voltage drop differences in driving signals output by different pixel circuits during transmission, thereby improving display uniformity. The display panel includes: an array substrate including a first pixel circuit and a second pixel circuit; a first light-emitting device and a second light-emitting device, wherein the first light-emitting device is electrically connected to the first pixel circuit via a first connecting portion, and the second light-emitting device is electrically connected to the second pixel circuit via a second connecting portion; the number of vias corresponding to the first connecting portion is greater than the number of vias corresponding to the second connecting portion; the length of the first connecting portion is greater than the length of the second connecting portion; or, the distance between the first light-emitting device and its corresponding first pixel circuit is greater than the distance between the second light-emitting device and its corresponding second pixel circuit; or, the distance from the first light-emitting device to the edge of the display panel is less than the distance from the second light-emitting device to the edge of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] The display panel includes electrically connected pixel circuits and light-emitting devices. The pixel circuits provide driving current to the light-emitting devices to drive them to emit light. However, the connection distance between the pixel circuits and the light-emitting devices may vary at different locations, which can lead to deviations in the driving signals applied to different light-emitting devices, ultimately causing uneven brightness of the display panel. Summary of the Invention

[0003] This invention provides a display panel and display device for reducing the voltage drop difference of the driving signals output by different pixel circuits during transmission, thereby improving display uniformity.

[0004] In a first aspect, embodiments of the present invention provide a display panel, comprising: An array substrate, including a first pixel circuit and a second pixel circuit; The light-emitting device is located on the array substrate and includes a first light-emitting device and a second light-emitting device. The first light-emitting device is electrically connected to its corresponding first pixel circuit through a first connecting part, and the second light-emitting device is electrically connected to its corresponding second pixel circuit through a second connecting part. The number of vias corresponding to the first connecting part is greater than the number of vias corresponding to the second connecting part; Wherein, the length of the first connecting part is greater than the length of the second connecting part; Alternatively, the distance between the first light-emitting device and its corresponding first pixel circuit is greater than the distance between the second light-emitting device and its corresponding second pixel circuit; Alternatively, the distance from the first light-emitting device to the edge of the display panel is less than the distance from the second light-emitting device to the edge of the display panel.

[0005] Secondly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the aforementioned display panel.

[0006] The technical solution provided by the embodiments of the present invention has the following beneficial effects: In this embodiment of the invention, the first pixel circuit outputs a first driving signal to its corresponding first light-emitting device to drive the first light-emitting device to emit light, and the second pixel circuit outputs a second driving signal to its corresponding second light-emitting device to drive the second light-emitting device to emit light. When the length of the first connecting portion is greater than the length of the second connecting portion, or the distance between the first light-emitting device and its corresponding first pixel circuit is greater than the distance between the second light-emitting device and its corresponding second pixel circuit, or the distance from the first light-emitting device to the edge of the display panel is less than the distance from the second light-emitting device to the edge of the display panel, it means that the extension distance of the first connecting portion will be longer, and correspondingly, the trace resistance of the first connecting portion will be greater. By increasing the number of vias corresponding to the first connecting portion, this embodiment of the invention can reduce the via resistance, thereby reducing the equivalent resistance of the transmission path where the first driving signal is located, balancing the difference in equivalent resistance of the transmission paths where the first driving signal and the second driving signal are located, thereby reducing the voltage drop difference between the first driving signal and the second driving signal during transmission, and improving the brightness uniformity of the display panel. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 A top view of a display panel provided in an embodiment of the present invention; Figure 2 for Figure 1 A partial schematic diagram; Figure 3 This is a schematic diagram showing a connection between a first pixel circuit and a first light-emitting device provided in an embodiment of the present invention; Figure 4 A schematic diagram of the connection between the second pixel circuit and the second light-emitting device provided in an embodiment of the present invention; Figure 5 This is another connection diagram of the first pixel circuit and the first light-emitting device provided in an embodiment of the present invention; Figure 6 A cross-sectional view of a display panel provided in an embodiment of the present invention; Figure 7 for Figure 2 A schematic diagram showing a connection between the first pixel circuit and the first light-emitting device in region A. Figure 8 A schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 9Another schematic diagram of the pixel circuit provided in an embodiment of the present invention; Figure 10 This is another schematic diagram showing the connection between the first pixel circuit and the first light-emitting device provided in an embodiment of the present invention; Figure 11 This is another connection diagram of the second pixel circuit and the second light-emitting device provided in an embodiment of the present invention; Figure 12 Another cross-sectional view of the display panel provided in an embodiment of the present invention; Figure 13 A schematic diagram of a first connecting portion provided in an embodiment of the present invention; Figure 14 Another cross-sectional view of the display panel provided in an embodiment of the present invention; Figure 15 Another schematic diagram of the first connecting portion provided in an embodiment of the present invention; Figure 16 Another cross-sectional view of the display panel provided in an embodiment of the present invention; Figure 17 Another schematic diagram of the first connecting portion provided in an embodiment of the present invention; Figure 18 Another cross-sectional view of the display panel provided in an embodiment of the present invention; Figure 19 Another cross-sectional view of the display panel provided in an embodiment of the present invention; Figure 20 A schematic diagram of a display device provided in an embodiment of the present invention; Figure 21 Another schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0009] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0010] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0011] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0012] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0013] This invention provides a display panel. Figure 1 This is a top view of a display panel provided in an embodiment of the present invention. Figure 2 for Figure 1 A partial schematic diagram (which can be understood as) Figure 2 (Lower right corner area) Figure 3 This is a schematic diagram showing a connection between a first pixel circuit and a first light-emitting device provided in an embodiment of the present invention. Figure 4 This is a schematic diagram showing a connection between the second pixel circuit and the second light-emitting device provided in an embodiment of the present invention, as shown below. Figures 1-4 As shown, the display panel includes an array substrate 1, which includes a first pixel circuit 2 and a second pixel circuit 3.

[0014] The display panel also includes light-emitting devices 4 located on the array substrate 1. These light-emitting devices can be LEDs (Light-Emitting Diodes), such as Micro LEDs or Mini LEDs. The light-emitting device 4 includes a first light-emitting device 5 and a second light-emitting device 6. The first light-emitting device 5 is electrically connected to its corresponding first pixel circuit 2 via a first connecting portion 7, and the second light-emitting device 6 is electrically connected to its corresponding second pixel circuit 3 via a second connecting portion 8. It should be noted that the light-emitting device 4 may include an anode and a cathode. The first connecting portion 7 is electrically connected to the anode of the first light-emitting device 5, and the second connecting portion 8 is electrically connected to the anode of the second light-emitting device 6.

[0015] The length of the first connecting part 7 is greater than the length of the second connecting part 8, that is, the extension distance of the first connecting part 7 is greater than the extension distance of the second connecting part 8.

[0016] Alternatively, the distance between the first light-emitting device 5 and its corresponding first pixel circuit 2 is greater than the distance between the second light-emitting device 6 and its corresponding second pixel circuit 3. For example, it could be like this: Figure 2 As illustrated, in the direction perpendicular to the plane of the array substrate 1, the second light-emitting device 6 overlaps with its corresponding second pixel circuit 3, and only a short second connecting portion 8 is needed to achieve electrical connection between the second light-emitting device 6 and its corresponding second pixel circuit 3. However, in the direction perpendicular to the plane of the array substrate 1, at least a portion of the first light-emitting device 5 does not overlap with its corresponding second pixel circuit 3, and a longer first connecting portion 7 is needed to achieve electrical connection between this portion of the first light-emitting device 5 and its corresponding second pixel circuit 3.

[0017] Alternatively, the distance from the first light-emitting device 5 to the edge of the display panel is less than the distance from the second light-emitting device 6 to the edge of the display panel; that is, the first light-emitting device 5 is closer to the edge of the display panel. For example, see... Figure 1 and Figure 2 To achieve a borderless display, in one design, at least some of the light-emitting devices at the edge positions can be ( Figure 1 The pixel circuits corresponding to the light-emitting devices (outside the dashed box) are designed to be recessed towards the center, increasing the distance between these light-emitting devices and their corresponding pixel circuits. Therefore, a longer connection is needed for electrical connection between these light-emitting devices and their corresponding pixel circuits. The light-emitting devices in the middle position (… Figure 1 The pixel circuits corresponding to the light-emitting devices (within the dashed box) remain in their original positions, resulting in a small distance between them. Therefore, only a short connection is needed for electrical connection between these light-emitting devices and their corresponding pixel circuits. Specifically, the light-emitting device at the edge can be understood as the first light-emitting device 5, its corresponding pixel circuit as the first pixel circuit 2, and the connection between them as the first connection part 7. The light-emitting device at the middle position can be understood as the second light-emitting device 6, its corresponding pixel circuit as the second pixel circuit 3, and the connection between them as the second connection part 8.

[0018] The number of vias corresponding to the first connecting portion 7 is greater than the number of vias corresponding to the second connecting portion 8. For ease of distinction, in the accompanying drawings of this invention, the vias corresponding to the first connecting portion 7 are indicated by reference numeral 9-1, and the vias corresponding to the second connecting portion 8 are indicated by reference numeral 9-2.

[0019] In this embodiment of the invention, the via 9-1 corresponding to the first connecting portion 7 can refer to a via that contacts the first connecting portion 7. For example, the via 9-1 corresponding to the first connecting portion 7 may include a connection via 9-11 between the first connecting portion 7 and its corresponding first pixel circuit 2, and a connection via 9-12 between the first connecting portion 7 and its corresponding first light-emitting device 5. The via 9-2 corresponding to the second connecting portion 8 can refer to a via that contacts the second connecting portion 8. For example, the via 9-2 corresponding to the second connecting portion 8 may include a connection via 9-21 between the second connecting portion 8 and its corresponding second pixel circuit 3, and a connection via 9-22 between the second connecting portion 8 and its corresponding second light-emitting device 6.

[0020] In this embodiment of the invention, the first pixel circuit 2 outputs a first driving signal to its corresponding first light-emitting device 5 to drive the first light-emitting device 5 to emit light, and the second pixel circuit 3 outputs a second driving signal to its corresponding second light-emitting device 6 to drive the second light-emitting device 6 to emit light. When the length of the first connecting portion 7 is greater than the length of the second connecting portion 8, or the distance between the first light-emitting device 5 and its corresponding first pixel circuit 2 is greater than the distance between the second light-emitting device 6 and its corresponding second pixel circuit 3, or the distance from the first light-emitting device 5 to the edge of the display panel is less than the distance from the second light-emitting device 6 to the edge of the display panel, it means that the extension distance of the first connecting portion 7 will be longer, and correspondingly, the trace resistance of the first connecting portion 7 will be greater. By increasing the number of vias corresponding to the first connecting portion 7, this embodiment of the invention can reduce the via resistance, thereby reducing the equivalent resistance of the transmission path where the first driving signal is located, balancing the difference in equivalent resistance of the transmission paths where the first driving signal and the second driving signal are located, thereby weakening the voltage drop difference between the first driving signal and the second driving signal during transmission, and improving the brightness uniformity of the display panel.

[0021] In some feasible implementations, the number of vias between the first connecting portion 7 and its corresponding first pixel circuit 2 is greater than the number of vias between the second connecting portion 8 and its corresponding second pixel circuit 3. For example, compared to Figure 3 and Figure 4 The number of vias 9-11 between the first connecting portion 7 and its corresponding first pixel circuit 2 is greater than the number of vias 9-21 between the second connecting portion 8 and its corresponding second pixel circuit 3. And / or, the number of vias between the first connecting portion 7 and its corresponding first light-emitting device 5 is greater than the number of vias between the second connecting portion 8 and its corresponding second light-emitting device 6. For example, Figure 5 This is another connection diagram of the first pixel circuit and the first light-emitting device provided in an embodiment of the present invention, for comparison. Figure 5 and Figure 4 The number of vias 9-12 between the first connecting part 7 and its corresponding first light-emitting device 5 is greater than the number of vias 9-22 between the second connecting part 8 and its corresponding second light-emitting device 6.

[0022] The equivalent resistance of the transmission path containing the first driving signal includes at least the via resistance between the first pixel circuit 2 and the first connecting portion 7, the trace resistance of the first connecting portion 7, and the via resistance between the first connecting portion 7 and the first light-emitting device 5. The equivalent resistance of the transmission path containing the second driving signal includes at least the via resistance between the second pixel circuit 3 and the second connecting portion 8, the trace resistance of the second connecting portion 8, and the via resistance between the second connecting portion 8 and the second light-emitting device 6. Since the first connecting portion 7 is longer, its trace resistance is greater than that of the second connecting portion 8.

[0023] In this embodiment of the invention, by providing a greater number of vias between the first connecting portion 7 and the first pixel circuit 2, the via resistance between the first pixel circuit 2 and the first connecting portion 7 can be reduced, and / or, by providing a greater number of vias between the first connecting portion 7 and the first light-emitting device 5, the via resistance between the first connecting portion 7 and the first light-emitting device 5 can be reduced, thereby using the via resistance difference to compensate for the resistance difference of the trace portion in the two transmission paths, so as to balance the voltage drop of the first driving signal and the second driving signal during transmission.

[0024] In one example, the number of vias 9-21 between the second connecting part 8 and the second pixel circuit 3 is 1, the number of vias 9-22 between the second connecting part 8 and the second light-emitting device 6 is 2, and the number of vias 9-11 between the first connecting part 7 and the first light-emitting device 5 is 2. By increasing the number of vias 9-12 between the first connecting part 7 and the first pixel circuit 2 to 2, the via resistance at the connection position between the first connecting part 7 and the first pixel circuit 2 can be reduced.

[0025] In some feasible implementations, Figure 6 A cross-sectional view of a display panel provided in an embodiment of the present invention, such as... Figure 6 As shown, the array substrate 1 includes a substrate 10, a transistor layer 11 located on one side of the substrate 10, a first metal layer 12 located on the side of the transistor layer 11 away from the substrate 10, a first planarization layer 13 located on the side of the first metal layer 12 away from the substrate 10, a second metal layer 14 located on the side of the first planarization layer 13 away from the substrate 10, a second planarization layer 15 located on the side of the second metal layer 14 away from the substrate 10, and a third metal layer 16 located on the side of the second planarization layer 15 away from the substrate 10.

[0026] The transistor layer 11 includes a first pixel circuit 2 and a second pixel circuit 3; the first metal layer 12 includes a first lead 17 and a second lead 18; the second metal layer 14 includes a first connection portion 7 and a second connection portion 8, the first connection portion 7 being electrically connected to its corresponding first pixel circuit 2 via the first lead 17, and the second connection portion 8 being electrically connected to its corresponding second pixel circuit 3 via the second lead 18; the third metal layer 16 includes a first electrode 19, and the first connection portion 7 being electrically connected to the first light-emitting device 5 via the first electrode 19. Furthermore, the third metal layer 16 also includes a second electrode 20, a third electrode 21, and a fourth electrode 22, the second connection portion 8 being electrically connected to the second light-emitting device 6 via the second electrode 20, the third electrode 21 being electrically connected to the first light-emitting device 5, and the fourth electrode 22 being electrically connected to the second light-emitting device 6. More specifically, the light-emitting device includes an anode and a cathode. In this configuration, the anode of the first light-emitting device 5 is electrically connected to the first electrode 19, the cathode of the first light-emitting device 5 is electrically connected to the third electrode 21, the anode of the second light-emitting device 6 is electrically connected to the second electrode 20, and the cathode of the second light-emitting device 6 is electrically connected to the fourth electrode 22.

[0027] In one example, see again Figure 5 The first pixel circuit 2 and the second pixel circuit 3 include multiple transistors T and capacitors C. The transistor layer 11 includes a buffer layer 32, a semiconductor layer 33, a first interlayer dielectric layer 34, a gate metal layer 35, a second interlayer dielectric layer 36, a plate metal layer 37, and a third interlayer dielectric layer 38 stacked along a direction away from the substrate 10. The semiconductor layer 33 includes the active layer p of the transistor T, the gate metal layer 35 includes the gate g of the transistor T and the first plate c1 of the capacitor C, and the plate metal layer 37 includes the second plate c2 of the capacitor C.

[0028] The number of vias between the first connecting portion 7 and the first lead 17 is greater than the number of vias between the second connecting portion 8 and the second lead 18, i.e., see [link to documentation]. Figure 6 The number of vias 9-1 between the first connecting part 7 and the first lead 17 is greater than the number of vias 9-2 between the second connecting part 8 and the second lead 18.

[0029] In the film structure of the array substrate 1, the first pixel circuit 2 is led to and connected to the first connection portion 7 via the first lead 17. The first connection portion 7 is then electrically connected to the first light-emitting device 5 via the first electrode 19. The first metal layer 12 where the first connection portion 7 is located is situated between the second metal layer 14 where the first lead 17 is located and the third metal layer 16 where the first electrode 19 is located, with a second planarization layer 15 separating the first metal layer 12 and the third metal layer 16. Therefore, by increasing the number of vias between the first connection portion 7 and the first lead 17, any unevenness in the film layer that might be caused by the added vias will be filled by the upper second planarization layer 15, thus not affecting the flatness of the upper film layer. In other words, choosing to add vias at this location has less limitation on the number of new vias, allowing for more vias to achieve lower via resistance.

[0030] Furthermore, see again Figure 3 The vias 9-11 between the first connecting part 7 and the first lead 17 are located on one side of the corresponding first pixel circuit 2 in the first direction x, and at least some of the vias are arranged along the second direction y, which intersects the first direction x.

[0031] When increasing the number of vias between the first connecting part 7 and the first lead 17, at least some of the vias are arranged laterally, which can reduce the vertical dimension required for the new vias. Thus, the end of the first lead 17 connected to the via can be extended laterally, and the spacing design between adjacent first pixel circuits 2 in the first direction x will not be affected due to wiring conflicts.

[0032] In some feasible implementations, combined with Figure 1 and Figure 2 The first pixel circuit 2 is located between the second pixel circuit 3 and the edge of the display panel, and at least part of the distance between the first pixel circuit 2 and the edge of the display panel is greater than the distance between its corresponding first light-emitting device 5 and the edge of the display panel.

[0033] In one example, the display panel includes a central display area and an edge display area surrounding the central display area, with a first pixel circuit 2 located in the edge display area and a second pixel circuit 3 located in the central display area.

[0034] Figure 7 for Figure 2 A schematic diagram of the connection between the first pixel circuit and the first light-emitting device in region A, combined with... Figure 1 , Figure 2 and Figure 7The first pixel circuit 2 includes a first sub-circuit 39 and a second sub-circuit 40. The distance between the first sub-circuit 39 and the edge of the display panel is less than the distance between the second sub-circuit 40 and the display panel, meaning the first sub-circuit is closer to the periphery. The length of the first connecting portion 7 connected to the first sub-circuit 39 is greater than the length of the first connecting portion 7 connected to the second sub-circuit 40, and the number of vias corresponding to the first connecting portion 7 connected to the first sub-circuit 39 is greater than the number of vias corresponding to the first connecting portion 7 connected to the second sub-circuit 40.

[0035] In one example, see Figure 7 Three vias 9-11 are provided between the first sub-circuit 39 and its corresponding first connection part 7, and two vias 9-11 are provided between the second sub-circuit 40 and its corresponding first connection part 7.

[0036] In some panel structures, to achieve a borderless design, the edge pixel circuits are recessed. When the edge pixel circuits are moved, the distance between them and their corresponding edge-emitting devices increases. This necessitates longer connecting lines to reach the corresponding edge-emitting devices, resulting in higher trace resistance for these connecting lines.

[0037] In this embodiment of the invention, these edge pixel circuits can be first pixel circuits 2, and correspondingly, the edge light-emitting devices are first light-emitting devices 5. By setting more vias on the connection lines corresponding to these edge pixel circuits, this embodiment of the invention can reduce the via resistance, thereby reducing the equivalent resistance on the signal transmission path, weakening the voltage drop difference of the driving signals output by the edge pixel circuits and the middle pixel circuits in the transmission path, and effectively improving the display consistency between the edge display area and the middle display area.

[0038] Furthermore, the connection distance between the edge pixel circuit and its corresponding edge light-emitting device may vary at different locations. For example, edge pixel circuits in different rows or columns may be recessed to varying degrees relative to their corresponding first light-emitting devices. Edge pixel circuits closer to the panel edge have a greater distance from their corresponding first light-emitting devices, resulting in a larger connection distance between these edge pixel circuits and their corresponding first light-emitting devices. To address this, this embodiment of the invention further differentiates the number of vias on the connecting lines of different edge pixel circuits. By setting more vias for longer first connecting portions, the equivalent resistance differences in the transmission paths of different first driving signals can be further balanced, making the voltage drop of the first driving signals output by different edge pixel circuits during transmission more consistent, thereby improving the display uniformity at different locations in the edge display area.

[0039] in, Figure 2The positions of the first sub-circuit 39 and the second sub-circuit 40 shown are for illustrative purposes only. There are multiple rows or columns of first pixel circuits 2 between the second pixel circuit 3 and the edge of the display panel. Among them, at least one row or column of first pixel circuits 2 closer to the edge of the panel is the first sub-circuit 39, and at least one row or column of first pixel circuits 2 closer to the second pixel circuit 3 is the second sub-circuit 40.

[0040] In one example, the upper and lower halves of the display panel each include 4 to 9 rows of first pixel circuits 2. In the upper half, the first and second rows of first pixel circuits 2, which are closer to the upper edge of the display panel, are first sub-circuits 39, and the third and fourth rows of first pixel circuits 2 are second sub-circuits 40. In the lower half, the last two rows of first pixel circuits 2, which are closer to the lower edge of the display panel, are first sub-circuits 39, and the third and fourth rows of first pixel circuits 2 are second sub-circuits 40.

[0041] In this embodiment of the invention, the circuit structures of the first pixel circuit 2 and the second pixel circuit 3 can be the same. Figure 8 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 9 The first pixel circuit 2 and the second pixel circuit 3 may respectively include a pulse amplitude modulation circuit (PAM) and a pulse width modulation circuit (PWM).

[0042] The pulse amplitude modulation (PAM) circuit includes a first sub-capacitor C1, a second sub-capacitor C2, a first driving transistor M3, a first data writing transistor M2, a first threshold compensation transistor M4, a first reset transistor M7, a second reset transistor M5, a first light-emitting control transistor M1, a second light-emitting control transistor M6, a first control transistor M8, a second control transistor M9, and a third control transistor M10. The pulse width modulation (PWM) circuit includes a second driving transistor M13, a second data writing transistor M12, a second threshold compensation transistor M14, a third reset transistor M15, a fourth reset transistor M17, a third light-emitting control transistor M11, a fourth light-emitting control transistor M16, and a third sub-capacitor C3.

[0043] The first pixel circuit 2 and the second pixel circuit 3 are respectively electrically connected to the first scan line PAM_S2, the second scan line PAM_S1, the third scan line PWM_S2, the fourth scan line PWM_S1, the first light emission control line PAM_EM, the second light emission control line PWM_EM, the first data line PAM_Data, the second data line PWM-Data, the first reset line PAM_INIT, the second reset line PAM_REF, the third reset line PWM_REF, the first power supply line PWM_VDD, the sweep frequency signal line SWEEP, and the second power supply line PAM_VDD.

[0044] The second power supply unit PAM_VDD can be disposed on the same layer as the first connecting part 7 and the second connecting part 8. The second power supply unit PAM_VDD has a large area and can be provided with multiple vent holes. The vent holes are used to discharge the gas generated in the film layer process below, preventing gas accumulation and film layer delamination problems.

[0045] Figure 10 This is another schematic diagram showing the connection between the first pixel circuit and the first light-emitting device provided in an embodiment of the present invention. Figure 11 This is another connection diagram of the second pixel circuit and the second light-emitting device provided in an embodiment of the present invention, as shown below. Figure 10 and Figure 11 As shown, the first pixel circuit 2 is led to the bottom of the first pixel circuit 2 via the first lead 17, and then led to the first electrode 19 via the first connecting part 7 and connected to the first electrode 19, and electrically connected to the first light-emitting device 5 via the first electrode 19. The second pixel circuit 3 is led to the bottom of the second pixel circuit 3 via the second lead 18, and then led to the second electrode 20 via the second connecting part 8 and connected to the second electrode 20, and electrically connected to the second light-emitting device 6 via the second electrode 20.

[0046] In some feasible implementations, Figure 12 Another cross-sectional view of the display panel provided in an embodiment of the present invention, such as... Figure 12 As shown, the first connecting part 7 is connected to the first through hole 41, and the second connecting part 8 is connected to the second through hole 42. In at least one direction, the size of at least one first through hole 41 is larger than the size of the second through hole 42.

[0047] In this configuration, at least a portion of the first via 41 and at least a portion of the second via 42 are located in the same layer. Within the same layer, in at least one direction, the size of at least one first via 41 is larger than the size of the second via 42. For example, the first via 41 includes a via 9-11 connecting the first pixel circuit 2 and the first connection portion 7, and the second via 42 includes a via 9-21 connecting the second pixel circuit 3 and the second connection portion 8. And / or, the first via 41 includes a via 9-12 connecting the first connection portion 7 and the first light-emitting device 5, and the second via 42 includes a via 9-22 connecting the second connection portion 8 and the second light-emitting device 6.

[0048] The larger the via size, the smaller the via resistance. Increasing the size of at least some of the vias corresponding to the first connection portion 7 can further reduce the equivalent resistance of the transmission path where the first drive signal is located, thereby further balancing the difference in equivalent resistance between the transmission paths where the first drive signal and the second drive signal are located.

[0049] In some feasible implementations, the number of vias corresponding to the first connection portion 7 connected to the first light-emitting device 5 of the first color is greater than the number of vias corresponding to the first connection portion 7 connected to the first light-emitting device 5 of the second color.

[0050] The number of vias corresponding to the first connection portion 7 connected to the first light-emitting device 5 of at least two colors is designed differently, and the voltage drop effect of the first driving signal received by the first light-emitting device 5 of different colors can be finely controlled to improve the display difference between the light-emitting devices of different colors to different degrees.

[0051] In one possible implementation, the first color includes green.

[0052] Green light has a more significant impact on the display effect. Therefore, the number of vias corresponding to the first connecting part 7 connected to the green first light-emitting device 5 can be designed to be greater, which can better balance the display difference between the green first light-emitting device 5 and the green second light-emitting device 6.

[0053] In some feasible implementations, the number of vias corresponding to the first connecting part 7 is m more than the number of vias corresponding to the second connecting part 8. m can be set to less than or equal to 9 to avoid the number of vias corresponding to the first connecting part 7 being too large and affecting the reliability of the film layer.

[0054] See again for some feasible implementations. Figure 3 The array substrate 1 includes a first conductive portion 43, and a first connecting portion 7 is in contact with the first conductive portion 43 through a corresponding at least partial via. In other words, the at least partial via corresponding to the first connecting portion 7 refers to the via connecting the first connecting portion 7 and the first conductive portion 43.

[0055] The first conductive portion 43 may include the aforementioned first lead 17 and first electrode 19. The first connection portion 7 is in contact with the first lead 17 through its corresponding partial via, thereby realizing the electrical connection between the first connection portion 7 and the first pixel circuit 2, and the first connection portion 7 is in contact with the first electrode 19 through its corresponding partial via.

[0056] See again for some feasible implementations. Figure 3 The array substrate 1 includes a first conductive part 43, and a first connecting part 7 is connected in parallel with the first conductive part 43 through at least two corresponding vias.

[0057] The first conductive portion 43 may include the aforementioned first lead 17 and first electrode 19. The first connecting portion 7 and the first conductive portion 43 are connected in parallel through at least two vias. The via resistance between the first connecting portion 7 and the first conductive portion 43 is reduced, which can effectively reduce the equivalent resistance of the transmission path, reduce the voltage drop loss of the first driving signal during transmission, and compensate for the voltage drop increase caused by the longer first connecting portion 7.

[0058] In some feasible implementations, Figure 13 This is a schematic diagram of a first connecting portion provided in an embodiment of the present invention. Figure 14 This is another cross-sectional view of the display panel provided in an embodiment of the present invention. Figure 15 This is another schematic diagram of the first connecting portion provided in an embodiment of the present invention. Figure 16 This is another cross-sectional view of the display panel provided in an embodiment of the present invention. Figure 17 This is another schematic diagram of the first connecting portion provided in an embodiment of the present invention. Figure 18 Another cross-sectional view of the display panel provided in the embodiment of the present invention, such as... Figures 13-18 As shown, the first connecting portion 7 includes at least two first connecting sub-ports 44. The at least two first connecting sub-ports 44 are on different layers and are electrically connected through vias. Each first connecting sub-port 44 corresponds to its own via. The via corresponding to the first connecting sub-port 44 can be understood as a via that contacts the first connecting sub-port 44.

[0059] In some implementations, see Figure 13 and Figure 14 The first connecting part 7 can be understood as the first connecting line 45 connecting the first lead 17 and the first electrode 19. This first connecting line 45 can adopt a cross-line design. The cross-lines of different layers can be regarded as at least two first connecting sub-parts 44 included in the first connecting part 7.

[0060] In some implementations, see Figures 15-18The first connection portion 7 can also be understood as the entire connection structure connecting the first pixel circuit 2 and the first light-emitting device 5. That is, the first connection portion 7 includes the first lead 17, the first electrode 19, and the first connection line 45 connecting the first lead 17 and the first electrode 19. The first lead 17 and the first electrode 19 can be considered as different first connection sub-ports 44. As for the first connection line 45 between the first lead 17 and the first electrode 19, when the first connection line 45 is a single-layer trace, see [reference needed]. Figure 15 and Figure 16 The first connecting line 45 can be considered as a first connecting sub-section 44. When the first connecting line 45 adopts a crossover design, see [reference needed]. Figure 17 and Figure 18 The crossover lines of different layers can be regarded as different first connecting subsections 44.

[0061] When the first connection portion 7 includes at least two first connection sub-ports 44, the connection vias between different first connection sub-ports 44 can be used to increase the number of vias corresponding to the first connection portion 7. For example, the first connection line 45 in the first connection portion 7 can be designed to cross lines, and different cross lines are connected by vias. Therefore, more vias can be set in its entire transmission path, so that the equivalent resistance of the transmission path is smaller.

[0062] To facilitate differentiation, in Figures 13-18 In the figure, the via between the first connecting line 45 and the first lead 17 is indicated by reference numeral 9-11, the via between the first connecting line 45 and the first electrode 19 is indicated by reference numeral 9-12, and the via between different cross lines in the first connecting line 45 is indicated by reference numeral 9-13.

[0063] See again for some feasible implementations. Figure 13 and Figure 17 The first connecting sub-part 44 includes a first sub-part 46 and a second sub-part 47, and the extending directions of the first sub-part 46 and the second sub-part 47 intersect. In one example, the first connecting line 45 adopts a cross-line design, and at least two first connecting sub-parts 44 corresponding to at least two layers of cross-lines include a first sub-part 46 and a second sub-part 47.

[0064] See Figure 2 The relative positional relationship between the first pixel circuit 2 and its corresponding first light-emitting device 5 at different locations is different. The first connecting part 7 usually has a longitudinally extending part and a laterally extending part during its extension process. By making the two extension directions of the part cross the line design, the need to avoid other lines can be met, making the extension method more flexible.

[0065] In some feasible implementations, at least some of the vias corresponding to the first connection portion 7 are located in different layers, wherein the total number of vias corresponding to the first connection portion 7 is greater than the total number of vias corresponding to the second connection portion 8.

[0066] In the through hole corresponding to the first connecting portion 7, for example, as shown... Figure 14 and Figure 18 As shown, the array substrate 1 also includes a third planarization layer 48, with vias 9-13 between the two crossover lines in the first connection line 45 located in the third planarization layer 48, vias 9-11 between the first connection line 45 and the first lead 17 located in the first planarization layer 13, and vias 9-12 between the first connection line 45 and the first electrode 19 located in the second planarization layer 15. Alternatively, as... Figure 16 As shown, the via 9-11 between the first connecting part 7 and the first lead 17 is located in the first planarization layer 13, and the via 9-12 between the first connecting part 7 and the first electrode 19 is located in the second planarization layer 15.

[0067] The vias corresponding to the first connection portion 7, distributed across different layers, are all located on the transmission path where the first driving signal is located, and therefore are all related to the equivalent resistance of that transmission path. The total number of vias corresponding to the first connection portion 7 is greater than the total number of vias corresponding to the second connection portion 8, resulting in a smaller via resistance in the transmission path where the first driving signal is located, and consequently a smaller equivalent resistance in that transmission path, reducing the difference in equivalent resistance with that of the second driving signal transmission path.

[0068] In some feasible implementations, Figure 19 Another cross-sectional view of the display panel provided in the embodiment of the present invention, such as... Figure 19 As shown, at least some of the vias corresponding to the first connection portion 7 are located in different insulating layers, wherein, in at least one layer, the number of vias corresponding to the first connection portion 7 is greater than the number of vias corresponding to the second connection portion 8.

[0069] In one example, see Figure 19 The second connection portion 8 includes a second connection line 49 connecting the second lead 18 and the second electrode 20. The second connection line 49 includes at least two second sub-connection portions 50, which are on different layers and connected by vias. Specifically, vias 9-13 and 9-23 between the two layers of crossover lines in the first connection line 45 are located in the third planarization layer 48; vias 9-11 between the first connection line 45 and the first lead 17, and vias 9-21 between the second connection line 49 and the second lead 18 are located in the first planarization layer 13; and vias 9-12 between the first connection line 45 and the first electrode 19, and vias 9-22 between the second connection line 49 and the second electrode 20 are located in the second planarization layer 15.

[0070] In the first planarization layer 13, the number of vias 9-11 corresponding to the first connecting portion 7 is greater than the number of vias 9-21 corresponding to the second connecting portion 8, and in the third planarization layer 48, the number of vias 9-13 corresponding to the first connecting portion 7 is greater than the number of vias 9-23 corresponding to the second connecting portion 8.

[0071] The vias corresponding to the first connection portion 7, distributed across different layers, are all located on the transmission path of the first driving signal, and therefore are all related to the equivalent resistance of that transmission path. In at least one layer, the number of vias corresponding to the first connection portion 7 is greater than the number of vias corresponding to the second connection portion 8. The number of vias corresponding to the first connection portion 7 can be increased by adding vias in at least one layer, thereby reducing the via resistance of the first driving signal transmission path, and further reducing the equivalent resistance of that transmission path, thus decreasing the difference in equivalent resistance with that of the second driving signal transmission path.

[0072] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 20 This is a schematic diagram of a display device provided in an embodiment of the present invention. Figure 21 Another schematic diagram of the display device provided in the embodiment of the present invention, such as... Figure 20 and Figure 21 As shown, the display device includes the aforementioned display panel 100.

[0073] The display device in the embodiments of the present invention can be Figure 20 The mobile phone shown, or electronic devices such as tablet computers, laptops, e-readers, or televisions, or, may also be... Figure 21 The electronic devices shown, such as large splicing screens, include at least two display panels 100 in their display devices.

[0074] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: An array substrate, including a first pixel circuit and a second pixel circuit; The light-emitting device is located on the array substrate and includes a first light-emitting device and a second light-emitting device. The first light-emitting device is electrically connected to its corresponding first pixel circuit through a first connecting part, and the second light-emitting device is electrically connected to its corresponding second pixel circuit through a second connecting part. The number of vias corresponding to the first connecting part is greater than the number of vias corresponding to the second connecting part; Wherein, the length of the first connecting part is greater than the length of the second connecting part; Alternatively, the distance between the first light-emitting device and its corresponding first pixel circuit is greater than the distance between the second light-emitting device and its corresponding second pixel circuit; Alternatively, the distance from the first light-emitting device to the edge of the display panel is less than the distance from the second light-emitting device to the edge of the display panel.

2. The display panel according to claim 1, characterized in that, The number of vias between the first connecting portion and its corresponding first pixel circuit is greater than the number of vias between the second connecting portion and its corresponding second pixel circuit; And / or, the number of vias between the first connecting portion and its corresponding first light-emitting device is greater than the number of vias between the second connecting portion and its corresponding second light-emitting device.

3. The display panel according to claim 1, characterized in that, The array substrate includes: Substrate; A transistor layer, located on one side of the substrate, includes the first pixel circuit and the second pixel circuit; A first metal layer, located on the side of the transistor layer away from the substrate, includes a first lead and a second lead; A first planarization layer is located on the side of the first metal layer away from the substrate; The second metal layer is located on the side of the first planarization layer away from the substrate, and includes the first connection portion and the second connection portion, wherein the first connection portion is electrically connected to the corresponding first pixel circuit through the first lead, and the second connection portion is electrically connected to the corresponding second pixel circuit through the second lead. The second planarization layer is located on the side of the second metal layer away from the substrate; The third metal layer, located on the side of the second planarization layer away from the substrate, includes a first electrode, and the first connection portion is electrically connected to the first light-emitting device through the first electrode; The number of vias between the first connecting portion and the first lead is greater than the number of vias between the second connecting portion and the second lead.

4. The display panel according to claim 3, characterized in that, The via between the first connection portion and the first lead is located on one side of the corresponding first pixel circuit in a first direction, and at least a portion of the vias are arranged along a second direction, which intersects the first direction.

5. The display panel according to claim 1, characterized in that, The first pixel circuit is located between the second pixel circuit and the edge of the display panel, and at least a portion of the distance between the first pixel circuit and the edge of the display panel is greater than the distance between its corresponding first light-emitting device and the edge of the display panel; The first pixel circuit includes a first sub-circuit and a second sub-circuit, wherein the distance between the first sub-circuit and the edge of the display panel is smaller than the distance between the second sub-circuit and the display panel; Wherein, the length of the first connection portion connected to the first sub-circuit is greater than the length of the first connection portion connected to the second sub-circuit, and the number of vias corresponding to the first connection portion connected to the first sub-circuit is greater than the number of vias corresponding to the first connection portion connected to the second sub-circuit.

6. The display panel according to claim 1, characterized in that, The first connecting part is connected to the first through hole, and the second connecting part is connected to the second through hole. In at least one direction, the size of at least one of the first through holes is larger than the size of the second through hole.

7. The display panel according to claim 1, characterized in that, The number of vias corresponding to the first connection portion connected to the first light-emitting device of the first color is greater than the number of vias corresponding to the first connection portion connected to the first light-emitting device of the second color.

8. The display panel according to claim 7, characterized in that, The first color includes green.

9. The display panel according to claim 1, characterized in that, The number of vias corresponding to the first connecting part is m more than the number of vias corresponding to the second connecting part, where m≤9.

10. The display panel according to claim 1, characterized in that, The array substrate includes a first conductive portion, and the first connecting portion is in contact with the first conductive portion through at least a portion of the corresponding via.

11. The display panel according to claim 1, characterized in that, The array substrate includes a first conductive portion, and the first connecting portion is connected in parallel with the first conductive portion through at least two corresponding vias.

12. The display panel according to claim 1, characterized in that, The first connection portion includes at least two first connection sub-parts, which are on different layers and electrically connected through the vias, with each first connection sub-part corresponding to its respective via.

13. The display panel according to claim 12, characterized in that, The first connecting sub-part includes a first sub-part and a second sub-part, and the extending directions of the first sub-part and the second sub-part intersect.

14. The display panel according to claim 1, characterized in that, At least some of the vias corresponding to the first connection portion are located in different layers, wherein the total number of vias corresponding to the first connection portion is greater than the total number of vias corresponding to the second connection portion.

15. The display panel according to claim 1, characterized in that, At least some of the vias corresponding to the first connection portion are located in different layers, wherein, in at least one layer, the number of vias corresponding to the first connection portion is greater than the number of vias corresponding to the second connection portion.

16. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 15.

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