A load adaptive distributed charge pump for an array of non-volatile devices

Abstract

The application discloses a load adaptive distributed charge pump for a nonvolatile device array and belongs to the technical field of integrated circuits. The circuit adopts a distributed and reconfigurable charge pump architecture, cooperates with a master-slave charge pump through a dynamic mode switching mechanism, and realizes high-efficiency voltage conversion and multi-voltage domain output in a wide load range; the circuit can cope with the demand for multiple high voltages in a memory computing array and greatly improves the stability and robustness of the memory computing array during operation.

Description

Technical Field

[0001] This invention relates to a load-adaptive distributed charge pump for non-volatile device arrays, belonging to the field of integrated circuit technology. Background Technology

[0002] With the explosive growth of data-intensive applications such as artificial intelligence and the Internet of Things, the traditional von Neumann architecture faces a severe "memory wall" challenge: the data access speed of memory lags far behind the processing speed of the processor, causing the CPU to frequently enter a waiting state, and the system energy efficiency encounters a bottleneck. In-memory computing architecture, as a breakthrough solution, embeds computing functions into storage units, completes operations directly within the storage array, and restructures the internal physical connections of the chip to reduce data transfer paths and frequency, which is expected to completely eliminate data migration overhead and break this long-standing bottleneck restricting computing performance. However, common solid-state non-volatile memories require charge pumps to generate the high voltage required for read and write operations (this is mainly because non-volatile memories rely on floating-gate transistors to store charge, and read and write operations are distinguished by changing the threshold voltage). Furthermore, read, program, and erase operations in flash memory each require different high voltages. This voltage mismatch of non-volatile memory devices brings a huge challenge to realizing in-memory computing.

[0003] To realize the storage and computing functions of the in-memory computing array based on non-volatile device arrays, the peripheral driving system of the in-memory computing array needs to generate, transmit and switch various positive and negative high voltages at the word lines and bit lines of the array. The LS-type driving system (Level Shifter) is mainly composed of level conversion circuits and switching transistors to realize voltage conversion between different voltage domains. The level conversion circuit used in the driving system converts the low-level digital signal into the positive or negative high voltage required by the in-memory computing device array.

[0004] Current research identifies two main types of driving systems for in-memory computing device arrays: one employs an on-chip LS-type driving system for voltage transmission and switching, while voltage generation is achieved externally via a power supply chip on the circuit board; the other integrates an on-chip charge pump in an LS-type driving system, where voltage generation is achieved using a charge pump circuit, and the LS driving circuit handles voltage transmission and switching. The first method, where voltage generation and usage occur on-chip and externally respectively, results in low system coupling, hindering stable performance. Furthermore, it requires additional PCB design and power management circuitry, increasing system cost and design complexity. This approach relies on an external auxiliary power supply to address the limitations of global voltage generation, failing to fully leverage the integrated advantages of the in-memory computing device array. In contrast, the second method offers advantages such as smaller size, lower power consumption, faster control, and easier integration. By employing an on-chip charge pump, voltage regulation and high-density power distribution can be achieved within the chip.

[0005] However, traditional switched-capacitor charge pumps employ a fixed topology, using a clock signal to control the switches and flying capacitors to achieve step-by-step charge transfer and voltage conversion. Their main drawback is that conversion efficiency is drastically affected by the load: under light load conditions, switching losses and static power consumption are too high, leading to a sharp drop in efficiency; under heavy load conditions, conduction losses caused by output impedance become dominant, limiting driving capability and efficiency. Furthermore, their output voltage is typically fixed or has a limited adjustment range, making it difficult to meet the needs of complex systems requiring multiple precise voltage domains.

[0006] On the other hand, in-memory computing chips consist of multiple in-memory computing arrays, each requiring different high voltages from the driving system. The highly parallel computing mode and dynamic sparse workload of the in-memory computing architecture pose extremely high challenges to on-chip power management. Specifically, the simultaneous switching of hundreds to thousands of processing units generates significant peak currents, which can lead to severe voltage drops in the power supply network, threatening the accuracy and reliability of the computation. For chips composed of multiple in-memory computing arrays, the power efficiency of the power supply module drops sharply under light loads when some arrays are in a dormant state. In addition, the analog computing arrays, digital logic, and interface circuits in in-memory computing chips typically require multiple voltage domains; traditional solutions relying on off-chip voltage regulators increase packaging complexity and I / O costs.

[0007] Furthermore, charge pump architectures have specific limitations in powering compute-in-memory (CIM) arrays. Wang, in "A small ripple and high-efficiency word line voltage generator for 3-D nandFlash memories," introduces a reconfigurable closed-loop charge pump that minimizes output ripple voltage through a proposed dynamic pump clock voltage and frequency scaling scheme. However, this charge pump is a single-branch pump without mode switching capabilities, resulting in significant efficiency fluctuations under wider load requirements. Xu, in "A programmable high efficiency charge pump system for embedded flash memory with improved current driving capability," proposes a high-efficiency word line voltage generator with a wide load range. This system adaptively activates appropriate charge pump combinations based on the current load. However, this design has only one output port, cannot provide multiple voltages, and is unsuitable for powering CIM arrays.

[0008] Therefore, there is an urgent need for a new type of charge pump architecture that can efficiently generate high voltage within a single chip, while having the ability to adaptively adjust according to the actual load scale and flexibly provide multiple stable voltage domains to meet the stringent power supply requirements of next-generation non-volatile in-memory computing chips and other high-performance integrated systems. Summary of the Invention

[0009] To efficiently generate high voltage within a single chip and possess the ability to adaptively adjust according to the actual load scale, while flexibly providing multiple stable voltage domains, this invention provides a load-adaptive distributed charge pump for non-volatile device arrays. The circuit adopts a distributed, reconfigurable charge pump architecture, and through master-slave charge pump cooperative operation and dynamic mode switching mechanism, it achieves high-efficiency voltage conversion and multi-voltage domain output over a wide load range.

[0010] This load-adaptive distributed charge pump includes a master charge pump module, a mode switching module, a slave charge pump module, and a clock generation module. These modules work closely together at the circuit and control levels to perform functions such as voltage boosting, load monitoring, and operating mode adjustment. Its core implementation steps are as follows: The main charge pump module receives external input voltage at its input terminal. V IN The output terminal is connected to the input terminals of several slave charge pump modules; the several slave charge pump modules together form a slave charge pump array. The output terminal of the clock generation module is connected to the master charge pump module, the slave charge pump array, and the mode switching module. The output of each slave charge pump module in the slave charge pump array is connected to the load on one side and to the mode switching module on the other side; the output terminal of the mode switching module is connected to the master charge pump module. The main charge pump module includes several main charge pump units and a first feedback resistor. R F1 Second feedback resistor R F2 First load capacitor C L A first comparator, several two-input AND gates, and a corresponding clock generator; Furthermore, the main charge pump module is used to receive off-chip input voltage. V IN and boost it to an intermediate voltage. V CP Then input to the charge pump array; Furthermore, several main charge pump units in the main charge pump module adopt a multi-row parallel charge pump branch structure, and each branch can be started and stopped independently. Furthermore, the outputs of several charge pump branches in the main charge pump module are sequentially connected to the first feedback resistor. RF1 Second feedback resistor R F2 Grounded, the other end is connected through the first load capacitor. C L Grounded; the inverting input of the first comparator is connected to the first feedback resistor. R F1 Second feedback resistor R F2 Between, the non-inverting input terminal is connected to the reference voltage. V REF The output of the first comparator is connected to one input of the two-input AND gate, the other input of the two-input AND gate is connected to the first clock signal CLK1, and the output of the previous two-input AND gate is connected to one input of the next two-input AND gate. The other input of the last two-input AND gate is connected to the mode switching signal EN issued by the mode switching module. In addition, the output of the two-input AND gate is connected to the input of the corresponding clock generator, and the output of the clock generator outputs the corresponding clock signal and transmits it to the corresponding main charge pump branch. Furthermore, the main charge pump module can dynamically adjust the number of charge pump branches during operation based on the control signal sent by the mode switching module, thereby realizing flexible switching between single-branch operation mode and multi-branch parallel operation mode. Furthermore, the number of main charge pump units and the scale of branches in the main charge pump module can be optimized in a coordinated manner according to the target intermediate voltage value and the load driving capability of the charge pump module. In this way, while ensuring the stability of the output voltage, the load adaptability range of the system can be expanded and the overall efficiency from light load to heavy load can be improved. Several charge pump modules are connected in parallel to form a charge pump array, wherein the charge pump module includes several charge pump units and a third feedback resistor. R f_3 Fourth feedback resistor R f_4 Second load capacitor C L1 The second comparator, the two-input AND gate, and the corresponding clock buffer; In this circuit, several charge pump units are connected in series to form a path, and the charge pump units spaced apart from each other form a group. The output of each charge pump unit passes through a third feedback resistor in sequence. R f_3 Fourth feedback resistor R f_4 Grounded, the other end is connected through the second load capacitor. C L1 Grounded; the inverting input of the second comparator is connected to the third feedback resistor. R f_3 Fourth feedback resistor Rf_4 Between, the non-inverting input terminal is connected V ref The output of the second comparator is connected to the clock buffer. The other input of the clock buffer is connected to the output of the two-input AND gate. The two inputs of the two-input AND gate are respectively connected to the second clock signal CLK2 and the charge pump operating status control signal EN_1_1. The clock buffer outputs two sets of clock signals CLKE and CLKF, which are respectively connected to two sets of charge pump units. Furthermore, the slave charge pump module in the charge pump array is used to receive the intermediate voltage provided by the main charge pump. V CP This further enhances the target high voltage required for non-volatile memory arrays. V OUT ; Furthermore, several slave charge pump modules can be independently controlled by signals, and each slave charge pump module can be arranged near the load according to the corresponding voltage domain requirements; Furthermore, the charge pump module includes several charge pump units connected in series. Each charge pump unit can receive an external enable signal to control its on or off state, and during normal operation, it feeds back a working status enable signal to the mode switching module, thereby indicating that its load domain is in an active state. The mode switching module is responsible for real-time monitoring of the number of charge pump modules in operation in the system, i.e., detecting the real-time load scale.

[0011] Furthermore, the mode switching module integrates a load detection circuit to receive and count the enable signal from the slave charge pump; the load detection circuit is a current mirror array, and each current mirror branch switch in the current mirror array receives the enable signal of the corresponding slave charge pump. Furthermore, the current mirror array includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, and so on. Sixteenth PMOS transistor MP16, seventeenth PMOS transistor MP17, eighteenth PMOS transistor MP18, nineteenth PMOS transistor MP19, twentieth PMOS transistor MP20, twenty-first PMOS transistor MP21, twenty-second PMOS transistor MP22, first NMOS transistor MN1, second NMOS transistor MN2, third NMOS transistor MN3, fourth NMOS transistor MN4, fifth NMOS transistor MN5, sixth PMOS transistor MN6, seventh NMOS transistor MN7, first current source, first resistor R1, second resistor R2; Furthermore, the gates and sources of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, and the ninth PMOS transistor MP9 are connected together, and the source is connected to VDD. The drain and gate of the first PMOS transistor MP1 are connected, and the drain is connected to the first current source. The other end of the first current source is grounded through the first resistor R1. Furthermore, the sources of the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the fourteenth PMOS transistor MP14, the fifteenth PMOS transistor MP15, the sixteenth PMOS transistor MP16, and the seventeenth PMOS transistor MP17 are connected sequentially to the drains of the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, and the ninth PMOS transistor MP9, respectively; the tenth PMOS transistor MP10... The gates of PMOS transistors MP10, MP11 (eleventh), MP12 (twelfth), MP13 (thirteenth), MP14 (fourteenth), MP15 (fifth), MP16 (sixteenth), and MP17 (seventeenth) are connected sequentially to the first enable signal EN_1_1, the second enable signal EN_1_2, the third enable signal EN_2_1, the fourth enable signal EN_2_2, the fifth enable signal EN_3_1, the sixth enable signal EN_3_2, the seventh enable signal EN_4_1, and the eighth enable signal EN_4_2, respectively. Furthermore, the sources of the eighteenth PMOS transistor MP18 and the nineteenth PMOS transistor MP19 are connected to VDD, their gates are connected to each other, and their drains are connected to the sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 through the first node fn and the second node fp, respectively. The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are grounded through the first resistor R1 and the second resistor R2, respectively, and their drains are connected to each other and connected to the source of the third NMOS transistor MN3. The drain of the third NMOS transistor MN3 is grounded. Furthermore, the source of the twentieth PMOS transistor MP20 is connected to VDD, and its drain is connected to the sources of the twenty-first PMOS transistor MP21 and the twenty-second PMOS transistor MP22. The drains of the twenty-first PMOS transistor MP21 and the twenty-second PMOS transistor MP22 are connected to the sources of the fifth NMOS transistor MN5 and the sixth PMOS transistor MN6, respectively, and their gates are connected to the gates of the fifth NMOS transistor MN5 and the sixth PMOS transistor MN6, respectively. In addition, the drain of the twenty-first PMOS transistor MP21 is also connected to the source of the fourth NMOS transistor MN4, and the drain of the twenty-second PMOS transistor MP22 is connected to the source of the seventh NMOS transistor MN7. The drains of the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the sixth PMOS transistor MN6, and the seventh NMOS transistor MN7 are grounded. Furthermore, the drain of the twenty-first PMOS transistor MP21 is connected to the gate of the twenty-second PMOS transistor MP22 and outputs OUTN; the gate of the twenty-first PMOS transistor MP21 is connected to the drain of the twenty-second PMOS transistor MP22 and outputs OUTP. Furthermore, after the current mirror branch switch is turned on, the current in this branch will be converted into voltage through a resistor. After comparing it with a preset threshold, the mode switching module issues a corresponding command to adjust the working state of the main charge pump. Furthermore, the mode switching module presets one or more configurable switching thresholds, which are designed collaboratively based on the load capabilities of the main charge pump and the slave charge pump: When the number of working charge pumps exceeds or falls below a set threshold, the mode switching module generates corresponding control commands to dynamically adjust the number of active branches in the main charge pump, thereby achieving automatic switching of the main charge pump's operating mode and ensuring that the system always operates near the optimal efficiency point that matches the load.

[0012] The clock generation module is responsible for providing a stable clock waveform to the main charge pump module, the slave charge pump module array, and the mode switching module, maintaining the coordinated operation of each module.

[0013] Furthermore, the clock generation module uses an externally supplied clock signal; Furthermore, the main charge pump unit is based on two sets of cross-coupled switching transistors and capacitors. The switching transistors are driven to turn on and off alternately by a periodic clock signal, so that the pump capacitor can obtain charge from the input power supply during the charging phase and transfer the charge to the output terminal and achieve voltage superposition during the discharging phase. At the same time, the cross-coupled structure is used to suppress voltage reverse leakage, and finally a stable DC voltage higher than the input voltage is obtained at the output terminal. Furthermore, the main charge pump unit 1 includes the 23rd PMOS transistor MP23, the 24th PMOS transistor MP24, the 25th PMOS transistor MP25, the 26th PMOS transistor MP26, the 27th PMOS transistor MP27, the 28th PMOS transistor MP28, the 29th PMOS transistor MP29, the 30th PMOS transistor MP30, the 31st PMOS transistor MP31, the 32nd PMOS transistor MP32, the 33rd PMOS transistor MP33, the 34th PMOS transistor MP34, a first capacitor C1, and a second capacitor C2; Specifically, the body electrode of the 23rd PMOS transistor MP23 is simultaneously connected to the source of both the 27th PMOS transistor MP27 and the 28th PMOS transistor MP28. The source of MP23 is also connected to the drain of the 27th PMOS transistor MP27 and the gate of the 28th PMOS transistor MP28, and the drain of MP24 is also connected to the gate of the 27th PMOS transistor MP27 and the drain of the 28th PMOS transistor MP28. The body electrode of the 24th PMOS transistor MP24 is simultaneously connected to the source of both the 29th PMOS transistor MP29 and the 30th PMOS transistor MP30. The source of MP24 is also connected to the drain of the 29th PMOS transistor MP29 and the gate of the 30th PMOS transistor MP30, and the drain of MP24 is also connected to the gate of the 29th PMOS transistor MP29 and the drain of the 30th PMOS transistor MP30. The body electrode of the 25th PMOS transistor MP25 is simultaneously connected to the source of both the 31st PMOS transistor MP31 and the 32nd PMOS transistor MP32, and the source of MP25 is also connected to the source of the 31st PMOS transistor MP31. The drain of MP31 is connected to the gate of the 32nd PMOS transistor MP32, and its drain is also connected to the gate of the 31st PMOS transistor MP31 and the drain of the 32nd PMOS transistor MP32. The body electrode of the 26th PMOS transistor MP26 is connected to the source of the 33rd PMOS transistor MP33 and the 34th PMOS transistor MP34, and its source is connected to the drain of the 33rd PMOS transistor MP33 and the gate of the 34th PMOS transistor MP34. The drain is also connected to the gate of the 33rd PMOS transistor MP33 and the drain of the 34th PMOS transistor MP34. One end of the first capacitor C1 is connected to the clock signal CLKA, and the other end of the first capacitor is connected to the gate of the 25th PMOS transistor MP25 and the gate of the 26th PMOS transistor MP26. One end of the first capacitor C2 is connected to the clock signal CLKB, and the other end of the second capacitor is connected to the gate of the 23rd PMOS transistor MP23 and the gate of the 24th PMOS transistor MP24. External input voltage. V IN The output terminal of the main charge pump unit 1 is connected to the drain of the 23rd PMOS transistor MP23 and the drain of the 25th PMOS transistor MP25. V a It is connected to the drain of the twenty-fourth PMOS transistor MP24 and the drain of the twenty-sixth PMOS transistor MP26; Furthermore, the charge pump unit, driven by a two-phase non-overlapping clock, utilizes the characteristic that capacitor voltage cannot change abruptly to transfer charge step by step, thereby achieving a multiplication of the output voltage; Furthermore, the charge pump unit includes the thirty-fifth PMOS transistor MP35, the thirty-sixth PMOS transistor MP36, the thirty-seventh PMOS transistor MP37, and the third capacitor C3. In this configuration, the gate of the 35th PMOS transistor MP35 is simultaneously connected to the source of the 35th PMOS transistor MP35, the drain of the 37th PMOS transistor MP37, and one end of the third capacitor C3. The drain of MP35 is simultaneously connected to the source of the 36th PMOS transistor MP36 and the gate of the 37th PMOS transistor MP37. The other end of the third capacitor C3 is connected to the clock signal CLKE generated by the clock buffer. The drain of the 35th PMOS transistor MP35 is also connected to the output of the main charge pump module. V CP The source of the thirty-fifth PMOS transistor MP35 is connected from the output terminal of charge pump unit 1. V e ; Another object of the present invention is to provide a method for using a load-adaptive distributed charge pump for arrays of non-volatile devices, the method comprising: The main charge pump module and the mode switching module share a clock signal CLK1, and all slave charge pump modules share a clock signal CLK2. The main charge pump includes several parallel multi-stage cross-coupled charge pump branches. The main charge pump mode is controlled by the enable signal EN issued by the mode switching module, and the corresponding number of branches are activated according to the corresponding signal. After the main charge pump module is connected to the input voltage and clock signal CLK1, it begins to pump the voltage normally. The main charge pump module uses pulse jump modulation and uses a feedback proportional resistor to set the target resistance. The comparator compares the current voltage with the set voltage, thereby controlling the clock generator to output the clock signal frequency, which in turn controls the main charge pump to output the set intermediate voltage.

[0014] After the input voltage and clock signal are connected from the charge pump module, CLK2 starts to pump the voltage normally. The charge pump module uses dynamic voltage frequency adjustment and uses a feedback proportional resistor to set the target resistance. The operational amplifier will change the amplitude of the clock signal output by the clock buffer according to the difference between the target voltage and the set voltage, thereby controlling the set voltage output from the charge pump.

[0015] The mode switching module consists of an accumulator circuit and a comparator circuit. The accumulator circuit includes a bandgap reference current source and a current mirror array. The current mirror array works by replicating the bias current into multiple parallel branches. Each branch has a corresponding switch. When a specific slave charge pump branch is activated, its corresponding switch also opens, and the branch current accumulates across the resistor. After comparing the voltage with a preset threshold, the mode switching module issues a corresponding command to adjust the operation of the main charge pump.

[0016] Upon receiving a shutdown signal, the slave charge pump sets its clock input to 0, thus stopping the slave charge pump. At this time, the current mirror array in the mode switching module shuts down the branch corresponding to the slave charge pump, reducing the current accumulated across the resistor. When the current decreases to a set threshold, the comparator circuit in the mode switching module sends a signal to the master charge pump. Upon receiving this signal, the master charge pump module sets the clock input of one or more branches to 0, thus stopping one or more branches of the master charge pump.

[0017] The beneficial effects of this invention are: First, the load-adaptive distributed charge pump provided by this invention provides distributed power supply compared to general charge pump circuits. It can provide high voltage according to the circuit needs, and the charge pump can be distributed close to the voltage demand point, effectively reducing IR drop and improving the output voltage accuracy of the charge pump. Secondly, the load-adaptive distributed charge pump provided by this invention reduces the number of off-chip power supply ports compared to general charge pump circuits. It can generate multiple high voltages required by the circuit from a single voltage source, effectively improving area utilization and reducing the electrostatic risks caused by multiple off-chip power supply ports. Third, the load-adaptive distributed charge pump provided by this invention adds a mode switching module compared to a general charge pump circuit. It can switch the operating state of the main charge pump based on the number of auxiliary charge pumps in operation, and adjust the operating state switching threshold according to actual circuit requirements, thereby improving the working efficiency of the charge pump and increasing its load capacity. Therefore, the present invention can meet the requirements for switching of the working state of part of the array in a chip with multiple non-volatile device memory arrays, and greatly improve the stability and robustness of the memory array during operation. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a structural block diagram of a load-adaptive distributed charge pump for non-volatile device arrays provided in Embodiment 1 of the present invention. Figure 2 This is a schematic diagram of the main charge pump module circuit in a load-adaptive distributed charge pump for non-volatile device arrays provided in Embodiment 1 of the present invention. Figure 3This is a schematic diagram of a slave charge pump module circuit in a load-adaptive distributed charge pump for non-volatile device arrays provided in Embodiment 1 of the present invention. Figure 4 This is a schematic diagram of a mode switching module circuit in a load-adaptive distributed charge pump for non-volatile device arrays provided in Embodiment 1 of the present invention. Figure 5 This is a circuit diagram of the main charge pump unit 1 in the main charge pump module of a load-adaptive distributed charge pump for non-volatile device arrays provided in Embodiment 1 of the present invention. Figure 6 This is a schematic diagram of the circuit of charge pump unit 1 in the charge pump module of a load adaptive distributed charge pump for non-volatile device arrays provided in Embodiment 1 of the present invention. Figure 7 This is a schematic diagram of the output waveform of a load-adaptive distributed charge pump for non-volatile device arrays provided in Embodiment 1 of the present invention. Figure 8 This is a schematic diagram of the working waveform of a mode switching module for a load-adaptive distributed charge pump for non-volatile device arrays, provided in Embodiment 1 of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0021] Example 1 This embodiment provides a load-adaptive distributed charge pump for non-volatile device arrays. The charge pump is described using a charge pump module with six main charge pump units divided into two main charge pump branches and four slave charge pump units as an example. The charge pump includes a main charge pump module, a mode switching module, slave charge pump modules, and a clock generation module; its overall structure is as follows: Figure 1 As shown, the input terminal of the main charge pump module receives an external input voltage. V IN The output terminal is connected to the input terminals of several slave charge pump modules; the several slave charge pump modules together form a slave charge pump array. The output terminal of the clock generation module is connected to the master charge pump module, the slave charge pump array, and the mode switching module. One side of the output of each slave charge pump module in the slave charge pump array is connected to the load, which includes an array composed of several decoding drive circuits and memory computing device arrays; the other side is connected to the mode switching module, and the output terminal of the mode switching module is connected to the master charge pump module. The main charge pump module is used to receive external input voltage. V IN And raise it to the intermediate voltage. VCP This provides a stable voltage to the input of the charge pump; the specific structure of the main charge pump module is as follows: Figure 2 As shown, it includes a first main charge pump unit 1, a second main charge pump unit 2, a third main charge pump unit 3, a fourth main charge pump unit 4, a fifth main charge pump unit 5, and a sixth main charge pump unit 6, a first comparator, and a first feedback resistor. R F1 Second feedback resistor R F2 First load capacitor C L First two-input AND gate AND2_1, second two-input AND gate AND2_2, first clock generator 1, second clock generator 2; The main charge pump module has two operating states, controlled by the mode switching module, where the first feedback resistor... R F1 Second feedback resistor R F2 The value can be flexibly selected according to the actual situation, so that the main charge pump module can output the ideal voltage value; The first main charge pump unit 1, the second main charge pump unit 2, and the third main charge pump unit 3 in the main charge pump module constitute the first main charge pump branch, and the fourth main charge pump unit 4, the fifth main charge pump unit 5, and the sixth main charge pump unit 6 constitute the second main charge pump branch. The output of the two branches are sequentially connected to the first feedback resistor. R F1 Second feedback resistor R F2 Grounded, the other end is connected through the first load capacitor. C L Grounded; the inverting input of the first comparator is connected to the first feedback resistor. R F1 Second feedback resistor R F2 Between, the non-inverting input terminal is connected to the reference voltage. V REF The output of the first comparator is connected to one input of the first two-input AND gate AND2_1, and the other input of the first two-input AND gate AND2_1 is connected to the clock signal CLK1. The output of the first two-input AND gate AND2_1 is simultaneously connected to the input of the first clock generator 1 and one input of the second two-input AND gate AND2_2. The other input of the second two-input AND gate AND2_2 is connected to EN. The first clock generator 1 outputs the first clock signal CLKA and the second clock signal CLKB. The second clock generator 2 outputs the third clock signal CLKC and the fourth clock signal CLKD. Specifically, the first clock signal CLKA and the second clock signal CLKB are input to the three main charge pump units of the first main charge pump branch, and the third clock signal CLKC and the fourth clock signal CLKD are input to the three main charge pump units of the second main charge pump branch.

[0022] The specific structure of the main charge pump unit is as follows: Figure 5 As shown, it includes the 23rd PMOS transistor MP23, the 24th PMOS transistor MP24, the 25th PMOS transistor MP25, the 26th PMOS transistor MP26, the 27th PMOS transistor MP27, the 28th PMOS transistor MP28, the 29th PMOS transistor MP29, the 30th PMOS transistor MP30, the 31st PMOS transistor MP31, the 32nd PMOS transistor MP32, the 33rd PMOS transistor MP33, the 34th PMOS transistor MP34, the first capacitor C1, and the second capacitor C2; When the enable signal EN controlling the operation of the main charge pump is high, the second clock buffer 2 can work normally and output a normal clock waveform. The fourth main charge pump unit 4, the fifth main charge pump unit 5, and the sixth main charge pump unit 6 can work normally. At this time, the main charge pump unit is in heavy load mode. When the enable signal EN controlling the operation of the main charge pump is low, the second clock buffer 2 stops working and does not output a clock waveform, and the fourth main charge pump unit 4, the fifth main charge pump unit 5, and the sixth main charge pump unit 6 stop working. At this time, the main charge pump unit is in light load mode. The charge pump module is used to receive intermediate voltage and boost it to the target voltage, providing a stable voltage to the memory array; such as Figure 3 As shown, the charge pump circuit includes a second charge pump unit 1, a third charge pump unit 2, a fourth charge pump unit 3, a second operational amplifier, a third two-input AND gate AND2_3, and a third feedback resistor. R f_3 Fourth feedback resistor R f_4 Second load capacitor C L1 Clock buffer 1; The charge pump module's operating state is controlled by an external signal, enabling the charge pump to output the ideal target voltage value; Four slave charge pump units are connected in sequence to receive output from the main charge pump module. V CP The output terminal is connected to the third feedback resistor in sequence. R f_3 Fourth feedback resistor R f_4 Grounded, the other end is connected through the second load capacitor. C L1Grounded; the inverting input of the second comparator is connected to the third feedback resistor. R f_3 Fourth feedback resistor R f_4 Between, the non-inverting input terminal is connected V ref The output of the second comparator is connected to the clock buffer. Another input of the clock buffer is connected to the output of the two-input AND gate. The two inputs of the third two-input AND gate are connected to the second clock signal CLK2 and the enable signal EN_1_1, respectively. The clock buffer 1 outputs two sets of clock signals CLKE and CLKF, which are connected to two sets of charge pump units, respectively. Driven by a two-phase non-overlapping clock, the charge pump unit transfers charge step by step using the characteristic that capacitor voltage cannot change abruptly, thereby doubling the output voltage. From the specific structure of the charge pump unit, such as Figure 6 As shown, it includes the thirty-fifth PMOS transistor MP35, the thirty-sixth PMOS transistor MP36, the thirty-seventh PMOS transistor MP37, and the third capacitor C3. Among them, the gate of the 35th PMOS transistor MP35 is connected to the source of the 35th PMOS transistor MP35, the drain of the 37th PMOS transistor MP37, and one end of the third capacitor C3. The drain is connected to the source of the 36th PMOS transistor MP36 and the gate of the 37th PMOS transistor MP37. The other end of the third capacitor C3 is connected to the clock signal CLK F or CLK E. The drain of the 35th PMOS transistor MP35 is also connected to the output VCP of the input main charge pump. The source of the 35th PMOS transistor MP35 is connected to the output Ve from the charge pump unit 1. When the control signal EN_1_1 for the charge pump is high, the clock generator 1 can work normally and output a normal clock waveform. The first charge pump unit 1, the second charge pump unit 2, the third charge pump unit 3, and the fourth charge pump unit 4 can work normally. At this time, the charge pump unit is working normally. When the control signal EN1 for the charge pump is low, the clock generator 1 stops working, and the first charge pump unit 1, the second charge pump unit 2, the third charge pump unit 3, and the fourth charge pump unit 4 stop working. At this time, the charge pump unit stops working. The mode switching module monitors the number of slave charge pumps in operation and adjusts the operating status of the master charge pump based on the number of slave charge pumps in operation, such as... Figure 4As shown, the mode switching module circuit includes the following PMOS transistors: MP1 (first), MP2 (second), MP3 (third), MP4 (fourth), MP5 (fifth), MP6 (sixth), MP7 (seventh), MP8 (eighth), MP9 (ninth), MP10 (tenth), MP11 (eleventh), MP12 (twelfth), MP13 (thirteenth), MP14 (fourteenth), and MP15 (fifth). The sixteenth PMOS transistor MP16, the seventeenth PMOS transistor MP17, the eighteenth PMOS transistor MP18, the nineteenth PMOS transistor MP19, the twentieth PMOS transistor MP20, the twenty-first PMOS transistor MP21, the twenty-second PMOS transistor MP22, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the sixth PMOS transistor MN6, the seventh NMOS transistor MN7, the first current source, the first resistor R1, and the second resistor R2; In the mode switching module, the current mirror array accumulates the current to the second resistor R2. Adjusting the resistance value of the first resistor R1 can change the EN signal toggling threshold, so that the mode switching module changes the enable signal EN at the appropriate time. The gates and sources of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, and the ninth PMOS transistor MP9 are connected together, and the source is connected to VDD. The drain and gate of the first PMOS transistor MP1 are connected, and the drain is connected to the first current source. The other end of the first current source is grounded through the first resistor R1. The sources of the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the fourteenth PMOS transistor MP14, the fifteenth PMOS transistor MP15, the sixteenth PMOS transistor MP16, and the seventeenth PMOS transistor MP17 are connected sequentially to the drains of the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, and the ninth PMOS transistor MP9; the tenth PMOS transistor... The gates of PMOS transistors MP10, MP11 (eleventh), MP12 (twelfth), MP13 (thirteenth), MP14 (fourteenth), MP15 (fifth), MP16 (sixteenth), and MP17 (seventeenth) are connected sequentially to the first enable signal EN1_1, the second enable signal EN1_2, the third enable signal EN2_1, the fourth enable signal EN2_2, the fifth enable signal EN3_1, the sixth enable signal EN3_2, the seventh enable signal EN4_1, and the eighth enable signal EN4_2, respectively; [Agent 1.1] The sources of the eighteenth PMOS transistor MP18 and the nineteenth PMOS transistor MP19 are connected to VDD, their gates are connected to each other, and their drains are connected to the sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 through the first node fn and the second node fp, respectively. The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are grounded through the first resistor R1 and the second resistor R2, respectively, and their drains are connected to each other and connected to the source of the third NMOS transistor MN3. The drain of the third NMOS transistor MN3 is grounded. The source of the 20th PMOS transistor MP20 is connected to VDD, and its drain is connected to the sources of the 21st PMOS transistor MP21 and the 22nd PMOS transistor MP22. The drains of the 21st PMOS transistor MP21 and the 22nd PMOS transistor MP22 are connected to the sources of the 5th NMOS transistor MN5 and the 6th PMOS transistor MN6, respectively, and their gates are connected to the gates of the 5th NMOS transistor MN5 and the 6th PMOS transistor MN6, respectively. In addition, the drain of the 21st PMOS transistor MP21 is also connected to the source of the 4th NMOS transistor MN4, and the drain of the 22nd PMOS transistor MP22 is connected to the source of the 7th NMOS transistor MN7. The drains of the 4th NMOS transistor MN4, the 5th NMOS transistor MN5, the 6th PMOS transistor MN6, and the 7th NMOS transistor MN7 are grounded. The drain of the 21st PMOS transistor MP21 is connected to the gate of the 22nd PMOS transistor MP22 and outputs OUTN. The gate of the 21st PMOS transistor MP21 is connected to the drain of the 22nd PMOS transistor MP22 and outputs OUTP. Each slave charge pump has a unique corresponding current mirror in the mode switching module. When the slave charge pump is working, the switch of its corresponding branch will be turned on, and the current of that branch will pass through the second resistor R2. Adjusting the resistance values ​​of the first resistor R1 and the second resistor R2 can change the EN signal toggling threshold.

[0023] The high and low levels of the clock signal CLK2 control the mode switching module during the reset and decision phases: When the CLK signal is low, the mode switching module operates in the reset phase, which works by precharging the fn and fp nodes to VDD and discharging the output node to ground. When the CLK signal is high, during the decision-making stage, the gate input signals of the first NMOS transistor MN1 and the gate input signals of the second NMOS transistor MN2 are compared, and then the EN signal that controls the main charge pump operating mode is output.

[0024] The main charge pump unit is based on two sets of cross-coupled switching transistors and capacitors. The switching transistors are driven to turn on and off alternately by a periodic clock signal, so that the pump capacitor can obtain charge from the input power supply during the charging phase and transfer the charge to the output terminal and achieve voltage superposition during the discharging phase. At the same time, the cross-coupled structure is used to suppress voltage reverse leakage, and finally a stable DC voltage higher than the input voltage is obtained at the output terminal. To verify the effectiveness of the charge pump provided in this embodiment, the present invention uses the Cadence simulator to simulate and verify the charge pump. The input voltage Vin in the main charge pump module is set to 2.5V, the first feedback resistor RF1 is set to 10kΩ, and the second feedback resistor RF2 is set to 60kΩ. The input voltage VCP of the slave charge pump module is the output voltage of the main charge pump, which is 7V. In this example, two load arrays are set up, and eight slave charge pumps are divided into four groups to power the load arrays. This shows that the slave charge pump module array can output multiple voltage values ​​and can power multiple arrays. The eight slave charge pumps are divided into four groups, and the feedback resistor of each group of slave charge pumps is adjusted to make them output the required voltage values ​​of 12V and 8V. This embodiment provides a schematic diagram of the output waveform of the charge pump, such as... Figure 7As shown; the first slave charge pump module output voltage Vout1_1 is 12V, the second slave charge pump module output voltage Vout1_2 is 8V, and the first and second slave charge pumps constitute the first power supply array. Each slave charge pump outputs a load current of 80μA. As the target voltage increases from low to high, the time to reach a stable voltage gradually increases. The third slave charge pump module output voltage Vout2_1 is 12V, the fourth slave charge pump module output voltage Vout2_2 is 8V, and the third and fourth slave charge pumps constitute the second power supply array. Each slave charge pump outputs a load current of 80μA. As the target voltage increases from low to high, the time to reach a stable voltage gradually increases. The fifth and sixth slave charge pump modules have output voltages of 12V (Vout3_1) and 8V respectively. These five and six slave charge pumps form the third power supply array, with each slave charge pump outputting a load current of 80μA. As the target voltage increases from low to high, the time to reach a stable voltage gradually increases. The seventh and eighth slave charge pump modules have output voltages of 12V (Vout4_1) and 8V respectively. These seven and eight slave charge pumps form the fourth power supply array, with each slave charge pump outputting a load current of 80μA. As the target voltage increases from low to high, the time to reach a stable voltage gradually increases. Depend on Figure 7 As can be seen, the charge pump provided in this embodiment can simultaneously provide the required different voltage values ​​to four arrays, achieving the expected results.

[0025] The schematic diagram of the working waveform of the charge pump mode switching module provided in this embodiment is as follows: Figure 8 As shown, the mode switching module sets the resistance of resistor R1 to 50kΩ and the resistance of resistor R2 to 12.5kΩ. Initially, the first slave charge pump module stops working, and the mode switching module receives signal EN_1_1 as 0V; the second slave charge pump module stops working, and the mode switching module receives signal EN_1_2 as 0V; the third slave charge pump module stops working, and the mode switching module receives signal EN_2_1 as 0V; the fourth slave charge pump module stops working, and the time interval between switching between stopping and normal operation is 5μs. The time interval between switching between 0V and 2.5V signals received by the mode switching module is [not specified in the original text]. 5μs; The fifth slave charge pump module is working normally, and the mode switching module receives signal EN_3_1 as 2.5V; The sixth slave charge pump module is working normally, and the mode switching module receives signal EN_3_2 as 2.5V; The fifth slave charge pump module is working normally, and the mode switching module receives signal EN_4_1 as 2.5V; The fifth slave charge pump module is working normally, and the mode switching module receives signal EN_4_2 as 2.5V; Therefore, when the load count is less than 5, the mode switching module outputs enable signal EN as 0V; when the load count exceeds 4, the mode switching module outputs enable signal EN as 2.5V.

[0026] Depend on Figure 8 It can be seen that the charge pump mode switching module provided in this embodiment can send the correct signal to regulate the working mode of the main charge pump under different signal conditions.

[0027] Some steps in the embodiments of the present invention can be implemented using software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0028] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A load-adaptive distributed charge pump for non-volatile device arrays, characterized in that, The charge pump includes a main charge pump module, a mode switching module, slave charge pump modules, and a clock generation module; wherein, several slave charge pump modules are provided, and the several slave charge pump modules form a slave charge pump array; the main charge pump module is used to receive external input voltage. V IN And raise it to the intermediate voltage. V CP This provides a stable voltage to the input of the charge pump; the charge pump module is used to receive intermediate voltage. V CP It boosts the voltage to the target voltage, providing a stable voltage to the memory array; the mode switching module controls the operating mode of the main charge pump module to heavy load mode or light load mode; the clock generation module provides clock signals to the main charge pump module, the mode switching module, and the slave charge pump module.

2. The charge pump according to claim 1, characterized in that, The main charge pump module is provided with several charge pump branches. When the main charge pump module operates in heavy load mode, multiple branches operate in parallel; when the main charge pump module operates in light load mode, a single branch operates. The mode switching module dynamically adjusts the operating mode of the main charge pump module according to the voltage required by the charge pump module.

3. The charge pump according to claim 2, characterized in that, The mode switching module integrates a load detection circuit to receive and count the enable signals from the slave charge pump. The load detection circuit is a current mirror array, in which each current mirror branch switch receives the enable signal of the corresponding slave charge pump.

4. The charge pump according to claim 3, characterized in that, Each charge pump branch is equipped with several main charge pump units. Each main charge pump unit is based on two sets of cross-coupled switching transistors and capacitors. The switching transistors are driven to turn on and off alternately by a periodic clock signal, so that the pump capacitor can obtain charge from the input power supply during the charging phase and transfer the charge to the output terminal and achieve voltage superposition during the discharging phase. At the same time, the cross-coupling structure is used to suppress voltage reverse leakage, and finally a stable DC voltage higher than the input voltage is obtained at the output terminal.

5. The charge pump according to claim 4, characterized in that, The main charge pump module includes several main charge pump units and a first feedback resistor. R F1 Second feedback resistor R F2 First load capacitor C L The system consists of a first comparator, several two-input AND gates, and a corresponding clock generator.

6. The charge pump according to claim 5, characterized in that, The outputs of several charge pump branches in the main charge pump module are sequentially connected to the first feedback resistor. R F1 Second feedback resistor R F2 Grounded, the other end is connected through the first load capacitor. C L Grounded; the inverting input of the first comparator is connected to the first feedback resistor. R F1 Second feedback resistor R F2 Between, the non-inverting input terminal is connected to the reference voltage. V REF The output of the first comparator is connected to one input of the two-input AND gate, the other input of the two-input AND gate is connected to the first clock signal CLK1, and the output of the previous two-input AND gate is connected to one input of the next two-input AND gate. The other input of the last two-input AND gate is connected to the mode switching signal EN issued by the mode switching module. In addition, the output of the two-input AND gate is connected to the input of the corresponding clock generator, and the output of the clock generator outputs the corresponding clock signal and transmits it to the corresponding main charge pump branch.

7. The charge pump according to claim 6, characterized in that, The main charge pump module and the mode switching module share a clock signal CLK1, while all slave charge pump modules share a clock signal CLK2; the main charge pump module is connected to an input voltage. V IN After the clock signal CLK1, the voltage begins to rise normally. The main charge pump module uses pulse jump modulation and uses a feedback proportional resistor to set the target resistance. The comparator compares the current voltage with the set voltage, thereby controlling the clock generator to output the clock signal frequency, which in turn controls the main charge pump to output the set intermediate voltage.

8. The charge pump according to claim 7, characterized in that, Each slave charge pump module includes several slave charge pump units and a third feedback resistor. R f_3 Fourth feedback resistor R f_4 Second load capacitor C L1 The circuit consists of a second comparator, a two-input AND gate, and a corresponding clock buffer; several charge pump units are connected in series to form a path, and the charge pump units are grouped together with each other spaced apart. The output of each charge pump unit passes through a third feedback resistor. R f_3 Fourth feedback resistor R f_4 Grounded, the other end is connected through the second load capacitor. C L1 Grounded; the inverting input of the second comparator is connected to the third feedback resistor. R f_3 Fourth feedback resistor R f_4 Between these two points, the non-inverting input of the second comparator is connected to the reference voltage. V ref The output of the second comparator is connected to the clock buffer. The other input of the clock buffer is connected to the output of the two-input AND gate. The two inputs of the two-input AND gate are respectively connected to the second clock signal CLK2 and the charge pump operating status control signal EN_1_1. The clock buffer outputs two sets of clock signals CLKE and CLKF, which are respectively connected to two sets of charge pump units.

9. The charge pump according to claim 8, characterized in that, The first feedback resistor in the main charge pump unit R F1 Second feedback resistor R F2 It is a variable resistance resistor.

10. A memory computing array, characterized in that, The in-memory computing array includes the charge pump as described in any one of claims 1-9.

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