Coordinated circuit of cdac and comparator based on dynamic power consumption optimization
By using a CDAC and comparator co-circuit with dynamic power optimization, the high power consumption and noise issues of SARADC at high sampling rates and high resolutions are solved, achieving a SARADC design with low power consumption, high performance and high stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SCHOOL OF SOFTWARE & MICROELECTRONICS PEKING UNIV
- Filing Date
- 2026-03-04
- Publication Date
- 2026-06-09
AI Technical Summary
In applications with a sampling rate of 48MS/s and a resolution of 10bit, the power consumption of existing SARADCs mainly comes from the comparator, CDAC, input buffer, and SAR logic circuit, resulting in high energy consumption and noise issues, and they are also sensitive to process fluctuations.
The CDAC and comparator co-circuit with dynamic power optimization includes an input buffer based on an RC high-pass filter, a comparator with a dynamic floating-point inverter amplifier, a redundant CDAC circuit, and an asynchronous clock architecture SAR logic circuit. By using current reuse, incomplete discharge of the load capacitor, optimized switching timing, and asynchronous clock design, the overall power consumption is reduced and the performance is improved.
It achieves extremely low power consumption, improves circuit stability and performance, meets the requirements of 48MS/s sampling rate and 10-bit resolution, increases power efficiency to 78%, reduces noise and offset, adapts to PVT fluctuations, and reduces overall power consumption to 2μW-5μW.
Smart Images
Figure CN122178914A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog integrated circuit technology, specifically relating to a CDAC and comparator collaborative circuit based on dynamic power consumption optimization. Background Technology
[0002] Analog-to-digital converters (ADCs) are core components connecting the analog world and digital systems, and are widely used in wired / wireless communication, data storage, and sensor applications. Successive approximation ADCs (SARADCs) have become the mainstream choice for medium-to-high speed and medium-to-high precision applications due to their advantages of low power consumption, small chip area, and low cost.
[0003] With the increasing prevalence of portable medical devices and IoT sensors, the demand for low power consumption in SAR ADCs is becoming increasingly stringent. The power consumption of existing SAR ADCs mainly comes from the comparator, CDAC (capacitor-to-digital converter), input buffer, and SAR logic circuitry. In applications with a sampling rate of 48 MS / s and a resolution of 10 bits, traditional designs suffer from the following technical drawbacks: The input buffer uses a simple source follower, and the quiescent current always exists, resulting in a power efficiency of only about 25%. The comparator consumes a large proportion of power during operation because the load capacitor is completely discharged, and it is also greatly affected by process corners and input common-mode voltage. The capacitor mismatch in the CDAC circuit limits the reduction of the unit capacitance, and the traditional switching timing results in high energy consumption for capacitor switching. Synchronous clock architecture SAR logic circuits require a high-frequency global clock, resulting in significant power consumption and noise issues.
[0004] Therefore, there is an urgent need for an innovative SARADC architecture design to solve the technical challenge of balancing low power consumption and high performance. Summary of the Invention
[0005] To address the shortcomings of existing technologies, the present invention aims to provide a CDAC and comparator collaborative circuit based on dynamic power consumption optimization, which significantly reduces the power consumption of the comparator, CDAC, input buffer, and SAR logic circuit while ensuring a sampling rate of 48MS / s and a resolution of 10 bits, thereby improving the circuit's adaptability to PVT fluctuations.
[0006] A CDAC and comparator co-processing circuit based on dynamic power optimization includes an ultra-low power 48MS / s 10-bit SARADC. This ultra-low power 48MS / s 10-bit SARADC includes a clock generation circuit, an input buffer, a reference voltage circuit, a sample-and-hold circuit, a differential CDAC circuit, a comparator, a SAR logic circuit, and an output latch circuit. The clock generation circuit receives a 50% duty cycle square wave CLK_IN and generates a sampling clock CLK_S, a plate control clock CLK_SP, a logic reset clock, and a synchronous output clock CLK_OUT. The input buffer is a push-pull source follower structure based on an RC high-pass filter, used to isolate the signal source from the sampling network and provide low-impedance drive. The sample-and-hold circuit uses a gate voltage bootstrap circuit. The circuit combines a differential sampling switch with a circuit to sample and hold the input signal on the CDAC circuit. The CDAC circuit is a binary capacitor array structure with redundant bits, using VCM_Based switching timing. The comparator is a positive feedback body-biased dynamic comparator with a dynamic floating-point inverter amplifier (FIA) to compare the CDAC output signal and output the result. The SAR logic circuit uses an asynchronous clock architecture and a low-power TSPC flip-flop to control the switching of the lower plate of the CDAC according to the comparison result. The output latch circuit is used to stably output a 10-bit digital code. The clock generation circuit includes a controllable delay DELAY module composed of 15 delay units, where CLK_SP and CLK_S are non-overlapping clocks with a falling edge interval of 128ps.
[0007] Furthermore, the push-pull source follower based on the RC high-pass filter consists of three parts: a negative feedback circuit, an RC high-pass filter circuit, and a push-pull source follower. The negative feedback circuit stabilizes the input node voltage at VCM (400mV). The RC high-pass filter circuit uses a 2pF capacitor and a 1G ohm back-to-back resistor to filter out low-frequency noise. The push-pull source follower has no constant bias current. When the input voltage is high, only the NMOS operates, and when the input voltage is low, only the PMOS operates, improving the power efficiency to 78%.
[0008] Furthermore, the positive feedback body bias dynamic comparator with dynamic floating-point inverter amplifier includes an FIA preamplifier and a subsequent positive feedback body bias-dynamic current rudder comparator. The FIA preamplifier uses an inverter-based input pair, powered by a floating capacitor CRES, to achieve current reuse and dynamic bias, preventing the load capacitor from fully discharging. The subsequent comparator cross-connects the output nodes VON and VOP of the first-stage preamplifier to the substrate of the input pair transistors, dynamically widening the threshold voltage Vth difference, shortening the comparison time by about 30%, and controlling the input reference noise to around 200µVrms.
[0009] Furthermore, the redundancy design of the CDAC circuit expands from 10 bits to 11 bits, adjusts the weight of the highest-order capacitor from 512 to 448, and allocates the split 64 bits to the lower bits, satisfying the requirement of Wi < Σ (j = 0 to i-1)Wj. The minimum unit capacitance is reduced from 3fF to 1fF. During capacitor switching, the VCM_Based switching timing switches one end of the capacitor from VCM to VREF or GND, with a normalized total energy of 0.25CV. 2 .
[0010] Furthermore, the gate voltage bootstrap circuit of the sample-and-hold circuit raises the gate potential of the sampling transistor to VDD+VIN through the bootstrap capacitor CB, so that VGS is constant at VDD; the differential sampling switch eliminates even-order harmonic distortion. The FFT simulation results under full PVT are: ENOB maximum value 12.5bit, typical value 12.1bit, minimum value 10.4bit; SNR maximum value 76.2dB, typical value 74.8dB, minimum value 65.4dB; SFDR maximum value 89.3dB, typical value 82.9dB, minimum value 76.6dB.
[0011] Furthermore, the asynchronous clock generation circuit of the SAR logic circuit consists of a comparator, a gate circuit, and a delay unit, and triggers the next comparison through the READYB signal; the TSPC flip-flop adds a cross-coupled inverter maintainer, adopts a high threshold device, and reduces the static power consumption to 2μW-5μW; the control logic unit outputs U<9:0>, UB<9:0>, CU<9:0>, CBU<9:0>, D<9:0>, DB<9:0>, CD<9:0>, and CBD<9:0> signals, which respectively control the connection between the upper and lower plates of CDAC and VREFN, VREFP, and VCM.
[0012] Furthermore, the controllable delay DELAY module of the clock generation circuit adjusts the sampling time through 4 control bits. When the control code is "0000", the sampling time is 3.37ns, and when the control code is "1111", the sampling time is 8.58ns. The control bit ratio is 8:4:2:1.
[0013] Furthermore, it adopts a 22nm process, a power supply voltage of 0.8V, and a sampling period of 21ns, of which 6ns are used for sampling, and the remaining time is used to complete 11 comparison quantizations and margin reservations. The comparison clock frequency is approximately 1GHz, and the single comparison period is 1.15ns.
[0014] The present invention has the following beneficial effects: 1. Extremely low power consumption: The overall extremely low power consumption design is achieved through current multiplexing of the input buffer, incomplete discharge of the comparator's load capacitor, optimized switching timing of the CDAC, and asynchronous architecture of the SAR logic with low-power triggers. 2. High performance: The innovative comparator architecture reduces noise and offset, the redundant design of the CDAC improves linearity, and the gate voltage bootstrap technology of the sample-and-hold circuit ensures sampling accuracy, meeting the requirements of 48MS / s sampling rate and 10-bit resolution. 3. High stability: The circuit's adaptability to PVT fluctuations is improved through the design of negative feedback circuits, on-chip adjustable clock circuits, and differential structures. 4. Simple structure: The design of each module takes into account both performance and implementation complexity, avoids overly complex calibration circuits, and reduces the layout area and the impact of parasitic parameters. Attached Figure Description
[0015] Figure 1 Overall architecture diagram of the SARADC of this invention; Figure 2 Circuit diagram of a push-pull source follower based on an RC high-pass filter; Figure 3 Circuit diagram of a positive feedback body-biased dynamic comparator with FIA; Figure 4 CDAC capacitor array structure diagram; Figure 5 Gate voltage bootstrap circuit; Figure 6 Differential sampling switch circuit diagram; Figure 7 Asynchronous clock generation circuit diagram; Figure 8 Waveform diagram of asynchronous clock generation circuit; Figure 9 TSPC flip-flop circuit schematic; Figure 10 Schematic diagram of clock generation circuit; Figure 11 Schematic diagram of clock generation circuit (2 diagrams) Figure 12 ADC timing waveform diagram. Detailed Implementation
[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0017] The core technical solution of this invention is as follows: (1) Overall architecture design The ADC (Analog-to-Digital Converter) system comprises a clock generation circuit, an input buffer, a reference voltage circuit, a sample-and-hold circuit, a differential CDAC (Comparator-to-Digital Converter) circuit, a comparator, a SAR (Specific Analog Array) logic circuit, and an output latch circuit. The clock generation circuit generates multiple timing signals to coordinate the operation of each module; the input buffer isolates the signal source from the sampling network and provides low-impedance drive; the sample-and-hold circuit achieves high-precision sampling through gate voltage bootstrapping technology; the CDAC circuit employs redundant design and optimized switching timing to reduce power consumption; the comparator uses an innovative architecture to balance power consumption and noise; the SAR logic circuit uses asynchronous timing and low-power triggers to reduce unnecessary power consumption; and the output latch circuit stably outputs digital codes.
[0018] (2) Core module design Input buffer: Employs a push-pull source follower structure based on an RC high-pass filter, consisting of a negative feedback circuit, an RC high-pass filter circuit, and a push-pull source follower. The negative feedback circuit stabilizes the output common-mode voltage, the RC high-pass filter removes low-frequency noise, and the push-pull source follower enables current multiplexing, improving power efficiency to 78%.
[0019] Comparator: Innovative design of a positive feedback body-biased dynamic comparator with FIA. The FIA preamplifier is powered by a floating capacitor, enabling current reuse and dynamic biasing, preventing the load capacitor from fully discharging; the subsequent positive feedback body-biased dynamic comparator utilizes the back-gate characteristics of the 22nm process, accelerating the comparison process through cross-body feedback and shortening the decision time by 30%.
[0020] CDAC circuit: It adopts a binary structure with added redundant bits, expanding 10 bits to 11 bits and reducing the minimum unit capacitance to 1fF; it adopts VCM_Based switching timing, switching from VCM to VREF or GND when switching capacitors, and the normalized total energy is only 25% of that of traditional switching timing.
[0021] Sample-and-hold circuit: Combining a gate voltage bootstrap circuit and a differential sampling switch. The gate voltage bootstrap circuit keeps the on-resistance of the sampling transistor constant, and the differential sampling switch eliminates even-order harmonic distortion. The simulation performance under full PVT meets the design requirements.
[0022] SAR logic circuit: It adopts an asynchronous clock architecture, which does not require a high-frequency global clock. It dynamically triggers the next comparison based on the comparison result. It uses a low-power TSPC flip-flop, adds a hold circuit and selects a high threshold device, reducing the static power consumption to 2μW-5μW.
[0023] Clock generation circuit: Design a controllable delay DELAY module to support sampling time duty cycle adjustment and adapt to different PVT changes; generate non-overlapping clocks CLK_SP and CLK_S with a falling edge interval of 128ps to ensure the normal operation of the CDAC circuit.
[0024] This invention uses a 22nm process, a power supply voltage of 0.8V, a VCM of 400mV, a sampling frequency of 48MS / s, and a sampling period of 21ns, of which 6ns are used for sampling, and the remaining time is used to complete 11 comparison quantizations and reserve margin. The comparison clock frequency is approximately 1GHz, and the single comparison period is 1.15ns.
[0025] Input buffer: The RC high-pass filter uses a 2pF capacitor and a 1G ohm back-to-back resistor. The output transistor is an LVT (Vth≈0.25V). The negative feedback circuit is composed of an operational amplifier and a MOSFET to stabilize the output common-mode voltage.
[0026] Comparator: The floating capacitor CRES of the FIA preamplifier is adapted to the operating frequency, and the feedback capacitors CF1 and CF2 adopt 2fF~5fF interlayer parasitic capacitance of the metal trace; the input pair of the comparator in the later stage is independently biased to the substrate, utilizing the characteristics of the 22nm FDSOI process.
[0027] CDAC circuit: The unit capacitor value is 1fF, and the redundant bit addition strategy is to split the highest bit 512 into 448+64, and adjust the weight of the lower bits accordingly; VCM_Based switch timing controls the capacitor switching path.
[0028] Sample and hold circuit: The value of the gate voltage bootstrap capacitor CB is adapted to the sampling frequency, and the width-to-length ratio of the differential sampling switch is set proportionally according to the capacitor weight, sharing the core module of the bootstrap circuit.
[0029] SAR logic circuit: The asynchronous clock delay unit parameters are set according to the comparator response speed. A very small cross-coupled inverter sustainer is added to the TSPC flip-flop. All transistors are HVT devices.
[0030] Clock generation circuit: The controllable delay DELAY module consists of 15 delay units, with 4 control bits controlling the sampling time in a ratio of 8:4:2:1, and the non-overlapping clock falling edge interval is 128ps.
[0031] (2) Work process Reset phase: CLK_IN is a 50% duty cycle square wave, CLK_S is high level, all modules are reset, CDAC circuit is initialized, and comparator output is high level.
[0032] Sampling phase: When CLK_S goes low, the gate voltage bootstrap circuit works, the sampling switch is turned on, the input signal is sampled through the input buffer and held on the CDAC capacitor array, and the sampling time is set to 3.37ns~8.58ns according to the control code.
[0033] Comparison and quantization stage: When CLK_C goes low, the comparator starts working, compares the CDAC output voltage with the reference voltage, and outputs the comparison result; the SAR logic circuit controls the switching of the lower plate of CDAC according to the comparison result, and adjusts the CDAC output voltage; the comparison process is repeated 11 times, gradually approximating the true value of the input signal.
[0034] Output stage: After 11 comparisons, the EOC signal goes high, and the output latch circuit outputs a 10-bit digital code before the next high level of CLK_OUT, completing one conversion.
[0035] Through the above implementation methods, this invention achieves real-time sensing, accurate calculation, rapid response, intelligent collaboration, and reliable management of building energy efficiency and carbon emissions, effectively supporting the green and low-carbon operation of buildings. It should be noted that, although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.
[0036] In addition, throughout this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.
Claims
1. A CDAC and comparator co-operation circuit based on dynamic power consumption optimization, characterized in that, This includes an ultra-low power 48MS / s 10-bit SAR ADC, comprising a clock generation circuit, an input buffer, a reference voltage circuit, a sample-and-hold circuit, a differential CDAC circuit, a comparator, SAR logic circuitry, and an output latch circuit. The clock generation circuit receives a 50% duty cycle square wave CLK_IN and generates a sampling clock CLK_S, a plate control clock CLK_SP, a logic reset clock, and a synchronous output clock CLK_OUT. The input buffer is a push-pull source follower structure based on an RC high-pass filter, used to isolate the signal source from the sampling network and provide low-impedance drive. The sample-and-hold circuit combines a gate voltage bootstrap circuit with a differential sampling switch. The structure samples and holds the input signal on the CDAC circuit; the CDAC circuit is a binary capacitor array structure with redundant bits, using VCM_Based switching timing; the comparator is a positive feedback body-biased dynamic comparator with dynamic floating-point inverter amplifier (FIA), which compares the CDAC output signal and outputs the result; the SAR logic circuit adopts an asynchronous clock architecture and a low-power TSPC flip-flop, controlling the switching of the lower plate of the CDAC according to the comparison result; the output latch circuit is used to stably output a 10-bit digital code; the clock generation circuit includes a controllable delay DELAY module composed of 15 delay units, CLK_SP and CLK_S are non-overlapping clocks with a falling edge interval of 128ps.
2. The CDAC and comparator collaborative circuit based on dynamic power consumption optimization according to claim 1, characterized in that, The push-pull source follower based on the RC high-pass filter consists of three parts: a negative feedback circuit, an RC high-pass filter circuit, and a push-pull source follower. The negative feedback circuit stabilizes the input node voltage at VCM (400mV). The RC high-pass filter circuit uses a 2pF capacitor and a 1G ohm back-to-back resistor to filter out low-frequency noise. The push-pull source follower has no constant bias current. When the input voltage is high, only the NMOS operates, and when the input voltage is low, only the PMOS operates, improving the power efficiency to 78%.
3. The CDAC and comparator collaborative circuit based on dynamic power consumption optimization according to claim 2, characterized in that, The positive feedback body bias dynamic comparator with dynamic floating-point inverter amplifier includes a FIA preamplifier and a subsequent positive feedback body bias-dynamic current rudder comparator. The FIA preamplifier uses an inverter-based input pair and is powered by a floating capacitor CRES to achieve current reuse and dynamic bias, preventing the load capacitor from fully discharging. The subsequent comparator cross-connects the output nodes VON and VOP of the first-stage preamplifier to the substrate of the input pair transistors, dynamically widening the threshold voltage Vth difference, shortening the comparison time by about 30%, and controlling the input reference noise to around 200µVrms.
4. The CDAC and comparator collaborative circuit based on dynamic power consumption optimization according to claim 3, characterized in that, The redundant design of the CDAC circuit expands the 10-bit to 11-bit architecture, adjusts the weight of the highest-order capacitor from 512 to 448, and allocates the split 64 bits to the lower bits, satisfying the requirement of Wi < Σ(j=0 to i-1)Wj. The minimum unit capacitance is reduced from 3fF to 1fF. In the VCM_Based switching timing, during capacitor switching, one end of the capacitor switches from VCM to VREF or GND, with a normalized total energy of 0.25CV. 2 .
5. The CDAC and comparator collaborative circuit based on dynamic power consumption optimization according to claim 4, characterized in that, The gate voltage bootstrap circuit of the sample-and-hold circuit raises the gate potential of the sampling transistor to VDD+VIN through the bootstrap capacitor CB, so that VGS is constant at VDD; the differential sampling switch eliminates even-order harmonic distortion. The FFT simulation results under full PVT are: ENOB maximum value 12.5bit, typical value 12.1bit, minimum value 10.4bit; SNR maximum value 76.2dB, typical value 74.8dB, minimum value 65.4dB; SFDR maximum value 89.3dB, typical value 82.9dB, minimum value 76.6dB.
6. The CDAC and comparator collaborative circuit based on dynamic power consumption optimization according to claim 5, characterized in that, The asynchronous clock generation circuit of the SAR logic circuit consists of a comparator, a gate circuit, and a delay unit, and triggers the next comparison through the READYB signal; the TSPC flip-flop adds a cross-coupled inverter maintainer, uses a high threshold device, and reduces the static power consumption to 2μW-5μW; the control logic unit outputs U<9:0>, UB<9:0>, CU<9:0>, CBU<9:0>, D<9:0>, DB<9:0>, CD<9:0>, and CBD<9:0> signals, which respectively control the connection of the upper and lower plates of CDAC to VREFN, VREFP, and VCM.
7. The CDAC and comparator collaborative circuit based on dynamic power consumption optimization according to claim 6, characterized in that, The controllable delay DELAY module of the clock generation circuit adjusts the sampling time through 4 control bits. When the control code is "0000", the sampling time is 3.37ns, and when the control code is "1111", the sampling time is 8.58ns. The control bit ratio is 8:4:2:
1.
8. The CDAC and comparator collaborative circuit based on dynamic power consumption optimization according to claim 7, characterized in that, It adopts a 22nm process, a power supply voltage of 0.8V, and a sampling period of 21ns, of which 6ns are used for sampling, and the remaining time is used to complete 11 comparison quantizations and margin reservations. The comparison clock frequency is approximately 1GHz, and the single comparison period is 1.15ns.