Interference IP core and interference method for LIN bus test

Abstract

This invention belongs to the field of automotive electronic communication network testing technology, specifically relating to an interference IP core and interference method for LIN bus testing. The interference IP core for LIN bus testing includes: a bus monitoring module for real-time monitoring of communication data on the LIN bus to identify the currently transmitted frame type and bus status, wherein the frame type includes a frame header and a response; a role determination module for determining the role played by the IP core based on the currently transmitted frame type and bus status, wherein the role includes a host role or a slave node role; and an interference execution module for executing interference according to preset interference configuration parameters and the role determined by the role determination module.

Description

Cross-references to related applications

[0001] This application is based on and claims priority to Chinese Patent Application No. 2025112463214, filed on September 2, 2025. The entire contents of the aforementioned application are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of automotive electronic communication network testing technology, and in particular to an interference IP core and interference method for LIN bus testing. Background Technology

[0003] LIN (Partial Interconnect Network) is a low-cost, single-wire serial communication protocol for automotive body control. Its communication is based on a master-slave architecture, with the host task controlling the scheduling table. In automotive electronic systems, LIN bus communication testing is crucial. Existing bus interference testing schemes mainly fall into two categories: one is host-simulated software interference, which modifies the scheduling table or frame data by running LIN master node simulation software on a PC. This method cannot simulate abnormal slave node behavior and is limited by software real-time constraints. The other is simple signal jammers, which use hardware to pull the LIN bus level low or high to simulate short circuits or open circuits. However, the interference mode is too low-level and simplistic, unable to simulate complex protocol logic errors. Existing interference schemes cannot disrupt the master-slave architecture, mostly initiating interference from the host's perspective. Furthermore, existing interference schemes are mostly concentrated at the physical layer or data content, lacking interference with frame structure integrity (such as PID verification and synchronization fields) and the ability to attack the scheduling mechanism, resulting in a limited testing dimension.

[0004] Therefore, existing technologies suffer from at least one technical problem: the lack of effective means to simulate "abnormal behavior of slave nodes," resulting in an insufficiently comprehensive range of LIN bus testing dimensions.

[0005] It should be noted that the information disclosed in this background section is only for understanding the background technology of the present application concept, and therefore, the above description is not considered to constitute prior art information. Summary of the Invention

[0006] The purpose of this invention is to provide an interference IP core and interference method for LIN bus testing.

[0007] To address the aforementioned technical problems, this invention provides an interference IP core for LIN bus testing, comprising: The bus monitoring module is used to monitor the communication data on the LIN bus in real time to identify the currently transmitted frame type and bus status, wherein the frame type includes: frame header and response; A role determination module is used to determine the role played by the IP core based on the current frame type and bus status, wherein the role includes a host role or a slave node role; and The interference execution module is used to perform interference according to the preset interference configuration parameters and the role determined by the role judgment module.

[0008] In another aspect, the present invention also provides an interference method for LIN bus testing, comprising: The communication data on the LIN bus is monitored in real time by the bus monitoring module to identify the currently transmitted frame type and bus status, wherein the frame type includes: frame header and response; The role determination module determines the role of the IP core based on the current frame type and bus status, whereby the role may be either a host or a slave node. The interference execution module performs interference based on preset interference configuration parameters and the role determined by the role judgment module.

[0009] Thirdly, the present invention also provides a LIN bus testing device, comprising: Main controller; LIN bus transceiver; As previously mentioned, the interference IP core; The interference IP core is connected to the main controller to receive interference configuration parameters output by the main controller; and The interference IP core is connected to the LIN bus via the LIN bus transceiver to perform interference on the host node under test and at least one slave node under test connected to the LIN bus by monitoring the LIN bus and the interference configuration parameters.

[0010] Fourthly, the present invention also provides a LIN bus interference testing system, comprising: The host computer and the LIN bus testing equipment as described above; The host computer is adapted to send preset interference configuration parameters to the main controller of the LIN bus test device.

[0011] Fifthly, the present invention also provides a readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the following operations: Real-time monitoring of communication data on the LIN bus to identify the currently transmitted frame type and bus status, wherein the frame type includes: frame header and response; Based on the current frame type and bus state, determine the role played by the IP core, which may be a host role or a slave node role; and Interference is executed based on preset interference configuration parameters and the determined role.

[0012] The beneficial effects of this invention are that the interference IP core for LIN bus testing breaks through the host-centric mode in traditional LIN bus testing through the coordinated cooperation of the bus monitoring module, role judgment module and interference execution module. It can initiate interference not only as a host but also as a slave node. At the same time, combined with preset interference configuration parameters, it can simulate various logical faults and abnormal node behaviors required in current LIN bus testing, which greatly improves the comprehensiveness, efficiency and depth of LIN bus testing, thereby improving the reliability of the entire vehicle control network.

[0013] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained through the structures particularly pointed out in the description and the drawings.

[0014] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 A schematic block diagram of a interference IP core for LIN bus testing is shown in some embodiments; Figure 2 The diagram illustrates the steps of an interference method for LIN bus testing as described in some embodiments; Figure 3 A schematic block diagram of a LIN bus test device involved in some embodiments is shown; Figure 4 A schematic block diagram of a LIN bus interference testing system according to some embodiments is shown. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Definitions of abbreviations and key terms IP core: Intellectual property core, a reusable circuit functional module unit.

[0019] LIN: Local Interconnect Network. A low-cost, single-wire serial communication protocol for automotive body control.

[0020] Scheduling table: A time sequence for LIN host task control bus communication, defining the order and time intervals of frame transmission.

[0021] Frame header / response: The basic unit of LIN communication. The frame header is sent by the host (containing the synchronization interval field, synchronization field, and protected identifier), and the response is sent by the slave node or the host (containing the data field and check field).

[0022] Protected Identifier (PID): LIN frame identifier, containing the frame ID and its check bits (P0, P1).

[0023] Existing interference schemes cannot overturn the master-slave architecture. Most of them are based on the host's perspective to initiate interference. Moreover, existing interference schemes are mostly concentrated on the physical layer or data content, lacking interference with the integrity of the frame structure (such as PID verification and synchronization field), and also lacking the ability to attack the scheduling mechanism. The testing dimensions are also limited.

[0024] Therefore, at least one embodiment provides an interference IP core for LIN bus testing, comprising: a bus monitoring module for real-time monitoring of communication data on the LIN bus to identify the currently transmitted frame type and bus status, wherein the frame type includes: a frame header and a response; a role determination module for determining the role played by the IP core based on the currently transmitted frame type and bus status, wherein the role includes a host role or a slave node role; and an interference execution module for executing interference according to preset interference configuration parameters and the role determined by the role determination module.

[0025] The interference IP core for LIN bus testing in this embodiment, through the coordinated operation of the bus monitoring module, role judgment module, and interference execution module, breaks through the host-centric mode in traditional LIN bus testing. It can initiate interference not only as a host but also as a slave node. In addition, combined with preset interference configuration parameters, it can simulate various logical faults and abnormal node behaviors required in current LIN bus testing, greatly improving the efficiency and depth of LIN bus testing, thereby enhancing the reliability of the entire vehicle control network.

[0026] The various non-limiting embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0027] like Figure 1 As shown, this embodiment provides an interference IP core for LIN bus testing, including: a bus monitoring module for real-time monitoring of communication data on the LIN bus to identify the currently transmitted frame type and bus status, wherein the frame type includes: frame header and response; a role determination module for determining the role played by the IP core based on the currently transmitted frame type and bus status, wherein the role includes a host role or a slave node role; and an interference execution module for executing interference according to preset interference configuration parameters and the role determined by the role determination module.

[0028] Specifically, the method by which the role determination module determines the role played by the IP core based on the currently transmitted frame type and bus state includes: when the bus monitoring module detects that the frame type currently transmitted on the LIN bus is a frame header, it determines that the IP core is a slave node; when the bus monitoring module detects that the frame type currently transmitted on the LIN bus is a response, it determines that the IP core is a master node; when the bus monitoring module detects that the LIN bus is in an idle state or a sleep state, it determines that the IP core is a master node; when the bus monitoring module detects that the LIN bus has abnormal communication that is not specified by the protocol, it determines that the IP core is a slave node.

[0029] In some embodiments, the interference IP core further includes: a configuration interface module for receiving the interference configuration parameters, the interference configuration parameters including interference mode, interference target parameters and interference data parameters.

[0030] Specifically, before the interference IP core starts working in this embodiment, the system software (such as the CPU) configures the operating parameters of the interference IP core in advance through the configuration interface module of the interference IP core, including: 1) Set the interference mode and interference target parameters to be tested.

[0031] Specifically, the interference modes include one or more of the following: response hijacking interference, slave node abnormal response interference, PID tampering interference, scheduling table timing distortion interference, synchronization field destruction interference, fake sleep command interference, and wake-up signal contention interference.

[0032] Specifically, the interference target parameters include, for example but not limited to, a target protected identifier (PID) used to determine the target frame.

[0033] 2) Configure the corresponding interference data parameters according to the interference mode and interference target parameters.

[0034] Specifically, the interference data parameters include, for example: erroneous or forged response data to be actively sent in response to hijacking interference; response data to be actively sent in response to abnormal response interference from slave nodes; target value of the time interval between frames to be modified in scheduling table timing distortion interference; and sleep command frames to be sent in forged sleep command interference.

[0035] In some embodiments, the interference execution module includes: a slave node role subversion unit; wherein the slave node role subversion unit is adapted to perform at least one of the response hijacking interference and the slave node abnormal response interference when the interference IP core plays the role of a slave node.

[0036] Specifically, the response hijacking interference is the process of actively sending erroneous or forged response data after the host has sent the frame header of the target frame, before the correct slave node responds; the response hijacking interference is used to test the host's conflict handling capabilities and the behavior of the correct slave node.

[0037] Specifically, the abnormal response interference of the slave node is to actively send response data outside the frame transmission time slot specified in the scheduling table; the abnormal response interference of the slave node is used to simulate the abnormal behavior of the slave node, such as simulating the slave node software crashing.

[0038] The interference IP core in this embodiment breaks through the host-centric mode in traditional LIN bus testing and pioneers a series of proactive attacks launched from the "slave node perspective", such as actively sending erroneous or forged response data and simulating abnormal behavior of slave nodes, in order to test the host's conflict handling capabilities and bus management robustness, greatly expanding the testing boundaries.

[0039] In some embodiments, the interference execution module includes: a scheduling table and frame structure attack unit; wherein the scheduling table and frame structure attack unit is adapted to perform at least one of the PID tampering interference, the scheduling table timing distortion interference, and the synchronization field destruction interference when the interference IP core plays the role of a host.

[0040] Specifically, the PID tampering interference modifies the target protected identifier (PID) in the target frame sent by the host and destroys the check bit of the target protected identifier (PID); the PID tampering interference is used to test the slave node's ability to identify illegal PIDs.

[0041] Specifically, the scheduling table timing distortion interference dynamically modifies the time interval between frames to compress or stretch the scheduling time slots, thereby disrupting the established communication rhythm. The scheduling table timing distortion interference is used to test the adaptability of master and slave nodes to non-uniform modulation.

[0042] Specifically, the synchronization field disruption interference modifies the synchronization field data in the target frame header, and the synchronization field disruption interference is used to test the baud rate self-synchronization capability of the slave node.

[0043] Specifically, through the interference IP core of this embodiment, it is possible to fully test whether the behavior of LIN slave nodes under deteriorated communication environment (such as abnormal synchronization field data or receiving illegal PID) meets the design expectations, and avoid system freeze caused by the failure of a single node.

[0044] Specifically, the interference IP core in this embodiment can interfere with the scheduling mechanism, dynamically distorting the time dimension of the LIN bus communication scheduling table, and testing the tolerance of LIN bus devices or systems to LIN bus communication timing anomalies.

[0045] In some embodiments, the interference execution module includes: a sleep / wake management interference unit; wherein The sleep / wake management interference unit is adapted to perform at least one of forged sleep command interference and wake-up signal contention interference when the interference IP core acts as a host.

[0046] Specifically, the fake sleep command interference is to mimic the host sending a legitimate sleep command frame, such as sending a sleep command frame with PID=0x3C and data=0x00, thereby inducing all nodes on the current LIN bus to enter a sleep state.

[0047] Specifically, the wake-up signal contention interference involves sending a pseudo-frame header immediately during or after the slave node sends a wake-up signal to create a bus conflict, thereby testing the host's wake-up processing mechanism.

[0048] Specifically, the interference IP core in this embodiment can provide a powerful verification method for the overall sleep or wake-up power management function of the LIN network, ensuring that the vehicle has no abnormal power consumption in a silent state.

[0049] In some embodiments, the configuration interface module includes: a configurable register group; and the configurable register group is adapted to store the interference configuration parameters.

[0050] like Figure 2 As shown, some embodiments also provide an interference method for LIN bus testing, including: Step S01: Monitor the communication data on the LIN bus in real time through the bus monitoring module to identify the currently transmitted frame type and bus status, wherein the frame type includes: frame header and response; Step S02: The role determination module determines the role played by the IP core based on the current transmitted frame type and bus status. The role includes either a host role or a slave node role. Step S03: The interference execution module performs interference according to the preset interference configuration parameters and the role determined by the role judgment module.

[0051] Specifically, the working methods or principles of the bus monitoring module, role judgment module, and interference execution module are described in the previous description of the interference IP core used for LIN bus testing, and will not be repeated here.

[0052] like Figure 3 As shown, some embodiments also provide a LIN bus test device, including: a master controller; a LIN bus transceiver; an interference IP core as described above; the interference IP core is connected to the master controller to receive interference configuration parameters output by the master controller; and the interference IP core is connected to the LIN bus through the LIN bus transceiver to perform interference on the host node under test and at least one slave node under test connected to the LIN bus by monitoring the LIN bus and the interference configuration parameters.

[0053] Specifically, the interference IP core is connected to the main controller via a standard interface; wherein the standard interface includes an APB interface or an AXI interface.

[0054] For details on the working method or principle of the interference IP core, please refer to the previous description of the interference IP core used for LIN bus testing, which will not be repeated here.

[0055] like Figure 4 As shown, some embodiments also provide a LIN bus interference testing system, including: a host computer and a LIN bus testing device as described above; the host computer is adapted to send preset interference configuration parameters to the main controller of the LIN bus testing device.

[0056] Some embodiments also provide a readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the following operations: real-time monitoring of communication data on the LIN bus to identify the currently transmitted frame type and bus state, wherein the frame type includes a frame header and a response; determining the role played by the IP core based on the currently transmitted frame type and bus state, the role including a host role or a slave node role; and performing interference according to preset interference configuration parameters and the determined role.

[0057] In some embodiments, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and embedded program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action.

[0058] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0059] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This embedded software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present invention.

[0060] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. An interference IP core for LIN bus testing, characterized in that, include: The bus monitoring module is used to monitor the communication data on the LIN bus in real time to identify the currently transmitted frame type and bus status, wherein the frame type includes: frame header and response; A role determination module is used to determine the role played by the IP core based on the current frame type and bus status, wherein the role includes a host role or a slave node role; and The interference execution module is used to perform interference according to the preset interference configuration parameters and the role determined by the role judgment module.

2. The interference IP core according to claim 1, characterized in that, The interference IP core also includes: The configuration interface module is used to receive the interference configuration parameters, which include interference mode, interference target parameters, and interference data parameters; wherein... The interference modes include one or more of the following: response hijacking interference, slave node abnormal response interference, PID tampering interference, scheduling table timing distortion interference, synchronization field destruction interference, fake sleep command interference, and wake-up signal contention interference.

3. The interference IP core according to claim 2, characterized in that, The interference execution module includes: a node role subversion unit; wherein... The slave node role subversion unit is adapted to perform at least one of the response hijacking interference and the slave node abnormal response interference when the interfering IP core plays the role of a slave node; and The response hijacking interference refers to the process where, after the host has sent the header of the target frame, it actively sends incorrect or forged response data before the correct slave node responds. The abnormal response interference of the slave node is to actively send response data outside the frame transmission time slot specified in the scheduling table in order to simulate the abnormal behavior of the slave node.

4. The interference IP core according to claim 2, characterized in that, The interference execution module includes: a scheduling table and a frame structure attack unit; wherein... The scheduling table and frame structure attack unit are adapted to perform at least one of the following when the interference IP core acts as a host: the PID tampering interference, the scheduling table timing distortion interference, and the synchronization field disruption interference; and The PID tampering interference modifies the target protected identifier PID in the target frame sent by the host and destroys the check bit of the target protected identifier PID. The scheduling table timing distortion interference dynamically modifies the time interval between frames to compress or stretch the scheduling time slots, thereby disrupting the established communication rhythm. The synchronization field disruption interference modifies the synchronization field data in the target frame header to test the baud rate self-synchronization capability of the slave node.

5. The interference IP core according to claim 2, characterized in that, The interference execution module includes: a sleep / wake management interference unit; wherein... The sleep / wake management interference unit is adapted to perform at least one of forged sleep command interference and wake-up signal contention interference when the interference IP core acts as a host; and The forged sleep command interference mimics the host sending a legitimate sleep command frame, inducing all nodes on the current LIN bus to enter a sleep state; The wake-up signal contention interference is to create a bus conflict by immediately sending a pseudo-frame header during or after the slave node sends a wake-up signal.

6. The interference IP core according to claim 2, characterized in that, The configuration interface module includes: a configurable register set; and The configurable register set is adapted to store the interference configuration parameters.

7. An interference method for LIN bus testing, characterized in that, include: The communication data on the LIN bus is monitored in real time by the bus monitoring module to identify the currently transmitted frame type and bus status, wherein the frame type includes: frame header and response; The role determination module determines the role of the IP core based on the current frame type and bus status, whereby the role may be either a host or a slave node. The interference execution module performs interference based on preset interference configuration parameters and the role determined by the role judgment module.

8. The interference method according to claim 7, characterized in that, Also includes: The interference configuration parameters are received through the configuration interface module. The interference configuration parameters include interference mode, interference target parameters, and interference data parameters. as well as The interference modes include one or more of the following: response hijacking interference, slave node abnormal response interference, PID tampering interference, scheduling table timing distortion interference, synchronization field destruction interference, fake sleep command interference, and wake-up signal contention interference.

9. A LIN bus testing device, characterized in that, include: Main controller; LIN bus transceiver; The interference IP core as described in any one of claims 1-6; The interference IP core is connected to the main controller to receive interference configuration parameters output by the main controller; as well as The interference IP core is connected to the LIN bus via the LIN bus transceiver to perform interference on the host node under test and at least one slave node under test connected to the LIN bus by monitoring the LIN bus and the interference configuration parameters.

10. The LIN bus testing device according to claim 9, characterized in that, The interference IP core is connected to the main controller via a standard interface; The standard interfaces include either the APB interface or the AXI interface.

11. A LIN bus interference testing system, characterized in that, include: The host computer and the LIN bus test device as described in any one of claims 9-10; The host computer is adapted to send preset interference configuration parameters to the main controller of the LIN bus test device.

12. A readable storage medium, characterized in that, The system stores instructions that, when executed by the processor, cause the processor to perform the following operations: Real-time monitoring of communication data on the LIN bus to identify the currently transmitted frame type and bus status, wherein the frame type includes: frame header and response; Based on the current frame type and bus state, determine the role played by the IP core, which may be a host role or a slave node role; and Interference is executed based on preset interference configuration parameters and the determined role.

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