Thermal failure handling circuit, thermal failure handling method, electronic device, medium, and product

Abstract

Embodiments of the present application provide a thermal failure processing circuit, a thermal failure processing method, an electronic device, a medium and a product. The thermal failure processing circuit comprises a power topology module, a signal processing module and a control module, wherein the power topology module comprises a first transistor and a second transistor, the control module is configured to control the first transistor and the second transistor to be turned on, a first detection unit is configured to collect a first voltage corresponding to a second end of the first transistor and send the first voltage to the control module, a second detection unit is configured to collect a second voltage corresponding to a second end of the second transistor and send the second voltage to the control module, and the control module is configured to perform thermal failure detection on the first transistor and / or the second transistor based on the first voltage and / or the second voltage, and start a preset processing mechanism when the first transistor and / or the second transistor is thermally failed. Based on the thermal failure processing circuit provided by the present application, the stability and reliability of the system can be improved.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a thermal failure handling circuit, thermal failure handling method, electronic device, medium and product. Background Technology

[0002] With the rapid development of the energy storage industry, silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOS) are widely used in half-bridge two-level inverter topologies to improve power density. However, in practical applications, the forward voltage drop (VF) of the body diode of a SiC MOS is significantly higher than that of an insulated-gate bipolar transistor (IGBT) or other transistors. Therefore, in a half-bridge topology, if the drive signal is abnormal, the freewheeling current will be forced through the body diode of the SiC MOS, resulting in abnormally high conduction losses. This loss causes a sharp rise in the local temperature of the SiC MOS, leading to thermal failure and seriously threatening system stability and safety.

[0003] Currently, in related technologies, synchronous rectification control strategies are commonly used to reduce the conduction losses of SiC MOS. These strategies primarily involve precisely controlling the switching timing of the upper and lower bridge arm SiC MOS to ensure that the freewheeling current always flows through the conducting SiC MOS rather than its internal diode. For example, the drive signal needs to have a reasonable dead time between the upper and lower bridge arm SiC MOS to avoid shoot-through short circuits.

[0004] However, the relevant technologies mainly rely on preset dead time and stable drive signals, lacking a real-time monitoring mechanism for abnormal operating conditions. They cannot identify and respond to abnormal operating conditions of SiC MOS in a timely manner, resulting in low stability and reliability of the energy storage system in which the half-bridge topology is located. Summary of the Invention

[0005] This application provides thermal failure handling circuits, thermal failure handling methods, electronic devices, media, and products for real-time monitoring of abnormal operating conditions of transistors in a half-bridge topology and timely handling of abnormal operating conditions of transistors to improve the stability and reliability of the system.

[0006] In a first aspect, embodiments of this application provide a thermal failure handling circuit, which includes: a power topology module, a signal processing module, and a control module. The power topology module includes a first transistor and a second transistor, with a first terminal of the first transistor connected to a second terminal of the second transistor and a second terminal of the first transistor connected to a first terminal of the second transistor. The signal processing module includes a first detection unit and a second detection unit.

[0007] The first terminal of the control module is connected to the control terminal of the first transistor and is used to send a first drive signal to the first transistor to control the first transistor to conduct.

[0008] The second terminal of the control module is connected to the control terminal of the second transistor and is used to send a first drive signal to the second transistor to control the second transistor to turn on.

[0009] The first end of the first detection unit is connected to the second end of the first transistor, and the second end of the first detection unit is connected to the third end of the control module. It is used to collect the first voltage corresponding to the second end of the first transistor and send the first voltage to the control module.

[0010] The first end of the second detection unit is connected to the second end of the second transistor, and the second end of the first detection unit is connected to the fourth end of the control module. It is used to collect the second voltage corresponding to the second end of the second transistor and send the second voltage to the control module.

[0011] The control module is used to perform thermal failure detection on the first transistor and / or the second transistor based on the first voltage and / or the second voltage, so as to determine whether the first transistor and / or the second transistor has thermal failure;

[0012] The control module is also used to activate a preset processing mechanism when the first transistor and / or the second transistor thermally fail.

[0013] In one possible implementation, the power topology module further includes: a first capacitor, a second capacitor, a third capacitor, and an inductor;

[0014] The first terminal of the first capacitor is connected to the first terminal of the first transistor, the second terminal of the first capacitor is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the second terminal of the second transistor, for the purpose of stabilizing the voltage.

[0015] The first end of the inductor is connected to the first end of the second transistor, and the second end of the inductor is connected to the first end of the third capacitor. This is used to charge the capacitor when the first transistor or the second transistor is turned on to store electrical energy, and to discharge the capacitor when the first transistor or the second transistor is turned off to release electrical energy.

[0016] The second terminal of the third capacitor is grounded and used to filter the voltage in the circuit.

[0017] In one possible implementation, the first detection unit includes a first power supply unit and a first acquisition unit, and the second detection unit includes a second power supply unit and a second acquisition unit.

[0018] The first terminal of the first power supply unit is connected to the second terminal of the first transistor, and the second terminal of the first power supply unit is connected to the first terminal of the first acquisition unit, for providing operating voltage to the first acquisition unit.

[0019] The second end of the first acquisition unit is connected to the third end of the control module, and is used to acquire the first voltage corresponding to the second end of the first transistor and send the first voltage to the control module.

[0020] The first terminal of the second power supply unit is connected to the second terminal of the second transistor, and the second terminal of the second power supply unit is connected to the first terminal of the second acquisition unit to provide operating voltage for the second acquisition unit.

[0021] The second terminal of the second acquisition unit is connected to the fourth terminal of the control module, and is used to acquire the second voltage corresponding to the second terminal of the second transistor and send the second voltage to the control module.

[0022] In one possible implementation, the first power supply unit includes a first diode, and the second power supply unit includes a second diode;

[0023] The first end of the first diode is connected to the second end of the first transistor, and the second end of the first diode is connected to the first power supply and the first end of the first acquisition unit to provide operating voltage to the first acquisition unit.

[0024] The first terminal of the second diode is connected to the second terminal of the second transistor, and the second terminal of the second diode is connected to the first terminal of the second power supply and the second acquisition unit to provide operating voltage for the second acquisition unit.

[0025] In one possible implementation, the first power supply unit further includes a first resistor and a second resistor, and the second power supply unit further includes a third resistor and a fourth resistor.

[0026] The first end of the first resistor is connected to the second end of the first diode, and the second end of the first resistor is connected to the first power supply.

[0027] The first end of the second resistor is connected to the first end of the first resistor, and the second end of the second resistor is connected to the first end of the first acquisition unit. The first resistor and the second resistor are used to reduce the current value in the path.

[0028] The first end of the third resistor is connected to the second end of the second diode, and the second end of the third resistor is connected to the second power supply.

[0029] The first end of the fourth resistor is connected to the first end of the third resistor, and the second end of the fourth resistor is connected to the first end of the second acquisition unit. The third and fourth resistors are used to reduce the current value in their respective paths.

[0030] In one possible implementation, the first acquisition unit includes a fourth capacitor and a first boost module, and the second acquisition unit includes a fifth capacitor and a second boost module.

[0031] The first terminal of the first boost module is connected to the third terminal of the third power supply and control module. The second terminal of the first boost module is grounded. The third terminal of the first boost module is grounded and connected to the first terminal of the fourth capacitor. The fourth terminal of the first boost module is connected to the second terminal of the second resistor. This is used to boost the voltage at the second terminal of the first transistor Q1 to obtain the first voltage.

[0032] The second terminal of the fourth capacitor is connected to the second terminal of the second resistor, and is used to filter the first voltage.

[0033] The first terminal of the second boost module is connected to the fourth terminal of the fourth power supply and control module. The second terminal of the second boost module is grounded. The third terminal of the second boost module is grounded and connected to the first terminal of the fifth capacitor. The fourth terminal of the second boost module is connected to the second terminal of the fourth resistor. This is used to boost the voltage of the second terminal of the second transistor to obtain the second voltage.

[0034] The second terminal of the fifth capacitor is connected to the second terminal of the fourth resistor to filter the second voltage.

[0035] In one possible implementation, the first boost module includes a third diode and a first transistor, and the second boost module includes a fourth diode and a second transistor;

[0036] The first terminal of the third diode is grounded, the second terminal of the third diode is connected to the second terminal of the second resistor, the first terminal of the first transistor is connected to the third power supply, the second terminal of the first transistor is grounded, and there is optical coupling isolation between the control terminal of the first transistor and the third diode.

[0037] The first terminal of the fourth diode is grounded, the second terminal of the fourth diode is connected to the second terminal of the fourth resistor, the first terminal of the second transistor is connected to the fourth power supply, the second terminal of the second transistor is grounded, and there is optical isolation between the control terminal of the second transistor and the fourth diode.

[0038] In one possible implementation, the first acquisition unit further includes a fifth resistor and a sixth resistor, and the second acquisition unit further includes a seventh resistor and an eighth resistor;

[0039] The first end of the fifth resistor is connected to the third power supply, and the second end of the fifth resistor is connected to the first end of the first transistor, which is used to divide the voltage of the third power supply.

[0040] The first end of the sixth resistor is connected to the second end of the third diode, and the second end of the sixth resistor is connected to the second end of the second resistor, which is used to divide the first voltage.

[0041] The first end of the seventh resistor is connected to the fourth power supply, and the second end of the seventh resistor is connected to the first end of the second transistor, which is used to divide the voltage of the fourth power supply.

[0042] The first end of the eighth resistor is connected to the second end of the fourth diode, and the second end of the eighth resistor is connected to the second end of the fourth resistor, which is used to perform voltage division on the second voltage.

[0043] Secondly, this application provides a thermal failure handling method, applied to the thermal failure handling circuit provided by the first aspect and / or various possible embodiments of the first aspect, wherein the thermal failure handling circuit includes: a power topology module, a signal processing module, and a control module, wherein the power topology module includes a first transistor and a second transistor, a first terminal of the first transistor is connected to a second terminal of the second transistor, and a second terminal of the first transistor is connected to a first terminal of the second transistor; the signal processing module includes a first detection unit and a second detection unit; the method includes:

[0044] The first voltage collected by the first detection unit is obtained, wherein the first voltage is the voltage corresponding to the second terminal of the first transistor;

[0045] The second voltage collected by the second detection unit is obtained, wherein the second voltage is the voltage corresponding to the second terminal of the second transistor;

[0046] Thermal failure detection is performed on the first transistor and / or the second transistor based on the first voltage and / or the second voltage to determine whether the first transistor and / or the second transistor has thermal failure.

[0047] When the first transistor and / or the second transistor thermally fail, a preset processing mechanism is activated.

[0048] Thirdly, embodiments of this application provide an electronic device, including: a memory and a processor;

[0049] The memory stores the instructions that the computer executes;

[0050] The processor executes computer execution instructions stored in memory, causing the processor to perform the implementation method described in the second aspect above.

[0051] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the embodiments described in the second aspect above.

[0052] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the implementation methods described in the second aspect above.

[0053] The thermal failure handling circuit, thermal failure handling method, electronic device, medium, and product provided in this application embodiment include a thermal failure handling circuit comprising a power topology module, a signal processing module, and a control module. The power topology module includes a first transistor and a second transistor, and the signal processing module includes a first detection unit and a second detection unit. The first detection unit acquires a first voltage at the second terminal of the first transistor, and the second detection unit acquires a second voltage at the second terminal of the second transistor. This allows the control module to determine whether the first transistor and / or the second transistor has thermally failed based on the first voltage and / or the second voltage, and to activate a preset processing mechanism when the first transistor and / or the second transistor thermally fails. Based on the thermal failure handling circuit provided in this application, the voltage at the second terminal of the first transistor and the second transistor can be monitored in real time to achieve the purpose of real-time monitoring of the operating conditions of the first transistor and the second transistor. Abnormal operating conditions of the first transistor and the second transistor can be identified in a timely manner and handled promptly to improve the stability and reliability of the system. Attached Figure Description

[0054] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0055] Figure 1 This is a schematic diagram of the half-bridge topology as exemplified in this application;

[0056] Figure 2 Schematic diagram of the thermal failure handling circuit provided in this application Figure 1 ;

[0057] Figure 3 Schematic diagram of the thermal failure handling circuit provided in this application Figure 2 ;

[0058] Figure 4 Schematic diagram of the thermal failure handling circuit provided in this application Figure 3 ;

[0059] Figure 5 Schematic diagram of the thermal failure handling circuit provided in this application Figure 4 ;

[0060] Figure 6 Schematic diagram of the thermal failure handling circuit provided in this application Figure 5 ;

[0061] Figure 7 Schematic diagram of the thermal failure handling circuit provided in this application Figure 6 ;

[0062] Figure 8 Schematic diagram of the thermal failure handling circuit provided in this application Figure 7 ;

[0063] Figure 9 Schematic diagram of the thermal failure handling circuit provided in this application Figure 8 ;

[0064] Figure 10 A schematic flowchart of the thermal failure treatment method provided in this application;

[0065] Figure 11 A schematic diagram of the structure of the electronic device provided in this application.

[0066] The above figures include the following reference numerals:

[0067] Q1: First transistor;

[0068] Q2: Second transistor;

[0069] Q3: First transistor;

[0070] Q4: Second transistor;

[0071] C1: First capacitor;

[0072] C2: Second capacitor;

[0073] C3: Third capacitor;

[0074] C4: Fourth capacitor;

[0075] C5: Fifth capacitor;

[0076] L: Inductance;

[0077] D1: First diode;

[0078] D2: Second diode;

[0079] D3: Third diode;

[0080] D4: Fourth diode;

[0081] VCC1: First power supply;

[0082] VCC2: Second power supply;

[0083] VCC3: Third power supply;

[0084] VCC4: Fourth power supply;

[0085] R1: First resistor;

[0086] R2: Second resistor;

[0087] R3: Third resistor;

[0088] R4: Fourth resistor;

[0089] R5: Fifth resistor;

[0090] R6: The sixth resistor;

[0091] R7: The seventh resistor;

[0092] R8: The eighth resistor.

[0093] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0094] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0095] Figure 1 This is a schematic diagram of a half-bridge topology as an example of the present application. With the explosive growth of the energy storage industry, SICMOS is widely used in two-level inverter topologies of half-bridge topologies to improve product power density. Figure 1As shown, a half-bridge topology includes SiC MOS transistors in both upper and lower arms, each containing a body diode. In this topology, when the drive signal to the SiC MOS is abnormal, the freewheeling current flowing through the SiC MOS is forced through the body diode, resulting in abnormally high conduction losses. This loss causes a sharp rise in the local temperature of the SiC MOS, leading to thermal failure and severely threatening system stability and safety. Currently, related technologies typically employ synchronous rectification control strategies to reduce SiC MOS conduction losses. These strategies primarily rely on precise control of the switching timing of the upper and lower arm SiC MOS transistors to ensure that the freewheeling current always flows through the on-state SiC MOS transistor rather than its body diode. For example, the drive signal needs to have a reasonable dead time between the upper and lower arm SiC MOS transistors to avoid shoot-through short circuits. However, these technologies mainly rely on preset dead times and stable drive signals, lacking real-time monitoring mechanisms for abnormal operating conditions. This makes it impossible to promptly identify and respond to abnormal SiC MOS conditions, resulting in low stability and reliability of the energy storage system using the half-bridge topology.

[0096] The thermal failure handling circuit provided in this application includes a power topology module, a signal processing module, and a control module. The power topology module includes a first transistor and a second transistor. The signal processing module includes a first detection unit and a second detection unit. The first detection unit acquires a first voltage at the second terminal of the first transistor, and the second detection unit acquires a second voltage at the second terminal of the second transistor. This allows the control module to determine whether the first transistor and / or the second transistor has thermally failed based on the first voltage and / or the second voltage. Upon thermal failure of the first transistor and / or the second transistor, a preset processing mechanism is activated. Therefore, based on the thermal failure handling circuit provided in this application, the voltage at the second terminal of the first transistor and the second transistor can be monitored in real time to achieve real-time monitoring of the operating conditions of the first and second transistors. Abnormal operating conditions of the first and second transistors can be identified and addressed promptly to improve the stability and reliability of the system.

[0097] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0098] Figure 2 Schematic diagram of the thermal failure handling circuit provided in this application Figure 1 ,like Figure 2As shown, the thermal failure handling circuit includes: a power topology module, a signal processing module, and a control module. The power topology module includes a first transistor Q1 and a second transistor Q2. The first terminal of the first transistor Q1 is connected to the second terminal of the second transistor Q2, and the second terminal of the first transistor Q1 is connected to the first terminal of the second transistor Q2. The signal processing module includes a first detection unit and a second detection unit.

[0099] The first terminal of the control module is connected to the control terminal of the first transistor Q1, and is used to send a first drive signal to the first transistor Q1 to control the first transistor Q1 to turn on;

[0100] The second terminal of the control module is connected to the control terminal of the second transistor Q2, and is used to send a first drive signal to the second transistor Q2 to control the second transistor Q2 to turn on;

[0101] The first terminal of the first detection unit is connected to the second terminal of the first transistor Q1, and the second terminal of the first detection unit is connected to the third terminal of the control module. It is used to collect the first voltage corresponding to the second terminal of the first transistor Q1 and send the first voltage to the control module.

[0102] The first terminal of the second detection unit is connected to the second terminal of the second transistor Q2, and the second terminal of the first detection unit is connected to the fourth terminal of the control module. It is used to collect the second voltage corresponding to the second terminal of the second transistor Q2 and send the second voltage to the control module.

[0103] The control module is used to perform thermal failure detection on the first transistor Q1 and / or the second transistor Q2 based on the first voltage and / or the second voltage, so as to determine whether the first transistor Q1 and / or the second transistor Q2 has thermal failure.

[0104] The control module is also used to activate a preset processing mechanism when the first transistor Q1 and / or the second transistor Q2 thermally fail.

[0105] Based on the scenario example, the control module can be selected as a Digital Signal Processor (DSP). A DSP is a programmable microprocessor designed specifically for real-time digital signal processing, possessing advantages such as high processing speed, low latency, and strong real-time performance. The first and second terminals of the control module can be the Pulse Width Modulation (PWM) interface of the DSP. The DSP emits a preset switching frequency through the PWM interface, for example, the switching frequency can be 20kHz. Therefore, the first drive signal sent by the DSP to the control terminal of the first transistor Q1 and the second drive signal sent to the control terminal of the second transistor Q2 can be a 20kHz switching frequency, so as to dynamically control the conduction of the first transistor Q1 or the second transistor Q2 according to the preset drive dead time.

[0106] Table 1 shows the timing information of the first and second drive signals in the example. As shown in Table 1, while the first drive signal controls the first transistor Q1 to turn on, the second drive signal controls the second transistor Q2 to turn off. Conversely, while the first drive signal controls the first transistor Q1 to turn off, the second drive signal controls the second transistor Q2 to turn on. Furthermore, there is a preset dead time between the on and off states of either the first transistor Q1 or the second transistor Q2 to prevent bridge arm shoot-through. Optionally, the preset dead time can be determined according to actual conditions and can be 1.5µs.

[0107] Table 1

[0108]

[0109] The first transistor Q1 and the second transistor Q2 can be SiC MOS. The first transistor Q1 and the second transistor Q2 alternately turn on and off with a preset dead time, converting the input DC voltage into a high-frequency square wave voltage to transfer energy to subsequent circuits. Both the first transistor Q1 and the second transistor Q2 include their respective body portions and diodes connected in parallel. The first terminal of the first transistor Q1 or the second transistor Q2 is the source of the SiC MOS, the second terminal is the drain of the SiC MOS, and the control terminal is the gate of the SiC MOS.

[0110] When the first transistor Q1 is turned on, the first voltage sampled by the first detection unit is the voltage at the drain of the first transistor Q1. If the first transistor Q1 is functioning normally, the freewheeling current flowing through it passes through the corresponding body portion of the transistor, resulting in a very small voltage drop. The voltage at the drain of the first transistor Q1 is typically no more than 0.5V, for example, it can be 0.15V. However, if the first transistor Q1 is malfunctioning, the freewheeling current flowing through it passes through the diode corresponding to it, resulting in a larger voltage drop. In this case, the voltage at the drain of the first transistor Q1 can reach approximately 5V.

[0111] Similarly, when the second transistor Q2 is turned on, the second voltage collected by the second detection unit is the voltage at the drain of the second transistor Q2. If the second transistor Q2 is functioning normally, the freewheeling current flowing through it passes through the corresponding body portion of the transistor, resulting in a very small voltage drop. The voltage at the drain of the second transistor Q2 is typically no more than 0.5V, for example, it can be 0.15V. However, if the second transistor Q2 is malfunctioning, the freewheeling current flowing through it passes through the diode corresponding to it, resulting in a larger voltage drop. In this case, the voltage at the drain of the second transistor Q2 can reach approximately 5V.

[0112] If the first voltage received by the control module is high multiple times consecutively, for example, if the first voltage received by the control module reaches 5V three times consecutively, then it can be determined that the first transistor Q1 is malfunctioning, and in this case, the first transistor Q1 is considered to have thermally failed. Similarly, if the second voltage received by the control module reaches 5V three times consecutively, then it can be determined that the second transistor Q2 is malfunctioning, and in this case, the second transistor Q2 is considered to have thermally failed.

[0113] For example, the preset processing mechanism could be to stop the output of the first drive signal and the second drive signal, or to report a system error via indicator lights. Therefore, when the first transistor Q1 and / or the second transistor Q2 thermally fail, the control module can stop the output of the first drive signal and the second drive signal, causing the first transistor Q1 and / or the second transistor Q2 to stop working. This is to prevent the first transistor Q1 and / or the second transistor Q2 from being damaged by overheating due to thermal failure.

[0114] Based on the thermal failure handling circuit provided in this example, the voltage at the second terminal of the first transistor and the voltage at the second terminal of the second transistor can be monitored in real time, so as to identify abnormal operating conditions of the first transistor and the second transistor in a timely manner, and to handle the abnormal operating conditions in a timely manner, thereby improving the stability and reliability of the system.

[0115] Optional, Figure 3 Schematic diagram of the thermal failure handling circuit provided in this application Figure 2 ,like Figure 3 As shown, the power topology module also includes: a first capacitor C1, a second capacitor C2, a third capacitor C3, and an inductor L;

[0116] The first terminal of the first capacitor C1 is connected to the first terminal of the first transistor Q1, the second terminal of the first capacitor C1 is connected to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 is connected to the second terminal of the second transistor Q2, for the purpose of stabilizing the voltage.

[0117] The first end of the inductor L is connected to the first end of the second transistor Q2, and the second end of the inductor L is connected to the first end of the third capacitor C3. It is used to charge the first transistor Q1 or the second transistor Q2 when it is turned on to store electrical energy, and to discharge the first transistor Q1 and the second transistor Q2 when they are turned off to release electrical energy.

[0118] The second terminal of the third capacitor C3 is grounded, and it is used to filter the voltage in the circuit.

[0119] In the example scenario, capacitors C1 and C2 serve as input support capacitors. On one hand, they can stabilize the input DC voltage and suppress voltage ripple on the input side. On the other hand, in a half-bridge topology, the input voltage can be evenly distributed. For example, when the input voltage is high, capacitors C1 and C2 each bear half of the input voltage, ensuring the stability of the voltage between them.

[0120] Inductor L is an energy storage / transfer element. When either the first transistor Q1 or the second transistor Q2 is turned on, inductor L "charges," storing energy and causing the current to rise. When both transistors Q1 and Q2 are turned off, inductor L "discharges," releasing energy and causing the current to decrease. Inductor L smooths the current and suppresses current ripple. Inductor L is typically paired with a third capacitor C3, which filters the voltage in the circuit to ensure voltage stability.

[0121] Optional, Figure 4 Schematic diagram of the thermal failure handling circuit provided in this application Figure 3 ,like Figure 4 As shown, the first detection unit includes a first power supply unit and a first acquisition unit, and the second detection unit includes a second power supply unit and a second acquisition unit.

[0122] The first terminal of the first power supply unit is connected to the second terminal of the first transistor Q1, and the second terminal of the first power supply unit is connected to the first terminal of the first acquisition unit, for providing operating voltage to the first acquisition unit.

[0123] The second end of the first acquisition unit is connected to the third end of the control module, and is used to acquire the first voltage corresponding to the second end of the first transistor Q1 and send the first voltage to the control module.

[0124] The first terminal of the second power supply unit is connected to the second terminal of the second transistor Q2, and the second terminal of the second power supply unit is connected to the first terminal of the second acquisition unit to provide operating voltage for the second acquisition unit.

[0125] The second terminal of the second acquisition unit is connected to the fourth terminal of the control module, and is used to acquire the second voltage corresponding to the second terminal of the second transistor Q2 and send the second voltage to the control module.

[0126] In a scenario example, the first power supply unit is connected to the drain of the first transistor Q1 to provide operating voltage to the first acquisition unit. The first acquisition unit, through the first power supply unit and the drain of the first transistor Q1, acquires the first voltage corresponding to the drain of the first transistor Q1. Similarly, the second power supply unit is connected to the drain of the second transistor Q2 to provide operating voltage to the second acquisition unit. The second acquisition unit, through the second power supply unit and the drain of the second transistor Q2, acquires the second voltage corresponding to the drain of the second transistor Q2.

[0127] Optional, Figure 5 Schematic diagram of the thermal failure handling circuit provided in this application Figure 4 ,like Figure 5 As shown, the first power supply unit includes a first diode D1, and the second power supply unit includes a second diode D2;

[0128] The first terminal of the first diode D1 is connected to the second terminal of the first transistor Q1, and the second terminal of the first diode D1 is connected to the first power supply VCC1 and the first terminal of the first acquisition unit, so as to provide the operating voltage of the first acquisition unit.

[0129] The first terminal of the second diode D2 is connected to the second terminal of the second transistor Q2, and the second terminal of the second diode D2 is connected to the second power supply VCC2 and the first terminal of the second acquisition unit, so as to provide the operating voltage for the second acquisition unit.

[0130] In the example scenario, the first terminal of the first diode D1 is connected to the drain of the first transistor Q1, and the second terminal of the first diode D1 is connected to the first power supply VCC1 and the first acquisition unit. The voltage of the first power supply VCC1 can be 15V. The source of the first transistor Q1 can be used as a virtual ground, and a 15V isolated power supply is formed between VCC1 and the source of the first transistor Q1 to provide the operating voltage to the first acquisition unit. When the first diode D1 is forward-biased, the first acquisition unit can acquire the drain voltage of the first transistor Q1 to obtain the corresponding first voltage.

[0131] Similarly, the first terminal of the second diode D2 is connected to the drain of the second transistor Q2, and the second terminal of the second diode D2 is connected to the second power supply VCC2 and the second acquisition unit. The voltage of the second power supply VCC2 is the same as the voltage of the first power supply VCC1, which can be 15V. The source of the second transistor Q2 can be used as a virtual ground, and VCC2 and the source of the second transistor Q2 form another 15V isolated power supply to provide the operating voltage to the second acquisition unit. When the second diode D2 is forward-biased, the second acquisition unit can acquire the drain voltage of the second transistor Q2 to obtain the corresponding second voltage.

[0132] Based on the current provided in this example, by constructing two independent power supplies to power the first acquisition unit and the second acquisition unit respectively, signal interference caused by the two acquisition units sharing a common ground can be avoided.

[0133] Optional, Figure 6 Schematic diagram of the thermal failure handling circuit provided in this application Figure 5 ,like Figure 6 As shown, the first power supply unit also includes a first resistor R1 and a second resistor R2, and the second power supply unit also includes a third resistor R3 and a fourth resistor R4.

[0134] The first end of the first resistor R1 is connected to the second end of the first diode D1, and the second end of the first resistor R1 is connected to the first power supply.

[0135] The first end of the second resistor R2 is connected to the first end of the first resistor R1, and the second end of the second resistor R2 is connected to the first end of the first acquisition unit. The first resistor R1 and the second resistor R2 are used to reduce the current value in the path.

[0136] The first end of the third resistor R3 is connected to the second end of the second diode D2, and the second end of the third resistor R3 is connected to the second power supply.

[0137] The first end of the fourth resistor R4 is connected to the first end of the third resistor R3, and the second end of the fourth resistor R4 is connected to the first end of the second acquisition unit. The third resistor R3 and the fourth resistor R4 are used to reduce the current value in their respective paths.

[0138] Based on the scenario example, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 can be determined according to the actual situation. They mainly play the role of current limiting in the circuit to prevent the main components in the circuit from being burned out due to excessive current.

[0139] Optional, Figure 7 Schematic diagram of the thermal failure handling circuit provided in this application Figure 6 ,like Figure 7 As shown, the first acquisition unit includes a fourth capacitor C4 and a first boost module, and the second acquisition unit includes a fifth capacitor C5 and a second boost module.

[0140] The first terminal of the first boost module is connected to the third power supply VCC3 and the third terminal of the control module. The second terminal of the first boost module is grounded. The third terminal of the first boost module is grounded and connected to the first terminal of the fourth capacitor C4. The fourth terminal of the first boost module is connected to the second terminal of the second resistor R2. This is used to boost the voltage at the second terminal of the first transistor Q1 to obtain the first voltage.

[0141] The second terminal of the fourth capacitor C4 is connected to the second terminal of the second resistor R2, and is used to filter the first voltage.

[0142] The first terminal of the second boost module is connected to the fourth power supply VCC4 and the fourth terminal of the control module. The second terminal of the second boost module is grounded. The third terminal of the second boost module is grounded and connected to the first terminal of the fifth capacitor C5. The fourth terminal of the second boost module is connected to the second terminal of the fourth resistor R4. This is used to boost the voltage at the second terminal of the second transistor Q2 to obtain the second voltage.

[0143] The second terminal of the fifth capacitor C5 is connected to the second terminal of the fourth resistor R4, and is used to filter the second voltage.

[0144] In the scenario example, the third power supply VCC3 and the fourth power supply VCC4 can be 3.3V, used to provide the operating voltage for the first or second boost module. As mentioned earlier, the voltage drop across the first transistor Q1 during normal conduction is very small, approximately 0.15V. However, the DSP control module has limited sampling resolution for "small signals," is susceptible to noise interference, and cannot accurately distinguish minute voltage differences. Therefore, if the sampled voltage at the drain of the first transistor Q1 is 0.15V, it can be boosted by the first boost module, for example, to 1.5V. This 1.5V is then used as the first voltage and transmitted to the control module. This allows the control module to clearly identify the difference between the normal conduction voltage drop (0.15V) and the abnormal diode conduction voltage drop (5V), improving the accuracy of anomaly detection. Conversely, if the sampled voltage at the drain of the first transistor Q1 is 5V, no boosting is necessary. Similarly, if the voltage of the drain of the second transistor Q2 is 0.15V, it can be boosted to 1.5V by the second boost module, and the 1.5V is then transmitted to the control module as the second voltage. In addition, if the voltage of the drain of the second transistor Q2 is 5V, there is no need to perform boosting.

[0145] The fourth capacitor C4 and the fifth capacitor C5 respectively filter the first voltage or the second voltage to improve the signal quality of the first voltage and the second voltage.

[0146] Optional, Figure 8 Schematic diagram of the thermal failure handling circuit provided in this application Figure 7 ,like Figure 8 As shown, the first boost module includes a third diode D3 and a first transistor Q3, and the second boost module includes a fourth diode D4 and a second transistor Q4;

[0147] The first terminal of the third diode D3 is grounded, the second terminal of the third diode D3 is connected to the second terminal of the second resistor R2, the first terminal of the first transistor Q3 is connected to the third power supply VCC3, the second terminal of the first transistor Q3 is grounded, and there is optocoupler isolation between the control terminal of the first transistor Q3 and the third diode D3.

[0148] The first terminal of the fourth diode D4 is grounded, the second terminal of the fourth diode D4 is connected to the second terminal of the fourth resistor R4, the first terminal of the second transistor Q4 is connected to the fourth power supply VCC4, the second terminal of the second transistor Q4 is grounded, and there is optical isolation between the control terminal of the second transistor Q4 and the fourth diode D4.

[0149] In the example scenario, diodes D3 and D4 prevent reverse current flow in the circuit. Transistors Q3 and Q4 are NPN transistors, with the first terminal being the collector, the second terminal the emitter, and the control terminal the base. The optocoupler isolation between the base of transistor Q3 and diode D3 isolates the control module from the first acquisition unit, preventing high-voltage signals acquired by the first acquisition unit from interfering with the control module. Similarly, the optocoupler isolation between the base of transistor Q4 and diode D4 isolates the control module from the second acquisition unit, preventing high-voltage signals acquired by the second acquisition unit from interfering with the control module.

[0150] Optional, Figure 9 Schematic diagram of the thermal failure handling circuit provided in this application Figure 8 ,like Figure 9 As shown, the first acquisition unit also includes a fifth resistor R5 and a sixth resistor R6, and the second acquisition unit also includes a seventh resistor R7 and an eighth resistor R8.

[0151] The first end of the fifth resistor R5 is connected to the third power supply VCC3, and the second end of the fifth resistor R5 is connected to the first end of the first transistor Q3, which is used to divide the voltage of the third power supply VCC3.

[0152] The first end of the sixth resistor R6 is connected to the second end of the third diode D3, and the second end of the sixth resistor R6 is connected to the second end of the second resistor R2, which is used to perform voltage division on the first voltage.

[0153] The first end of the seventh resistor R7 is connected to the fourth power supply VCC4, and the second end of the seventh resistor R7 is connected to the first end of the second transistor Q4, which is used to divide the voltage of the fourth power supply VCC4.

[0154] The first end of the eighth resistor R8 is connected to the second end of the fourth diode D4, and the second end of the eighth resistor R8 is connected to the second end of the fourth resistor R4, which is used to perform voltage division on the second voltage.

[0155] Based on the scenario example, the resistance values ​​of the fifth resistor R5, sixth resistor R6, seventh resistor R7, and eighth resistor R8 can be determined according to the actual situation. Their main function in the circuit is voltage division to prevent excessively high voltages from being transmitted to the control module. For example, if the first transistor Q1 malfunctions, the measured drain voltage of Q1 will be 5V, while the voltage range that the control module DSP can withstand is typically no more than 3.3V. Therefore, the sixth resistor R6 can be used to divide the drain voltage of the first transistor Q1 to a certain extent to match the DSP's tolerance range. Similarly, if the second transistor Q2 malfunctions, and the measured drain voltage of Q2 is 5V, the eighth resistor R8 can be used to divide the drain voltage of Q2 to a certain extent to match the DSP's tolerance range.

[0156] Based on the thermal failure handling circuit provided in this embodiment, the voltage at the second terminal of the first transistor and the voltage at the second terminal of the second transistor can be monitored in real time to achieve the purpose of real-time monitoring of the operating conditions of the first transistor and the second transistor. Abnormal operating conditions of the first transistor and the second transistor can be identified in a timely manner and handled in a timely manner to improve the stability and reliability of the system.

[0157] Figure 10 This is a flowchart illustrating the thermal failure handling method provided in this application. The thermal failure handling method is applied to a thermal failure handling circuit, which includes a power topology module, a signal processing module, and a control module. The power topology module includes a first transistor and a second transistor, with a first terminal of the first transistor connected to a second terminal of the second transistor, and a second terminal of the first transistor connected to a first terminal of the second transistor. The signal processing module includes a first detection unit and a second detection unit. Figure 10 As shown, the method includes:

[0158] S1001. Obtain the first voltage collected by the first detection unit, wherein the first voltage is the voltage corresponding to the second terminal of the first transistor.

[0159] Based on the scenario example, the execution subject of this method embodiment can be the control module in the thermal failure handling circuit, i.e., the DSP.

[0160] As described above, the first transistor Q1 and the second transistor Q2 can be SiC MOS transistors. The first transistor Q1 and the second transistor Q2 alternately turn on and off with a preset dead time, converting the input DC voltage into a high-frequency square wave voltage to transfer energy to subsequent circuits. Both the first transistor Q1 and the second transistor Q2 include their respective body portions and diodes connected in parallel. The first terminal of the first transistor Q1 or the second transistor Q2 is the source of the SiC MOS transistor, the second terminal is the drain of the SiC MOS transistor, and the control terminal is the gate of the SiC MOS transistor.

[0161] When the first transistor Q1 is turned on, the first voltage sampled by the first detection unit is the voltage at the drain of the first transistor Q1. If the first transistor Q1 is functioning normally, the freewheeling current flowing through it passes through the corresponding body portion of the transistor, resulting in a very small voltage drop. The voltage at the drain of the first transistor Q1 is typically no more than 0.5V, for example, it can be 0.15V. However, if the first transistor Q1 is malfunctioning, the freewheeling current flowing through it passes through the diode corresponding to it, resulting in a larger voltage drop. In this case, the voltage at the drain of the first transistor Q1 can reach approximately 5V.

[0162] S1002. Obtain the second voltage collected by the second detection unit, wherein the second voltage is the voltage corresponding to the second terminal of the second transistor.

[0163] In the scenario example, when the second transistor Q2 is turned on, the second voltage collected by the second detection unit is the voltage at the drain of the second transistor Q2. If the second transistor Q2 is functioning normally, the freewheeling current flowing through it passes through the corresponding body portion of the transistor, resulting in a very small voltage drop. The voltage at the drain of the second transistor Q2 is typically no more than 0.5V, for example, it can be 0.15V. However, if the second transistor Q2 is malfunctioning, the freewheeling current flowing through it passes through the diode corresponding to it, resulting in a larger voltage drop. In this case, the voltage at the drain of the second transistor Q2 can reach approximately 5V.

[0164] S1003. Based on the first voltage and / or the second voltage, perform thermal failure detection on the first transistor and / or the second transistor to determine whether the first transistor and / or the second transistor has thermal failure.

[0165] Based on the scenario example, if the first voltage received by the control module is high multiple times consecutively, for example, if the first voltage received by the control module reaches 5V three times consecutively, then it can be determined that the first transistor Q1 is abnormal, and in this case, the first transistor Q1 can be determined to have thermal failure. Similarly, if the second voltage received by the control module reaches 5V three times consecutively, then it can be determined that the second transistor Q2 is abnormal, and in this case, the second transistor Q2 can be determined to have thermal failure.

[0166] S1004. When the first transistor and / or the second transistor thermally fail, a preset processing mechanism is activated.

[0167] Based on the scenario example, the preset processing mechanism can be to stop one transistor Q1 and / or the second transistor Q2 from operating, or to report a system error through indicator lights, etc.

[0168] Based on the thermal failure handling method provided in this embodiment, the voltage at the second terminal of the first transistor and the voltage at the second terminal of the second transistor can be monitored in real time, so as to identify the abnormal operating conditions of the first transistor and the second transistor in a timely manner, and to handle the abnormal operating conditions in a timely manner, thereby improving the stability and reliability of the system.

[0169] Figure 11 A schematic diagram of the structure of the electronic device provided in this application. Figure 11 As shown, the electronic device 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the electronic device 50 further includes a communication component 503. The processor 501, memory 502, and communication component 503 are connected via a bus.

[0170] In a specific implementation, at least one processor 501 executes computer execution instructions stored in memory 502, causing at least one processor 501 to perform the above-described method.

[0171] The specific implementation process of processor 501 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0172] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0173] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0174] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0175] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described embodiments of the device identifier update method when running.

[0176] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0177] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the device identifier update method embodiments described above.

[0178] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described device identifier update method embodiments.

[0179] It should be noted that the division of units is merely a logical functional division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0180] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0181] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0182] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0183] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0184] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0185] It should be understood that the above-described device embodiments are merely illustrative, and the device of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation.

[0186] The foregoing has provided a detailed description of a device identification update system, method, electronic device, medium, and product provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A thermal failure handling circuit, characterized in that, The thermal failure handling circuit includes: a power topology module, a signal processing module, and a control module. The power topology module includes a first transistor (Q1) and a second transistor (Q2). A first terminal of the first transistor (Q1) is connected to a second terminal of the second transistor (Q2), and a second terminal of the first transistor (Q1) is connected to a first terminal of the second transistor (Q2). The signal processing module includes a first detection unit and a second detection unit. The first terminal of the control module is connected to the control terminal of the first transistor (Q1) and is used to send a first drive signal to the first transistor (Q1) to control the first transistor (Q1) to turn on. The second terminal of the control module is connected to the control terminal of the second transistor (Q2) and is used to send a first drive signal to the second transistor (Q2) to control the second transistor (Q2) to turn on; The first terminal of the first detection unit is connected to the second terminal of the first transistor (Q1), and the second terminal of the first detection unit is connected to the third terminal of the control module. It is used to collect the first voltage corresponding to the second terminal of the first transistor (Q1) and send the first voltage to the control module. The first terminal of the second detection unit is connected to the second terminal of the second transistor (Q2), and the second terminal of the first detection unit is connected to the fourth terminal of the control module. It is used to collect the second voltage corresponding to the second terminal of the second transistor (Q2) and send the second voltage to the control module. The control module is used to perform thermal failure detection on the first transistor (Q1) and / or the second transistor (Q2) based on the first voltage and / or the second voltage, so as to determine whether the first transistor (Q1) and / or the second transistor (Q2) has thermal failure; The control module is also used to activate a preset processing mechanism when the first transistor (Q1) and / or the second transistor (Q2) thermally fail.

2. The circuit according to claim 1, characterized in that, The power topology module also includes: a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), and an inductor (L); The first terminal of the first capacitor (C1) is connected to the first terminal of the first transistor (Q1), the second terminal of the first capacitor (C1) is connected to the first terminal of the second capacitor (C2), and the second terminal of the second capacitor (C2) is connected to the second terminal of the second transistor (Q2) for stabilizing the voltage. The first end of the inductor (L) is connected to the first end of the second transistor (Q2), and the second end of the inductor (L) is connected to the first end of the third capacitor (C3). The inductor is used to charge the capacitor to store electrical energy when the first transistor (Q1) or the second transistor (Q2) is turned on, and to discharge the capacitor to release electrical energy when the first transistor (Q1) and the second transistor (Q2) are turned off. The second terminal of the third capacitor (C3) is grounded and used to filter the voltage in the circuit.

3. The circuit according to claim 2, characterized in that, The first detection unit includes a first power supply unit and a first acquisition unit, and the second detection unit includes a second power supply unit and a second acquisition unit; The first terminal of the first power supply unit is connected to the second terminal of the first transistor (Q1), and the second terminal of the first power supply unit is connected to the first terminal of the first acquisition unit, for providing operating voltage to the first acquisition unit; The second end of the first acquisition unit is connected to the third end of the control module, and is used to acquire the first voltage corresponding to the second end of the first transistor (Q1) and send the first voltage to the control module; The first terminal of the second power supply unit is connected to the second terminal of the second transistor (Q2), and the second terminal of the second power supply unit is connected to the first terminal of the second acquisition unit, for providing operating voltage to the second acquisition unit; The second terminal of the second acquisition unit is connected to the fourth terminal of the control module, and is used to acquire the second voltage corresponding to the second terminal of the second transistor (Q2) and send the second voltage to the control module.

4. The circuit according to claim 3, characterized in that, The first power supply unit includes a first diode (D1), and the second power supply unit includes a second diode (D2). The first terminal of the first diode (D1) is connected to the second terminal of the first transistor (Q1), and the second terminal of the first diode (D1) is connected to the first power supply (VCC1) and the first terminal of the first acquisition unit to provide operating voltage for the first acquisition unit. The first terminal of the second diode (D2) is connected to the second terminal of the second transistor (Q2), and the second terminal of the second diode (D2) is connected to the second power supply (VCC2) and the first terminal of the second acquisition unit to provide operating voltage for the second acquisition unit.

5. The circuit according to claim 4, characterized in that, The first power supply unit further includes a first resistor (R1) and a second resistor (R2), and the second power supply unit further includes a third resistor (R3) and a fourth resistor (R4). The first end of the first resistor (R1) is connected to the second end of the first diode (D1), and the second end of the first resistor (R1) is connected to the first power supply (VCC1). The first end of the second resistor (R2) is connected to the first end of the first resistor (R1), and the second end of the second resistor (R2) is connected to the first end of the first acquisition unit. The first resistor (R1) and the second resistor (R2) are used to reduce the current value in the path. The first end of the third resistor (R3) is connected to the second end of the second diode (D2), and the second end of the third resistor (R3) is connected to the second power supply (VCC2). The first end of the fourth resistor (R4) is connected to the first end of the third resistor (R3), and the second end of the fourth resistor (R4) is connected to the first end of the second acquisition unit. The third resistor (R3) and the fourth resistor (R4) are used to reduce the current value in the corresponding path.

6. The circuit according to claim 5, characterized in that, The first acquisition unit includes a fourth capacitor (C4) and a first boost module, and the second acquisition unit includes a fifth capacitor (C5) and a second boost module; The first terminal of the first boost module is connected to the third power supply (VCC3) and the third terminal of the control module. The second terminal of the first boost module is grounded. The third terminal of the first boost module is grounded and connected to the first terminal of the fourth capacitor (C4). The fourth terminal of the first boost module is connected to the second terminal of the second resistor (R2). This is used to boost the voltage at the second terminal of the first transistor (Q1) to obtain the first voltage. The second terminal of the fourth capacitor (C4) is connected to the second terminal of the second resistor (R2) for filtering the first voltage; The first terminal of the second boost module is connected to the fourth power supply (VCC4) and the fourth terminal of the control module. The second terminal of the second boost module is grounded. The third terminal of the second boost module is grounded and connected to the first terminal of the fifth capacitor (C5). The fourth terminal of the second boost module is connected to the second terminal of the fourth resistor (R4). This is used to boost the voltage at the second terminal of the second transistor (Q2) to obtain the second voltage. The second terminal of the fifth capacitor (C5) is connected to the second terminal of the fourth resistor (R4) for filtering the second voltage.

7. The circuit according to claim 6, characterized in that, The first boost module includes a third diode (D3) and a first transistor (Q3), and the second boost module includes a fourth diode (D4) and a second transistor (Q4). The first terminal of the third diode (D3) is grounded, the second terminal of the third diode (D3) is connected to the second terminal of the second resistor (R2), the first terminal of the first transistor (Q3) is connected to the third power supply (VCC3), the second terminal of the first transistor (Q3) is grounded, and there is optical isolation between the control terminal of the first transistor (Q3) and the third diode (D3). The first terminal of the fourth diode (D4) is grounded, the second terminal of the fourth diode (D4) is connected to the second terminal of the fourth resistor (R4), the first terminal of the second transistor (Q4) is connected to the fourth power supply (VCC4), the second terminal of the second transistor (Q4) is grounded, and there is optical isolation between the control terminal of the second transistor (Q4) and the fourth diode (D4).

8. The circuit according to claim 7, characterized in that, The first acquisition unit further includes a fifth resistor (R5) and a sixth resistor (R6), and the second acquisition unit further includes a seventh resistor (R7) and an eighth resistor (R8). The first end of the fifth resistor (R5) is connected to the third power supply (VCC3), and the second end of the fifth resistor (R5) is connected to the first end of the first transistor (Q3), which is used to divide the voltage of the third power supply (VCC3). The first end of the sixth resistor (R6) is connected to the second end of the third diode (D3), and the second end of the sixth resistor (R6) is connected to the second end of the second resistor (R2), for voltage division of the first voltage; The first end of the seventh resistor (R7) is connected to the fourth power supply (VCC4), and the second end of the seventh resistor (R7) is connected to the first end of the second transistor (Q4), which is used to divide the voltage of the fourth power supply (VCC4). The first end of the eighth resistor (R8) is connected to the second end of the fourth diode (D4), and the second end of the eighth resistor (R8) is connected to the second end of the fourth resistor (R4) to perform voltage division on the second voltage.

9. A method for handling thermal failure, characterized in that, An application is made to the thermal failure handling circuit according to any one of claims 1-8, wherein the thermal failure handling circuit comprises: a power topology module, a signal processing module, and a control module, wherein the power topology module comprises a first transistor (Q1) and a second transistor (Q2), a first terminal of the first transistor (Q1) is connected to a second terminal of the second transistor (Q2), and a second terminal of the first transistor (Q1) is connected to a first terminal of the second transistor (Q2), and the signal processing module comprises a first detection unit and a second detection unit; the method comprises: The first voltage collected by the first detection unit is obtained, wherein the first voltage is the voltage corresponding to the second terminal of the first transistor (Q1); The second voltage collected by the second detection unit is obtained, wherein the second voltage is the voltage corresponding to the second terminal of the second transistor (Q2); Based on the first voltage and / or the second voltage, thermal failure detection is performed on the first transistor (Q1) and / or the second transistor (Q2) to determine whether the first transistor (Q1) and / or the second transistor (Q2) have thermal failure. When the first transistor (Q1) and / or the second transistor (Q2) thermally fail, a preset processing mechanism is activated.

10. An electronic device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the thermal failure handling method as described in claim 9.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the thermal failure handling method as described in claim 9.

12. A computer program product, characterized in that, Includes a computer program, which, when executed by a processor, is used to implement the thermal failure handling method as described in claim 9.

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