Chip testing circuit, system and chip
By dividing the chip into multiple scan test zones and setting corresponding scan clock signal transmission circuits, the problem of insufficient scan test clock frequency of the SCAN circuit is solved, and efficient chip testing is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI BIREN TECH CO LTD
- Filing Date
- 2026-04-10
- Publication Date
- 2026-06-12
AI Technical Summary
The existing SCAN circuit cannot achieve a high scan test clock frequency during scan testing, resulting in a long scan test time and reduced chip testing efficiency.
The chip is divided into multiple scan test zones, and a corresponding scan clock signal transmission circuit is set up for each zone. The scan clock signal input port is placed close to the scan test module, the scan clock signal transmission path is optimized, and a high scan clock frequency is ensured.
It significantly reduces the transmission delay of the scan clock signal, increases the scan test clock frequency, shortens the SCAN test time, and improves chip testing efficiency.
Smart Images
Figure CN122193887A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of artificial intelligence chip technology, and in particular to a chip testing circuit, a chip testing system, and a chip. Background Technology
[0002] In chip manufacturing, SCAN-based testing is typically required to detect defects introduced during the manufacturing process. As chips become larger, the number of registers in the scan chain also increases. The time it takes for chip test data to move from the chip's I / O ports to all registers in the scan chain is related to the scan chain length and the scan test clock frequency. However, existing SCAN circuits cannot achieve high scan test clock frequencies during scan testing, resulting in longer SCAN test times and reduced chip testing efficiency. Summary of the Invention
[0003] This invention provides a chip testing circuit, system, and chip to solve the technical problem in related technologies where the SCAN circuit cannot achieve a high scanning test clock frequency during scanning testing, resulting in a long SCAN test time.
[0004] To address the aforementioned technical problems, a first aspect of the present invention provides a chip testing circuit, comprising at least one chip scanning test partition and at least one scanning clock signal transmission circuit corresponding to the chip scanning test partition; at least one scanning test module is provided within the chip scanning test partition; The scanning clock signal input port of the scanning clock signal transmission circuit is positioned close to the scanning test module; the scanning clock signal transmission circuit is used to receive the scanning clock signal through the scanning clock signal input port and output it to the scanning test module.
[0005] As a preferred embodiment, the scanning test module includes a data input port, a data output port, and multiple registers; the multiple registers are connected sequentially to form a scanning test link; the first-level register on the scanning test link is connected to the data input port, and the last-level register on the scanning test link is connected to the data output port; The data input port is used to receive test excitation signals and transmit them to the scan test link; the data output port is used to receive test feedback signals from the scan test link and feed them back to the test host; the output of the scan clock signal transmission circuit is connected to the clock signal input of each of the registers respectively.
[0006] As a preferred embodiment, the first-stage register is positioned close to the data input port, and the last-stage register is positioned close to the data output port.
[0007] As a preferred embodiment, the chip scanning test partition is determined based on the distance between the various scanning test modules located within the same chip.
[0008] As a preferred embodiment, when at least two scanning test modules are provided in the chip scanning test partition, the setting position of the scanning clock signal input port is determined based on the transmission delay of the scanning clock signal from the scanning clock signal input port to each of the scanning test modules in the corresponding chip scanning test partition.
[0009] As a preferred embodiment, the plurality of registers includes at least two beat registers and a plurality of scan registers; the plurality of scan registers are connected between any two of the beat registers; the first-level register and the last-level register are both beat registers.
[0010] As a preferred embodiment, when at least two scanning test modules are provided in the chip scanning test partition, and at least one scanning clock signal transmission circuit is connected to at least two scanning test modules respectively, the scanning clock signal input port is connected to the clock signal input terminal of the last stage register of the at least two connected scanning test modules through a clock tree synthesis CTS buffer.
[0011] As a preferred embodiment, each of the scanning clock signal transmission circuits corresponding to the chip scanning test partition corresponds one-to-one with each of the scanning test modules set within the chip scanning test partition.
[0012] A second aspect of the present invention provides a chip testing system, including a test host and a chip testing circuit as described in any of the first aspects; the scan clock signal output terminal of the test host is connected to the scan clock signal input port in the chip testing circuit, and the test excitation signal output port and the test feedback signal input port of the test host are respectively connected to the scan test module in the chip testing circuit.
[0013] A third aspect of the present invention provides a chip, including a chip test circuit as described in any of the first aspects.
[0014] The beneficial effect of this invention is that by setting at least one corresponding scan clock signal transmission circuit for each chip scan test partition, and setting the scan clock signal input port of the scan clock signal transmission circuit close to the scan test module in the chip scan test partition, the distance from the scan clock signal input port to the scan test module can be significantly reduced, effectively reducing the scan clock signal transmission delay from the scan clock signal input port to the scan test module, thereby ensuring a high scan test clock frequency, shortening the SCAN test time and improving chip test efficiency. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of the connection structure of the chip testing circuit in an embodiment of the present invention; Figure 2 This is a schematic diagram of the chip scanning test partition of the chip test circuit in an embodiment of the present invention; Figure 3 This is a schematic diagram showing how the scan clock signal input port in this embodiment of the invention is connected to the clock signal input terminal of the last-stage register of each connected scan test module through a CTS buffer. Figure 4 This is a schematic diagram of the connection structure of the chip testing system in an embodiment of the present invention; Among them, 100 is the scan clock signal transmission circuit; 101 is the scan clock signal input port; 200 is the scan test module; 201 is the data input port; 202 is the data output port; 203 is the scan register; 204 is the stamping register; 300 is the CTS buffer; and 400 is the test host. Detailed Implementation
[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0017] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "connected" should be interpreted broadly. "Connected" or "connected" in circuit structures can refer not only to physical connections but also to electrical or signal connections. For example, it can be a direct connection (physical connection) or an indirect connection through at least one intermediate component, as long as the circuit is connected. It can also refer to the internal connection between two components. Signal connections can refer to connections through circuits or through media, such as radio waves. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the use of the modifier "multiple" in this application is illustrative rather than restrictive. Those skilled in the art should understand that, unless explicitly stated in the context, "multiple" should be understood as two or more.
[0018] Please see Figure 1 The first aspect of the present invention provides a chip testing circuit, including at least one chip scanning test partition and at least one scanning clock signal transmission circuit 100 corresponding to the chip scanning test partition; at least one scanning test module 200 is provided in the chip scanning test partition; The scanning clock signal input port 101 of the scanning clock signal transmission circuit 100 is set close to the scanning test module 200; the scanning clock signal transmission circuit 100 is used to receive the scanning clock signal through the scanning clock signal input port 101 and output it to the scanning test module 200.
[0019] It is worth noting that a chip can be viewed as a collection of combinational logic between a large number of registers. The chip scan test treats these registers as scan cells, and then strings all the scan cells together into a scan chain. By inputting test stimulus signals into these scan chains, the test feedback signals output by these scan chains are compared with the test stimulus signals. If they are the same, it indicates that the scan test has passed. If they are different, it indicates that there is an open circuit or short circuit in the scan chain, that is, some registers have failed, in order to complete the logic test of the chip.
[0020] In related technologies, the scan clock signal input port 101 in the SCAN circuit is usually located in a corner of the chip, while the IO ports (Input / Output Ports) that serve as the chip's SCAN test channel are scattered around the chip. Since each IO port corresponds to a different logic module under test, the physical distance between the scan clock signal input port 101 and some IO ports is too long, resulting in significant delays and making it difficult to achieve a high scan clock frequency. This limits the upper limit of the scan clock frequency and consequently leads to a long SCAN test time. To address the shortcomings of related technologies, this embodiment first divides the chip into at least one chip scan test partition, and assigns at least one scan clock signal transmission circuit 100 to each chip scan test partition. Each chip scan test partition contains at least one scan test module 200, and each scan test module 200 corresponds to a logic module under test (tile). This ensures that each scan test module 200 within the chip scan test partition is equipped with a similar scan clock signal transmission circuit 100 to complete the scan test process, ensuring that the scan clock signal transmission path is not too long and thus shortening the scan clock signal transmission delay.
[0021] Furthermore, this embodiment specifies that the scan clock signal input port 101 of the scan clock signal transmission circuit 100 is positioned close to the scan test module 200. It is understood that since the scan clock signal input port 101 is used to receive the scan clock signal, its proximity to the scan test module 200 further ensures a shorter scan clock signal transmission path from the scan clock signal input port 101 to the scan test module 200, thereby increasing the scan clock signal frequency of each scan test module 200 during the scan test process. For example, this embodiment can pre-set a distance threshold, ensuring that the distance between the scan clock signal input port 101 and the scan test module 200 is less than this distance threshold when setting the scan clock signal input port 101, thus achieving the goal of positioning the scan clock signal input port 101 close to the scan test module 200. It is worth noting that, due to the different delays per unit distance under different chip manufacturing processes, the achievable scan clock signal frequencies are different. Therefore, this embodiment does not limit the above-mentioned distance threshold and the distance between the scan clock signal input port 101 and the scan test module 200. The distance threshold and the distance between the scan clock signal input port 101 and the scan test module 200 can be set according to the actual scan clock signal frequency requirements.
[0022] Understandably, during the scan test, the shifting of the test stimulus signal in the scan chain needs to be triggered by the scan clock signal. If the scan clock signal frequency is low, each scan clock cycle will be long, which will affect the waiting time required for each shift of the test stimulus signal in the scan chain. Therefore, by increasing the scan clock signal frequency, the waiting time required for each shift of the test stimulus signal in the scan chain can be reduced, thereby improving the output efficiency of the test feedback signal and shortening the SCAN test time.
[0023] The chip testing circuit provided in this embodiment of the invention, by setting at least one corresponding scan clock signal transmission circuit 100 for each chip scan test partition, and setting the scan clock signal input port 101 of the scan clock signal transmission circuit 100 close to the scan test module 200 in the chip scan test partition, can significantly reduce the distance from the scan clock signal input port 101 to the scan test module 200, effectively reduce the scan clock signal transmission delay from the scan clock signal input port 101 to the scan test module 200, thereby ensuring a high scan test clock frequency, shortening the SCAN test time and improving chip testing efficiency.
[0024] As a preferred embodiment, the scanning test module 200 includes a data input port 201, a data output port 202, and multiple registers; the multiple registers are connected in sequence to form a scanning test link; the first-level register on the scanning test link is connected to the data input port 201, and the last-level register on the scanning test link is connected to the data output port 202. The data input port 201 is used to receive the test excitation signal and transmit it to the scan test link; the data output port 202 is used to receive the test feedback signal from the scan test link and feed it back to the test host 400; the output terminal of the scan clock signal transmission circuit 100 is connected to the clock signal input terminal of each of the registers respectively.
[0025] Specifically, the scan test module 200 in this embodiment further includes a data input port 201, a data output port 202, and multiple registers. It is worth noting that registers are components in the chip used to store binary code. In this embodiment, multiple registers are connected sequentially to form a scan test link. For example, all registers in the chip can be connected sequentially to form a long scan test link. In this case, the chip test circuit only includes one chip scan test partition, and the chip scan test partition only includes one scan test module 200. Alternatively, the chip can be divided into multiple logic modules, and the registers in each logic module can be connected sequentially to form a short scan test link.
[0026] Preferably, this embodiment divides the chip into multiple logic modules and further divides these logic modules into multiple chip scan test partitions. This shortens the length of the scan test link in the scan test module 200, thereby reducing the scan test time for that module. Furthermore, by adding a scan clock signal transmission circuit 100 to each chip scan test partition, this embodiment ensures that the scan clock signal input port 101 is closer to the scan test module 200 within the same chip scan test partition, resulting in less scan clock signal transmission delay. Moreover, different scan clock signal transmission circuits 100 allow for parallel scanning tests of different chip scan test partitions, further reducing the chip scan test time. Figure 2 As shown, Figure 2 The system comprises four chip scanning test zones. Each chip scanning test zone is equipped with a scanning clock signal transmission circuit 100 and a scanning test module 200. Since the scanning clock signal input port 101 of each scanning clock signal transmission circuit 100 is set close to the scanning test module 200 in the corresponding chip scanning test zone, the scanning clock signal transmission path corresponding to each scanning test module 200 is shorter. This ensures that the scanning clock signal transmission delay of each scanning test module 200 during the scanning test is small, and a higher scanning test clock frequency can be achieved.
[0027] It is worth noting that, when considering the distance between the scan clock signal input port 101 and the scan test module 200, the clock signal input port 101 can be moved closer to the scan test module 200 by setting the distance between the scan clock signal input port 101 and the data input port 201 of the scan test module 200 to be less than a preset distance threshold; alternatively, the clock signal input port 101 can be moved closer to the scan test module 200 by setting the distance between the scan clock signal input port 101 and the data output port 202 of the scan test module 200 to be less than a preset distance threshold; or alternatively, the clock signal input port 101 can be moved closer to the scan test module 200 by setting the distance between the scan clock signal input port 101 and the registers in the scan test module 200 to be less than a preset distance threshold. This embodiment does not impose any specific limitations on these limitations.
[0028] During the scan test, the test stimulus signal is accessed through the data input port 201 and transmitted to the first-level register on the scan test link. Then, under the periodic transmission of the scan clock signal, the test stimulus signal is sequentially shifted from the first-level register into all registers of the scan test link. Meanwhile, the test feedback signal is shifted out from the last-level register on the scan test link and fed back to the test host 400 through the data output port 202 to verify the scan test results. For example, assuming the high / low level value represented by the test excitation signal is 1101, in the scan test state, the first bit "1" is input to the first-level register in the first scan clock cycle; in the second scan clock cycle, the bit "1" stored in the first-level register is shifted to the second-level register, and the second bit "0" is input to the first-level register; in the third scan clock cycle, the bit "1" stored in the second-level register is shifted to the third-level register, the bit "0" stored in the first-level register is shifted to the second-level register, and the third bit "1" is input to the first-level register; in the fourth scan clock cycle, the bit "1" stored in the third-level register is shifted to the fourth-level register, the bit "0" stored in the second-level register is shifted to the third-level register, the bit "1" stored in the first-level register is shifted to the second-level register, and the fourth bit "1" is input to the first-level register, thereby serially shifting the test excitation signal into the scan test link.
[0029] As a preferred embodiment, the first-level register is configured near the data input port 201, and the last-level register is configured near the data output port 202.
[0030] Specifically, since the test excitation signal is moved into the first-stage register from the data input port 201, and the test feedback signal is moved out from the last-stage register to the data output port 202, the distance between the first-stage register and the data input port 201 directly affects the delay of the test excitation signal moving into the scan test link, and the distance between the last-stage register and the data output port 202 directly affects the delay of the test feedback signal being fed back to the test host 400, thus affecting the scan test efficiency. Therefore, this embodiment further limits the first-stage register to be set close to the data input port 201, so that the data input port 201 can move the test stimulus signal into the first-stage register with the shortest transmission path, reducing the delay of the test stimulus signal moving into the scan test link; while the last-stage register is set close to the data output port 202, so that the last-stage register can transmit the test feedback signal to the data output port 202 with the shortest transmission path, reducing the delay of the test feedback signal feeding back to the test host 400, thereby further shortening the scan test time and improving the scan test efficiency. Moreover, the smaller the delay of the test stimulus signal moving into the scan test link and the delay of the test feedback signal feeding back to the test host 400, the higher the upper limit of the allowed scan test clock frequency.
[0031] For example, in this embodiment, a distance threshold can be preset. By setting the distance between the first-level register and the data input port 201, and the distance between the last-level register and the data output port 202, both are less than this distance threshold, so that the first-level register is set closer to the data input port 201, and the last-level register is set closer to the data output port 202. Since the delay per unit distance varies under different chip manufacturing processes, this embodiment does not specifically limit the distance threshold, which can be set according to the actual scanning test efficiency requirements.
[0032] As a preferred embodiment, the chip scanning test partition is determined based on the distance between the various scanning test modules 200 located within the same chip.
[0033] Specifically, considering that the length of the data transmission path limits the upper limit of the scan test clock frequency, in order to ensure a high scan test clock frequency for each scan test module 200 within the same chip scan test partition, the distance between each scan test module 200 needs to be considered when dividing multiple logic modules within the same chip into chip scan test partitions. It is understandable that if at least two scan test modules 200 are far apart within the same chip scan test partition, and due to limitations in chip manufacturing costs and the number of chip ports, only one scan clock signal transmission circuit 100 can be configured in that chip scan test partition, then when the scan clock signal input port 101 is set near one of the at least two far apart scan test modules 200, it will inevitably be far from the other scan test modules 200, thus failing to achieve a high scan test clock frequency. Therefore, this embodiment needs to ensure that the distance between each scan test module 200 within the same chip scan test partition is short, to ensure that the scan clock signal transmission delay from the corresponding scan clock signal input port 101 to each scan test module 200 is small.
[0034] For example, for the division of chip scanning test partitions, a distance threshold can be preset. The chip scanning test partitions can be divided by limiting the distance between each scanning test module 200 in the partitioned area to be less than the distance threshold. Alternatively, a clustering algorithm can be used to cluster the position information of each scanning test module 200 to achieve the division of chip scanning test partitions. This embodiment does not make specific limitations here.
[0035] It is worth noting that since the number of registers included in different scan test modules 200 is different, the distance between each scan test module 200 can be determined based on the distance between the input and output ports. For example, the distance between data input ports 201 can be used as the distance between scan test modules 200, or the distance between data output ports 202 can be used as the distance between scan test modules 200. This embodiment does not make specific limitations here.
[0036] As a preferred embodiment, when at least two scanning test modules 200 are provided in the chip scanning test partition, the setting position of the scanning clock signal input port 101 is determined based on the transmission delay of the scanning clock signal from the scanning clock signal input port 101 to each of the scanning test modules 200 in the corresponding chip scanning test partition.
[0037] It is worth noting that, given limitations in chip manufacturing costs or the number of chip ports, there may be a situation where one scan clock signal input port 101 corresponds to at least two scan test modules 200 within the chip scan test partition. To ensure a high scan test clock frequency, the setting of the scan clock signal input port 101 needs to consider the scan clock signal transmission delay of each scan test module 200. Specifically, for the scan clock signal input port 101 corresponding to at least two scan test modules 200, its setting position must ensure that the scan clock signal transmission delay from the scan clock signal input port 101 to each scan test module 200 is as consistent as possible. This can be achieved by pre-setting a delay difference threshold, and using the setting position where the difference between the scan clock signal transmission delay from the scan clock signal input port 101 to each scan test module 200 is less than this delay difference threshold as the target setting position for the scan clock signal input port 101. By determining the setting position of the scan clock signal input port 101 with the goal of ensuring that the transmission delay of the scan clock signal from the scan clock signal input port 101 to each scan test module 200 is as consistent as possible, it is possible to ensure that the scan test clock frequency of each scan test module 200 corresponding to the scan clock signal input port 101 is high. This avoids the scan test clock frequency of one scan test module 200 being low due to a high transmission delay of the scan clock signal from the scan clock signal input port 101 to that scan test module 200, and also limits the scan test clock frequency of the other scan test modules 200.
[0038] It is worth noting that since the scan clock signal transmission circuit 100 is used to transmit the scan clock signal to the registers in the scan test module 200, the transmission delay of the scan clock signal from the scan clock signal input port 101 to the scan test module 200 can be the transmission delay of the scan clock signal from the scan clock signal input port 101 to the registers in the scan test module 200. For example, it can be the transmission delay of the scan clock signal from the scan clock signal input port 101 to the first-level register of the scan test link in the scan test module 200, that is, the time difference between the time when the test host 400 sends the scan clock signal and the time when the clock signal input terminal of the first-level register receives the scan clock signal; it can also be the transmission delay of the scan clock signal from the scan clock signal input port 101 to the last-level register of the scan test link in the scan test module 200, that is, the time difference between the time when the test host 400 sends the scan clock signal and the time when the clock signal input terminal of the last-level register receives the scan clock signal. This embodiment does not make specific limitations here.
[0039] As a preferred embodiment, the plurality of registers includes at least two beat registers 204 and a plurality of scan registers 203; the plurality of scan registers 203 are connected between any two of the beat registers 204; the first-level register and the last-level register are both beat registers 204.
[0040] Specifically, such as Figure 2 As shown, in this embodiment, the multiple registers forming the scan test link further include a pipeline register 204 and a scan register 203. The pipeline register 204 is set between the data input port 201 and the logic under test or between the data output port 202 and the logic under test. The scan test link may include multiple pipeline registers 204, such as 2 pipeline registers 204, 3 pipeline registers 204, 4 pipeline registers 204, 5 pipeline registers 204, etc. This embodiment does not make specific limitations. It is worth noting that by setting the beat register 204, the timing requirements of the internal logic module and the I / O ports (i.e., data input port 201 and data output port 202) can be decoupled. This allows the internal logic module to focus only on the timing with the adjacent beat register 204, avoiding the formation of a long registerless path on the interface pads from the internal logic module to the I / O port. This allows the scan clock signal input port 101 to operate at a higher scan test clock frequency. In addition, the beat register 204, located close to the data output port 202, helps to synchronize the scan output data. It can re-beat the serial data transmitted by the scan register 203 at the scan clock edge, ensuring that the test feedback signal is free of glitches and has a fixed timing. This, together with the CTS buffer 300, meets the setup time and hold time requirements of the test host 400.
[0041] As a preferred embodiment, when at least two scanning test modules 200 are provided in the chip scanning test partition, and at least one scanning clock signal transmission circuit 100 is connected to at least two scanning test modules 200 respectively, the scanning clock signal input port 101 is connected to the clock signal input terminal of the last stage register of the at least two connected scanning test modules 200 respectively through the clock tree synthesis CTS buffer 300.
[0042] Specifically, such as Figure 3As shown, in a chip scan test partition with at least two logic modules under test (DUTs) and at least two corresponding scan test modules 200, and with a scan clock signal transmission circuit 100 connected to at least two scan test modules 200 respectively, in order to ensure that the delay of the test feedback signal feedback to the test host 400 is as small as possible, that is, the time difference between the time when the last-stage register receives the test feedback signal and the time when the test host 400 receives the test feedback signal is as small as possible, this embodiment sets a clock tree synthesis (CTS) for the last-stage register of each connected scan test module 200. The CTS buffer 300 is used to optimize the clock tree from the input scan clock port to the last-level register on the scan data path. This allows for precise fine-tuning of the arrival time of the scan clock signal at each last-level register, ensuring balanced arrival times of the scan clock signal at each last-level register. It also compensates for differences in wiring length and corrects clock skew, ensuring that each connected scan test module 200 can output test feedback signals at the highest achievable scan test clock frequency. This significantly reduces the delay of the test feedback signal feedback to the test host 400, thereby effectively shortening the SCAN test time and improving chip test efficiency.
[0043] As a preferred embodiment, each of the scanning clock signal transmission circuits 100 corresponding to the chip scanning test partition corresponds one-to-one with each of the scanning test modules 200 set in the chip scanning test partition.
[0044] Specifically, this embodiment further limits different logic modules under test to use different scan clock signal transmission circuits 100 during scan testing. That is, within the same chip scan test partition, different scan test modules 200 correspond to different scan clock signal input ports 101, thereby ensuring that each scan test module 200 can reach its highest achievable scan test clock frequency. At the same time, by having one scan clock signal input port 101 correspond to one scan test module 200, the scan test clock frequency will not be reduced due to taking into account the scan clock signal transmission delay of other scan test modules 200 when setting the position of the scan clock signal input port 101.
[0045] Furthermore, by having each scan clock signal transmission circuit 100 correspond one-to-one with each scan test module 200 set in the chip scan test partition, independent scan test of each logic module under test can be achieved, and the abnormal logic module can be quickly located when a scan test abnormality occurs.
[0046] Please see Figure 4The second aspect of the present invention provides a chip testing system, including a test host 400 and a chip testing circuit as described in any embodiment of the first aspect; the scan clock signal output terminal of the test host 400 is connected to the scan clock signal input port 101 in the chip testing circuit, and the test excitation signal output port and the test feedback signal input port of the test host 400 are respectively connected to the scan test module 200 in the chip testing circuit.
[0047] It is worth noting that in this embodiment, the test host 400 (i.e., ATE, Automatic Test System) is connected to the various ports of the chip under test, and the test excitation signal output port (i.e. Figure 4 The “DATAOUT” port in the test module 200 is connected to the data input port 201 of the scan test module 200 to input a specific test excitation signal; the test feedback signal input port (i.e., Figure 4 The “DATA IN” port is connected to the data output port 202 of the scan test module 200 to receive the test feedback signal and compare it with the test excitation signal, thereby detecting whether there is a fault in the corresponding internal logic module; by connecting the scan clock signal output terminal (i.e. Figure 4 The “CLK” port in the scan test module 200 is connected to the scan clock signal input port 101 corresponding to the scan clock signal input to realize the input of the scan clock signal.
[0048] The specific process of chip scanning test is as follows: Since the scan clock signal input port 101 and scan test module 200 under each chip scanning test partition are determined before the scanning test, the corresponding target chip scanning test partition, target scan clock signal input port 101, and target data input port 201 and target data output port 202 of the target scanning test module 200 can be determined based on the logic module under test that needs to be scanned. First, the test host 400 sends a mode selection signal to make each register of the scanning test link in the target scanning test module 200 enter "shift mode". Then, the test stimulus signal is input to the target data input port 201 through the test stimulus signal output port. If there are multiple target scan test modules 200, the corresponding test stimulus signals can be input to each target scan test module 200 in parallel. Further, the scan clock signal output terminal drives each register of the scan test link according to the preset scan test clock frequency. With each rising edge of the scan clock, the scan test link shifts once, allowing the test stimulus signal to be transmitted step-by-step in the scan test link until the entire scan test link is fully loaded. Further, the test host 400 sends a mode selection signal. This causes each register in the scan test link of the target scan test module 200 to enter "capture mode," latching the output of the logic module under test inside the chip into the registers in the scan test link. Then, the test host 400 sends a mode selection signal again, causing each register in the scan test link of the target scan test module 200 to enter "shift mode" again. The scan clock signal output continues to drive each register in the scan test link according to the preset scan test clock frequency, causing the latched test feedback signal to be shifted out of the scan test link sequentially, passing through the last stage near the target data output port 202. After synchronization, the data from the stamping register 204 is transmitted to the target data output port 202. The test feedback signal is acquired within the strobe valid window through the test feedback signal input port of the test host 400. The test host 400 observes the output response of the target scan test module 200 and compares each of its binary bits with the corresponding binary bits in the test excitation signal. If the comparison results of each binary bit are consistent, the scan test result is determined to be passed. If the comparison results of any binary bit are inconsistent, the scan test result is determined to be failed, so as to determine whether there is a logical defect or manufacturing failure.
[0049] Preferably, since the scan test clock frequency may be different under different chip scan test partitions, and the scan test clock frequency of different scan test modules 200 under the same chip scan test partition may also be different, for each scan clock signal input port 101 in the chip test circuit, during the scan test, the test host 400 connects to different scan clock signal input ports 101 through different scan clock signal output terminals, thereby ensuring that different scan test modules 200 can be scanned at the highest scan test clock frequency, ensuring the efficiency of chip scan test.
[0050] The chip testing system provided in this embodiment of the invention employs the chip testing circuit described in any embodiment of the first aspect, and sets at least one corresponding scan clock signal transmission circuit 100 for each chip scan test partition. The scan clock signal input port 101 of the scan clock signal transmission circuit 100 is set close to the scan test module 200 in the chip scan test partition, thereby significantly reducing the distance from the scan clock signal input port 101 to the scan test module 200, effectively reducing the scan clock signal transmission delay from the scan clock signal input port 101 to the scan test module 200, thereby ensuring a high scan test clock frequency, shortening the SCAN test time and improving chip testing efficiency.
[0051] A third aspect of the present invention provides a chip including a chip testing circuit as described in any embodiment of the first aspect.
[0052] It is worth noting that the chip in this embodiment can be any one of a CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit).
[0053] The chip provided in this embodiment of the invention integrates a chip test circuit as described in any embodiment of the first aspect. At least one corresponding scan clock signal transmission circuit is provided for each chip scan test partition, and the scan clock signal input port of the scan clock signal transmission circuit is located close to the scan test module within the chip scan test partition. This significantly reduces the distance from the scan clock signal input port to the scan test module, effectively reducing the scan clock signal transmission delay from the scan clock signal input port to the scan test module. Consequently, a high scan test clock frequency is ensured, shortening the SCAN test time and improving chip test efficiency.
[0054] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.
Claims
1. A chip testing circuit, characterized in that, It includes at least one chip scan test partition and at least one scan clock signal transmission circuit corresponding to the chip scan test partition; at least one scan test module is provided in the chip scan test partition; The scanning clock signal input port of the scanning clock signal transmission circuit is positioned close to the scanning test module; the scanning clock signal transmission circuit is used to receive the scanning clock signal through the scanning clock signal input port and output it to the scanning test module.
2. The chip testing circuit as described in claim 1, characterized in that, The scanning test module includes a data input port, a data output port, and multiple registers; the multiple registers are connected sequentially to form a scanning test link; the first-level register on the scanning test link is connected to the data input port, and the last-level register on the scanning test link is connected to the data output port; The data input port is used to receive test excitation signals and transmit them to the scan test link; the data output port is used to receive test feedback signals from the scan test link and feed them back to the test host; the output of the scan clock signal transmission circuit is connected to the clock signal input of each of the registers respectively.
3. The chip testing circuit as described in claim 2, characterized in that, The first-level register is configured near the data input port, and the last-level register is configured near the data output port.
4. The chip testing circuit as described in claim 1, characterized in that, The chip scanning test partition is determined based on the distance between the various scanning test modules located within the same chip.
5. The chip testing circuit as described in claim 1, characterized in that, When at least two scanning test modules are set in the chip scanning test partition, the setting position of the scanning clock signal input port is determined based on the transmission delay of the scanning clock signal from the scanning clock signal input port to each of the scanning test modules in the corresponding chip scanning test partition.
6. The chip testing circuit as described in claim 2, characterized in that, The plurality of registers includes at least two beat registers and a plurality of scan registers; the plurality of scan registers are connected between any two of the beat registers; the first-level register and the last-level register are both beat registers.
7. The chip testing circuit as described in claim 6, characterized in that, When at least two scan test modules are provided in the chip scan test partition, and at least one scan clock signal transmission circuit is connected to at least two scan test modules respectively, the scan clock signal input port is connected to the clock signal input terminal of the last stage register of the at least two connected scan test modules through the clock tree synthesis CTS buffer.
8. The chip testing circuit as described in claim 1, characterized in that, Each of the scanning clock signal transmission circuits corresponding to the chip scanning test partition corresponds one-to-one with each of the scanning test modules set within the chip scanning test partition.
9. A chip testing system, characterized in that, It includes a test host and a chip test circuit as described in any one of claims 1 to 8; the scan clock signal output terminal of the test host is connected to the scan clock signal input port in the chip test circuit, and the test excitation signal output port and the test feedback signal input port of the test host are respectively connected to the scan test module in the chip test circuit.
10. A chip, characterized in that, Includes the chip test circuit as described in any one of claims 1 to 8.