Display panel and display device

Abstract

The application relates to the technical field of display, and provides a display panel and a display device. The display panel comprises a plurality of scanning lines, a plurality of data lines and a plurality of arrayed pixel units. The scanning lines extend along a first direction, the data lines extend along a second direction, and the second direction intersects the first direction. The pixel unit comprises a plurality of sub-pixels arranged along the second direction in sequence. The sub-pixel comprises a thin film transistor and a pixel electrode electrically connected with the thin film transistor. In the first direction, a plurality of data lines are arranged between two adjacent rows of pixel units. The plurality of thin film transistors in the pixel unit are connected with the same scanning line and connected with the plurality of data lines respectively. The thin film transistors of the plurality of sub-pixels are arranged in a concentrated area. The display panel and the display device provided by the application can improve the aperture ratio.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In display panels, pixel aperture ratio is a core indicator affecting display brightness, contrast, and power consumption. The metal traces of subpixels, such as thin-film transistors, storage capacitors, data lines, and scan lines, can block light from the backlight, occupying a significant amount of pixel space.

[0003] Improving the aperture ratio of display panels is an urgent problem to be solved. Summary of the Invention

[0004] The purpose of this application is to provide a display panel and display device that aims to increase the aperture ratio of the display panel.

[0005] An embodiment of the first aspect of this application provides a display panel, the display panel including multiple scan lines, multiple data lines, and multiple arrayed pixel units; the scan lines extend along a first direction, the data lines extend along a second direction, the second direction intersects the first direction; each pixel unit includes multiple sub-pixels arranged sequentially along the second direction, each sub-pixel including a thin-film transistor and a pixel electrode electrically connected to the thin-film transistor; in the first direction, multiple data lines are provided between two adjacent rows of pixel units, the thin-film transistors in each pixel unit are connected to the same scan line and respectively connected to the multiple data lines, and the thin-film transistors of the multiple sub-pixels are located in a concentrated area.

[0006] The display panel provided in this application embodiment includes a scan line extending along a first direction, a data line extending along a second direction, and a pixel unit. The pixel unit includes multiple sub-pixels arranged along the second direction. By concentrating multiple data lines on one side of the pixel unit, the data lines and the pixel electrode area can be separated, avoiding the data lines from vertically dividing the pixel and occupying the space of the pixel electrode. Furthermore, the thin-film transistors of multiple sub-pixels are connected to multiple data lines and the same scan line, so that the thin-film transistors of multiple sub-pixels can be concentrated in a concentrated area. The pixel electrode can form a continuous light-transmitting area outside the concentrated area, reducing the segmentation and occupancy of the light-transmitting area by the thin-film transistors, increasing the area of ​​the pixel electrode, increasing the aperture ratio of the display panel, which is beneficial to improving the brightness and contrast of the display panel and reducing power consumption, thereby improving the performance of the display panel.

[0007] In some embodiments, the scan line includes a scan line body extending along the first direction and a plurality of scan line branches connected to the scan line body. The plurality of scan line branches are arranged at intervals along the first direction of separation and obstruction. The scan line branches extend along the second direction. The scan line branch corresponding to the pixel unit and the plurality of data lines are located on the same side of the pixel unit.

[0008] In some embodiments, the concentrated region is disposed on one side of one of the pixel electrodes along the first direction.

[0009] In some embodiments, the plurality of sub-pixels within the pixel unit are respectively a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially and having different light-emitting colors; The area of ​​the pixel electrode corresponding to the concentrated region is at least smaller than the area of ​​the other pixel electrode.

[0010] In some embodiments, the first sub-pixel is close to the corresponding scan line body; Wherein, the scan line branch extends into the first sub-pixel, and the concentrated region is located on one side of the first sub-pixel; or, The scan line branch extends into the second sub-pixel, and the concentrated area is located on one side of the second sub-pixel; or, The scan line branch extends into the third sub-pixel, and the concentrated area is located on one side of the third sub-pixel.

[0011] In some embodiments, the thin-film transistor includes a gate, a source, and a drain; one side of the scan line branch has two data lines forming two gates, and the other side has one data line forming one gate; the drain in the first sub-pixel and the drain in the second sub-pixel are located between two adjacent data lines.

[0012] In some embodiments, the data line near the pixel electrode has a bend that protrudes toward the pixel electrode, and the drain in the first sub-pixel and the drain in the second sub-pixel are located between the bend and the adjacent data line.

[0013] In some embodiments, the display panel further includes multiple common electrode lines, and a common electrode is provided within the sub-pixel. The common electrode is electrically connected to the common electrode lines through vias. The common electrode is stacked above the pixel electrode. The common electrode has multiple slits within it, and the common electrode and the pixel electrode can form a lateral electric field.

[0014] In some embodiments, the common electrode line and the data line are located in the same metal layer, the common electrode line extends along the second direction, and the common electrode line and the multiple data lines are respectively disposed on both sides of the corresponding pixel unit.

[0015] An embodiment of the second aspect of this application provides a display device including a display panel as provided in the first aspect.

[0016] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 These are schematic diagrams of the display panel structure provided in some embodiments of this application; Figure 2 This is a schematic diagram of the pixel structure of a display panel provided in some embodiments of this application; Figure 3 This is a schematic diagram of the structure of scan lines in a display panel provided in some embodiments of this application; Figure 4 This is a schematic diagram of the structure of scan lines, data lines and thin-film transistors in a display panel provided in some embodiments of this application; Figure 5 This is a schematic diagram of the structure of scan lines, data lines, thin-film transistors and pixel electrodes in a display panel provided in some embodiments of this application.

[0019] Explanation of key component symbols: 100. Display panel; 10. Scan line; 11. Scan line body; 12. Scan line branch; 20. Data line; 21. Bending part; 30. Pixel unit; 30a. First sub-pixel; 30b. Second sub-pixel; 30c. Third sub-pixel; 31. Thin film transistor; 311. Gate; 312. Source; 313. Drain; 32. Pixel electrode; 321. Electrode connection part; 40. Common electrode line; 50. Common electrode; 51. Slit; 61. First via; 62. Second via. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0021] It should be noted that when a component is referred to as "fixed to" or "set on" another component, it can be directly or indirectly attached to that other component. When a component is referred to as "connected to" another component, it can be directly or indirectly connected to that other component. The terms "upper," "lower," "left," "right," etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are for descriptive convenience only, not indicating or implying that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the patent. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features. "A plurality" means two or more, unless otherwise explicitly defined.

[0022] In this specification, references to "one embodiment," "some embodiments," or simply "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0023] In display panels, pixel aperture ratio is a core indicator affecting display brightness, contrast, and power consumption. Specifically, the metal traces of subpixels, such as thin-film transistors, storage capacitors, data lines, and scan lines, can block light from the backlight, occupying a significant amount of pixel space and thus affecting the display panel's aperture ratio.

[0024] Typically, in a pixel unit, the thin-film transistors of three sub-pixels are distributed within their respective sub-pixels. This results in the sub-pixel's light-transmitting area being divided, and each sub-pixel has its space occupied by the thin-film transistors, making it impossible to fully utilize the pixel space, thus leading to a decrease in the pixel's aperture ratio.

[0025] In view of this, this application provides a display panel and display device. By arranging multiple data lines on the same side of a row of pixel units and arranging the thin-film transistors of multiple sub-pixels in a concentrated area, the pixel electrodes can form a continuous light-transmitting area outside the concentrated area. This reduces the segmentation and occlusion of the light-transmitting area by the thin-film transistors, increases the area of ​​the pixel electrodes, increases the aperture ratio of the display panel, and helps to improve the brightness and contrast of the display panel, reduce power consumption, and improve the performance of the display panel.

[0026] An embodiment of the first aspect of this application provides a display panel 100. Please refer to... Figure 1 and Figure 2 The display panel 100 includes multiple scan lines 10, multiple data lines 20, and multiple arrayed pixel units 30. The scan lines 10 extend along a first direction Y, and the data lines 20 extend along a second direction X, which intersects with the first direction Y. Each pixel unit 30 includes multiple sub-pixels arranged sequentially along the second direction X. Each sub-pixel includes a thin-film transistor 31 and a pixel electrode 32 electrically connected to the thin-film transistor 31. In the first direction Y, multiple data lines 20 are provided between two adjacent rows of pixel units 30. The thin-film transistors 31 in each pixel unit 30 are connected to the same scan line 10 and are respectively connected to multiple data lines 20. The thin-film transistors 31 of multiple sub-pixels are located in a concentrated area.

[0027] For example, the first direction Y intersects the second direction X perpendicularly. For ease of description, the first direction Y is called the column direction, and the second direction X is called the row direction.

[0028] A gate line, also known as a gate line or gate select line, is used to control the switching of a thin-film transistor; a data line, also known as a source line or signal line, is used to transmit voltage or current signals that represent image brightness and color information.

[0029] For example, pixel unit 30 includes three sub-pixels arranged sequentially along the second direction X. The three sub-pixels emit different colors of light; for example, the three sub-pixels are a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. It is understood that the number of sub-pixels in pixel unit 30 can also be other; for example, pixel unit 30 can also include two or four sub-pixels (e.g., red, green, blue, and white sub-pixels).

[0030] Multiple data lines 20 are provided between two adjacent rows of pixel units 30 in the first direction Y. That is, the multiple data lines 20 corresponding to the pixel unit 30 are located on the same side of the pixel unit 30 in the first direction Y. It can be understood that the number of data lines 20 connected to a pixel unit 30 is the same as the number of sub-pixels in that pixel unit 30. Thus, in a pixel unit 30, the thin-film transistor 31 of each sub-pixel is connected to a corresponding data line 20, and the thin-film transistors 31 of multiple sub-pixels are connected to different data lines 20. At the same time, the thin-film transistors 31 of multiple sub-pixels are also connected to the same scan line 10, so that the brightness of multiple sub-pixels can be individually controlled.

[0031] For example, such as Figure 1 and Figure 2 As shown, a pixel unit 30 includes three sub-pixels, and three data lines 20 are provided between two adjacent rows of pixel units 30. It can be understood that in a row of pixel units 30, there are multiple pixel units 30 arranged sequentially along the row direction. One data line 20 connects the sub-pixels of these multiple pixel units 30. For example, one data line 20 connects the red sub-pixel of the multiple pixel units 30, another data line 20 connects the green sub-pixel of the multiple pixel units 30, and yet another data line 20 connects the blue sub-pixel of the multiple pixel units 30.

[0032] Since multiple data lines 20 are provided between two adjacent rows of pixel units 30, the data lines 20 are physically separated from the display area of ​​the pixel electrode 32. The data lines 20 are located in the gaps between the pixel rows, rather than passing through the gaps between adjacent pixel electrodes 32, thus avoiding vertical segmentation and occlusion of the pixel electrode 32, which is beneficial to improving the pixel aperture ratio.

[0033] Each sub-pixel includes a thin-film transistor (TFT) 31 and a pixel electrode 32 connected to the TFT 31. The TFT 31 can be an amorphous silicon TFT (a-Si TFT), a low-temperature polycrystalline silicon (LTPS) TFT, a metal oxide TFT (IGZO TFT), etc. The pixel electrode 32 is a transparent electrode, and the pixel electrode 32 can be an ITO (indium tin oxide) electrode, etc.

[0034] In this embodiment, the thin-film transistors 31 of multiple sub-pixels within the pixel unit 30 are disposed in a concentrated area, meaning that the thin-film transistors 31 of multiple sub-pixels are concentrated in one area. This concentrated area can be located in the area of ​​multiple data lines 20, or it can be disposed close to the multiple data lines 20.

[0035] In some existing technologies, the thin-film transistors 31 of each sub-pixel are located in the corresponding sub-pixel region, which makes the multiple thin-film transistors 31 of the pixel unit 30 dispersed, which is not conducive to forming a pixel electrode 32 with a large area. In the embodiment of this application, the thin-film transistors 31 of multiple sub-pixels are located in a concentrated region, so that most of the other regions can be used to form the pixel electrode 32, which is conducive to increasing the area of ​​the pixel electrode 32, thereby increasing the aperture ratio.

[0036] The display panel 100 provided in this application embodiment includes a scan line 10 extending along a first direction Y, a data line 20 extending along a second direction X, and a pixel unit 30. The pixel unit 30 includes a plurality of sub-pixels arranged along the second direction X, that is, the arrangement direction of the sub-pixels is parallel to the extension direction of the data line 20. By placing the plurality of data lines 20 on one side of the pixel unit 30, the area of ​​the data lines 20 and the pixel electrode 32 can be separated, avoiding the data lines 20 from vertically dividing the pixels and occupying the space of the pixel electrode 32. Furthermore, the thin-film transistors 31 of the plurality of sub-pixels are connected to the plurality of data lines 20 and the same scan line 10, so that the thin-film transistors 31 of the plurality of sub-pixels can be concentrated in a concentrated area, and the pixel electrode 32 can form a continuous light-transmitting area outside the concentrated area, reducing the division and blocking of the light-transmitting area by the thin-film transistors 31, increasing the area of ​​the pixel electrode 32, increasing the aperture ratio of the display panel 100, which is beneficial to improving the brightness and contrast of the display panel 100 and reducing power consumption, thereby improving the performance of the display panel 100.

[0037] In some embodiments, among the multiple data lines 20 between two adjacent rows of pixel units, the spacing between any two adjacent data lines 20 is 3.5 micrometers to 4.5 micrometers, for example, 3.5 micrometers, 3.6 micrometers, 3.7 micrometers, 3.8 micrometers, 3.9 micrometers, 4.0 micrometers, 4.1 micrometers, 4.2 micrometers, 4.3 micrometers, 4.5 micrometers, etc. A spacing of not less than 3.5 micrometers between adjacent data lines 20 facilitates manufacturing and achieves better manufacturing yield; a spacing of not more than 4.5 micrometers between adjacent data lines 20 helps to improve the aperture ratio of the display panel 100.

[0038] In other embodiments, the spacing between two adjacent data lines 20 may also be other ranges, which can be adjusted according to design requirements and process capabilities.

[0039] In some embodiments, the scan line 10 includes a scan line body 11 extending along a first direction Y and a plurality of scan line branches 12 connected to the scan line body 11. The plurality of scan line branches 12 are arranged sequentially at intervals along the first direction Y, and the scan line branches 12 extend along a second direction X. The scan line branch 12 corresponding to the pixel unit 30 and the plurality of data lines 20 are located on the same side of the corresponding pixel unit 30.

[0040] The scan line branch 12 and the scan line body 11 are integrally connected and made of the same metal layer. The multiple scan line branches 12 are respectively connected to multiple pixel units 30 arranged along the first direction Y.

[0041] For example, scan line branch 12 can extend to the middle sub-pixel; it can be understood that scan line branch 12 can also extend to any sub-pixel.

[0042] The scan line branch 12 and multiple data lines 20 are located on the same side of the pixel unit 30. That is, the scan line branch 12 and multiple data lines 20 corresponding to the same pixel unit 30 are arranged adjacent to each other on the same side of the pixel unit 30. In this way, the scan line branch 12 and multiple data lines 20 can be concentrated and distributed, reducing the occupation of the pixel electrode 32 area.

[0043] By setting up the scan line branch 12, wiring can be facilitated, and multiple gates 311 can be fabricated on the scan line branch 12, which is beneficial to concentrate multiple thin film transistors 31 in a concentrated area. By setting the scan line branch 12 and multiple data lines 20 on the same side of the pixel unit 30, the wiring can be made more compact, which is beneficial to improving the aperture ratio of the display panel 100.

[0044] In some embodiments, a concentrated region is disposed on one side of one of the pixel electrodes 32 along the first direction Y.

[0045] The concentrated area is located on one side of one of the pixel electrodes 32 along the first direction Y, which means that the concentrated area is only located on one side of one pixel electrode 32, and the concentrated area is staggered from the pixel electrodes 32 of other sub-pixels in the first direction Y; it can be understood that the multiple thin film transistors 31 of the pixel unit 30 are located on one side of one of the pixel electrodes 32.

[0046] For example, pixel unit 30 includes three sub-pixels, with a concentrated region located on one side of the pixel electrode 32 of the middle sub-pixel along the first direction Y. In other embodiments, the concentrated region may also be located on one side of other sub-pixels, for example, on the side of the pixel electrode 32 closest to the scan line 10.

[0047] Since the concentrated area is located on one side of one of the pixel electrodes 32, the pixel electrodes 32 of other sub-pixels of the pixel unit 30 can extend toward the direction of the corresponding data line 20. The concentrated area does not occupy the light-transmitting area of ​​other sub-pixels, so that the pixel electrodes 32 of other sub-pixels can be set with a larger area to improve the aperture ratio of the sub-pixels and the overall aperture ratio of the display panel 100.

[0048] In some embodiments, the multiple sub-pixels within the pixel unit 30 are a first sub-pixel 30a, a second sub-pixel 30b, and a third sub-pixel 30c arranged sequentially and having different light-emitting colors, and the area of ​​the pixel electrode 32 corresponding to the concentrated region is at least smaller than the area of ​​another pixel electrode 32.

[0049] The first sub-pixel 30a, the second sub-pixel 30b, and the third sub-pixel 30c emit different colors of light. For example, they could be red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels, respectively. That is to say, the color filters corresponding to these three sub-pixels are red (R), green (G), and blue (B), respectively. It can be understood that the color order of the three sub-pixels is not limited to this.

[0050] In some embodiments, the concentrated region is located on one side of the second pixel, that is, the concentrated region corresponds to the second sub-pixel 30b. The area of ​​the pixel electrode 32 of the first sub-pixel 30a is larger than the area of ​​the pixel electrode 32 of the second sub-pixel 30b, and / or, the area of ​​the pixel electrode 32 of the third sub-pixel 30c is larger than the area of ​​the pixel electrode 32 of the second sub-pixel 30b.

[0051] For example, the concentrated area is located on one side of the second pixel. The areas of the pixel electrode 32 of the first sub-pixel 30a and the pixel electrode 32 of the third sub-pixel 30c are both larger than the area of ​​the pixel electrode 32 of the second sub-pixel 30b. Thus, the aperture ratio of the first sub-pixel 30a and / or the third sub-pixel 30c can be greater than the aperture ratio of the second sub-pixel 30b. The pixel electrodes 32 of the first sub-pixel 30a and the third sub-pixel 30c can extend to a position close to the data line 20, and the pixel electrode 32 of the second sub-pixel 30b can extend to a position close to the concentrated area, thereby allowing the first sub-pixel 30a and the third sub-pixel 30c to have larger pixel electrode areas.

[0052] In other embodiments, the concentrated area may also be located on one side of the third sub-pixel 30c, in which case the area of ​​the pixel electrode 32 of the third sub-pixel 30c is smaller than the area of ​​the pixel electrode 32 of the first sub-pixel 30a and / or the second sub-pixel 30b.

[0053] By adopting the above technical solution, since the first sub-pixel 30a, the second sub-pixel 30b, and the third sub-pixel 30c emit different colors of light, and by setting the concentrated area on one side of one of the sub-pixels, the concentrated area does not occupy the space of other sub-pixels. This allows for convenient adjustment of the aperture ratios of multiple sub-pixels, thereby adjusting the display effect of the display panel 100, including adjusting the viewing angle. By setting different aperture ratios for multiple sub-pixels, the viewing angle of the display panel 100 can be adjusted.

[0054] In other embodiments, the pixel electrodes 32 of multiple sub-pixels can also be configured with the same area. Since multiple thin-film transistors 31 are centrally arranged, the pixel electrodes 32 of multiple sub-pixels can be configured with a continuous large area extension region, which can also improve the aperture ratio of the sub-pixels.

[0055] In some embodiments, the first sub-pixel 30a is close to the corresponding scan line body 11, wherein the scan line branch 12 extends into the first sub-pixel, and the concentrated area is located on one side of the first sub-pixel 30a; or, the scan line branch 12 extends into the second sub-pixel 30b, and the concentrated area is located on one side of the second sub-pixel 30b; or, the scan line branch 12 extends into the third sub-pixel 30c, and the concentrated area is located on one side of the third sub-pixel 30c.

[0056] By adopting the above technical solution, the concentrated area can be set on one side of any sub-pixel without occupying the space of other sub-pixels, and the aperture ratio of multiple sub-pixels and the display effect of the display panel 100 can be easily adjusted.

[0057] In some embodiments, from the side closest to the corresponding scan line 10, the three sub-pixels are sequentially designated as R sub-pixel, G sub-pixel, and B sub-pixel. Optionally, since the aperture ratio of the R sub-pixel has a significant impact on chromaticity, the concentrated area can be set on one side of the G sub-pixel or the B sub-pixel.

[0058] By adopting the above technical solution, the scan line branch 12 extends into the second sub-pixel 30b located in the middle, which facilitates the connection of the gates 311 of the three thin-film transistors 31 to the scan line branch 12. The concentrated area is set on one side of the second sub-pixel 30b, which facilitates the connection of the thin-film transistors 31 of the first sub-pixel 30a and the third sub-pixel 30c to the pixel electrode 32. Similarly, the scan line branch 12 extending to the third sub-pixel 30c can also achieve the concentrated arrangement of the thin-film transistors 31.

[0059] In some embodiments, the thin-film transistor 31 includes a gate electrode 311, a source electrode 312, and a drain electrode 313; a concentrated region is disposed on one side of the second sub-pixel 30b, two data lines 20 are disposed on one side of the scan line branch 12 and two gate electrodes 311 are formed, and one data line 20 is disposed on the other side of the scan line branch 12 and one gate electrode 311 is formed; the drain electrode 313 in the first sub-pixel 30a and the drain electrode 313 in the second sub-pixel 30b are located between two adjacent data lines 20.

[0060] In the thin-film transistor 31, the gate 311 is connected to the scan line 10, the source 312 is connected to the data line 20, and the drain 313 is connected to the pixel electrode 32. The thin-film transistor 31 also includes an active layer, which is disposed between the gate 311 and the source 312 and drain 313.

[0061] like Figure 3 and Figure 4 As shown, two data lines 20 are provided on one side of the scan line branch 12, forming two gates 311, and one data line 20 is provided on the other side of the scan line branch 12, forming one gate 311. All three gates 311 are located on one side of the second sub-pixel 30b. At the same time, the drain 313 in the first sub-pixel 30a and the drain 313 in the second sub-pixel 30b are located between two adjacent data lines 20. Thus, two thin-film transistors 31 are formed on the side of the scan line branch 12 along the first direction Y close to the pixel electrode 32, and one thin-film transistor 31 is formed on the side of the scan line branch 12 away from the pixel electrode 32.

[0062] By adopting the above wiring method, the three thin-film transistors 31 can be concentrated in a concentrated area, which is located in the distribution area of ​​the scan line branch 12 and the three data lines 20, so that the thin-film transistors 31 occupy less space.

[0063] like Figure 1 , Figure 4 and Figure 5 As shown, the main body of the pixel electrode 32 has a continuous large area. The pixel electrode 32 has an electrode connection portion 321, which extends from the main body of the pixel electrode 32 to the corresponding drain electrode 313 to realize the electrical connection between the pixel electrode 32 and the thin-film transistor 31. It can be understood that the electrode connection portion 321 and the drain electrode 313 are electrically connected through an interlayer via (first via 61).

[0064] Optionally, the data line 20 near the pixel electrode 32 has a bend 21 protruding toward the pixel electrode 32, and two drains 313 are located between the bend 21 and the adjacent data line 20. In this way, the thin-film transistors 31 of the first sub-pixel 30a and the second sub-pixel 30b can obtain sufficient channel length, and other areas of the two data lines 20 can maintain a small spacing to reduce the wiring area.

[0065] Optionally, the drain 313 of the third sub-pixel 30c is overlapped with the scan line branch 12 to further reduce the wiring area.

[0066] In some embodiments, the display panel 100 further includes multiple common electrode lines 40, and a common electrode 50 is provided in the sub-pixel. The common electrode 50 and the common electrode lines 40 are electrically connected through a via (second via 62). The common electrode 50 is stacked above the pixel electrode 32. Multiple slits 51 are provided in the common electrode 50. The common electrode 50 and the pixel electrode 32 can form a lateral electric field.

[0067] The common electrode line 40 is used to input a common voltage to the common electrode 50. The common electrode 50 is located above the pixel electrode 32, that is, the common electrode 50 is located on the side of the pixel electrode 32 away from the substrate. It can be understood that an insulating layer is provided between the common electrode 50 and the common electrode line 40. The common electrode 50 and the common electrode line 40 are electrically connected through a via penetrating the insulating layer.

[0068] The common electrode 50 has multiple slits 51, and the common electrode 50 and the pixel electrode 32 can form a lateral electric field.

[0069] In this embodiment, the pixel electrode 32 is a plate-shaped electrode, and there is a gap between the pixel electrodes 32 of different sub-pixels, which can separate adjacent sub-pixel regions. It can be understood that the pixel electrode 32 may also be provided with multiple slits 51.

[0070] In this embodiment, the common electrode 50 is provided with a plurality of slits 51 in the region of each sub-pixel, the common electrode 50 and the pixel electrode 32 are respectively subjected to voltage, and a transverse electric field can be formed between the common electrode 50 and the pixel electrode 32.

[0071] For example, the display panel 100 is a fringe field switching (FFS) panel, the pixel electrode 32 is a plate-shaped electrode, and multiple finger-shaped slits 51 are formed on the common electrode 50. The common electrode 50 and the pixel electrode 32 are separated by an insulating layer. The common electrode 50 and the pixel electrode 32 can form a lateral electric field and an edge electric field. The edge electric field extends upward from the edge of the finger-shaped electrode and can drive the liquid crystal molecules deeper inside.

[0072] Optionally, the pixel electrode 32 is arranged to overlap with the common electrode line 40, that is, one side of the pixel electrode 32 extends to the side of the common electrode line 40 away from the thin-film transistor, and the other side extends to the side of the data line 20. In this way, the pixel electrode 32 can obtain a larger area.

[0073] The display panel 100 can also be an in-plane switching (IPS) panel, where a parallel lateral electric field is formed between the common electrode 50 and the pixel electrode 32.

[0074] By adopting the above technical solution, the display panel 100 provided in this application embodiment can form a lateral electric field through the common electrode 50 and the pixel electrode 32, resulting in excellent viewing angle and color accuracy. Furthermore, when the concentrated area is set on one side of a sub-pixel, the remaining sub-pixels can obtain a larger pixel electrode 32 area, and the display panel 100 can adjust the aperture ratio of different sub-pixels to optimize the viewing angle.

[0075] In other embodiments, the display panel 100 may also be other types of panels, such as a vertical alignment (VA) panel.

[0076] In some embodiments, the common electrode line 40 and the data line 20 are disposed on the same metal layer, the common electrode line 40 extends along the second direction X, the common electrode line 40 and the data line 20 are parallel and spaced apart, and the common electrode line 40 and the data line 20 are respectively disposed on opposite sides of the pixel unit 30.

[0077] The common electrode line 40 and the data line 20 are obtained by patterning the same metal layer, while the scan line 10 is located in another metal layer. It can be understood that the common electrode 50 intersects with the scan line 10, and the common electrode 50 and the scan line 10 can be located in different metal layers to avoid short circuits between them.

[0078] By adopting the above technical solution, the common electrode 50 and the data line 20 are arranged parallel and spaced apart, and the common electrode 50 intersects with the scan line 10. The common electrode 50 and the scan line 10 can be disposed in different metal layers to avoid short circuits between them. The common electrode 50 and the data line 20 are respectively disposed on opposite sides of the pixel unit 30. It can be understood that the common electrode line 40 and the data line 20 corresponding to the pixel unit 30 in the adjacent row are arranged side by side, so that the common electrode line 40 and the data line 20 are concentrated, which can reduce the area occupied by the common electrode 50 in the light-transmitting area. The embodiment of this application optimizes the design of the common electrode line 40, further improving the pixel aperture ratio.

[0079] The display panel 100 includes a first substrate, a second substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. The pixel structure is disposed on the first substrate, and the second substrate is provided with a color filter film and a light-shielding matrix. The light-shielding matrix can be a black matrix.

[0080] The color filter can cover the pixel electrode 32. Optionally, the color filter can also cover the entire sub-pixel area to reduce reflections from the metal traces.

[0081] Please refer to Figures 1 to 5Some embodiments of this application provide a display panel 100, including multiple scan lines 10, multiple data lines 20, and multiple arrayed pixel units 30; the scan lines 10 extend along a first direction Y, the data lines 20 extend along a second direction X, and the pixel unit 30 includes multiple sub-pixels arranged sequentially along the second direction X. In the first direction Y, multiple data lines 20 are provided between two adjacent rows of pixel units 30. Multiple thin-film transistors 31 in the pixel unit 30 are connected to the same scan line 10 and are respectively connected to the multiple data lines 20. The thin-film transistors 31 of the multiple sub-pixels are disposed in a concentrated area. The concentrated area is disposed on one side of one of the pixel electrodes 32 along the first direction Y. A common electrode line 40 extends along the second direction X, and the common electrode line 40 and the multiple data lines 20 are respectively disposed on both sides of the corresponding pixel unit 30.

[0082] The display panel 100 provided in this application embodiment achieves a compact TFT layout, optimized wiring, and increased area of ​​the light-transmitting region, thereby improving the utilization rate of edge space. By concentrating the three data lines 20 below the pixel unit 30, the vertical arrangement of the data lines 20 avoids occupying the light-transmitting region. Furthermore, by concentrating the TFTs of multiple sub-pixels of the pixel unit 30 in a concentrated area, the problem of TFTs occupying a large area due to dispersed arrangement is solved. The TFT channel can be reduced in size. Optionally, the LTPS channel can be reduced to below 5μm. Further, the LTPS channel length can be reduced to 4μm~5μm. By tightly arranging the three TFTs, the total occupied area is only 1 / 2 to 1 / 3 of that of the traditional dispersed layout, and the aperture ratio of the pixel unit 30 can be increased by 5%-10%.

[0083] In addition, based on increasing the area of ​​the light-transmitting area, multiple sub-pixels of the pixel unit share the scan line 10, and multiple sub-pixels are respectively connected to multiple data lines located on the same side of the pixel unit, so that the driving circuit can adapt to the pixel design and the brightness of the three RGB sub-pixels can be adjusted independently.

[0084] Meanwhile, by placing the three TFTs below one of the sub-pixels, the space of the other two sub-pixels will not be encroached upon. The electrodes of the other two sub-pixels can be extended to the data line 20 to expand the area, enabling differentiated design of RGB sub-pixels. By adjusting the aperture ratio of the RGB sub-pixels, the viewing angle of the display panel 100 can be optimized.

[0085] An embodiment of the second aspect of this application provides a display device including a display panel 100 as provided in the first aspect. The display device also has the advantage of a large aperture ratio.

[0086] The display device can be a television, monitor, digital photo frame, laptop, tablet, mobile phone, smart wearable device, in-vehicle display device, virtual reality device, augmented reality device, medical display device, or public information display device.

[0087] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes multiple scan lines, multiple data lines, and multiple pixel units arranged in an array; The scan line extends along a first direction, and the data line extends along a second direction, the second direction intersecting the first direction; The pixel unit includes a plurality of sub-pixels arranged sequentially along the second direction, and the sub-pixel includes a thin-film transistor and a pixel electrode electrically connected to the thin-film transistor; In the first direction, multiple data lines are provided between two adjacent rows of pixel units. Multiple thin-film transistors in the pixel unit are connected to the same scan line and are respectively connected to multiple data lines. The thin-film transistors of multiple sub-pixels are located in a concentrated area.

2. The display panel as described in claim 1, characterized in that, The scan line includes a scan line body extending along the first direction and a plurality of scan line branches connected to the scan line body. The plurality of scan line branches are arranged at intervals along the first direction, and the scan line branches extend along the second direction. The scan line branch corresponding to the pixel unit and the multiple data lines are located on the same side of the pixel unit.

3. The display panel as described in claim 2, characterized in that, The concentrated area is located on one side of one of the pixel electrodes along the first direction.

4. The display panel as described in claim 3, characterized in that, The multiple sub-pixels within the pixel unit are respectively a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially and having different light-emitting colors; The area of ​​the pixel electrode corresponding to the concentrated region is at least smaller than the area of ​​the other pixel electrode.

5. The display panel as described in claim 4, characterized in that, The first sub-pixel is close to the corresponding scan line body; Wherein, the scan line branch extends into the first sub-pixel, and the concentrated region is located on one side of the first sub-pixel; or, The scan line branch extends into the second sub-pixel, and the concentrated area is located on one side of the second sub-pixel; or, The scan line branch extends into the third sub-pixel, and the concentrated area is located on one side of the third sub-pixel.

6. The display panel as described in claim 5, characterized in that, The thin-film transistor includes a gate, a source, and a drain; The scan line branch has two data lines on one side and forms two gates, and one data line on the other side and forms one gate. The drain in the first sub-pixel and the drain in the second sub-pixel are located between two adjacent data lines.

7. The display panel as described in claim 6, characterized in that, The data line near the pixel electrode has a bend that protrudes toward the pixel electrode, and the drain in the first sub-pixel and the drain in the second sub-pixel are located between the bend and the adjacent data line.

8. The display panel as described in any one of claims 1-7, characterized in that, The display panel also includes multiple common electrode lines, and a common electrode is provided in the sub-pixel. The common electrode and the common electrode lines are electrically connected through vias. The common electrode is stacked on top of the pixel electrode. The common electrode has multiple slits. The common electrode and the pixel electrode can form a lateral electric field.

9. The display panel as described in claim 8, characterized in that, The common electrode line and the data line are located in the same metal layer. The common electrode line extends along the second direction. The common electrode line and the multiple data lines are respectively located on both sides of the corresponding pixel unit.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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