Electronic device

Abstract

The present disclosure provides an electronic device, characterized in that, comprising: a substrate structure comprising: a substrate; a first conductive layer disposed on the substrate and comprising a first common electrode line extending in a first direction; a second conductive layer disposed on the first conductive layer and comprising a second common electrode line extending in a second direction, the first direction being different from the second direction, wherein, in the normal direction of the substrate, the first common electrode line and the second common electrode line partially overlap, wherein the second common electrode line has a first portion and a second portion, and in the first direction, the width of the first portion is greater than the width of the second portion; and a pixel electrode, at least a portion of the pixel electrode is disposed on the second conductive layer, and in the normal direction of the substrate, the pixel electrode and the second common electrode line partially overlap.

Description

Technical Field

[0001] This disclosure relates to an electronic device, specifically an electronic device having a common electrode line. Background Technology

[0002] With the continuous advancement of technology and the constant improvement of display technology, consumers are becoming increasingly particular about display quality, leading manufacturers to dedicate themselves to improving the display quality of electronic devices in order to meet consumer demands.

[0003] When the resistance of the common electrode line is too high, it can easily affect the stability of signal transmission, leading to a deterioration in display quality. Therefore, there is an urgent need to provide an electronic device that can improve upon these shortcomings. Summary of the Invention

[0004] This disclosure provides an electronic device, characterized in that it comprises: a substrate structure, comprising: a substrate; a first conductive layer disposed on the substrate and including a first common electrode line extending along a first direction; a second conductive layer disposed on the first conductive layer and including a second common electrode line extending along a second direction, the first direction being different from the second direction, wherein, in the normal direction of the substrate, the first common electrode line and the second common electrode line partially overlap, wherein the second common electrode line has a first portion and a second portion, and in the first direction, the width of the first portion is greater than the width of the second portion; and a pixel electrode, at least a portion of the pixel electrode being disposed on the second conductive layer, and in the normal direction of the substrate, the pixel electrode and the second common electrode line partially overlap. Attached Figure Description

[0005] Figure 1 This is a top view schematic diagram of a substrate structure according to an embodiment of the present disclosure.

[0006] Figure 2A and Figure 2B This is a top view schematic diagram of a partial substrate structure according to an embodiment of the present disclosure.

[0007] Figure 2C for Figure 2A A cross-sectional diagram of line segment A-A'.

[0008] Figures 3A to 3C This is a top view schematic diagram of a partial substrate structure according to an embodiment of the present disclosure.

[0009] Figure 3D for Figure 3A A cross-sectional diagram of line segment B-B'.

[0010] Figure 4 This is an equivalent circuit diagram of an embodiment of the present disclosure.

[0011] Figure 5 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0012] Figure 6 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0013] Explanation of reference numerals in the attached figures:

[0014] 1 substrate structure 11 substrate 12 First conductive layer 121 First common electrode line 121A Part Three 121B Part Four 122 gate line 123 First gate 124 Second gate 125、176 Conductive block 13、18 Second conductive layer 131、181 Second common electrode line 131A, 181A Part One 131B, 181B Part Two 132、171 Data cable 133、172 First Source 134、173 First drain electrode 135、174 Second source pole 136、175 Second drain 14 Circuit elements 15 Pixel Electrode 161 First Semiconductor 162 Second Semiconductor 17 Third conductive layer 171 Data cable 183 concavity 185s, 186s side 101 First insulating layer 102 Second insulating layer 103 Third insulating layer 104 Fourth insulation layer 1011、1021、1022、1023、1031、1032、1033、1041 Through hole 2 Display layer 2s sidewall 21 Electrophoretic layer 211 charged particles 211A Black particles 211B White particles 3 common electrode layer 4 Protective substrate 5 Circuit structure 61、62 Adhesive layer 7 protective layer 8 opposite substrate 9 Frame glue AA Active Zone B Surrounding areas Cst Storage capacitor Cst1 First capacitor Cst2 Second capacitor Cst3 Third capacitor Cst4 Fourth capacitor Cst5 Fifth capacitor DL Data cable GL gate line H1 First through hole H2 Second through hole H3 Third through hole L1, L2 wire TFT1 First transistor TFT2 Second transistor W1, W2, W3, W4 width X Second direction Y First direction Z Normal direction Detailed Implementation

[0015] The following describes the implementation of this disclosure through specific embodiments. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed for different viewpoints and applications without departing from the spirit of this invention.

[0016] It should be noted that, unless otherwise specified herein, the presence of an element "a" is not limited to having a single element, but may include one or more of the elements. Furthermore, the ordinal numbers used in the specification and claims, such as "first" and "second," to modify elements of a claim, do not in themselves imply or represent any prior ordinal number for that claimed element, nor do they represent the order of one claimed element with another, or the order of manufacture. The use of these ordinal numbers is solely to clearly distinguish one claimed element with a given name from another claimed element with the same name.

[0017] Throughout this disclosure and in the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as “comprising,” “containing,” and “having” are open-ended terms and should therefore be interpreted as “containing but not limited to…”. Thus, when the terms “comprising,” “containing,” and / or “having” are used in the description of this disclosure, they specify the presence of the corresponding feature, area, step, operation, and / or component, but do not exclude the presence of one or more of the corresponding feature, area, step, operation, and / or component.

[0018] In this text, the terms "about," "approximately," "substantially," and "roughly" typically indicate that a given value or range is within 10%, 5%, 3%, 2%, 1%, or 0.5%. The given quantity is an approximate quantity; that is, even without specific mention of "about," "approximately," "substantially," or "roughly," the meaning of these terms is implied. Furthermore, the phrases "range from the first value to the second value" or "range between the first value and the second value" indicate that the range includes the first value, the second value, and other values ​​in between.

[0019] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined herein.

[0020] Furthermore, relative terms such as "below" or "bottom" and "above" or "top" may be used in the embodiments to describe the relative relationship of one element to another in the diagram. It is understood that if the device in the diagram is flipped upside down, an element depicted on the "below" side will become an element on the "above" side. When a corresponding component (e.g., a membrane or region) is referred to as "on another component," it can be directly on the other component, or there may be other components between them. On the other hand, when a component is referred to as "directly on another component," there are no components between them. Additionally, when a component is referred to as "on another component," there is a vertical relationship between them in the top view, and this component can be above or below the other component, depending on the orientation of the device.

[0021] In this disclosure, the thickness, length, width, or distance and angle between components can be measured using an optical microscopy (OM), a scanning electron microscope (SEM), an alpha-step thickness gauge, an ellipsometry, or other suitable methods. Specifically, according to some embodiments, a scanning electron microscope can be used to obtain cross-sectional images of the structure and measure the thickness, length, width, or distance and angle between components. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error of approximately 10% between the first and second values; if the first direction is perpendicular to the second direction, the angle between the first and second directions may be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle between the first and second directions may be between 0 and 10 degrees.

[0022] The embodiments disclosed herein should be understood in conjunction with the accompanying drawings, which are also considered part of the disclosure. It should be understood that the drawings of this disclosure are not drawn to scale; in fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly demonstrate the features of this disclosure.

[0023] It should be noted that the technical solutions provided in the different embodiments below can be substituted for, combined or mixed with each other to constitute another embodiment without violating the spirit of this disclosure.

[0024] Figure 1 This is a top view schematic diagram of a substrate structure according to an embodiment of the present disclosure.

[0025] In one embodiment of this disclosure, the electronic device may include a substrate structure 1, such as Figure 1 As shown, the substrate structure 1 may include: a substrate 11; a first conductive layer 12 disposed on the substrate 11 and including a first common electrode line 121; and a second conductive layer 13 disposed on the first conductive layer 12 and including a second common electrode line 131, wherein the first common electrode line 121 and the second common electrode line 131 partially overlap in the normal direction Z of the substrate 11.

[0026] In one embodiment of this disclosure, such as Figure 1 As shown, the substrate structure 1 may include a circuit element 14 disposed in the peripheral region B on the substrate 11. For example, the circuit element 14 may be an integrated circuit (IC), and the circuit element 14 may be electrically connected to the first common electrode line 121 and the second common electrode line 131, thereby transmitting a common signal to the first common electrode line 121 and the second common electrode line 131. In one embodiment of this disclosure, as... Figure 1 As shown, the substrate structure 1 may include an active region AA and a peripheral region B, wherein the peripheral region B surrounds the active region AA. In the active region AA, a first common electrode line 121 may extend along a first direction Y, and a second common electrode line 131 may extend along a second direction X, wherein the first direction Y is different from the second direction X. For example, the first direction Y may be perpendicular to the second direction X, but this disclosure is not limited thereto. Circuit elements 14 may be disposed in the peripheral region B. In one embodiment of this disclosure, as... Figure 1 As shown, the first conductive layer 12 may include multiple first common electrode lines 121, which can be electrically connected to the circuit element 14 via a conductor L1 disposed in the peripheral region B. Similarly, the second conductive layer 13 may include multiple second common electrode lines 131, which can be electrically connected to the circuit element 14 via a conductor L2 disposed in the peripheral region B, but this disclosure is not limited thereto. In other embodiments, although not shown in the figures, the multiple first common electrode lines 121 and / or the multiple second common electrode lines 131 can be directly electrically connected to the circuit element 14 without the need for conductors L1 and / or L2. According to some embodiments, at least a portion of the multiple first common electrode lines 121 is disposed in the active region AA, and at least a portion of the multiple second common electrode lines 131 is disposed in the active region AA.

[0027] According to other embodiments, although not shown in the figures, the circuit element 14 may not be disposed on the substrate 11, but may be disposed outside the substrate 11.

[0028] This disclosure reduces trace resistance and thus stabilizes the signal by using a first common electrode line 121 and a second common electrode line 131. The detailed features of the first common electrode line 121 and the second common electrode line 131 will be described in detail below.

[0029] Figure 2A and Figure 2B This is a top view schematic diagram of a partial substrate structure according to an embodiment of the present disclosure. Figure 2C for Figure 2A A cross-sectional view of line segment A-A'. Figure 2A and Figure 2B Can be regarded as Figure 1 Enlarged portion (e.g.) Figure 1 (at the dotted line), and Figure 2A and Figure 2B They are the same, but for the sake of explanation, Figure 2B Some components have been omitted. Figure 2A There is a display pixel electrode 15. Figure 2B Pixel electrode 15 is not shown.

[0030] In one embodiment of this disclosure, such as Figure 2A and Figure 2BAs shown, the second common electrode line 131 has a first portion 131A and a second portion 131B. In the first direction Y, the width W1 of the first portion 131A is greater than the width W2 of the second portion 131B. According to some embodiments, such as... Figure 2A As shown, the width W1 of the first portion 131A can be the minimum width of the first portion 131A, and the width W2 of the second portion 131B can be the minimum width of the second portion 131B. According to some embodiments, the width W1 of the first portion 131A can be measured at the center position of the first portion 131A, and the width W2 of the second portion 131B can be measured at the center position of the second portion 131B. According to some embodiments, the width W2 of the second portion 131B can be measured at the portion overlapping with the gate line 122. According to some embodiments, the width W2 of the second portion 131B can be measured at the portion overlapping with the first common electrode line 121.

[0031] In detail, the second common electrode line 131 includes multiple first portions 131A and multiple second portions 131B, which are staggered and connected to each other. That is, the arrangement order of the second common electrode line 131 in the second direction X is...first portion 131A, second portion 131B, first portion 131A, second portion 131B... and so on. Figure 2A As shown, in the second direction X, a first portion 131A is disposed and connected between two adjacent second portions 131B. In the second direction X, a second portion 131B is disposed and connected between two adjacent first portions 131A. The first portion 131A can be referred to as an enlarged portion, and the area of ​​the first portion 131A is larger than that of the second portion 131B. Compared to the second portion 131B, the width of the first portion 131A in the first direction Y is larger. In one embodiment of this disclosure, as... Figure 2A As shown, in the normal direction Z of the substrate 11, the first common electrode line 121 and the second portion 131B of the second common electrode line 131 at least partially overlap. In other words, in the normal direction Z of the substrate 11, the first common electrode line 121 extending along the first direction Y and the second portion 131B of the second common electrode line 131 (131B extends along the second direction X) are intersecting.

[0032] In one embodiment of this disclosure, such as Figure 2A and Figure 2C As shown, the substrate structure 1 may include a pixel electrode 15, at least a portion of which is disposed on the second conductive layer 13. In the normal direction Z of the substrate 11, the pixel electrode 15 partially overlaps with the second common electrode line 131. More specifically, in the normal direction Z of the substrate 11, a portion of the pixel electrode 15 overlaps with a first portion 131A of the second common electrode line 131.

[0033] In one embodiment of this disclosure, such as Figure 2A and Figure 2B As shown, the first conductive layer 12 further includes a gate line 122 extending along a first direction Y, wherein the gate line 122 is electrically insulated from the first common electrode line 121. The first conductive layer 12 may also include a first gate 123 and a second gate 124 extending along a second direction X, wherein the first gate 123 and the second gate 124 are electrically connected to the gate line 122. The gate line 122 can transmit gate signals to the first gate 123 and the second gate 124. Figure 2A As shown, the second portion 131B of the second common electrode line 131 extending along the second direction X can also be interleaved on the gate line 122. The first conductive layer 12 may include multiple first common electrode lines 121 and multiple gate lines 122. In the second direction X, the first common electrode lines 121 and gate lines 122 can be interleaved; in other words, one gate line 122 can be disposed between two first common electrode lines 121. The gate line 122 can be electrically connected to a gate driver (not shown), and the gate driver can provide a signal to the gate line 122. The gate driver (not shown) can be disposed in the peripheral region B (e.g., Figure 1 (As shown)

[0034] In one embodiment of this disclosure, such as Figure 2A and Figure 2B As shown, the second conductive layer 13 further includes a data line 132 extending along the second direction X, wherein the data line 132 is electrically insulated from the second common electrode line 131. The second conductive layer 13 may also include a first source 133, a first drain 134, a second source 135, and a second drain 136, wherein the first source 133 is electrically connected to the data line 132, and the second drain 136 is electrically connected to the pixel electrode 15. The data line 132 can transmit data signals to the first source 133. Figure 2A and Figure 2B As shown, data lines 132 extending along the second direction X can be interleaved on the first common electrode line 121 and the gate line 122. The second conductive layer 13 may include multiple second common electrode lines 131 and multiple data lines 132. In the first direction Y, the second portion 131B of the second common electrode line 131 and the data line 132 can be interleaved; in other words, one data line 132 can be disposed between the second portions 131B of two second common electrode lines 131. The data line 132 can be electrically connected to a data driver (not shown), and the data driver can provide signals to the data line 132. The data driver (not shown) can be disposed in the peripheral area B (e.g., Figure 1 (As shown)

[0035] In one embodiment of this disclosure, such as Figure 2C As shown, substrate structure 1 further includes a first semiconductor 161 and a second semiconductor 162 disposed on the first conductive layer 12, wherein a first source 133 and a first drain 134 are electrically connected to the first semiconductor 161, and a second source 135 and a second drain 136 are electrically connected to the second semiconductor 162. The first gate 123, the first source 133, the first drain 134, and the first semiconductor 161 can form a first transistor TFT1, and the second gate 124, the second source 135, the second drain 136, and the second semiconductor 162 can form a second transistor TFT2. In one embodiment of this disclosure, the first transistor TFT1 and the second transistor TFT2 can be connected in series. More specifically, the first drain 134 can extend and connect to the second source 135, thereby electrically connecting the first transistor TFT1 and the second transistor TFT2. The transistors in the figures are merely illustrative, and the invention is not limited thereto. According to some embodiments, the number of transistors in substrate structure 1 is not limited; it may include only one transistor or more transistors. Figure 2C As shown, the first conductive layer 12 (or the first gate 123) is disposed between the substrate 11 and the first semiconductor 161, thereby constituting a bottom gate type transistor. According to other embodiments, although not shown in the figure, the first semiconductor 161 may be disposed between the substrate 11 and the first conductive layer 12 (or the first gate 123), thereby constituting a top gate type transistor.

[0036] In one embodiment of this disclosure, such as Figure 2A and Figure 2B As shown, the first conductive layer 12 may further include a conductive block 125, wherein the conductive block 125 is electrically insulated from the first common electrode line 121. In one embodiment of this disclosure, as... Figure 2A and Figure 2C As shown, the pixel electrode 15 can be electrically connected to the conductive block 125 through a first through-hole H1. More specifically, the substrate structure 1 may include: a first insulating layer 101 disposed on a first conductive layer 12; a second insulating layer 102 disposed on a second conductive layer 13; and a third insulating layer 103 disposed on the second insulating layer 102, wherein the first insulating layer 101 includes a through-hole 1011, the second insulating layer 102 includes a through-hole 1021, and the third insulating layer 103 includes a through-hole 1031. The through-holes 1011, 1021, and 1031 form the first through-hole H1, and the pixel electrode 15 is electrically connected to the conductive block 125 through the first through-hole H1. According to some embodiments, the substrate structure 1 may not have the conductive block 125, may not have the first through-hole H1, and the pixel electrode 15 may not need to be directly connected to the first conductive layer 12. According to some embodiments, such as Figure 2AAs shown, the pixel electrode 15 may not overlap with the first common electrode line 121. Alternatively, according to some embodiments (not shown in the figures), the pixel electrode 15 may partially overlap with the first common electrode line 121.

[0037] In one embodiment of this disclosure, such as Figure 2A and Figure 2C As shown, the pixel electrode 15 can be electrically connected to the second drain 136 through a second through-hole H2. More specifically, the second insulating layer 102 includes a through-hole 1022, and the third insulating layer 103 includes a through-hole 1032. The through-hole 1022 and the through-hole 1032 form the second through-hole H2, and the pixel electrode 15 is electrically connected to the second drain 136 through the second through-hole H2.

[0038] In one embodiment of this disclosure, such as Figures 2A to 2C As shown, in the normal direction Z of the substrate 11, the conductive block 125 and the second common electrode line 131 partially overlap to form a first capacitor Cst1, and the pixel electrode 15 and the second common electrode line 131 partially overlap to form a second capacitor Cst2. The overlapping portions of the conductive block 125 and the second common electrode line 131 can be used as capacitor electrodes of the first capacitor Cst1, and the overlapping portions of the pixel electrode 15 and the second common electrode line 131 can be used as capacitor electrodes of the second capacitor Cst2.

[0039] In this disclosure, the substrate 11 may be a rigid substrate or a flexible substrate. Suitable materials may include glass, quartz, sapphire, ceramics, plastics, organic materials, inorganic materials, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), polymethyl methacrylate (PMMA), other suitable materials, or combinations of the above materials, but this disclosure is not limited thereto.

[0040] In this disclosure, the materials of the first conductive layer 12 and the second conductive layer 13 may each comprise suitable metallic materials, such as gold, silver, copper, palladium, platinum, ruthenium, aluminum, cobalt, nickel, titanium, molybdenum, manganese, tungsten, alloys of the above, or combinations thereof, but this disclosure is not limited thereto. In this disclosure, the material of the pixel electrode 15 may comprise a transparent conductive material, such as indium zinc oxide (IZO), indium tin oxide (ITO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), aluminum zinc oxide (AZO), or combinations thereof, but this disclosure is not limited thereto.

[0041] In this disclosure, the materials of the first semiconductor 161 and the second semiconductor 162 may each comprise amorphous silicon, polycrystalline silicon (e.g., low-temperature polycrystalline silicon (LTPS)), or oxide semiconductors, such as metal oxides (e.g., indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), or indium gallium tin zinc oxide (IGTZO)), but this disclosure is not limited thereto. In one embodiment of this disclosure, the first semiconductor 161 and the second semiconductor 162 may selectively comprise doping carriers, such as N-type carriers or P-type carriers, thereby forming a doped N-semiconductor or a doped P-semiconductor, but this disclosure is not limited thereto.

[0042] In this disclosure, the materials of the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may each be inorganic materials, organic materials, or combinations thereof. For example, the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may each comprise silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, aluminum oxide, or combinations thereof, but this disclosure is not limited thereto. Suitable organic materials include acrylic acid, polyimide, benzocyclobutene resin, acrylate resin, or combinations thereof, but this disclosure is not limited thereto.

[0043] As described above, in this disclosure, by using common electrode lines extending in different directions, the resistance value of the common electrode lines can be reduced, thereby achieving the effect of stable signal transmission. Specifically, the first common electrode line 121 extends along the first direction Y, and the second common electrode line 121 extends along the second direction X, which can reduce the resistance value of the traces, achieve the effect of stable signal transmission, and thus improve the display quality of the electronic device.

[0044] Figures 3A to 3C This is a top view schematic diagram of a partial substrate structure according to an embodiment of the present disclosure. Figure 3D for Figure 3A A cross-sectional view of line segment B-B'. Wherein, Figures 3A to 3C Can be regarded as Figure 1 Enlarged portion (e.g.) Figure 1 (at the dotted line), and Figures 3A to 3C They are the same, but for the sake of explanation, Figures 3A to 3C Some components have been omitted.

[0045] like Figure 3A and Figure 3D As shown, the substrate structure 1 further includes a third conductive layer 17, which is disposed between the first conductive layer 12 and the second conductive layer 18. For ease of explanation, Figure 3A Only the first conductive layer 12 and the third conductive layer 17 are shown; the second conductive layer 18 is not shown. This is for ease of explanation. Figure 3B Only the first conductive layer 12 and the second conductive layer 18 are shown; the third conductive layer 17 is not shown. This is for ease of explanation. Figure 3COnly the second conductive layer 18 and the third conductive layer 17 are shown; the first conductive layer 12 is not shown. Figure 3A and Figure 3D There is a display pixel electrode 15. Figure 3B and Figure 3C Pixel electrode 15 is not shown.

[0046] In one embodiment of this disclosure, such as Figures 3B to 3D As shown, the second common electrode line 181 has a first portion 181A and a second portion 181B. In the first direction Y, the width W5 of the first portion 181A is greater than the width W6 of the second portion 181B. According to some embodiments, such as... Figure 3B As shown, the width W5 of the first portion 181A can be the minimum width of the first portion 181A, and the width W6 of the second portion 181B can be the minimum width of the second portion 181B. According to some embodiments, the width W5 of the first portion 181A can be measured at the center position of the first portion 181A, and the width W6 of the second portion 181B can be measured at the center position of the second portion 181B. According to some embodiments, the width W6 of the second portion 181B can be measured at the portion overlapping with the gate line 122.

[0047] In detail, the second common electrode line 181 includes multiple first portions 181A and multiple second portions 181B, which are staggered and connected to each other. That is, the arrangement order of the second common electrode line 181 in the second direction X is...first portion 181A, second portion 181B, first portion 181A, second portion 181B... and so on. Figure 3B As shown, in the second direction X, a first portion 181A is disposed and connected between two adjacent second portions 181B. In the second direction X, a second portion 181B is disposed and connected between two adjacent first portions 181A. The first portion 181A can be referred to as an enlarged portion, and the area of ​​the first portion 181A is larger than that of the second portion 181B. Compared to the second portion 181B, the width of the first portion 181A in the first direction Y is larger.

[0048] In one embodiment of this disclosure, such as Figure 3A and Figure 3B As shown, the first common electrode line 121 has a third portion 121A and a fourth portion 121B. In the second direction X, the width W3 of the third portion 121A is greater than the width W4 of the fourth portion 121B. According to some embodiments, such as... Figure 3AAs shown, the width W3 of the third part 121A can be the minimum width of the third part 121A, and the width W4 of the fourth part 121B can be the minimum width of the fourth part 121B. According to some embodiments, the width W3 of the third part 121A can be measured at the center position of the third part 121A, and the width W4 of the fourth part 121B can be measured at the center position of the fourth part 121B. Although Figure 3B Not shown, according to some embodiments, the width of the first portion 181A in the second direction X can be relatively... Figure 3B The value shown is small. Specifically, along the second direction X, the first portion 181A includes two opposing sides 185s and 186s. Side 185s can be separated from the fourth portion 121B of the first common electrode line 121; that is, the first portion 181A of the second common electrode line 181 may not overlap with the fourth portion 121B of the first common electrode line 121, and the second portion 181B of the second common electrode line 181 may overlap with the fourth portion 121B of the first common electrode line 121. In this case, the width W6 of the second portion 181B of the second common electrode line 181 can be measured at the portion overlapping with the fourth portion 121B of the first common electrode line 121.

[0049] In detail, such as Figure 3A As shown, the first common electrode line 121 includes multiple third portions 121A and multiple fourth portions 121B, which are staggered and connected to each other. That is, the arrangement order of the first common electrode line 121 in the first direction Y is… third portion 121A, fourth portion 121B, third portion 121A, fourth portion 121B… and so on. Figure 3A As shown, in the first direction Y, a third portion 121A is disposed and connected between two adjacent fourth portions 121B. In the first direction Y, a fourth portion 121B is disposed and connected between two adjacent third portions 121A. The third portion 121A can be referred to as an enlarged portion, and the area of ​​the third portion 121A is larger than that of the fourth portion 121B. Compared to the fourth portion 121B, the width of the third portion 121A in the second direction X is larger. In one embodiment of this disclosure, as... Figure 3B As shown, in the normal direction Z of the substrate 11, the third portion 121A of the first common electrode line 121 and the first portion 181A of the second common electrode line 181 at least partially overlap.

[0050] In one embodiment of this disclosure, such as Figure 3A and Figure 3DAs shown, the substrate structure 1 may include a pixel electrode 15, at least a portion of which is disposed on the second conductive layer 18. In the normal direction Z of the substrate 11, the pixel electrode 15 partially overlaps with the second common electrode line 181. More specifically, in the normal direction Z of the substrate 11, the pixel electrode 15 overlaps with a first portion 181A of the second common electrode line 181.

[0051] In one embodiment of this disclosure, such as Figure 3A and Figure 3B As shown, the first conductive layer 12 further includes a gate line 122 extending along a first direction Y, wherein the gate line 122 is electrically insulated from the first common electrode line 121. The first conductive layer 12 may also include a first gate 123 and a second gate 124 extending along a second direction X, wherein the first gate 123 and the second gate 124 are electrically connected to the gate line 122. The gate line 122 can transmit gate signals to the first gate 123 and the second gate 124. Figure 3B As shown, the second portion 181B of the second common electrode line 181 extending along the second direction X can be intersected on the gate line 122.

[0052] In one embodiment of this disclosure, such as Figure 3A , Figure 3C and Figure 3D As shown, the third conductive layer 17 may include a data line 171 extending along the second direction X. The third conductive layer 17 may also include a first source 172, a first drain 173, a second source 174, and a second drain 175, wherein the first source 172 is electrically connected to the data line 171, and the second drain 175 is electrically connected to the pixel electrode 15. The data line 171 can transmit data signals to the first source 172. The third conductive layer 17 may also include a conductive block 176 connected to the second drain 175, wherein, in the normal direction Z of the substrate 11, the conductive block 176 at least partially overlaps with the third portion 121A of the first common electrode line 121. Figure 3A As shown, the data line 171 extending along the second direction X can be intersected on the first common electrode line 121 and the gate line 122.

[0053] In one embodiment of this disclosure, such as Figure 3DAs shown, the substrate structure 1 further includes a first semiconductor 161 and a second semiconductor 162 disposed on the first conductive layer 12. A first source 172 and a first drain 173 are electrically connected to the first semiconductor 161, and a second source 174 and a second drain 175 are electrically connected to the second semiconductor 162. The first gate 123, the first source 172, the first drain 173, and the first semiconductor 161 can form a first transistor TFT1, and the second gate 124, the second source 174, the second drain 175, and the second semiconductor 162 can form a second transistor TFT2. In one embodiment of this disclosure, the first transistor TFT1 and the second transistor TFT2 can be connected in series. More specifically, the first drain 173 can extend and connect to the second source 174, thereby electrically connecting the first transistor TFT1 and the second transistor TFT2.

[0054] Figure 3D The transistors shown are merely illustrative examples, and the invention is not limited thereto. According to some embodiments, the number of transistors in substrate structure 1 is not limited; it may include only one transistor or more. Figure 3D As shown, the first conductive layer 12 (or the first gate 123) is disposed between the substrate 11 and the first semiconductor 161, thereby constituting a bottom-gate transistor. According to other embodiments, although not shown in the figure, the first semiconductor 161 may be disposed between the substrate 11 and the first conductive layer 12 (or the first gate 123), thereby constituting a top-gate transistor.

[0055] In one embodiment of this disclosure, such as Figure 3A and Figure 3D As shown, the pixel electrode 15 can be electrically connected to the second drain 175 through a third via H3. More specifically, the substrate structure 1 may include: a first insulating layer 101 disposed on a first conductive layer 12; a second insulating layer 102 disposed on a third conductive layer 17; a third insulating layer 103 disposed on the second insulating layer 102; and a fourth insulating layer 104 disposed on the second conductive layer 18. The second insulating layer 102 includes a via 1023, the third insulating layer 103 includes a via 1033, and the fourth insulating layer 104 includes a via 1041, the vias 1023, 1033, and 1041 forming the third via H3. The pixel electrode 15 is disposed on the fourth insulating layer 104, and the pixel electrode 15 is electrically connected to the second drain 175 through the third via H3. The second conductive layer 18 does not overlap the third via H3. Figure 3C and Figure 3DAs shown, the second conductive layer 18 has a recess 183, corresponding to the location of the third via H3. Thus, the pixel electrode 15 can be electrically connected to the second drain 175 via the recess 183 of the second conductive layer 18. According to some embodiments, the recess 183 of the second conductive layer 18 can overlap the third via H3. In the first direction Y, the width of the recess 183 of the second conductive layer 18 can be greater than the width of the third via H3. According to some embodiments, the width of the third via H3 can be the width of the bottom of the third via H3, or it can be the width of the bottom of the via 1023 of the second insulating layer 102.

[0056] In one embodiment of this disclosure, such as Figures 3A to 3D As shown, in the normal direction Z of the substrate 11, the first common electrode line 121 and the conductive block 176 partially overlap to form a third capacitor Cst3, the conductive block 176 and the second common electrode line 181 partially overlap to form a fourth capacitor Cst4, and the second common electrode line 181 and the pixel electrode 15 partially overlap to form a fifth capacitor Cst5. The overlapping portions of the first common electrode line 121 and the conductive block 176 can be used as capacitor electrodes of the third capacitor Cst3, the overlapping portions of the conductive block 176 and the second common electrode line 181 can be used as capacitor electrodes of the fourth capacitor Cst4, and the overlapping portions of the second common electrode line 181 and the pixel electrode 15 can be used as capacitor electrodes of the fifth capacitor Cst5.

[0057] In this disclosure, the materials suitable for the substrate 11 are as described above and will not be repeated here. The materials suitable for the first conductive layer 12, the second conductive layer 18, and the third conductive layer 17 are as described above for the first conductive layer 12 and the second conductive layer 13 and will not be repeated here. The materials suitable for the insulating layer and the semiconductor are as described above and will not be repeated here.

[0058] Figure 4 This is an equivalent circuit diagram of an embodiment of the present disclosure.

[0059] In one embodiment of this disclosure, such as Figure 4 As shown, substrate structure 1 (as Figure 1 The image (shown) includes: a first transistor TFT1; a second transistor TFT2, wherein the first transistor TFT1 and the second transistor TFT2 are electrically connected; and a storage capacitor Cst. A gate line GL transmits a gate signal to the first transistor TFT1 and the second transistor TFT2 to control the switching of the first transistor TFT1 and the second transistor TFT2. A data line DL transmits a data signal to the pixel electrode 15 via the first transistor TFT1 and the second transistor TFT2. A first common electrode line 121 and second common electrode lines 131 and 181 respectively receive a common signal.

[0060] In one embodiment of this disclosure, when the substrate structure 1 has such Figures 2A to 2C In the structure shown, the gate line GL in the equivalent circuit diagram can be, for example, as Figure 2A and Figure 2B The gate line 122 shown can be represented by, for example, the data line DL in the equivalent circuit diagram. Figure 2A and Figure 2B The data line 132 shown, the storage capacitor Cst in the equivalent circuit diagram may include Figure 2C The first capacitor Cst1 and / or the second capacitor Cst2 are shown, but this disclosure is not limited thereto.

[0061] In one embodiment of this disclosure, when the substrate structure 1 has such Figures 3A to 3D In the structure shown, the gate line GL in the equivalent circuit diagram can be, for example, as Figure 3A and Figure 3B The gate line 122 shown can be represented by, for example, the data line DL in the equivalent circuit diagram. Figure 3A and Figure 3C The data line 171 shown, the storage capacitor Cst in the equivalent circuit diagram may include Figure 3D The third capacitor Cst3, the fourth capacitor Cst4, the fifth capacitor Cst5, or combinations thereof are shown, but this disclosure is not limited thereto.

[0062] Figure 5 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0063] In one embodiment of this disclosure, such as Figure 5 As shown, the electronic device may include: a substrate structure 1, a display layer 2, a common electrode layer 3, and a protective substrate 4. The substrate structure 1 includes an active region AA and a peripheral region B, wherein the peripheral region B may be disposed adjacent to the active region AA, for example, the peripheral region B may surround the active region AA. The display layer 2 is disposed on the substrate structure 1 and corresponds to the active region AA. The common electrode layer 3 is disposed on the display layer 2. The protective substrate 4 is disposed opposite to the substrate structure 1, wherein the display layer 2 and the common electrode layer 3 are disposed between the substrate structure 1 and the protective substrate 4. In this disclosure, the detailed structure of the substrate structure 1 may be, for example... Figures 1 to 3D As shown, it will not be described again here. The common electrode layer 3 can be electrically connected to the substrate structure 1 through a conductive element (not shown in the figure), thereby applying a voltage to the common electrode layer 3.

[0064] In one embodiment of this disclosure, such as Figure 5As shown, the display layer 2 may include an electrophoretic layer 21, which contains a plurality of charged particles 211. By applying a voltage to the substrate structure 1 and the common electrode layer 3, the plurality of charged particles 211 in the electrophoretic layer 21 can be attracted or repelled, thereby achieving the effect of displaying an image. Therefore, in one embodiment of this disclosure, the electronic device may be an electrophoretic display device, but this disclosure is not limited thereto. According to some embodiments, it may be... Figure 1 The circuit element 14 transmits a common signal to the first common electrode line 121 and the second common electrode line 131, thereby applying a voltage to the substrate structure 1. In this disclosure, the plurality of charged particles 211 may be a combination of colored particles with different charges, such as a two-color particle combination of black and white particles with different charges; a three-color particle combination of black, red, and white particles with different charges; a four-color particle combination of black, red, yellow, and white particles with different charges; a four-color particle combination of blue, red, yellow, and white particles with different charges; or a four-color particle combination of yellow, cyan, magenta, and white particles with different charges, but this disclosure is not limited thereto. The term "with different charges" may, for example, refer to particles with different charge polarities, particles with different charge magnitudes, or combinations thereof. Here, Figure 5 The electrophoretic layer 21 in the example uses a combination of two-color particles, black particles 211A and white particles 211B, with different charges, but this disclosure is not limited thereto. In one embodiment of this disclosure, the plurality of charged particles 211 may be a combination of two-color particles, black particles 211A with positive charges and white particles 211B with negative charges. In one embodiment of this disclosure, the plurality of charged particles 211 may be a combination of four-color particles, namely black particles with positive charges, red particles with positive charges, yellow particles with negative charges, and white particles with negative charges. When the plurality of charged particles 211 are a combination of two-color particles, black particles 211A and white particles 211B, the electronic device can display a black and white image; when the plurality of charged particles 211 are a combination of three-color particles or a combination of four-color particles, the electronic device can display a color image.

[0065] In this disclosure, the common electrode layer 3 can be a full-surface common electrode layer or a patterned common electrode layer. In this disclosure, the material of the common electrode layer 3 can include transparent conductive materials, such as indium zinc oxide (IZO), indium tin oxide (ITO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), aluminum zinc oxide (AZO), or combinations thereof, but this disclosure is not limited to these. In this disclosure, a material similar to substrate 11 can be used as the protective substrate 4, which will not be elaborated here. Alternatively, an organic polymer material can be used as the protective substrate 4, such as polyimide (PI), polyethylene (PE), polyvinyl chloride (PVC), polystyrene (PS), acrylic, fluorinated polymer, polyester, nylon, or other suitable organic materials, but this disclosure is not limited to these.

[0066] In one embodiment of this disclosure, such as Figure 5 As shown, the electronic device may include a circuit structure 5 disposed in the peripheral region B of the substrate structure 1, wherein the circuit structure 5 may be electrically connected to components (not shown) on the substrate structure 1, thereby transmitting drive signals to the substrate structure 1. In this disclosure, the circuit structure 5 may be, for example, a printed circuit board (PCB), a flexible printed circuit board (FPC), or a combination thereof, but this disclosure is not limited thereto.

[0067] In one embodiment of this disclosure, such as Figure 5 As shown, the electronic device may include an adhesive layer 61 disposed between the substrate structure 1 and the display layer 2, thereby bonding the substrate structure 1 and the display layer 2. In one embodiment of this disclosure, as... Figure 5 As shown, the electronic device may include an adhesive layer 62 disposed between the protective substrate 4 and the display layer 2, thereby bonding the protective substrate 4 and the display layer 2. In this disclosure, the materials of the adhesive layer 61 and the adhesive layer 62 may each include glass glue, optical glue, silicone, tape, hot melt glue, AB glue, UV-curable glue, polymer adhesive, resin or a combination thereof, but this disclosure is not limited thereto.

[0068] In one embodiment of this disclosure, such as Figure 5 As shown, the electronic device may include a protective layer 7 disposed in the peripheral region B of the substrate structure 1 and surrounding the display layer 2. The protective layer 7 can be used to prevent external air or moisture from entering the display layer 2, thereby improving the reliability of the electronic device. In one embodiment of this disclosure, as... Figure 5 As shown, the protective layer 7 can contact the sidewall 2s of the display layer 2. In this disclosure, the material of the protective layer 7 may include glass glue, optical glue, silicone, hot melt glue, AB glue, light-curing glue, polymer adhesive, resin or a combination thereof, but this disclosure is not limited thereto.

[0069] Figure 6 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0070] In one embodiment of this disclosure, such as Figure 6 As shown, the electronic device may include: a substrate structure 1, a display layer 2, a pair of side substrates 8, and a frame adhesive 9. The substrate structure 1 includes an active region AA and a peripheral region B, the peripheral region B being disposed adjacent to the active region AA, for example, the peripheral region B surrounding the active region AA. The side substrates 8 are disposed opposite to the substrate structure 1. The display layer 2 is disposed between the substrate structure 1 and the side substrates 8. The frame adhesive 9 is disposed between the substrate structure 1 and the side substrates 8 and surrounds the display layer 2. In this disclosure, the detailed structure of the substrate structure 1 may be, for example... Figures 1 to 3D As shown, it will not be described in detail here. In addition, a material similar to substrate 11 can be used as the opposite substrate 8, which will not be described in detail here.

[0071] In one embodiment of this disclosure, such as Figure 6 As shown, display layer 2 may comprise liquid crystal material. Therefore, in one embodiment of this disclosure, the electronic device may be a liquid crystal display device, but this disclosure is not limited thereto. In this disclosure, suitable liquid crystal materials include, for example, twisted nematic liquid crystal (TN LC), super twisted nematic liquid crystal (STN LC), cholesteric texture liquid crystal, polymer-stabilized cholesteric texture (PSCT), polymer-dispersed liquid crystal (PDLC), polymer network liquid crystal (PNLC), other suitable liquid crystal materials, or combinations thereof, but this disclosure is not limited thereto, and the liquid crystal material is not limited to positive or negative liquid crystal. According to some embodiments, display layer 2 may comprise liquid crystal, inorganic light emitting diode, organic light emitting diode, or a combination thereof.

[0072] In one embodiment of this disclosure, although not shown in the figures, the electronic device may optionally include a filter layer, an alignment film, a prism sheet, a polarizer, a reflector, a backlight module, other suitable elements, or combinations thereof. In one embodiment of this disclosure, the electronic device may also include a touch layer (not shown in the figures), therefore, the electronic device may be a touch display device.

[0073] In this disclosure, by setting a first common electrode line 121 and / or a second common electrode line 131, 181 with a special structural design, the resistance value of the trace can be reduced, thereby achieving the effect of stable signal transmission and improving the display quality of the electronic device.

[0074] The specific embodiments described above should be interpreted as merely illustrative and not as limiting the remainder of this disclosure in any way.

Claims

1. An electronic device, characterized in that, Include: A substrate structure comprising: One substrate; A first conductive layer is disposed on the substrate and includes a first common electrode line extending along a first direction; A second conductive layer is disposed on the first conductive layer and includes a second common electrode line extending along a second direction, the first direction being different from the second direction. In the normal direction of the substrate, the first common electrode line and the second common electrode line partially overlap. The second common electrode line has a first portion and a second portion, and in the first direction, the width of the first portion is greater than the width of the second portion. A pixel electrode, at least a portion of which is disposed on the second conductive layer, and which partially overlaps with the second common electrode line in the normal direction of the substrate.

2. The electronic device as claimed in claim 1, characterized in that, The first conductive layer further includes a gate line extending along the first direction, wherein the gate line is electrically insulated from the first common electrode line.

3. The electronic device as claimed in claim 1, characterized in that, The second conductive layer also includes a data line extending along the second direction, wherein the data line is electrically insulated from the second common electrode line.

4. The electronic device as claimed in claim 1, characterized in that, The substrate structure also includes a third conductive layer, which includes a data line extending along the second direction.

5. The electronic device as claimed in claim 4, characterized in that, The third conductive layer is disposed between the first conductive layer and the second conductive layer.

6. The electronic device as claimed in claim 5, characterized in that, The first common electrode line has a third portion and a fourth portion, wherein in the second direction, the width of the third portion is greater than the width of the fourth portion.

7. The electronic device as claimed in claim 6, characterized in that, In the normal direction of the substrate, the third portion of the first common electrode line at least partially overlaps with the first portion of the second common electrode line.

8. The electronic device as claimed in claim 1, characterized in that, In the normal direction of the substrate, the pixel electrode overlaps with the first portion of the second common electrode line.

9. The electronic device as claimed in claim 1, characterized in that, In the normal direction of the substrate, the first common electrode line and the second portion of the second common electrode line at least partially overlap.

10. The electronic device as claimed in claim 1, characterized in that, It also includes a display layer disposed on the substrate structure.

11. The electronic device as claimed in claim 10, characterized in that, The display layer includes an electrophoretic layer containing multiple charged particles.

12. The electronic device as claimed in claim 1, characterized in that, The first conductive layer includes a conductive block that is linearly insulated from the first common electrode.

13. The electronic device as claimed in claim 12, characterized in that, The pixel electrode is electrically connected to the conductive block through a first through-hole.

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