Operator compilation method and device for artificial intelligence chip, equipment and product

Abstract

The present disclosure provides an operator compilation method and device for artificial intelligence chips, equipment and products, relating to the technical field of computers, and in particular to the technical field of artificial intelligence chips. The specific implementation scheme is: obtaining the initial intermediate representation code of the to-be-compiled operator of the target artificial intelligence chip, and determining the operator type of the to-be-compiled operator based on the initial intermediate representation code; in the case where the peak register number required for executing the parallel instruction sequence in the initial intermediate representation code is greater than the preset register number, the to-be-compiled operator is reconstructed according to the operator type of the to-be-compiled operator to obtain the target intermediate representation code; and performing instruction selection and register allocation on the target intermediate representation code to generate the target machine code. The scheme of the present disclosure can effectively prevent the problem of register overflow in the operator compilation process of the artificial intelligence chip, and improves the performance of the artificial intelligence chip.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more particularly to the field of artificial intelligence chip technology, specifically to an operator compilation method, apparatus, device, and product for artificial intelligence chips. Background Technology

[0002] OpenAI Triton is a new type of AI (Artificial Intelligence) compiler. Its programming language (Triton Language) is an open-source programming language similar to Python. The goal is to provide an open-source environment for writing code quickly with higher productivity than CUDA (Compute Unified Device Architecture) and greater flexibility than other existing DSLs (Domain-Specific Languages).

[0003] However, when ported to AI chips with significantly limited register resources, the amount of data residing in the registers at the same time far exceeds the physical limit because a single core needs to process large data blocks. This forces intermediate data to overflow into low-speed global video memory, causing a serious performance bottleneck. Summary of the Invention

[0004] This disclosure provides an operator compilation method, apparatus, device, and product for artificial intelligence chips.

[0005] According to one aspect of this disclosure, an operator compilation method for artificial intelligence chips is provided, comprising: Obtain the initial intermediate representation code of the operator to be compiled of the target artificial intelligence chip, and determine the operator type of the operator to be compiled based on the initial intermediate representation code; If it is determined that the peak number of registers required to execute the parallel instruction sequence in the initial intermediate representation code is greater than the preset number of registers, the operator to be compiled is reconstructed according to the operator type of the operator to be compiled to obtain the target intermediate representation code; Instruction selection and register allocation are performed on the target intermediate representation code to generate target machine code.

[0006] According to another aspect of this disclosure, an operator compilation apparatus for artificial intelligence chips is provided, comprising: The operator type determination module is used to obtain the initial intermediate representation code of the operator to be compiled of the target artificial intelligence chip, and determine the operator type of the operator to be compiled based on the initial intermediate representation code; The intermediate representation code determination module is used to reconstruct the operator to be compiled according to the operator type of the operator to be compiled, when it is determined that the peak number of registers required to execute the parallel instruction sequence in the initial intermediate representation code is greater than the preset number of registers, so as to obtain the target intermediate representation code; The target machine code generation module is used to select instructions and allocate registers for the target intermediate representation code to generate target machine code.

[0007] According to another aspect of this disclosure, an electronic device is provided, comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the operator compilation method for artificial intelligence chips as described in any embodiment of this disclosure.

[0008] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause the computer to execute the operator compilation method for artificial intelligence chips according to any embodiment of this disclosure.

[0009] According to another aspect of this disclosure, a computer program product is provided, including a computer program / instructions that, when executed by a processor, implement the operator compilation method for artificial intelligence chips according to any embodiment of this disclosure.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0011] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein: Figure 1 This is a schematic diagram of an operator compilation method for artificial intelligence chips provided according to an embodiment of this disclosure; Figure 2 This is a schematic diagram of another operator compilation method for artificial intelligence chips provided according to an embodiment of this disclosure; Figure 3 This is a schematic diagram of another operator compilation method for artificial intelligence chips provided according to an embodiment of this disclosure; Figure 4 This is a schematic diagram comparing register usage before and after reconstruction for a pointwise operator according to an embodiment of this disclosure; Figure 5 This is a schematic diagram comparing register usage before and after reconstruction of a reduction operator according to an embodiment of the present disclosure; Figure 6 This is a schematic diagram of the structure of an operator compilation device for artificial intelligence chips according to an embodiment of this disclosure; Figure 7 This is a block diagram of an electronic device used to implement the method for operator compilation for artificial intelligence chips according to embodiments of the present disclosure. Detailed Implementation

[0012] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0013] Figure 1 This diagram illustrates an operator compilation method for artificial intelligence chips according to an embodiment of this disclosure. This embodiment is applicable to reconstructing operators of artificial intelligence chips during the compilation stage to prevent register overflow. The method can be executed by an operator compilation device for artificial intelligence chips, which can be implemented in hardware and / or software and can be configured in an electronic device. (Reference) Figure 1 The method specifically includes the following: S110. Obtain the initial intermediate representation code of the operator to be compiled of the target artificial intelligence chip, and determine the operator type of the operator to be compiled based on the initial intermediate representation code.

[0014] Specifically, the target AI chip can be a dedicated processor hardware designed specifically for performing AI tasks such as deep learning, neural network inference, or training. AI chips can employ domain-specific architectures, integrating numerous parallel computing units, high-bandwidth on-chip storage resources, and dedicated data transfer engines, aiming to efficiently handle large-scale matrix and vector operations. Compared to general-purpose central processing units, target AI chips offer significant advantages in energy efficiency and throughput, but their number of physical registers is relatively limited.

[0015] Operators to be compiled refer to basic functional units that perform specific mathematical operations in an artificial intelligence model, and are the core building blocks of neural network layers. Each operator to be compiled can correspond to an independent computational logic, such as convolution, matrix multiplication, activation function calculation, or pooling operation. During compilation, operators to be compiled are represented as source code or intermediate code snippets described in a high-level language, which the compiler needs to convert into a sequence of machine instructions that can be directly executed on the target AI chip. For example, in a convolutional layer of a residual neural network, a three-dimensional convolution operation is an operator to be compiled; in attention mechanisms, the combination of matrix multiplication and activation functions can also be considered an operator to be compiled. The computational characteristics of these operators directly determine their requirements for register resources and memory bandwidth.

[0016] The initial intermediate representation code refers to a structured sequence of low-level instructions generated by the compiler front-end after parsing the high-level source code of the operator to be compiled. It is independent of the specific hardware architecture. It preserves the logical operation relationships, data dependencies, and memory access patterns of the operator, serving as the foundational data carrier for subsequent hardware-related optimizations. In this embodiment, the initial intermediate representation code typically presents as a fully expanded parallel instruction sequence, meaning that the computation of each data point corresponds to an independent instruction block.

[0017] Operator types refer to the classification based on the logical characteristics of the data processing within the operator, mainly distinguishing whether there are dependencies between data and whether there are reduction operations. These can include pointwise operators and reduction operators. In a pointwise operator, each element of the output data depends only on the corresponding element in the input data; the data points are independent of each other, with no cross-data dependencies. For example, element-wise addition of two matrices of the same dimension and calculation of the ReLU activation function are pointwise operators. Reduction operators, on the other hand, aggregate the output data from a subset of the input data through specific mathematical operations, exhibiting clear data dependencies and reduction semantics. For example, summing all elements of a vector to obtain a scalar value and calculating the maximum value of each row of a matrix are reduction operators; these operators require maintaining intermediate accumulation states during computation.

[0018] Optionally, in this embodiment, after receiving the instruction to compile the application deployed in the target AI chip, the compiler front-end first loads the initial intermediate representation code file of the operator to be compiled. This file contains a fully expanded parallel instruction sequence generated by translating a high-level language. In this sequence, each instruction inherently records its operation type, source operand identifier, destination operand identifier, and memory access address information. The parsing module then starts a linear scan program, reading the instructions one by one, and parsing the specific opcode, source register number, destination register number, and memory address offset corresponding to the load or store instruction from the instruction structure, thus establishing a basic dataset for subsequent dependency analysis.

[0019] Furthermore, based on the extracted register read / write information, the parsing module traces the definition and usage locations of each data register and constructs an instruction dependency graph. During this graph construction process, if it is found that the destination register of a certain instruction is read again as a source register in a subsequent instruction, a directed dependency edge is established between the two instructions, representing the data flow from producer to consumer. The parsing module pays particular attention to long-distance dependency edges that cross originally independent parallel computing units, as well as convergent dependency edges where multiple different source instructions point to the same destination register. Simultaneously, the processing unit synchronously counts the opcode types appearing in the graph, highlighting aggregation operations with reduction semantics, such as accumulation, multiplication, and maximum value taking.

[0020] Furthermore, the operator type can be determined based on the graph characteristics of the constructed instruction dependency graph. For example, the constructed instruction dependency graph can be logically traversed to check for closed-loop dependency paths or many-to-one convergence structures. If the graph shows that all instruction nodes have only local, linear data transfer relationships—that is, the output of each loaded instruction is only used by the corresponding single computation instruction, and the computation result is directly sent to the corresponding storage instruction—and there are no cross-iteration data backhauls or convergence nodes in the graph, then the operator to be compiled is identified as a pointwise operator. Conversely, if the graph contains obvious convergence nodes—that is, the outputs of multiple preceding instructions are used together as the input of a certain computation instruction, or a certain register node is repeatedly read and updated to accumulate computation results—then the operator to be compiled is identified as a reduction operator.

[0021] S120. If the number of peak registers required to execute the parallel instruction sequence in the initial intermediate representation code is greater than the preset number of registers, the operator to be compiled is reconstructed according to the operator type of the operator to be compiled, and the target intermediate representation code is obtained.

[0022] Optionally, in this embodiment, after determining the operator type of the operator to be compiled, the number of peak registers required to execute the parallel instruction sequence in the initial intermediate representation code can be further determined, and the number of peak registers can be compared with the preset number of registers. If it is determined that the number of peak registers is greater than the preset number of registers, the operator to be compiled can be further reconstructed according to the operator type of the operator to be compiled, thereby obtaining the target intermediate representation code.

[0023] The peak register count refers to the maximum amount of data that needs to reside in physical registers simultaneously during the execution of the fully expanded parallel instruction sequence in the initial intermediate representation code. Because the full expansion strategy generates the computation of each data point as an independent instruction block, the compiler must allocate independent registers for all parallel intermediate results, causing register requirements to grow linearly with the amount of data. For example, if a vector addition operator contains 10,000 elements, and each element requires 3 temporary registers for computation, the peak register count could be as high as 30,000.

[0024] The preset register value refers to a threshold number of registers pre-set according to the hardware specifications of the target AI chip. It can be slightly less than or equal to the total number of physical registers actually owned by the chip, reserving a small number of registers for control flow instructions or emergency overflow handling. This value is the critical point for triggering code refactoring. When the estimated peak number of registers exceeds this threshold, it indicates that direct compilation will lead to register overflow, and an optimization and refactoring process must be initiated. For example, if a chip has 256 physical registers, the preset register value can be set to 240 or 250.

[0025] Optionally, in this embodiment, the initial intermediate representation code can be traversed to identify repetitive computation patterns generated based on the full expansion strategy. The total number of times the pattern is repeated is counted as the expansion count, and the maximum number of registers required during the execution of a single pattern is calculated. The expansion count is multiplied by the maximum number of registers to obtain the peak register count. Further, this calculated value can be compared with the preset register count of the target AI chip. Once the peak register count is detected to exceed the threshold, the reconstruction process is immediately activated, and the corresponding conversion path is selected based on the operator type determined in the previous steps.

[0026] In an optional implementation of this embodiment, when the operator type is a pointwise operator, a loop generation method based on instruction block folding can be used. For example, the fully expanded instruction sequence can be divided into multiple identical instruction blocks at a predetermined granularity, and the first instruction block is selected as the base template. Using an address calculation unit, the static address offsets of all load and store instructions in the template are parsed out and rewritten into a dynamic expression containing a loop counter through algebraic transformations, so that the address automatically increments with loop iteration. Furthermore, a loop counter clearing instruction is inserted at the beginning of the instruction stream, and a counter increment and conditional jump instruction is inserted at the end, constructing a closed loop control framework. In this way, all redundant instruction blocks in the original sequence except the first instruction block are deleted, leaving only the loop framework. Through this folding, the massive amount of intermediate data that originally needed to reside simultaneously is compressed into a small amount of data that only needs to meet the requirements of a single iteration, and the registers are repeatedly reused in multiple iterations.

[0027] In another optional implementation of this embodiment, when the operator type is a reduction operator, a loop generation method based on maintaining local memory state can be adopted. Similarly, the fully expanded sequence can be first divided into multiple iterative units and a template extracted. However, before constructing the loop body, a dedicated buffer is allocated in the on-chip high-speed memory area of ​​the target chip, and an initialization instruction is generated to clear its contents. Furthermore, the computation instructions within the template are reconstructed, severing the long dependency chains originally passed between registers. The computation logic is modified to: load the current slice data from global memory, read the accumulated intermediate results from the previous round from the on-chip buffer, perform the reduction operation, and then overwrite the new results back to the on-chip buffer. The address offset is also replaced with a dynamic expression based on the loop variable. After the loop control framework is closed, a final output instruction is appended outside the loop body to move the accumulated results in the buffer to a specified location in global memory.

[0028] For example, taking an image convolution operator as an example, the initial code uses a full unfolding strategy to process 4096 pixels. Each pixel calculation requires 5 registers, resulting in a peak register count of 20480. The target chip's preset threshold is 512. Because 20480 is much larger than 512 and the operator is point-by-point, reconstruction is triggered. The 4096 independent calculation instructions can be folded into a structure that loops 4096 times, with the address offset changed from fixed 0, 4, 8... to "i×4". After reconstruction, only 5 registers are needed to process all pixels in turn, reducing the peak register usage to 5.

[0029] Taking a batch normalization operator as an example, averaging 2048 data points would require 6144 registers under full expansion, exceeding the threshold of 512 and falling under the reduction type. During reconstruction, a 4-byte buffer is first allocated in on-chip memory and zeroed out. Within the loop, one data point is loaded for each iteration, added to the current value in the buffer, and then written back to the buffer, with the address offset varying with the loop variable. After the loop ends, the final value in the buffer is written out. This process reduces register usage from 6144 to 3, with all other states handled by on-chip memory.

[0030] S130: Select instructions and allocate registers for the target intermediate representation code to generate the target machine code.

[0031] Optionally, in this embodiment, after reconstructing the operator to be compiled according to its operator type to obtain the target intermediate representation code, instruction selection and register allocation can be further performed on the target intermediate representation code to obtain the final target machine code. The target machine code refers to the final generated instruction sequence, composed of binary opcodes and operands, which can be directly decoded and executed by the target AI chip processor. It includes specific opcodes, physical register numbers, memory address offsets, and control flow jump target addresses, and is the final product of the compilation process.

[0032] In one optional implementation of this embodiment, after reconstructing the operator to be compiled according to the operator type to obtain the target intermediate representation code, the compiler can first read the instruction set specification file of the target artificial intelligence chip and parse the abstract operations in the target intermediate representation code line by line, accurately mapping them to the specific instructions supported by the chip hardware. During the mapping process, if consecutive multiplication and addition operations are identified, the chip's built-in multiplication-addition fusion instructions can be used to replace them, effectively compressing the total number of instructions and improving pipeline throughput efficiency, generating an intermediate instruction sequence that contains hardware opcodes but whose operands are still virtual register numbers.

[0033] Furthermore, based on the loop structure characteristics generated in the above steps, the survival interval of each virtual register in a single iteration is directly calculated. Taking advantage of the fact that the length of this interval is strictly less than the total number of physical registers, a one-to-one static mapping relationship between virtual registers and physical registers is established. This skips the dynamic decision-making steps such as interference graph construction, coloring judgment, and overflow variable selection, and directly binds all virtual registers to idle physical registers. Finally, according to the chip encoding specification, the determined opcode, the bound physical register number, and the address offset are filled into a fixed binary bit field. The relative offset of the jump instruction is calculated, and all instructions are encoded into a continuous binary data stream, forming target machine code that can be directly decoded and executed by the chip.

[0034] The solution in this embodiment obtains the initial intermediate representation code of the operator to be compiled in the target artificial intelligence chip, and determines the operator type of the operator to be compiled based on the initial intermediate representation code. This helps to quickly reconstruct the operator to be compiled when it is necessary to reconstruct the compiled operator later. When it is determined that the peak number of registers required to execute the parallel instruction sequence in the initial intermediate representation code is greater than the preset number of registers, the operator to be compiled is reconstructed according to the operator type to obtain the target intermediate representation code. This allows for rapid reconstruction of the operator to be compiled to obtain the target intermediate representation code. By performing instruction selection and register allocation on the target intermediate representation code to generate the target machine code, the problem of register overflow during the operator compilation process of the artificial intelligence chip can be effectively prevented, thus improving the performance of the artificial intelligence chip.

[0035] Figure 2 This is a schematic diagram of another operator compilation method for artificial intelligence chips according to an embodiment of this disclosure. This embodiment is a further refinement of the above technical solution, and the technical solution in this embodiment can be combined with various optional solutions in one or more of the above embodiments. Figure 2 As shown, the method specifically includes the following: S210. In response to the compilation instructions for the target application of the target artificial intelligence chip, the code of the target application is parsed, each operator to be compiled in the target application is determined, and the initial intermediate representation code of each operator to be compiled is extracted respectively.

[0036] The target application is a software program deployed and running on the target AI chip, such as an inference program for image classification, object detection, or natural language processing tasks. The compilation command refers to an operation signal triggered by the development environment or command-line tools, explicitly specifying the target chip model and the application source code path, used to initiate the entire compilation process.

[0037] Optionally, in this embodiment, after receiving the compilation code containing the target AI chip identifier and the source code path of the target application, the compiler can first perform lexical analysis on the source code of the target application, dividing the character sequence into basic lexical units such as keywords, identifiers, operators, and constants; then, it constructs an abstract syntax tree based on predefined syntax rules, clearly presenting the program's function structure, control logic, and call relationships. Optionally, the compiler can traverse all nodes of the syntax tree and perform intelligent matching through a pre-set operator feature pattern library to identify all operator nodes to be compiled; for example, these nodes can be manifested as call statements to standard operators such as convolution, matrix multiplication, and activation functions in a neural network computing library, or operator declaration blocks conforming to domain-specific language specifications.

[0038] In this embodiment, for each identified operator to be compiled, its name identifier, the dimension parameters of the input and output tensors, and the description of its internal computational logic can be extracted. A dedicated front-end compilation subroutine is then invoked based on the operator type; for example, a convolution operator triggers a dedicated convolution conversion process, and a normalization operator triggers a dedicated normalization conversion process. After semantic verification, the front-end compilation subroutine converts the high-level language logic layer by layer into a structured sequence of intermediate instructions. This sequence fully preserves the original data dependencies and execution order and is organized in a fully expanded form, meaning that the calculation of each output data point corresponds to an independent set of loading, operation, and storage instructions, without introducing loop control structures. Each instruction explicitly records the operation type, virtual register number, and memory address offset. Furthermore, the initial intermediate representation code of each operator to be compiled is independently encapsulated, associated with a unique identifier and metadata information, forming a clearly structured and semantically complete set of operator code, providing a standardized and high-quality input foundation for subsequent register pressure analysis and loop reconstruction stages.

[0039] In one example of this embodiment, after receiving the compilation instructions, the compiler parses the model definition file and identifies that the model contains 49 convolution operators, 1 fully connected operator, and several activation function operators, totaling 53 operators to be compiled. For the first 3x3 convolution operator, the front-end compiler subroutine converts its high-level language description into initial intermediate representation code: this code contains a sequence of instructions for loading the input feature map and convolution kernel data, 9 multiply-accumulate operations within the sliding window, and a write-back instruction for the result. All instructions are fully expanded and arranged in the order of the output pixels, generating a total of 3072 intermediate instructions. Each instruction is clearly marked with its opcode, virtual register number, and memory address offset, and no loop control structure is introduced, completely preserving the original computational logic and data flow characteristics.

[0040] The solution in this embodiment, by parsing the source code of the target application and accurately decomposing it into independent operator units, achieves a standardized conversion from high-level application logic to an optimizable intermediate representation, significantly reducing the need for manual intervention and improving the automation level and repeatability of the compilation process.

[0041] S220. Determine the operator type of the operator to be compiled based on the initial intermediate representation code.

[0042] Optionally, after obtaining the initial intermediate representation code of each operator to be compiled, the operator type of the operator to be compiled can be further determined based on the initial intermediate representation code. Optionally, in this embodiment, determining the operator type of the operator to be compiled based on the initial intermediate representation code may include: obtaining the parallel instruction sequence in the initial intermediate representation code; the parallel instruction sequence is generated based on the full expansion strategy; determining whether there is cross-data dependency and reduction semantic operation between each input data corresponding to the parallel instruction sequence; when it is determined that there is no cross-data dependency and no reduction semantic operation between each input data corresponding to the parallel instruction sequence, the operator to be compiled is determined as a pointwise operator; when it is determined that there is cross-data dependency or reduction semantic operation between each input data corresponding to the parallel instruction sequence, the operator to be compiled is determined as a reduction operator.

[0043] In this context, the parallel instruction sequence refers to the set of instructions generated in the initial intermediate representation code by the full expansion strategy, which can be executed in parallel. The full expansion strategy completely expands the loop body, so that the computation of each data point corresponds to an independent instruction block. For example, to process vector addition with 1024 elements, 1024 sets of load, addition, and store instructions are generated, and each set of instructions processes one element independently.

[0044] Cross-data dependency refers to the existence of data transfer relationships between calculations of different data points. In other words, the calculation result of one data point is used by calculations of other data points that are not in the corresponding position. For example, in vector summation, the current accumulated value depends on the result of the previous iteration, forming a chain dependency. Reduction semantics refers to the operation of compressing multiple input data into a smaller output through aggregation operations.

[0045] In one optional implementation of this embodiment, after obtaining the initial intermediate representation code of each operator to be compiled, the parallel instruction sequence generated by the full expansion strategy is extracted from the initial intermediate representation code. Each instruction in the sequence is traversed, recording the definition and usage locations of registers, and constructing a register data flow chain. If it is detected that the input register of an instruction is written by a preceding instruction that is not adjacent or does not correspond to a data point, and the dependency path spans independent computation units, then a cross-data dependency is marked. The opcode field of the instruction sequence is simultaneously scanned and matched against a preset reduction operation feature library. If aggregation-type operation patterns such as accumulation, multiplication, taking the maximum or minimum value are identified, then a reduction semantic operation is marked.

[0046] Furthermore, the determination can be made based on the labeling results: when cross-data dependencies are not labeled and reduction semantic operations are not labeled, the operator to be compiled is determined as a pointwise operator; when cross-data dependencies are labeled or reduction semantic operations are labeled, the operator to be compiled is determined as a reduction operator. It should be noted that in this embodiment, the above process supports multiple implementation paths, including detecting dependencies based on overlapping register active regions, identifying data associations through memory address offset patterns, or matching reduction features using opcode keywords, ensuring that the classification logic is rigorous and reliable, and providing clear input for subsequent reconstruction strategies.

[0047] For example, for a 1024-dimensional vector addition operator, the extracted parallel instruction sequence contains 1024 independent instruction groups. Data dependency analysis shows that the input of the Nth addition instruction group comes only from the load instruction of this group, and the output is only written to the store instruction of this group, with no cross-group register transfer; operation semantic analysis only identifies ordinary addition opcodes. Neither analysis is marked, thus identifying it as a pointwise operator. For a 1024-dimensional vector summation operator, the outputs of all addition instructions in the instruction sequence are continuously written to the same accumulation register. Data dependency analysis detects and marks long-chain dependencies spanning all 1024 iterations; operation semantic analysis also identifies and marks the accumulation opcode, thus identifying it as a reduction operator.

[0048] The solution in this embodiment can accurately identify the inherent data dependency characteristics and computational semantic features of operators, realize automated and highly reliable classification of operator types, and provide assistance for the subsequent accurate reconstruction of each operator to be compiled.

[0049] S230. Determine the number of peak registers required to execute the parallel instruction sequence in the initial intermediate representation code.

[0050] Optionally, in this embodiment, determining the number of peak registers required to execute the parallel instruction sequence in the initial intermediate representation code may include: determining the fully expanded structure corresponding to the parallel instruction sequence, and determining the number of expansions based on the number of repeated computation units in the fully expanded structure; determining the number of registers occupied by a single expansion based on the number of registers referenced by any repeated computation unit in the fully expanded structure; and determining the number of peak registers based on the number of expansions and the number of registers occupied by a single expansion.

[0051] In a fully expanded sequence, a repeating computation unit is the smallest combination of instructions that repeats and performs the same computational logic. For example, in vector addition, each group contains a block with two load instructions, one addition instruction, and one store instruction. The number of expansions is the total number of repeating computation units appearing in the sequence, equal to the original loop iteration count. For example, 2048 elements correspond to 2048 expansions. The number of registers occupied in a single expansion is the total number of registers simultaneously active within a single repeating computation unit. For example, a unit requires 3 registers: input A, input B, and intermediate result. The peak number of registers is the sum of the register requirements of all units in the fully expanded state, i.e., the number of expansions × the number of registers occupied per expansion, for example, 2048 × 3 = 6144.

[0052] Optionally, in this embodiment, after obtaining the initial intermediate representation code of the operator to be compiled, the parallel instruction sequence in the initial intermediate representation code can be further scanned to identify the smallest repeating instruction combination, which is the repeated computation unit. For example, the identification method may include comparing whether the opcode sequences of adjacent instruction blocks are completely identical, and whether the register numbers referenced by each corresponding instruction exhibit a fixed mapping relationship. After confirming the boundary of the repeated computation unit, the entire parallel instruction sequence is divided according to the unit length, the total number of units obtained after division is counted, and this number is determined as the number of expansions.

[0053] Furthermore, any repetitive computation unit can be selected, and all instructions within it can be traversed. The source register number and destination register number appearing in each instruction can be extracted. After merging all the numbers and removing duplicates, the set of registers actually referenced by that unit can be obtained. The number of registers contained in this set is the number of registers occupied in a single expansion. Finally, the number of expansions is multiplied by the number of registers occupied in a single expansion, and the result is the peak number of registers required to execute the parallel instruction sequence.

[0054] In one example of this embodiment, taking an operator that performs exponential operations on 1024 elements as an example, its initial intermediate representation code is generated using a full expansion strategy. The parallel instruction sequence consists of 1024 computational units with identical structures arranged consecutively. Each unit contains three instructions: load, exponent calculation, and storage, and each unit uses non-overlapping registers. After identifying duplicate computational units, the number of expansions is determined to be 1024. If a unit is randomly selected, it references two non-overlapping registers, so the number of registers occupied by a single expansion is 2. Based on the characteristic that all intermediate results of all units must reside simultaneously in the full expansion mode, the peak number of registers is 1024 multiplied by 2, which equals 2048.

[0055] This embodiment's solution accurately extracts the number of repeatedly computed units and the single register usage by parsing the fully expanded structure of the parallel instruction sequence, and calculates the peak register count based on their product, thus achieving precise quantification of register resource requirements. It relies entirely on static code structure, eliminating the need for runtime sampling or empirical estimation, and avoiding optimization misjudgments caused by resource assessment biases in traditional compilers.

[0056] S240. If the number of peak registers required to execute the parallel instruction sequence in the initial intermediate representation code is greater than the preset number of registers, the operator to be compiled is reconstructed according to the operator type of the operator to be compiled, and the target intermediate representation code is obtained.

[0057] S250: Map the target intermediate representation code to the machine instruction sequence of the target artificial intelligence chip; allocate physical registers to the virtual registers in the machine instruction sequence, and encode the machine instruction sequence after register allocation into the binary machine code of the target artificial intelligence chip.

[0058] Optionally, in this embodiment, after reconstructing the operator to be compiled to obtain the target intermediate representation code, the target intermediate representation code can be further mapped to the machine instruction sequence of the target artificial intelligence chip; furthermore, physical registers are allocated to the virtual registers in the machine instruction sequence, and the machine instruction sequence after register allocation is encoded into the binary machine code of the target artificial intelligence chip. The machine instruction sequence is the result of mapping the abstract operations in the intermediate representation code to the specific hardware instructions supported by the target artificial intelligence chip. Its opcode and format conform to the chip instruction set specification, but the operands still use virtual registers. Virtual registers are an unlimited number of logical registers used by the compiler in the intermediate representation stage to represent data streams and do not correspond to real hardware resources. The binary machine code is the final binary instruction stream that can be directly decoded and executed by the target artificial intelligence chip. Each instruction is composed of fields such as opcode, physical register number, and address offset, concatenated with a fixed bit width.

[0059] In an optional implementation of this embodiment, after reconstructing the operator to be compiled to obtain the target intermediate representation code, the control flow graph of the target intermediate representation code can be traversed first. Instruction selection is performed on each operation node, and it is converted into a specific machine instruction that is semantically equivalent to the instruction set of the target artificial intelligence chip through tree pattern matching, generating a machine instruction sequence containing a definite opcode but operands that still reference virtual registers. During the matching process, if consecutive multiplication and addition operations are identified, the chip's built-in multiply-add fusion instruction is preferentially used for replacement to compress the number of instructions and improve execution efficiency. Further, the definition and usage position of all virtual registers in the machine instruction sequence are scanned to determine the active range of each virtual register in a single loop iteration. Finally, the virtual register number in each instruction is replaced with the allocated physical register number, and according to the instruction encoding specification of the target chip, the opcode field, physical register number field, memory address offset field, and jump offset field are filled into a preset binary bit width, and all instructions are concatenated in program order to generate a continuous and standardized binary machine code stream, which can be directly loaded and decoded by the chip's instruction fetch unit.

[0060] It should be noted that in this embodiment, since the preceding steps have ensured that the number of registers required for a single iteration does not exceed the total number of physical registers in the chip, each virtual register is directly and statically bound to an idle physical register in sequence, so that no overflow instruction to temporarily store data in memory is generated.

[0061] For example, a reconstructed 4096-iteration vector multiply-accumulate loop has a target intermediate representation code containing a loop body with three instructions: load, multiply-accumulate, and store, involving three virtual registers v0, v1, and v2. During the instruction selection phase, the multiply-accumulate operation is mapped to chip instructions, generating a machine instruction sequence: LOAD v0, addr; FMAC v2, v0, v1; STORE v2, addr. During the register allocation phase, analysis confirms that v0, v1, and v2 are active simultaneously in a single iteration. Since the chip provides 16 physical registers, v0 is directly allocated to R0, v1 to R1, and v2 to R2. In the binary encoding stage, the machine instruction sequence opcode is filled into the high 6 bits, R2 is filled into the destination register field, R0 and R1 are filled into the source register field, and the address offset is filled into the low 16 bits, generating a 32-bit instruction such as 101101 00010 00000 00001 00000000000000000, and finally outputting a continuous binary stream as the target machine code.

[0062] The solution in this embodiment achieves efficient conversion from high-level intermediate code to hardware executable code by accurately mapping the optimized intermediate representation to the chip's native instructions and implementing register allocation and standardized binary encoding. The entire process has low computational overhead and strong determinism, which not only ensures the correctness and execution efficiency of the generated code, but also fully leverages the hardware characteristics of the target AI chip, providing solid support for the stable and efficient operation of large-scale deep learning operators in resource-constrained environments.

[0063] Figure 3 This is a schematic diagram of another operator compilation method for artificial intelligence chips according to an embodiment of this disclosure. This embodiment is a further refinement of the above technical solution, and the technical solution in this embodiment can be combined with various optional solutions in one or more of the above embodiments. Figure 3 As shown, the method specifically includes the following: S310. Obtain the initial intermediate representation code of the operator to be compiled of the target artificial intelligence chip, and determine the operator type of the operator to be compiled based on the initial intermediate representation code.

[0064] S320. Determine that the number of peak registers required to execute the parallel instruction sequence in the initial intermediate representation code is greater than the preset number of registers.

[0065] S330. Divide the fully expanded parallel instruction sequence in the initial intermediate representation code into multiple iteration units.

[0066] Optionally, in this embodiment, after determining that the peak number of registers required to execute the parallel instruction sequence in the initial intermediate representation code is greater than the preset number of registers, the fully expanded parallel instruction sequence in the initial intermediate representation code can be further divided into multiple iteration units based on the operator type of the operator to be compiled. Then, the constant address offset in each iteration unit can be replaced with an address offset expression based on a loop variable, and a loop control flow can be constructed based on the replaced iteration units to obtain the target intermediate representation code. Here, the constant address offset is a fixed numerical offset used by memory access instructions in the fully expanded sequence, such as the load instruction access address base+0, base+4, base+8, etc. The address offset expression based on the loop variable is to rewrite the constant offset as "base address + loop variable × step size," so that the address changes dynamically with loop iteration, for example, base + i × 4.

[0067] In an optional implementation of this embodiment, after determining that the number of peak registers required to execute the parallel instruction sequence in the initial intermediate representation code is greater than the preset number of registers, the fully expanded parallel instruction sequence in the initial intermediate representation code can be further divided according to the boundaries of the repeated calculation units to obtain multiple iterative units with the same structure; wherein, the division is based on the consistency of the opcode sequence of adjacent instruction blocks and the regularity of the register usage pattern.

[0068] Optionally, in this embodiment, dividing the fully expanded parallel instruction sequence in the initial intermediate representation code into multiple iteration units may include: determining the ratio of the peak number of registers to the number of physical registers, and using a target integer greater than or equal to the ratio as a loop expansion factor; calculating the number of multiple iteration units based on the loop expansion factor, the total amount of data corresponding to the parallel instruction sequence, and the number of processing units of the target AI chip; wherein the loop expansion factor is configured such that the number of registers required for a single iteration does not exceed the number of physical registers. The target integer can be the smallest integer representing the ratio.

[0069] In this embodiment, the loop unrolling factor refers to the number of original data points processed by each iteration unit after reconstruction, used to control the loop granularity. The larger the factor, the more data is processed in a single iteration, but the required registers also increase accordingly. Its value can be set to a minimum integer not less than the "peak register count divided by the physical register count" to ensure that the register requirement for a single iteration does not exceed the physical limit. For example, if the calculated ratio is 24, then the loop unrolling factor is 24, indicating that 24 data points are processed in each loop. The total data volume refers to the total number of data elements corresponding to the parallel instruction sequence, i.e., the data scale covered by the original fully expanded structure. For example, if the vector length is 2048, then the total data volume is 2048.

[0070] In one optional implementation of this embodiment, the determined peak register count and the physical register count of the target AI chip can be read first, and the ratio of the peak register count to the physical register count can be calculated. Further, this ratio is rounded up to obtain the smallest integer greater than or equal to the ratio, and this integer is recorded as the loop unrolling factor, where the loop unrolling factor represents the number of original data points processed by each iteration unit after reconstruction. Further, it can be verified whether the number of registers required for a single iteration does not exceed the number of physical registers. If the verification result is that it exceeds the limit, the loop unrolling factor is incremented and the verification is repeated until the register constraint condition is met.

[0071] After the loop unrolling factor is determined, the total amount of data corresponding to the parallel instruction sequence and the number of processing units of the target artificial intelligence chip can be read. The result of dividing the total amount of data by the loop unrolling factor can be calculated. If there is a remainder, it can be rounded up to obtain the initial iteration number. Then, the initial iteration number is adjusted to the smallest integer that is greater than or equal to itself and can be divided by the number of processing units. Finally, the adjusted value is determined as the number of multiple iteration units.

[0072] For example, after a certain operator is fully expanded, the peak register count is 6144, and the chip's physical register count is 256. The ratio is calculated as 6144 / 256 = 24, rounded up to 24. Here, the loop expansion factor is 24, indicating that each iteration unit will process 24 original data points. Given that the original single expansion occupies 3 registers, an iteration unit processing 24 data points requires 3 × 24 = 72 registers, which is less than 256, satisfying the constraint. If the total data volume is 2048 and the number of processing units is 8, the initial number of iterations is 2048 / 24 ≈ 85.33, rounded up to 86; since 86 is not divisible by 8, it is adjusted to 96; the final number of iteration units is 96.

[0073] The solution in this embodiment ensures that the register requirements for a single iteration are strictly controlled within the physical register capacity by determining the loop unrolling factor, fundamentally avoiding the risk of register overflow. This significantly improves the compiler's adaptability to heterogeneous AI chips and the execution stability of the generated code, providing a reliable guarantee for the efficient deployment of large-scale operators with limited hardware resources.

[0074] S340. Replace the constant address offsets in each iteration unit with address offset expressions based on loop variables, and construct a loop control flow based on the replaced iteration units to obtain the target intermediate representation code.

[0075] In this embodiment, after dividing the fully expanded parallel instruction sequence in the initial intermediate representation code into multiple iteration units, all load and store instructions within each iteration unit can be further traversed. The constant offset value in the memory address field is extracted and replaced with an address offset expression consisting of a loop variable multiplied by a fixed step size. The step size is determined based on the byte size of the data element; for example, a four-byte element corresponds to a step size of four. Next, a loop variable initialization instruction is inserted at the beginning of the instruction sequence, assigning the loop variable a value of zero. An increment instruction is inserted at the end of the last iteration unit, increasing the loop variable by one each time. Then, a conditional jump instruction is inserted to determine if the loop variable is less than the total number of iteration units. If true, the jump proceeds to the beginning of the first iteration unit; otherwise, subsequent instructions are executed sequentially. Through these operations, the original fully expanded sequence without a loop structure can be converted into target intermediate representation code containing complete loop control logic.

[0076] For example, a general computational operator processing 1024 data elements initially contains 1024 groups of structurally identical instruction blocks, each with 4 instructions, for a total of 4096 instructions. The address offsets of each loaded instruction are 0, 4, 8, ..., 4092. First, the sequence is divided into iterative units of 4 instructions each, resulting in 1024 iterative units. Then, the constant value with an address offset of 4×k in the k-th unit is replaced with the expression "base address + i×4", where i is the loop variable. Next, "i=0" is inserted at the beginning of the sequence, and "i=i+1" and "if i<1024, jump to the beginning of the loop" are inserted at the end of the unit. The final generated target intermediate representation code contains only a loop body of 4 instructions and 3 loop control instructions.

[0077] The solution in this embodiment effectively eliminates the code bloat and instantaneous register resource overload problems caused by fully expanded parallel instruction sequences by reconstructing them into a compact form with cyclic control flow. This reconstruction process is entirely based on static code structure analysis and is applicable to various operators with repetitive computation patterns. It significantly improves the compiler's ability to handle large-scale data parallel tasks and lays the foundation for efficiently executing complex operators on AI chips with limited physical register resources.

[0078] S341. Replace the address offset constants of the first load instruction and the first store instruction of each iteration unit in the parallel instruction sequence with the product expression of the loop variable and the fixed step size; construct the first loop control flow based on the replaced instruction sequence.

[0079] The loop body of the first loop control flow contains a single iteration unit, and the number of iterations of the first loop control flow is equal to the number of iteration units.

[0080] Optionally, in this embodiment, the operator type can be a pointwise operator, and the parallel instruction sequence is composed of multiple calculated iterative units arranged consecutively. Each iterative unit includes: a first loading instruction, a first calculation instruction, and a first storage instruction, wherein the first loading instruction is used to load input data, the first calculation instruction is used to perform element-wise calculation, and the first storage instruction is used to store output data.

[0081] Accordingly, replacing the constant address offsets in each iteration unit with address offset expressions based on loop variables, and constructing a loop control flow based on the replaced iteration units, may include: replacing the constant address offsets of the first load instruction and the first store instruction in each iteration unit of the parallel instruction sequence with a product expression of a loop variable and a fixed step size; and constructing a first loop control flow based on the replaced instruction sequence.

[0082] In one optional implementation of this embodiment, all instructions in the parallel instruction sequence are traversed to identify the first load instruction and the first store instruction belonging to each iteration unit. For each identified load or store instruction, its memory address operand is parsed. If the operand consists of a base address register and an immediate offset, the immediate offset is extracted as an address offset constant. Further, a fixed step size can be determined according to the data type processed by the operator. For example, when the data type is a 32-bit floating-point number, the fixed step size is 4, and when the data type is a 64-bit integer, the fixed step size is 8. Each extracted address offset constant is replaced with a product expression of the loop variable and the fixed step size to form a new address calculation form, that is, the original address expression "base address + offset constant" is replaced with "base address + loop variable × fixed step size". After all replacements are completed, an assignment instruction is inserted at the beginning of the instruction sequence to initialize the loop variable to 0. An arithmetic addition instruction is inserted at the end of the instruction sequence to increment the value of the loop variable by 1 after each iteration unit is executed. Furthermore, a conditional jump instruction is inserted. This instruction reads the current value of the loop variable and compares it with the preset total number of iteration units. If the loop variable is less than the total number, the jump target points to the position of the first load instruction in the first iteration unit, causing the program to return to the beginning of the loop and continue execution. If the loop variable is greater than or equal to the total number, the jump is skipped, and subsequent instructions are executed sequentially. Through the above address expression substitution and the insertion of three control instructions, a first loop control flow that is structurally complete, semantically correct, and can be directly scheduled by the target artificial intelligence chip is constructed.

[0083] For example, a point-by-point squaring operator that processes 2048 32-bit floating-point numbers has a parallel instruction sequence consisting of 2048 consecutive iteration units. Each iteration unit contains a first load instruction, a first calculation instruction, and a first store instruction. The address offset constant for the load instruction in unit 0 is 0, for unit 1 it is 4, for unit 2 it is 8, ..., and for unit k it is 4×k. During reconstruction, firstly, the address offset constants in all first load and first store instructions are identified; based on the 32-bit floating-point data, a fixed step size of 4 is determined; each offset constant 4×k is uniformly replaced with the expression "i×4", where i is the loop variable; then, an initialization instruction "i=0" is inserted at the beginning of the instruction sequence, and an increment instruction "i=i+1" and a conditional jump instruction "if i<2048, jump to the first load instruction" are inserted at the end of the last iteration unit, thus completing the construction of the first loop control flow. This compresses the original 6144 fully expanded instructions into a loop body of 3 instructions plus 3 control instructions.

[0084] The solution in this embodiment effectively eliminates the redundancy of the fully expanded code and significantly compresses the instruction size by replacing the address offset constant with the product expression of the loop variable and the fixed step size, and constructing a first loop control flow containing initialization, increment and conditional jump instructions.

[0085] In an optional implementation of this embodiment, constructing a first loop control flow based on the replaced instruction sequence includes: generating a first loop control flow, the first loop control flow including a loop variable, a starting iteration value, a ending iteration value, and an iteration step size; setting the starting iteration value to 0, the ending iteration value to the number of multiple iteration units, and the iteration step size to 1; embedding a single iteration unit into the loop body region of the first loop control flow, wherein the loop variable is referenced in the address offset expression.

[0086] The loop variable is an integer variable that changes dynamically during the loop execution, used to index data positions or control the number of executions. For example, variable i increments from 0 to N-1 in each iteration. The initial iteration value is the initial value of the loop variable, usually set to 0, indicating that processing starts from the first data element. The termination iteration value is the boundary condition value at the end of the loop, equal to the total number of iteration units; the loop stops when the loop variable reaches this value. The iteration step size is the increment of the loop variable in each iteration, usually set to 1, indicating that data units are processed one by one.

[0087] Optionally, in this embodiment, during the construction of the first loop control flow, the control parameters of the first loop control flow can be set first: define an integer loop variable, set the initial iteration value to 0, set the final iteration value to the number of iteration units, and set the iteration step size to 1. Further, an assignment instruction is inserted at the beginning of the code in the middle of the target to initialize the loop variable to the initial iteration value of 0. Then, the single iteration unit that has completed the address offset expression replacement is placed after this assignment instruction as the content of the loop body region. An arithmetic addition instruction is inserted at the end of the single iteration unit to increase the value of the loop variable by the iteration step size of 1. Immediately following, a conditional jump instruction is inserted. This instruction reads the current value of the loop variable and compares it with the final iteration value. If the loop variable is less than the final iteration value, the jump target points to the beginning of the single iteration unit; otherwise, subsequent instructions are executed sequentially. Through the above operations, the single iteration unit is embedded into the loop body region of the first loop control flow, forming a complete loop execution structure that can be correctly scheduled by the target AI chip.

[0088] The solution in this embodiment constructs a first loop control flow that includes loop variables, starting iteration values, ending iteration values, and iteration step sizes, and embeds individual iteration units into their loop body regions, so that loop variables directly participate in the calculation of address offset expressions. This ensures the consistency between memory access and iteration logic, and effectively improves the execution efficiency and resource utilization of code generated on the target artificial intelligence chip.

[0089] S342. Create a first buffer in the on-chip storage area of ​​the target artificial intelligence chip; replace the target address of the second storage instruction in the iteration unit with the address of the first buffer; modify the second calculation instruction in the iteration unit to read the intermediate result of the previous iteration from the first buffer, perform reduction calculation with the current input data, and write the calculation result into the first buffer; construct a second loop control flow based on the replaced and modified instruction sequence.

[0090] The size of the first buffer is determined based on the loop unrolling factor and the amount of data in a single iteration unit. The loop body of the second loop control flow contains a single iteration unit, and the number of iterations of the second loop control flow is equal to the number of iteration units. The second storage instruction is the instruction in the iteration unit used to write intermediate calculation results into memory. In the reduction operator reconstruction, its target address needs to be changed from the global output address to the address of the first buffer. The second calculation instruction is the core instruction used to perform the reduction operation, such as accumulation and taking the maximum value. Its input includes the current data and the intermediate results of the previous iteration.

[0091] Optionally, in this embodiment, the operator type is a reduction operator, and the parallel instruction sequence is composed of multiple calculated iterative units arranged consecutively. Each iterative unit includes: a second loading instruction, a second calculation instruction, and a second storage instruction, wherein the second loading instruction is used to load input data, the second calculation instruction is used to perform reduction calculation, and the second storage instruction is used to store intermediate results.

[0092] Accordingly, replacing the constant address offsets in each iteration unit with address offset expressions based on loop variables, and constructing a loop control flow based on the replaced iteration units, may include: creating a first buffer in the on-chip storage area of ​​the target AI chip; replacing the target address of the second storage instruction in the iteration unit with the address of the first buffer; modifying the second calculation instruction in the iteration unit to read the intermediate result of the previous iteration from the first buffer, perform a reduction calculation with the current input data, and write the calculation result into the first buffer; and constructing a second loop control flow based on the replaced and modified instruction sequence. In an optional implementation of this embodiment, a contiguous storage space can be allocated as a first buffer in the on-chip storage region of the target AI chip. Its size is determined based on the loop unrolling factor and the amount of data processed in a single iteration, specifically the number of bytes occupied by the intermediate state data required for the reduction operation. For scalar reduction, such as summation or finding the maximum value, the buffer size is equal to the number of bytes of a single data element. Further, the target address field of the second storage instruction in the iteration unit is replaced with the physical address of the first buffer, so that the intermediate results are no longer written to the global output memory but are temporarily stored in the on-chip buffer. Simultaneously, the second calculation instruction in the iteration unit is modified, setting one source operand to data read from the first buffer and the other source operand to the input data loaded in the current iteration. After performing the reduction semantic operation, the result is written back to the first buffer, thus forming a state transfer chain. After completing the above replacements and modifications, the iteration unit is used as the loop body. Loop variable initialization instructions, increment instructions, and conditional jump instructions are inserted before and after it to construct the second loop control flow. The initial value of the loop variable is zero, the iteration step size is one, and the termination value is the number of iteration units to ensure that the number of times the loop body is executed is consistent with the original partition. The final generated target intermediate representation code maintains the reduction state between iterations through the first buffer to achieve correct cumulative calculation.

[0093] For example, a reduction operator summing 4096 32-bit floating-point numbers has a loop expansion factor of 64, resulting in 64 iteration units. The first buffer is set to 4 bytes to store the accumulated value. The original iteration unit contains instructions to load 64 data points, perform a local summation, and write the local sum to the output address. During reconstruction, the target address of the stored instructions is changed to the address of the first buffer; the summation instruction is modified to "read the current accumulated value from the first buffer, add the local sum of the current 64 elements, and write the result back to the first buffer". A second loop control flow is then constructed: i=0 initialization, the loop body executes the modified unit, and at the end, i=i+1; if i<64, the loop body is skipped. After the loop ends, the value in the first buffer is the final summation result, which can be moved to global memory by subsequent instructions.

[0094] This embodiment effectively maintains the transfer of reduction state between iterations by creating a first buffer in the on-chip storage area and redirecting intermediate result read / write operations of the reduction operator to this buffer. The buffer size is precisely determined based on the loop expansion factor and the amount of data in a single iteration, avoiding resource waste. This enables large-scale reduction calculations to be executed efficiently on AI chips with limited registers and bandwidth, improving the compiler's adaptability to reduction operators and the running efficiency of the generated code.

[0095] In an optional implementation of this embodiment, constructing a second loop control flow based on the replaced and modified instruction sequence may include: generating a second loop control flow, which includes a loop variable, a starting iteration value, a ending iteration value, and an iteration step size; setting the starting iteration value to 0, the ending iteration value to the number of multiple iteration units, and the iteration step size to 1; embedding a single iteration unit into the loop body region of the second loop control flow, wherein the loop variable is used to determine the offset position for reading data from the first buffer; and generating a reduction operation outside the second loop control flow, wherein the input of the reduction operation is all intermediate results stored in the first buffer, and the output is the final reduction result.

[0096] Optionally, in this embodiment, during the construction of the second loop control flow, an integer loop variable is first defined, and the initial iteration value is set to 0, the final iteration value is set to the number of iteration units, and the iteration step size is set to 1. An assignment instruction is inserted at the beginning of the code in the middle of the target to initialize the loop variable to 0. Further, a single iteration unit that has completed memory address redirection and computation logic modification is placed after the assignment instruction as the loop body region of the second loop control flow. When the iteration unit accesses the first buffer, its address offset is obtained by multiplying the loop variable by the number of bytes occupied by the single intermediate result, thereby ensuring that the i-th iteration... Read or write the i-th storage location in the first buffer; insert an arithmetic addition instruction at the end of a single iteration unit to increment the value of the loop variable by 1; insert a conditional jump instruction that compares the current value of the loop variable with the termination iteration value. If the loop variable is less than the termination iteration value, jump to the beginning of the single iteration unit to continue executing the loop body; otherwise, execute subsequent instructions sequentially; after all instructions in the second loop control flow, append one or more reduction operation instructions. The reduction operation takes the starting address of the first buffer and the total number of intermediate results as input, performs aggregation calculations on all intermediate results stored in the buffer, and outputs a unique final reduction result.

[0097] This embodiment constructs a second loop control flow indexed by a loop variable to determine the offset of the first buffer. This allows each iteration unit to independently write intermediate results to different locations in the buffer, eliminating data dependencies between iterations. After the loop ends, a reduction operation is performed outside the control flow to aggregate all intermediate results and generate the final output. This method decomposes large-scale reduction into two stages: parallel local reduction and small-scale final reduction. While satisfying register resource constraints, it preserves hardware parallelism, significantly reduces memory access overhead, and improves the execution efficiency and schedulability of reduction operators on AI chips.

[0098] S350: Select instructions and allocate registers for the target intermediate representation code to generate the target machine code.

[0099] In one optional implementation of this embodiment, the input tensors are first moved from the global storage area to the on-chip local storage area, with each tensor containing 32,768 data elements. Then, a load instruction moves the data from the local storage area to registers. This process employs vectorized operations to improve data throughput efficiency. When the computation task is distributed across 64 processing cores for parallel execution, the original 2048 data transfer and computation operations, if fully expanded, require 16 expansion operations to achieve load balancing.

[0100] After introducing loop control refactoring, the load instruction, vector addition calculation instruction, and store instruction are encapsulated into a single loop. Based on the hardware parallel scheduling requirements, the upper limit of loop expansion is set to 2. Combining the parallel capabilities of 64 processing cores, the total number of loop iterations is calculated to be 2048 divided by (64 multiplied by 2), resulting in 16. The loop step size is set to 1.

[0101] Accordingly, the length of the data blocks operated on by the load, compute, and store instructions is synchronously adjusted to one-sixteenth of the original length, i.e., 2048 divided by 16 equals 128. These 128 data elements are evenly distributed across 64 processing cores, allowing each core to process two data elements in a single iteration. Simultaneously, the current loop variable is embedded in the load and store instructions as an address index offset to locate the corresponding data position in the local storage area, providing explicit iterative access logic for subsequent transitions to the lower-level intermediate representation stage.

[0102] In this embodiment, for the processing of the two-dimensional reduction operator, the original intermediate representation code contains 2048 vector elements, each of which is a vector composed of 16 32-bit floating-point numbers, totaling 2048×16 data. This data is evenly distributed to 64 processing cores for execution. If loop control reconstruction is not performed, each core needs to process 32 vectors simultaneously, corresponding to occupying 32 vector registers, which puts significant pressure on register resources.

[0103] To reduce register requirements, a loop-controlled refactoring mechanism is introduced, and an additional temporary buffer, buf0, is allocated in the on-chip local storage area. First, buf0 is initialized to all zeros to store the accumulated intermediate results during the reduction process. Then, a loop structure is constructed with 16 iterations and a step size of 1. In each iteration, the current batch of data block bufi (i starting from 1) is loaded from the input data, and a reduction operation (such as summation) is performed between it and the current accumulated value in buf0. The result is then written back to buf0, overwriting the original content, thus gradually accumulating the global reduction state during the iteration process.

[0104] After the loop completes, `buf0` stores the intermediate reduction result of 128 vector elements (i.e., 128 × vector<16 × float32>). This result is then further processed outside the loop: `buf0` is divided into multiple segments, with the initial value `buf00` serving as the baseline and the remaining segments `buf0i` as input for subsequent reductions. These 128 vector elements are then evenly distributed across 64 processing cores. Within each core, a local reduction is performed on its assigned two vectors, generating 64 scalar results. Finally, a global reduction operation is performed across these 64 scalar results, outputting the final single reduced value. Throughout this process, the loop variable is used to index the data block position processed in the current iteration and ensures that `buf0` is correctly updated in each iteration, thus significantly reducing register usage while maintaining the correctness of the reduction semantics and execution efficiency.

[0105] Figure 4 This is a schematic diagram comparing register usage before and after reconstruction for a pointwise operator according to an embodiment of this disclosure; as shown. Figure 4 As shown, before loop control optimization (left side), during the execution of the point-to-point operator, each computational unit needs to independently load input data, perform computation, and store results. This results in the simultaneous use of 2048 vector registers within a computational cluster, each register being a vector type of 16 32-bit floating-point numbers, totaling 2048 × 3 vector registers. Since all operations are executed in a fully expanded manner, the register resource requirements are extremely high, making register overflow highly likely.

[0106] After introducing loop control and refactoring (right side), the original fully expanded structure is transformed into a loop containing 16 iterations, processing 128 data elements per iteration. Efficient register reuse is achieved by reusing the same set of vector registers within the loop. At this point, each computation cluster requires only 128 vector registers, each still being a vector of 16 32-bit floating-point numbers, reducing the total register requirement to one-sixteenth of the original. This optimization significantly reduces register usage, greatly reduces the risk of register overflow, and improves the schedulability and execution efficiency of the code on the target AI chip.

[0107] Figure 5 This is a schematic diagram comparing register usage before and after reconstruction of a reduction operator according to an embodiment of this disclosure; as shown. Figure 5 As shown, before loop control optimization (left side), during the execution of the reduction operator, each processing core needs to load 2048 vector elements simultaneously (each a vector composed of 16 32-bit floating-point numbers) and perform cumulative calculations, resulting in each core needing to occupy 32 16×f32 type vector registers to store intermediate results. Since all data is processed in parallel in a single operation, the register resource requirements are high.

[0108] After introducing loop control and refactoring (right side), the original fully expanded structure is transformed into a loop containing 16 iterations, processing 128 vector elements per iteration. By reusing a small number of vector registers within the loop and utilizing local storage areas to temporarily store intermediate accumulated values, efficient register reuse is achieved. Now, each core only requires two 16×f32 type vector registers to complete the computation, reducing register usage to one-sixteenth of the original. This optimization significantly reduces register pressure and effectively mitigates the risk of register overflow.

[0109] The scheme disclosed herein effectively reduces register usage in the fully expanded mode and avoids register overflow by introducing a resource-constrained loop control refactoring mechanism, thus significantly improving the execution performance of the generated code. At the same time, it supports flexible adjustment of instruction parallelism, maintaining efficient instruction pipelining and hardware resource utilization while ensuring that the physical register capacity is not exceeded. The entire refactoring process completely preserves the original computational semantics and has good portability and engineering practicality.

[0110] Figure 6 This is a schematic diagram of an operator compilation device for artificial intelligence chips provided according to an embodiment of the present disclosure. This device can execute the operator compilation method for artificial intelligence chips involved in any embodiment of the present disclosure; Reference Figure 6 An operator compilation device 600 for artificial intelligence chips includes: an operator type determination module 610, an intermediate representation code determination module 620, and a target machine code generation module 630.

[0111] The operator type determination module 610 is used to obtain the initial intermediate representation code of the operator to be compiled of the target artificial intelligence chip, and determine the operator type of the operator to be compiled based on the initial intermediate representation code; The intermediate representation code determination module 620 is used to reconstruct the operator to be compiled according to the operator type of the operator to be compiled, when it is determined that the number of peak registers required to execute the parallel instruction sequence in the initial intermediate representation code is greater than the number of preset registers, so as to obtain the target intermediate representation code; The target machine code generation module 630 is used to select instructions and allocate registers for the target intermediate representation code to generate target machine code.

[0112] In an optional implementation of this embodiment, the operator type determination module 610 includes an initial intermediate representation code acquisition submodule, which is used to parse the code of the target application in response to the compilation instructions of the target application of the target artificial intelligence chip, determine each operator to be compiled in the target application, and extract the initial intermediate representation code of each operator to be compiled.

[0113] In an optional implementation of this embodiment, the operator type determination module 610 further includes an operator type determination submodule, used to obtain the parallel instruction sequence in the initial intermediate representation code; the parallel instruction sequence is generated based on a full expansion strategy; Determine whether there are cross-data dependencies and reduction semantic operations among the input data corresponding to the parallel instruction sequence; When it is determined that there is no cross-data dependency and no reduction semantic operation between the input data corresponding to the parallel instruction sequence, the operator to be compiled is determined as a pointwise operator; When it is determined that there is a cross-data dependency or a reduction semantic operation between the input data corresponding to the parallel instruction sequence, the operator to be compiled is determined as a reduction operator.

[0114] In an optional implementation of this embodiment, the operator compilation device for artificial intelligence chips further includes: a peak register number determination module, used to determine the fully expanded structure corresponding to the parallel instruction sequence, and to determine the number of expansions based on the number of repeated computation units in the fully expanded structure; The number of registers used in a single expansion is determined based on the number of registers referenced by any repeated computation unit in the fully expanded structure. The peak number of registers is determined based on the number of expansions and the number of registers occupied by each expansion.

[0115] In an optional implementation of this embodiment, the intermediate representation code determination module 620 is specifically used to divide the fully expanded parallel instruction sequence in the initial intermediate representation code into multiple iteration units; The constant address offsets in each of the iterative units are replaced with address offset expressions based on loop variables, and a loop control flow is constructed based on the replaced iterative units to obtain the target intermediate representation code.

[0116] In an optional implementation of this embodiment, the intermediate code determination module 620 includes an iterative unit determination submodule, used to determine the ratio of the number of peak registers to the number of physical registers, and to use the smallest integer greater than or equal to the ratio as the loop expansion factor; The number of the plurality of iteration units is calculated based on the loop unrolling factor, the total amount of data corresponding to the parallel instruction sequence, and the number of processing units of the target artificial intelligence chip. The loop unrolling factor is configured such that the number of registers required for a single iteration does not exceed the number of physical registers.

[0117] In an optional implementation of this embodiment, the operator type is a pointwise operator, and the parallel instruction sequence is formed by arranging the calculated multiple iteration units consecutively. Each iteration unit includes: a first loading instruction, a first calculation instruction, and a first storage instruction, wherein the first loading instruction is used to load input data, the first calculation instruction is used to perform element-wise calculation, and the first storage instruction is used to store output data. The intermediate code determination module 620 also includes a first loop control flow construction submodule, which is used to replace the address offset constants of the first load instruction and the first store instruction of each iteration unit in the parallel instruction sequence with a product expression of a loop variable and a fixed step size. A first loop control flow is constructed based on the replaced instruction sequence, wherein the loop body of the first loop control flow contains a single iteration unit, and the number of iterations of the first loop control flow is equal to the number of the plurality of iteration units.

[0118] In an optional implementation of this embodiment, the first loop control flow construction submodule is specifically used to generate the first loop control flow, which includes a loop variable, a starting iteration value, a ending iteration value, and an iteration step size. Set the starting iteration value to 0, the ending iteration value to the number of the plurality of iteration units, and the iteration step size to 1; The single iterative unit is embedded into the loop body region of the first loop control flow, wherein the loop variable is referenced in the address offset expression.

[0119] In an optional implementation of this embodiment, the operator type is a reduction operator, and the parallel instruction sequence is formed by arranging the calculated multiple iteration units consecutively. Each iteration unit includes: a second loading instruction, a second calculation instruction, and a second storage instruction, wherein the second loading instruction is used to load input data, the second calculation instruction is used to perform reduction calculation, and the second storage instruction is used to store intermediate results. The intermediate code determination module 620 further includes a second loop control flow construction submodule, used to create a first buffer in the on-chip storage area of ​​the target artificial intelligence chip; wherein the size of the first buffer is determined based on the loop unrolling factor and the amount of data in a single iteration unit; Replace the target address of the second stored instruction in the iteration unit with the address of the first buffer; The second calculation instruction in the iterative unit is modified to read the intermediate result of the previous iteration from the first buffer, perform a reduction calculation with the current input data, and write the calculation result into the first buffer; A second loop control flow is constructed based on the replaced and modified instruction sequence, wherein the loop body of the second loop control flow contains a single iteration unit, and the number of iterations of the second loop control flow is equal to the number of the plurality of iteration units.

[0120] In an optional implementation of this embodiment, the second loop control flow construction submodule is specifically used to generate the second loop control flow, which includes a loop variable, a starting iteration value, a ending iteration value, and an iteration step size. Set the starting iteration value to 0, the ending iteration value to the number of the plurality of iteration units, and the iteration step size to 1; The single iteration unit is embedded into the loop body region of the second loop control flow, wherein the loop variable is used to determine the offset position for reading data from the first buffer; A reduction operation is generated outside the second loop control flow. The input of the reduction operation is all the intermediate results stored in the first buffer, and the output is the final reduction result.

[0121] In an optional implementation of this embodiment, the target machine code generation module 630 is specifically used to map the target intermediate representation code into a machine instruction sequence of the target artificial intelligence chip; Physical registers are allocated to the virtual registers in the machine instruction sequence, and the machine instruction sequence after register allocation is encoded into the binary machine code of the target artificial intelligence chip.

[0122] The collection, storage, use, processing, transmission, provision, and disclosure of artificial intelligence chip data involved in this technical solution comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0123] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0124] Figure 7 A schematic block diagram of an example electronic device 700 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0125] like Figure 7 As shown, device 700 includes a computing unit 701, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 702 or a computer program loaded into random access memory (RAM) 703 from storage unit 708. The RAM 703 may also store various programs and data required for the operation of device 700. The computing unit 701, ROM 702, and RAM 703 are interconnected via bus 704. Input / output (I / O) interface 705 is also connected to bus 704.

[0126] Multiple components in device 700 are connected to I / O interface 705, including: input unit 706, such as keyboard, mouse, etc.; output unit 707, such as various types of monitors, speakers, etc.; storage unit 708, such as disk, optical disk, etc.; and communication unit 709, such as network card, modem, wireless transceiver, etc. Communication unit 709 allows device 700 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0127] The computing unit 701 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 performs the various methods and processes described above, such as the operator compilation method for AI chips. For example, in some embodiments, the operator compilation method for AI chips can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 708. In some embodiments, part or all of the computer program can be loaded and / or installed on device 700 via ROM 702 and / or communication unit 709. When the computer program is loaded into RAM 703 and executed by the computing unit 701, one or more steps of the operator compilation method for AI chips described above can be performed. Alternatively, in other embodiments, computing unit 701 may be configured to perform operator compilation methods for artificial intelligence chips by any other suitable means (e.g., by means of firmware).

[0128] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include: implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0129] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0130] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0131] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0132] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0133] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is established by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service ecosystem that addresses the management difficulties and weak business scalability inherent in traditional physical hosting and VPS services. Servers can also be servers for distributed systems or servers integrated with blockchain technology.

[0134] Artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies mainly include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0135] Cloud computing refers to a technology system that enables access to a shared pool of physical or virtual resources via a network. These resources can include servers, operating systems, networks, software, applications, and storage devices, and can be deployed and managed on demand and in a self-service manner. Cloud computing technology can provide efficient and powerful data processing capabilities for applications such as artificial intelligence and blockchain, as well as for model training.

[0136] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution provided in this disclosure can be achieved, and this is not limited herein.

[0137] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An operator compilation method for artificial intelligence chips, comprising: Obtain the initial intermediate representation code of the operator to be compiled of the target artificial intelligence chip, and determine the operator type of the operator to be compiled based on the initial intermediate representation code; If it is determined that the peak number of registers required to execute the parallel instruction sequence in the initial intermediate representation code is greater than the preset number of registers, the operator to be compiled is reconstructed according to the operator type of the operator to be compiled to obtain the target intermediate representation code; Instruction selection and register allocation are performed on the target intermediate representation code to generate target machine code.

2. The method according to claim 1, wherein, The initial intermediate representation code for obtaining the operator to be compiled from the target AI chip includes: In response to the compilation instructions for the target application of the target artificial intelligence chip, the code of the target application is parsed to determine each operator to be compiled in the target application, and the initial intermediate representation code of each operator to be compiled is extracted respectively.

3. The method according to claim 1, wherein, Determining the operator type of the operator to be compiled based on the initial intermediate representation code includes: Obtain the parallel instruction sequence from the initial intermediate representation code; the parallel instruction sequence is generated based on a full expansion strategy. Determine whether there are cross-data dependencies and reduction semantic operations among the input data corresponding to the parallel instruction sequence; When it is determined that there is no cross-data dependency and no reduction semantic operation between the input data corresponding to the parallel instruction sequence, the operator to be compiled is determined as a pointwise operator; When it is determined that there is a cross-data dependency or a reduction semantic operation between the input data corresponding to the parallel instruction sequence, the operator to be compiled is determined as a reduction operator.

4. The method according to claim 1, wherein, Determining the peak number of registers required to execute the parallel instruction sequence in the initial intermediate representation code includes: Determine the fully expanded structure corresponding to the parallel instruction sequence, and determine the number of expansions based on the number of repeated computation units in the fully expanded structure; The number of registers used in a single expansion is determined based on the number of registers referenced by any repeated computation unit in the fully expanded structure. The peak number of registers is determined based on the number of expansions and the number of registers occupied by each expansion.

5. The method according to claim 1, wherein, The step of reconstructing the operator to be compiled according to the operator type to obtain the target intermediate representation code includes: The fully expanded parallel instruction sequence in the initial intermediate representation code is divided into multiple iteration units; The constant address offsets in each of the iterative units are replaced with address offset expressions based on loop variables, and a loop control flow is constructed based on the replaced iterative units to obtain the target intermediate representation code.

6. The method according to claim 5, wherein, The step of dividing the fully expanded parallel instruction sequence in the initial intermediate representation code into multiple iteration units includes: Determine the ratio of the peak register count to the physical register count, and use a target integer greater than or equal to the ratio as a loop expansion factor; The number of the plurality of iteration units is calculated based on the loop unrolling factor, the total amount of data corresponding to the parallel instruction sequence, and the number of processing units of the target artificial intelligence chip. The loop unrolling factor is configured such that the number of registers required for a single iteration does not exceed the number of physical registers.

7. The method according to claim 6, wherein, The operator type is a pointwise operator, and the parallel instruction sequence is formed by the continuous arrangement of the calculated multiple iterative units. Each iterative unit includes: a first loading instruction, a first calculation instruction, and a first storage instruction, wherein the first loading instruction is used to load input data, the first calculation instruction is used to perform element-wise calculation, and the first storage instruction is used to store output data. The step of replacing the constant address offsets in each of the iterative units with address offset expressions based on loop variables, and constructing a loop control flow based on the replaced iterative units, includes: Replace the address offset constants of the first load instruction and the first store instruction in each iteration unit of the parallel instruction sequence with a product expression of a loop variable and a fixed step size; A first loop control flow is constructed based on the replaced instruction sequence, wherein the loop body of the first loop control flow contains a single iteration unit, and the number of iterations of the first loop control flow is equal to the number of the plurality of iteration units.

8. The method according to claim 7, wherein, The construction of the first loop control flow based on the replaced instruction sequence includes: Generate the first loop control flow, which includes a loop variable, a start iteration value, a stop iteration value, and an iteration step size; Set the starting iteration value to 0, the ending iteration value to the number of the plurality of iteration units, and the iteration step size to 1; The single iterative unit is embedded into the loop body region of the first loop control flow, wherein the loop variable is referenced in the address offset expression.

9. The method according to claim 6, wherein, The operator type is a reduction operator, and the parallel instruction sequence is formed by the continuous arrangement of the calculated multiple iterative units. Each iterative unit includes: a second loading instruction, a second calculation instruction, and a second storage instruction, wherein the second loading instruction is used to load input data, the second calculation instruction is used to perform reduction calculation, and the second storage instruction is used to store intermediate results. The step of replacing the constant address offsets in each of the iterative units with address offset expressions based on loop variables, and constructing a loop control flow based on the replaced iterative units, includes: A first buffer is created in the on-chip storage area of ​​the target artificial intelligence chip; wherein the size of the first buffer is determined based on the loop unrolling factor and the amount of data in a single iteration unit; Replace the target address of the second stored instruction in the iteration unit with the address of the first buffer; The second calculation instruction in the iterative unit is modified to read the intermediate result of the previous iteration from the first buffer, perform a reduction calculation with the current input data, and write the calculation result into the first buffer; A second loop control flow is constructed based on the replaced and modified instruction sequence, wherein the loop body of the second loop control flow contains a single iteration unit, and the number of iterations of the second loop control flow is equal to the number of the plurality of iteration units.

10. The method according to claim 9, wherein, The construction of the second loop control flow based on the replaced and modified instruction sequence includes: Generate the second loop control flow, which includes a loop variable, a start iteration value, a stop iteration value, and an iteration step size; Set the starting iteration value to 0, the ending iteration value to the number of the plurality of iteration units, and the iteration step size to 1; The single iteration unit is embedded into the loop body region of the second loop control flow, wherein the loop variable is used to determine the offset position for reading data from the first buffer; A reduction operation is generated outside the second loop control flow. The input of the reduction operation is all the intermediate results stored in the first buffer, and the output is the final reduction result.

11. The method according to claim 1, wherein, The step of performing instruction selection and register allocation on the target intermediate representation code to generate target machine code includes: Map the target intermediate representation code to the machine instruction sequence of the target artificial intelligence chip; Physical registers are allocated to the virtual registers in the machine instruction sequence, and the machine instruction sequence after register allocation is encoded into the binary machine code of the target artificial intelligence chip.

12. An operator compilation device for artificial intelligence chips, comprising: The operator type determination module is used to obtain the initial intermediate representation code of the operator to be compiled of the target artificial intelligence chip, and determine the operator type of the operator to be compiled based on the initial intermediate representation code; The intermediate representation code determination module is used to reconstruct the operator to be compiled according to the operator type of the operator to be compiled, when it is determined that the peak number of registers required to execute the parallel instruction sequence in the initial intermediate representation code is greater than the preset number of registers, so as to obtain the target intermediate representation code; The target machine code generation module is used to select instructions and allocate registers for the target intermediate representation code to generate target machine code.

13. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the operator compilation method for artificial intelligence chips according to any one of claims 1-11.

14. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to execute the operator compilation method for artificial intelligence chips according to any one of claims 1-11.

15. A computer program product comprising a computer program / instructions, wherein the computer program / instructions, when executed by a processor, implement the operator compilation method for artificial intelligence chips according to any one of claims 1-11.

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