Chip defect detection method, electronic device, and computer program product

Abstract

The present disclosure provides a chip defect detection method, an electronic device and a computer program product, and relates to the technical field of computers. The method of the present disclosure comprises: recognizing a scribe lane image in a to-be-detected image of a to-be-detected chip, the scribe lane image being an image other than a sealing ring in the to-be-detected image; performing feature extraction on the scribe lane image to determine an image feature of the scribe lane image; matching the image feature of the scribe lane image with each candidate scribe lane image in a standard template library to determine a target scribe lane image in the standard template library; and performing a gray scale comparison between the scribe lane image and the target scribe lane image to determine a gray scale difference value of the scribe lane image, and determining that the to-be-detected chip has a defect when the gray scale difference value is greater than a preset threshold.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a chip defect detection method, electronic device, and computer program product. Background Technology

[0002] In the field of advanced packaging, ensuring that each chip is functionally intact and free of defects or cracks is a fundamental requirement. Traditional Automated Optical Inspection (AOI) only inspects the area within the seal ring, ignoring the area outside the seal ring (i.e., the dicing area). The pattern outside the seal ring lacks the repeatable characteristics of the chip's interior, making it impossible to use standard templates with single patterns (such as Golden patterns) for inspection. However, with the recent surge in chip prices in advanced packaging, inspection standards have become more stringent. The inspection area has expanded from inside the seal ring to the dicing area, and the integrity of the circuitry along the dicing area must be rigorously inspected. Summary of the Invention

[0003] This disclosure provides a chip defect detection method, an electronic device, and a computer program product.

[0004] According to one aspect of this disclosure, a chip defect detection method is provided, comprising: identifying a cut-out image in an image to be inspected of a chip to be inspected, wherein the cut-out image is an image other than a sealing ring in the image to be inspected; extracting features from the cut-out image to determine image features of the cut-out image; matching the image features of the cut-out image with each candidate cut-out image in a standard template library to determine a target cut-out image in the standard template library; and comparing the grayscale of the cut-out image and the target cut-out image to determine a grayscale difference value of the cut-out image, wherein when the grayscale difference value is greater than a preset threshold, it is determined that the chip to be inspected has a defect.

[0005] According to at least one embodiment of the chip defect detection method disclosed herein, the method identifies the cutting area outside the sealing ring in the image to be inspected and extracts its image features; it matches the image to be inspected with each candidate cutting area image in a standard template library, automatically selecting the most suitable target template, thus solving the problem that traditional single templates cannot effectively detect defects due to the diversity of cutting area patterns. By performing precise grayscale comparison between the image to be inspected and the target template, a defect is determined to exist when the grayscale difference exceeds a preset threshold, thereby stably and reliably capturing minute damage such as hidden cracks and edge chipping, improving the accuracy, automation level, and product yield of the detection.

[0006] According to at least one embodiment of the chip defect detection method of this disclosure, the process of constructing a standard template library includes: identifying first dicing images in silicon-through images of multiple candidate chips; extracting features from the first dicing images of multiple candidate chips to determine the image features of the first dicing images; classifying each first dicing image by pattern type based on the image features of each first dicing image to determine first dicing images of different pattern types; averaging multiple first dicing images under the same pattern type to determine a candidate dicing image corresponding to each pattern type; and constructing a standard template library containing candidate dicing images of different pattern types.

[0007] According to at least one embodiment of the chip defect detection method of this disclosure, based on the image features of each first dicing image, each dicing image is classified into pattern types to determine first dicing images of different pattern types, including: selecting one first dicing image from multiple first dicing images as a second dicing image; traversing the remaining first dicing images and performing feature matching with the second dicing image respectively to determine the matching score between the remaining first dicing images and the second dicing image; and determining the first dicing image whose matching score is greater than or equal to a target matching threshold as having the same pattern type as the second dicing image.

[0008] According to at least one embodiment of the chip defect detection method of this disclosure, averaging multiple first dicing images under the same pattern type to determine a candidate dicing image corresponding to each pattern type includes: performing an affine transformation on multiple first dicing images under the same pattern type and spatially aligning the affine transformed first dicing images; averaging the spatially aligned first dicing images to determine a candidate dicing image corresponding to each pattern type.

[0009] According to at least one embodiment of the chip defect detection method of this disclosure, after traversing the remaining first cut track images, a cut track image is re-selected from the unclassified first cut track images as the second cut track image for matching and classification, until all cut track images are classified.

[0010] According to at least one embodiment of the chip defect detection method of this disclosure, before identifying the cut path image in the image to be tested of the chip to be tested, the method includes: acquiring a partial silicon-transparent image of the chip to be tested; positioning and stitching the partial silicon-transparent images of the chip to be tested to determine the silicon-transparent image of each chip to be tested; and preprocessing the silicon-transparent images to determine the cut path image in the silicon-transparent images.

[0011] According to at least one embodiment of the chip defect detection method of this disclosure, matching the image features of the cut track image with each candidate cut track image in a standard template library to determine the target cut track image in the standard template library includes: calculating the normalized cross-correlation coefficient between the image features of the cut track image and each candidate cut track image in the standard template library, and determining the similarity score of each candidate cut track image in the standard template library; filtering each candidate cut track image in the standard template library based on the similarity score to determine the target cut track image in the standard template library.

[0012] According to at least one embodiment of the chip defect detection method of this disclosure, matching the image features of the cut track image with each candidate cut track image in a standard template library to determine the target cut track image in the standard template library includes: extracting edge features from the cut track image and each candidate cut track image in the standard template library respectively; calculating the similarity between the edge features of the cut track image and the edge features of each candidate cut track image in the standard template library to determine the similarity score of each candidate cut track image in the standard template library; and filtering each candidate cut track image in the standard template library based on the similarity score to determine the target cut track image in the standard template library.

[0013] According to at least one embodiment of the chip defect detection method of this disclosure, when the grayscale difference is greater than a preset threshold, it is determined that the chip to be detected has a defect, including: calculating the grayscale difference of corresponding pixels on the cut-out image and the target cut-out image to determine a difference image between the cut-out image and the target cut-out image; performing binarization processing on the grayscale difference in the difference image to determine that pixels in the difference image with a grayscale difference greater than a preset threshold are defective pixels; when the area of ​​the connected region of the defective pixel is greater than or equal to an area threshold, it is determined that the chip to be detected has a defect.

[0014] According to at least one embodiment of the chip defect detection method of this disclosure, when the image features of the cut track image fail to match each candidate cut track image in the standard template library, an alarm is triggered and an error report is generated.

[0015] According to at least one embodiment of the chip defect detection method of this disclosure, the number of first cut track images under the same pattern type is greater than or equal to the target number.

[0016] According to the chip defect detection method disclosed herein, feature extraction and classification of dicing patterns are performed to generate a high-quality candidate dicing pattern image (i.e., a standard template) for each pattern type, thereby solving the problem that traditional automated optical inspection technology cannot effectively detect defects due to the non-repetitive nature of dicing patterns. During inspection, the dicing pattern image is compared with the best-matching standard template, and minute defects such as hidden cracks or edge chipping are identified through precise grayscale comparison. This improves the accuracy and reliability of inspection, prevents later chip failures caused by the failure to detect early minute defects, and enhances inspection efficiency and automation.

[0017] According to another aspect of this disclosure, an electronic device is provided, comprising: a memory storing execution instructions; and a processor executing the execution instructions stored in the memory, causing the processor to perform a chip defect detection method according to any embodiment of this disclosure.

[0018] According to another aspect of this disclosure, a readable storage medium is provided, wherein executable instructions are stored therein, which, when executed by a processor, are used to implement a chip defect detection method according to any embodiment of this disclosure.

[0019] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements a chip defect detection method according to any embodiment of this disclosure.

[0020] The technical advantages of the chip defect detection method disclosed herein are at least as follows: By identifying the cutting area outside the sealing ring in the image to be inspected and extracting its image features; by matching the image to be inspected with each candidate cutting area image in the standard template library, the most suitable target template is automatically selected, solving the problem that traditional single templates cannot effectively detect defects due to the diversity of cutting area patterns. By performing precise grayscale comparison between the image to be inspected and the target template, a defect is determined when the grayscale difference exceeds a preset threshold, thereby stably and reliably capturing minute damage such as hidden cracks and edge chipping, improving the accuracy, automation level, and product yield of the detection. Attached Figure Description

[0021] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0022] Figure 1 This is a schematic diagram of the overall process of a chip defect detection method according to one embodiment of the present disclosure.

[0023] Figure 2This is a schematic flowchart of a chip defect detection method according to one embodiment of the present disclosure.

[0024] Figure 3 This is a schematic diagram of the process for constructing a standard template library in a chip defect detection method according to one embodiment of the present disclosure.

[0025] Figure 4 This is a schematic flowchart illustrating the process of determining a first kerf image of a different pattern type in a chip defect detection method according to one embodiment of the present disclosure.

[0026] Figure 5 This is a schematic flowchart illustrating the process of determining a candidate cut path image corresponding to each pattern type in a chip defect detection method according to one embodiment of the present disclosure.

[0027] Figure 6 This is a schematic flowchart illustrating the process of determining a target cut line image in a standard template library in a chip defect detection method according to one embodiment of the present disclosure.

[0028] Figure 7 This is a schematic flowchart illustrating the process of determining a target cut line image in a standard template library in a chip defect detection method according to another embodiment of the present disclosure.

[0029] Figure 8 This is a schematic flowchart illustrating the process of determining the presence of defects in a chip under test according to one embodiment of the present disclosure.

[0030] Figure 9 This is a schematic diagram of a chip defect detection method according to one embodiment of the present disclosure, including a cutting path 1, an effective area 2 inside the chip, and a seal ring line 3.

[0031] Figure 10 This is a schematic diagram illustrating the construction of a template library in a chip defect detection method according to one embodiment of the present disclosure.

[0032] Figure 11 This is a schematic structural block diagram of a chip defect detection device according to one embodiment of the present disclosure.

[0033] Figure 12 This is a schematic structural block diagram of an electronic device according to one embodiment of the present disclosure. Detailed Implementation

[0034] The present disclosure will now be described in further detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0035] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0036] The dicing areas of chips on wafers exhibit a variety of pattern features (such as straight lines, grids, irregular patterns, etc.). These patterns vary widely within a single wafer or across different batches, making it impossible to effectively inspect them using traditional single Golden templates. When conventional automated optical inspection methods are used, only defects inside the seal ring can be identified, while minute microcracks or edge chips in the dicing area cannot be detected in time. These defects may lie dormant for weeks or even months after chip packaging, gradually expanding with temperature changes and mechanical stress, ultimately causing high-value chips to suddenly fail at the customer's site.

[0037] To address this, this disclosure proposes a chip defect detection method. By identifying and extracting features from an image of the dicing area of ​​the chip to be inspected, and matching it with a standard template library containing multiple pattern types to determine the optimal comparison target, the method calculates the grayscale difference through grayscale comparison and determines the defect based on a preset threshold. This overcomes the limitation of traditional single Golden templates being unable to adapt to diverse patterns in the dicing area, and achieves accurate detection of defects such as microcracks and edge chipping in the dicing area outside the sealing ring. It can complete early warning and interception before the defect penetrates into the sealing ring, effectively avoiding sudden failures of high-value chips due to the latent expansion of dicing defects, and improving the detection coverage and reliability assurance capability of advanced packaged chips.

[0038] To facilitate description and make the technical solutions of this disclosure easier to understand, the terminology of this disclosure will be explained before describing the technical solutions of this disclosure.

[0039] A sealing ring is a closed metal structure around the chip. Its main function is to protect the internal circuitry of the chip, prevent external moisture and contaminants from entering, and ensure the long-term reliability of the chip.

[0040] A dicing track is a blank area between two adjacent chips on a wafer. After chip manufacturing is completed, the wafer is diced or cut along the dicing track to separate the entire wafer into individual chips.

[0041] The chip defect detection method disclosed herein can be deployed on an automated optical inspection server in an advanced semiconductor packaging production line. It acquires images of the wafer dicing area using a silicon-through imaging device, and the server performs image recognition, template matching, and defect determination, enabling online batch detection of defects such as hidden cracks and edge chipping in high-value BGA chips. It can also be applied to cloud-based quality inspection platforms, supporting the sharing of standard template libraries across multiple production lines and factories, and remote defect analysis, facilitating unified testing standards across regions. Furthermore, it can be embedded in terminal inspection equipment (such as portable microscopic imaging terminals) to perform rapid defect verification of individual chips during pre-shipment sampling inspections or customer return scenarios, meeting the flexibility and timeliness requirements for dicing area detection in different scenarios.

[0042] Figure 1 A schematic diagram illustrating the overall flow of a chip defect detection method according to one embodiment of this disclosure is shown. Figure 1 The method shown includes steps S110 to S140. This method can be executed by an electronic device such as a server or an automated optical inspection device.

[0043] In step S110, the cut line image in the image to be tested of the chip to be tested is identified. The cut line image is the image outside the sealing ring in the image to be tested.

[0044] The sealing ring on the wafer serves as a clear boundary between the chip's functional areas and the dicing channels. By identifying and locating the dicing channel areas outside the sealing ring, the complex global image of the wafer can be decomposed.

[0045] Preferably, the wafer is scanned using an infrared short-wave imaging module to acquire multiple local silicon-transmitted images (i.e., infrared transmission images, including images of the dicing lines) of the chip to be inspected on the wafer, with an image resolution of approximately 0.69 μm / pixels. These multiple local silicon-transmitted images are then positioned and stitched together to determine the silicon-transmitted image of the chip to be inspected. The silicon-transmitted image of the chip to be inspected is then preprocessed to obtain the image of the chip to be inspected.

[0046] In step S120, feature extraction is performed on the cutting track image to determine the image features of the cutting track image.

[0047] In actual testing scenarios on advanced semiconductor packaging production lines, wafers of the same type may be produced at different times and by different equipment, which may result in slight differences in the dicing images (such as contrast changes and minor deformations). Therefore, feature extraction is performed on the dicing images to remove interfering factors and accurately identify the characteristics of the dicing.

[0048] In step S130, the image features of the cutting path image are matched with each candidate cutting path image in the standard template library to determine the target cutting path image in the standard template library.

[0049] The aforementioned standard template library is a pre-established database that stores candidate dicing images for different pattern types in the wafer dicing area.

[0050] Preferably, the image features of the cutting path image are matched with each candidate cutting path image in the standard template library using NCC pixel grayscale and / or Shape edge features, and the candidate cutting path image with the highest matching score is selected as the target cutting path image.

[0051] In step S140, the grayscale of the cut track image and the target cut track image are compared to determine the grayscale difference between the cut track images. When the grayscale difference is greater than a preset threshold, it is determined that the chip to be detected has a defect.

[0052] Preferably, the preset threshold is ±15.

[0053] Preferably, when the cut path image fails to match each candidate cut path image in the standard template library, an alarm is triggered and an error report is generated, and the standard template library is updated.

[0054] The error report may include a timestamp, the coordinates of the chip under test, and the matching score.

[0055] Therefore, the chip defect detection method disclosed herein acquires high-resolution through-silicon images using infrared short-wave imaging and positions and stitches them together to accurately identify the dicing area outside the sealing ring. Then, feature extraction is performed on the dicing image to remove interference factors such as equipment differences and illumination variations. This image is matched with a pre-built standard template library containing various pattern types to determine the optimal target dicing image. Finally, grayscale difference is calculated through grayscale comparison, and defects are determined based on a preset threshold. Simultaneously, alarms, error report generation, and automatic template library updates are supported for matching failures. This achieves adaptive and accurate detection of diverse patterns in wafer dicing areas, effectively overcoming the limitation of traditional single Golden templates (i.e., candidate dicing images) being unable to adapt to diverse dicing pattern distributions. It enables early warning and interception before defects penetrate the sealing ring, improving the detection coverage and defect identification accuracy of advanced packaged high-value chips.

[0056] Regarding step S110, prior to identifying the cut line image in the image to be inspected of the chip to be inspected, some embodiments of this disclosure may include, for example... Figure 2 Steps S210 to S230 are shown.

[0057] In step S210, a partial silicon-through image of the chip to be tested is acquired.

[0058] The infrared short-wave imaging module scans the chip under test on the wafer to obtain multiple local through-silicon images, including images of the dicing area.

[0059] In step S220, the local silicon transmittance images of the chips to be tested are positioned and stitched together to determine the silicon transmittance image of each chip to be tested.

[0060] Multiple local silicon-through images are located and stitched together. Spatial alignment and fusion are performed using the overlapping area features between the images to determine the complete silicon-through image of the chip to be tested.

[0061] In step S230, the silicon-through image is preprocessed to determine the dicing pattern in the silicon-through image.

[0062] Preprocessing operations are performed on the complete through-silicon image, including denoising, grayscale conversion, geometric correction and / or region segmentation, to improve image quality and highlight the contrast between the sealing ring and the dicing area, ultimately obtaining the image of the chip to be inspected.

[0063] Therefore, by acquiring and stitching together local transparent silicon images, a complete view of the chip under test can be constructed, solving the problem that a single image cannot cover a large area.

[0064] Regarding step S130, the process of constructing the standard template library. In some embodiments of this disclosure, it may include, for example... Figure 3 Steps S310 to S350 are shown.

[0065] In step S310, the first dicing pattern image in the through-silicon images of multiple candidate chips is identified.

[0066] Optionally, the candidate chip is a chip without obvious defects.

[0067] In step S320, feature extraction is performed on the first cutting track images of multiple candidate chips to determine the image features of the first cutting track images.

[0068] In step S330, based on the image features of each first cutting track image, each first cutting track image is classified into pattern types to determine first cutting track images of different pattern types.

[0069] The above pattern types include pattern style, size, and texture features.

[0070] In step S340, multiple first cutting path images under the same pattern type are averaged to determine a candidate cutting path image corresponding to each pattern type.

[0071] Multiple first cutting path images under the same pattern type are averaged pixel by pixel. The gray values ​​of corresponding pixels are arithmetically averaged or weighted averaged to generate an averaged image with lower noise and stronger representativeness, namely the candidate cutting path image.

[0072] In step S350, a standard template library containing candidate cutting path images of different pattern types is constructed.

[0073] Preferably, the number of first diced images under the same pattern type is greater than or equal to the target number. When the number of first diced images under the same pattern type is less than the target number, a new wafer is scanned, and through-silicon images of candidate chips are collected. Preferably, the target number is 5.

[0074] Therefore, by analyzing dicing images of multiple candidate chips, all different pattern types are automatically identified and classified, solving the problem of dicing pattern diversity caused by wafer position differences. Averaging multiple images for each pattern type generates candidate dicing images with lower noise and greater representativeness, improving the quality and reliability of the standard template. The final standard template library covers a variety of dicing patterns.

[0075] Regarding step S330, based on the image features of each first cutting track image, each first cutting track image is classified into pattern types to determine first cutting track images of different pattern types. In some embodiments of this disclosure, this may include, for example... Figure 4 Steps S410 to S430 are shown.

[0076] In step S410, one first cutting track image is selected from multiple first cutting track images as the second cutting track image.

[0077] In step S420, the remaining first cutting path images are traversed, and feature matching is performed with the second cutting path images respectively to determine the matching score between the remaining first cutting path images and the second cutting path images.

[0078] In step S430, the first cut path image with a matching score greater than or equal to the target matching threshold is determined to be the same pattern type as the second cut path image.

[0079] Preferably, the target matching threshold is 0.95.

[0080] Preferably, after traversing the remaining first cutting path images, a new cutting path image is selected from the unclassified first cutting path images as the second cutting path image for matching and classification, until all first cutting path images are classified.

[0081] Therefore, automated grouping of cutting path images is achieved through iterative matching and classification. A second cutting path image is selected as the benchmark, and all similar first cutting path images are grouped into one category through feature matching. If there are still unclassified images after one round of traversal, a new benchmark is selected for the next round of matching, ensuring that all images can be accurately classified.

[0082] Regarding step S340, multiple first cutting path images under the same pattern type are averaged to determine a candidate cutting path image corresponding to each pattern type. In some embodiments of this disclosure, this may include, for example... Figure 5 Steps S510 to S520 are shown.

[0083] In step S510, an affine transformation is performed on multiple first cutting path images under the same pattern type, and the first cutting path images after the affine transformation are spatially aligned.

[0084] By performing affine transformations on multiple first cutting path images under the same pattern type, and calculating spatial transformation parameters using feature point matching or contour registration, pixel-level spatial alignment of each image is achieved.

[0085] In step S520, the spatially aligned first cutting path image is averaged to determine a candidate cutting path image corresponding to each pattern type.

[0086] The gray values ​​of the corresponding pixels are averaged arithmetically or by weighted average to generate a candidate cutting path image with lower noise, clearer details, and stronger representativeness.

[0087] Therefore, it can eliminate image spatial inconsistencies caused by imaging angle, position offset or slight deformation, and suppress random noise and local abnormal interference in a single image, thereby improving the accuracy and robustness of defect detection in the cutting area.

[0088] Regarding step S130, the image features of the cutting path image are matched with each candidate cutting path image in the standard template library to determine the target cutting path image in the standard template library. In some embodiments of this disclosure, it may include, for example... Figure 6 Steps S610 to S620 are shown.

[0089] In step S610, the normalized cross-correlation coefficient between the image features of the cutting path image and each candidate cutting path image in the standard template library is calculated to determine the similarity score of each candidate cutting path image in the standard template library.

[0090] In step S620, each candidate cutting path image in the standard template library is filtered based on the similarity score to determine the target cutting path image in the standard template library.

[0091] Therefore, it achieves accurate matching and adaptive filtering of the dicing pattern of the chip under test with various pattern types in the standard template library, effectively overcoming the limitation that the traditional single Golden template cannot adapt to the diverse patterns of the dicing, ensuring that the dicing image can be compared with the most similar and suitable template, and improving the accuracy of template matching and the reliability of defect judgment.

[0092] Regarding step S130, the image features of the cutting path image are matched with each candidate cutting path image in the standard template library to determine the target cutting path image in the standard template library. In some embodiments of this disclosure, it may include, for example... Figure 7 Steps S710 to S730 are shown.

[0093] In step S710, edge features are extracted from the cutting path image and each candidate cutting path image in the standard template library, respectively.

[0094] In step S720, the similarity between the edge features of the cutting track image and the edge features of each candidate cutting track image in the standard template library is calculated to determine the similarity score of each candidate cutting track image in the standard template library.

[0095] In step S730, each candidate cutting path image in the standard template library is filtered based on the similarity score to determine the target cutting path image in the standard template library.

[0096] Therefore, accurate template matching based on pattern contour structure is achieved, which effectively makes up for the shortcomings of simply relying on pixel grayscale for matching, which is easily affected by changes in illumination and contrast fluctuations. It improves the robustness to changes in the geometric shape of the cutting pattern, and ensures that the pattern type can still be accurately identified and the optimal comparison template can be determined even when there are differences in grayscale distribution. This enhances the adaptability and reliability of the defect detection system under different imaging conditions.

[0097] Regarding step S140, when the grayscale difference is greater than a preset threshold, it is determined that the chip to be tested has a defect. In some embodiments of this disclosure, it may include, for example... Figure 8 Steps S810 to S830 are shown.

[0098] In step S810, the grayscale difference between the corresponding pixels on the cutting path image and the target cutting path image is calculated to determine the difference image between the cutting path image and the target cutting path image.

[0099] A difference image is generated by calculating the grayscale difference between corresponding pixels on the cut path image and the target cut path image to quantify the degree of grayscale deviation between the two.

[0100] In step S820, the gray-level difference in the differential image is binarized to determine the pixels in the differential image whose gray-level difference is greater than a preset threshold as defective pixels.

[0101] By binarizing the differential image, pixels with grayscale differences greater than a preset threshold are accurately marked as defective pixels, effectively suppressing noise interference caused by minute grayscale fluctuations.

[0102] In step S830, when the area of ​​the connected region of the defective pixel is greater than or equal to the area threshold, it is determined that the chip to be tested has a defect.

[0103] By judging whether the area of ​​the connected region of the defective pixel reaches the area threshold, false alarms of isolated noise points are eliminated, and the chip under test is only determined to be defective when there is a significant gray-level anomaly with a certain spatial continuity.

[0104] Therefore, it achieves hierarchical judgment from pixel-level differences to regional defects, improves the accuracy of defect detection, and ensures accurate identification and reliable interception of real defects such as micro-cracks and edge chipping in the cutting area.

[0105] The technical solution of this disclosure will be further explained below with a specific implementation example.

[0106] Scan 1-2 wafers using an infrared short-wave imaging module to acquire local through-silicon images (including local images of dicing lines), with an image resolution of approximately 0.69µm / pixels. Position and align each local image, then stitch them together to form a complete through-silicon image. For example... Figure 9 As indicated by reference numeral 1, it will be as follows Figure 9 The area outside the Seal ring line shown in label 3 is defined as the cutting track.

[0107] The image to be detected is obtained from the outer region of the wafer seal ring. The acquired image is then processed by denoising, grayscale conversion, geometric correction, and region segmentation to extract the effective image (i.e., the image to be detected) of the pattern region outside the seal ring, removing background interference and the effects of wafer offset.

[0108] Feature extraction is performed on the preprocessed valid image to be detected to identify its pattern type (including pattern style, size, and texture features), and the corresponding target golden template (i.e., target cutting path image) is matched from the multi-golden template library (i.e., standard template library). If no corresponding template is matched, it is determined that the pattern type is abnormal and a detection alarm is output.

[0109] Preferably, pixel grayscale comparison is performed using NCC (Network Control Classification). Specifically, the pixel grayscale sub-template of the target golden template is invoked, and a pixel-by-pixel grayscale difference comparison algorithm is employed to calculate the grayscale difference between the image to be detected and the grayscale sub-template. A dynamic grayscale threshold is set, and when the grayscale similarity value exceeds the set threshold, the same type of golden template is marked.

[0110] Preferably, comparison is performed using shape edge features. Specifically, the edge feature sub-template of the target golden template is called, and the edge features of the image to be detected and the edge sub-template are extracted using the Canny edge detection algorithm. The edge similarity between the two is calculated, and an edge similarity threshold is set. When the edge similarity is higher than the threshold, the same type of golden template is marked.

[0111] The two matching methods described above can be used in combination, or only one of them can be used, depending on the characteristics of the image to be detected. When used in combination, the similarity between the image to be detected and the target Golden template in terms of overall grayscale distribution is calculated using the NCC algorithm. At the same time, the Canny algorithm is used to extract the contour edges of the two images and calculate the similarity of the edge structures. The two matching scores are then weighted and fused to obtain a comprehensive matching score. Only when the comprehensive matching score exceeds a preset threshold are the two images determined to be of the same type.

[0112] In one specific embodiment, such as Figure 10 As shown, in the image to be matched (i.e., the first cut-out image), a candidate chip pattern (i.e., the second cut-out image or the initial chip pattern) is selected and defaults to the first Golden template in the Golden template library (i.e., the initial Golden template). The same identification and matching operation is performed on the remaining chip images. If the matching score is greater than a set threshold (e.g., 0.95), the chip is considered to be in the same category and removed from the matching group. After the first round of identification and matching, a chip image is taken from the matching group and used as the second Golden template. The process for the first Golden template is repeated until all chip images to be matched are assigned to the template library, i.e., the matching group is empty. The matching accuracy is then confirmed by personnel; if any abnormalities are found, the grouping is adjusted.

[0113] Preferably, when the cutting pattern image of the subsequent image to be detected is matched and identified with the standard template library, if the matching score is lower than the threshold (e.g., 0.5), an alarm is triggered and a log is recorded, indicating that a new cutting pattern has appeared and the Golden template library needs to add a new set of Golden images.

[0114] Preferably, a standard Golden image (i.e., candidate dicing image) can be generated once the number of chips in each type of Golden group exceeds 5. If the number is insufficient, a new wafer is scanned and chip images are collected.

[0115] In one specific embodiment, the cut path image of the image to be detected is localized and affine-aligned. The processed image to be detected is then matched with a multi-golden template library, and the Golden template with the highest matching value is selected as the target Golden template. If the highest matching value is lower than a threshold, the multi-golden template library is updated. Finally, the cut path image and the adapted target Golden template are compared in grayscale. If the grayscale difference exceeds a preset threshold (±15), it is judged as a defect.

[0116] Based on any of the above embodiments, this disclosure also provides a chip defect detection device.

[0117] Figure 11 This is a schematic block diagram of a chip defect detection device according to one embodiment of the present disclosure.

[0118] like Figure 11 As shown, the chip defect detection device includes: The image recognition module 1102 identifies the cutting path image in the image to be tested of the chip to be tested. The cutting path image is the image outside the sealing ring in the image to be tested. Feature extraction module 1104 extracts features from the cutting path image to determine the image features of the cutting path image; The image matching module 1106 matches the image features of the cutting path image with each candidate cutting path image in the standard template library to determine the target cutting path image in the standard template library. The defect detection module 1108 compares the grayscale of the cut path image with the target cut path image to determine the grayscale difference between the cut path images. When the grayscale difference is greater than a preset threshold, it is determined that there is a defect in the chip to be detected.

[0119] The aforementioned chip defect detection device can be in the form of computer software, and each module of the aforementioned chip defect detection device can be implemented through computer software modules.

[0120] The specific implementation process of the functions and roles of each module in the above chip defect detection device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0121] Therefore, based on any of the above embodiments, this disclosure also provides an electronic device that can execute the chip defect detection method of any of the embodiments described above.

[0122] Figure 12 This is a schematic block diagram of an electronic device 1000 according to one embodiment of the present disclosure.

[0123] The hardware architecture of the electronic device 1000 can be implemented using a bus architecture. The bus architecture can include any number of interconnect buses and bridges, depending on the specific application of the hardware and overall design constraints. Bus 1100 connects various circuits, including one or more processors 1200, memory 1300, and / or hardware modules. Bus 1100 can also connect various other circuits 1400, such as peripheral devices, voltage regulators, power management circuits, external antennas, etc.

[0124] Bus 1100 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, this diagram uses only one connection line, but this does not imply that there is only one bus or one type of bus.

[0125] This disclosure also provides a readable storage medium storing a computer program that, when executed by a processor, is used to implement the methods described above. A "readable storage medium" can be any means capable of containing, storing, communicating, propagating, or transmitting a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples of a readable storage medium include: an electrical connection with one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable read-only memory (CDROM), etc.

[0126] This disclosure also provides a computer program product, the methods of which can be implemented wholly or partially through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented wholly or partially as a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed, all or part of the processes or functions of this disclosure are performed.

[0127] Computer programs or instructions can be stored in a readable storage medium or transferred from one readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The readable storage medium can be any available medium capable of access, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a digital video optical disc; or a semiconductor medium, such as a solid-state drive. The computer-readable storage medium can be a volatile or non-volatile storage medium, or it can include both volatile and non-volatile types of storage media.

[0128] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0129] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0130] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0131] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0132] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., refer to specific features, structures, or characteristics described in connection with that embodiment / mode or example, which are included in at least one embodiment / mode or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0133] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0134] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A chip defect detection method, characterized in that, include: The cut path image in the image to be tested of the chip to be tested is identified, wherein the cut path image is the image outside the sealing ring in the image to be tested; Feature extraction is performed on the cutting path image to determine the image features of the cutting path image; The image features of the cut track image are matched with each candidate cut track image in the standard template library to determine the target cut track image in the standard template library; as well as The grayscale values ​​of the cut path image and the target cut path image are compared to determine the grayscale difference value of the cut path image. When the grayscale difference value is greater than a preset threshold, it is determined that the chip to be detected has a defect.

2. The chip defect detection method as described in claim 1, characterized in that, The process of building a standard template library includes: Identify the first dicing pattern in the silicon-through images of multiple candidate chips; Feature extraction is performed on the first cutting track images of multiple candidate chips to determine the image features of the first cutting track images; Based on the image features of each first cutting track image, the pattern type of each first cutting track image is classified to determine the first cutting track images of different pattern types; Averaging is performed on multiple first cutting path images under the same pattern type to determine a candidate cutting path image corresponding to each pattern type. Construct a standard template library containing candidate cut path images of different pattern types.

3. The chip defect detection method as described in claim 2, characterized in that, Based on the image features of each first cutting track image, each cutting track image is classified into pattern types to determine the first cutting track images of different pattern types, including: Select one first cutting track image from multiple first cutting track images as the second cutting track image; The remaining first cutting path images are traversed, and feature matching is performed with the second cutting path images respectively to determine the matching score between the remaining first cutting path images and the second cutting path images; The first cut track image whose matching score is greater than or equal to the target matching threshold is determined to be the same pattern type as the second cut track image.

4. The chip defect detection method as described in claim 2, characterized in that, For multiple first cutting path images under the same pattern type, average processing is performed to determine one candidate cutting path image corresponding to each pattern type, including: Affine transformation is performed on multiple first cutting path images under the same pattern type, and the first cutting path images after affine transformation are spatially aligned. The first cut path image after spatial alignment is averaged to determine a candidate cut path image corresponding to each pattern type.

5. The chip defect detection method as described in claim 1, characterized in that, Before identifying the cut lines in the image of the chip to be inspected, the process includes: Acquire a local silicon-through image of the chip under test; The local silicon transmittance images of the chip to be tested are positioned and stitched together to determine the silicon transmittance image of each chip to be tested; The silicon-through image is preprocessed to determine the cut path image in the silicon-through image.

6. The chip defect detection method as described in claim 1, characterized in that, Matching the image features of the cut track image with each candidate cut track image in the standard template library to determine the target cut track image in the standard template library includes: Calculate the normalized cross-correlation coefficient between the image features of the cut track image and each candidate cut track image in the standard template library, and determine the similarity score of each candidate cut track image in the standard template library. Based on the similarity score, each candidate cutting path image in the standard template library is filtered to determine the target cutting path image in the standard template library.

7. The chip defect detection method as described in claim 1, characterized in that, Matching the image features of the cut track image with each candidate cut track image in the standard template library to determine the target cut track image in the standard template library includes: Edge features are extracted from the cut path image and each candidate cut path image in the standard template library, respectively. The similarity between the edge features of the cut track image and the edge features of each candidate cut track image in the standard template library is calculated to determine the similarity score of each candidate cut track image in the standard template library. Based on the similarity score, each candidate cutting path image in the standard template library is filtered to determine the target cutting path image in the standard template library.

8. The chip defect detection method as described in claim 1, characterized in that, When the grayscale difference is greater than a preset threshold, it is determined that the chip under test has a defect, including: The grayscale difference between the corresponding pixels in the cut path image and the target cut path image is calculated to determine the difference image between the cut path image and the target cut path image; The gray-level difference in the difference image is binarized to determine the pixels in the difference image whose gray-level difference is greater than a preset threshold as defective pixels. When the area of ​​the connected region of the defective pixel is greater than or equal to the area threshold, it is determined that the chip under test has a defect.

9. An electronic device, characterized in that, include: The memory stores execution instructions; as well as A processor that executes the execution instructions stored in the memory, causing the processor to perform the chip defect detection method according to any one of claims 1 to 8.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the chip defect detection method according to any one of claims 1 to 8.

Images