Memory device and memory system for controlling operating voltage

Abstract

The present disclosure relates to a memory device and a storage system controlling an operating voltage. A memory device includes a base die stacked on an interposer and a plurality of core dies. The base die receives an input / output power supply voltage and operates at the voltage, and each of the plurality of core dies receives the power supply voltage through the base die to generate a peripheral voltage having a voltage level lower than the power supply voltage and operates at the peripheral voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Application No. 10-2024-0183143, filed with the Korean Intellectual Property Office on December 10, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to storage devices and storage systems, including but not limited to storage devices and storage systems for controlling operating voltage. Background Technology

[0004] Stacked memory systems, such as high-bandwidth memory (HBM) devices, are widely used in a wide range of applications due to their high bandwidth and energy efficiency. Unlike traditional memory systems that use parallel data buses, stacked memory systems consist of stacked memory devices, which include base dies interconnected via through-silicon vias (TSVs) and multiple core dies. Stacked memory devices include physical interfaces, such as a physical layer for communicating with the processor. The physical layer is designed for high-speed data transfer and efficient communication. Summary of the Invention

[0005] This disclosure describes a memory system that may include an interposer disposed on a substrate, and memory devices and a processor disposed on the interposer and connected by wiring within the interposer. The memory devices may include a base die and a plurality of core dies stacked on the interposer. The base die is operable at an input / output power supply voltage, and each of the plurality of core dies can generate and operate at an external voltage. Each of the plurality of core dies can receive a power supply voltage through the base die to generate an external voltage with a voltage level lower than the power supply voltage, and operate at that external voltage.

[0006] This disclosure describes a memory device including a base die configured to receive and operate under an input / output power supply voltage, and a plurality of core dies stacked on the base die. Each of the plurality of core dies can receive the power supply voltage through the base die to generate an external voltage with a voltage level lower than the input / output power supply voltage, and operate under that external voltage.

[0007] This disclosure describes a method for controlling an operating voltage, comprising: pulling up an external voltage supplied to the core die to a power supply voltage when a power-on signal is activated; and pulling down the external voltage to ground when the power-on signal is deactivated. The power-on signal is activated according to the power supply voltage until the startup operation terminates, and is deactivated synchronously with the termination time of the startup operation.

[0008] The storage device may include a core die configured to include multiple peripheral voltage control circuits. Each peripheral voltage control circuit is configured to be pull-up driven and pull-down driven to generate a peripheral voltage. The core die operates under the peripheral voltage, receiving a power supply voltage and generating a peripheral voltage with a voltage level lower than the power supply voltage. Attached Figure Description

[0009] Figure 1 A storage system according to an embodiment of the present disclosure is shown.

[0010] Figure 2 The core die is shown according to an embodiment of this disclosure.

[0011] Figure 3 An external voltage control circuit according to an embodiment of the present disclosure is shown.

[0012] Figure 4 An embodiment of a pull-up drive circuit according to an embodiment of the present disclosure is shown.

[0013] Figure 5 An embodiment of a pull-down drive circuit according to an embodiment of the present disclosure is shown.

[0014] Figure 6 An embodiment of a leakage current switching signal generation circuit according to an embodiment of the present disclosure is shown.

[0015] Figure 7 An embodiment of a leakage current drive circuit according to an embodiment of the present disclosure is shown.

[0016] Figure 8 This is a timing diagram illustrating the operation of a peripheral voltage control circuit according to an embodiment of the present disclosure.

[0017] Figure 9 An external voltage control circuit according to an embodiment of the present disclosure is shown.

[0018] Figure 10 An embodiment of a first pull-down drive circuit according to an embodiment of the present disclosure is shown.

[0019] Figure 11 An embodiment of a first leakage current switching signal generation circuit according to an embodiment of the present disclosure is shown.

[0020] Figure 12 An embodiment of a second pull-down drive circuit according to an embodiment of the present disclosure is shown.

[0021] Figure 13 An embodiment of a second leakage current switching signal generation circuit according to an embodiment of the present disclosure is shown.

[0022] Figure 14This is a timing diagram illustrating the operation of a peripheral voltage control circuit according to an embodiment of the present disclosure. Detailed Implementation

[0023] The cross shading throughout the figure indicates corresponding or similar areas between figures, rather than indicating material related to these areas.

[0024] Terms such as "first" and "second" are used to distinguish multiple elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be named the second element, while in another example, the second element may be named the first element.

[0025] When a component is marked as "connected" to another component, these components can be connected directly or through an intermediary component between them. When two components are marked as "directly connected," one component is directly connected to the other, and there is no intermediary component between the two components.

[0026] Logic "high" and logic "low" levels can be used to describe the logic levels of electrical signals. A signal at a logic high level is different from a signal at a logic low level. For example, when a signal at a first voltage level corresponds to a signal at a logic high level, a signal at a second voltage level corresponds to a signal at a logic low level. In one embodiment, a logic high level can be a voltage level higher than a logic low level. According to this embodiment, the logic levels of signals can be different or opposite. For example, a signal at a logic high level in one embodiment can be at a logic low level in another embodiment, and vice versa.

[0027] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0028] Figure 1 A storage system 1 according to an embodiment of the present disclosure is shown.

[0029] like Figure 1 As shown, the storage system 1 includes a printed circuit board (PCB) 11, a substrate 13, an interposer 15, a storage device 17, and a processor 19.

[0030] Printed circuit board 11 connects various electronic components to form an electronic circuit (not shown). The electronic circuit includes a storage system 1. A copper (Cu) layer, a solder mask, screen printing, etc., are formed on the printed circuit board 11. Circuit paths for transmitting or transferring signals or electricity are formed in the copper (Cu) layer. The solder mask prevents damage to the circuit and protects the specific area where components are soldered. Screen printing uses characters or symbols printed on the surface of the printed circuit board 11 to indicate the location or information of the electronic components.

[0031] A substrate 13 is disposed on a printed circuit board 11, and bump pads are provided therebetween, such as bump pads 111 for mechanically supporting the interposer 15, the memory device 17, and the processor 19. The substrate 13 serves as the physical substrate for the printed circuit board 11 and is an insulator. The substrate 13 may include materials such as FR4 as an insulator made of glass fiber and epoxy resin, ceramics capable of withstanding high temperatures, having suitable thermal conductivity and used in high-frequency circuits, and polyimide, which is used as a base material for flexible PCBs due to its flexibility.

[0032] An interposer 15 is disposed on the substrate 13, with bump pads therein, and includes wiring connecting electronic components (e.g., memory device 17 and processor 19) having mismatched or different form factors or pin arrangements. The interposer 15 converts signals used for communication between different interfaces (e.g., DDR, HBM, PCIe).

[0033] Memory device 17 is disposed on interposer layer 15, with pads, such as microbumps 113, therebetween. Memory device 17 stores data received from processor 19, or outputs stored data to processor 19 under the control of processor 19. Memory device 17 includes a base die 120 and a plurality of core dies 121-1 to 121-L, where L is an integer greater than 1. Core dies 121-1 to 121-L are stacked on the base die 120, with microbump pads between them. The base die 120 and the core dies 121-1 to 121-L are perpendicularly connected to each other using vias and microbump pads. Base die 120 controls effective data transfer between processor 19 and core dies 121-1 to 121-L. Base die 120 receives the input / output power supply voltage (voltage drain-drain for I / O, also known as the output stage drain power supply voltage) VDDQ as the operating voltage used during the operation of the internal circuitry included in base die 120. Base die 120 receives the input / output power supply voltage VDDQ from the printed circuit board 11 via substrate 13 and interposer 15. The input / output power supply voltage VDDQ is the voltage supplied to the buffer transmitting data and is different from or distinct from the power supply voltage VDD. During operation of the internal circuitry included in core dies 121-1 to 121-L, core dies 121-1 to 121-L use the peripheral voltage VPERI as their operating voltage. Core dies 121-1 to 121-L generate the peripheral voltage VPERI from the power supply voltage VDD received through base die 120. Core dies 121-1 to 121-L generate a peripheral voltage VPERI with a voltage level lower than the power supply voltage VDD and use the peripheral voltage VPERI as their operating voltage. Each of core dies 121-1 to 121-L includes multiple independently operating channel regions, such as eight or sixteen channel regions. Each of the multiple channel regions is assigned an independently operating channel for receiving or transmitting data. The number L of core dies 121-1 to 121-L can be four, eight, twelve, sixteen, etc. For example, when each of core dies 121-1 to 121-12 has eight channels, core dies 121-1 to 121-4, core dies 121-5 to 121-8, and core dies 121-9 to 121-12 each include thirty-two channel areas, and send and receive data with processor 19 in groups of thirty-two channels.

[0034] Figure 2 The core die 121-1 according to an embodiment of the present disclosure is shown.

[0035] like Figure 2As shown, the core die 121-1 includes a first central region 131-1, a first edge region 131-2, and a second edge region 131-3. The first central region 131-1 is located at the center of the core die 121-1. The first edge region 131-2 is located on a first side of the first central region 131-1 in a direction opposite to the first direction X, while the second edge region 131-3 is located on a second side of the first central region 131-1 in the first direction X. Although each of the first central region 131-3, the first edge region 131-2, and the second edge region 131-3 is shown as longer in the second direction Y than in the first direction X in this example, the present disclosure is not limited to this example.

[0036] The first peripheral voltage generating circuit 133-1 to the fourth peripheral voltage generating circuit 133-4 and the first peripheral voltage control circuit 135-1 to the fourth peripheral voltage control circuit 135-4 are located in the first central region 131-1. The peripheral voltage generating circuits 133-1 to 133-4 are spaced apart at equal intervals in the second direction Y. The peripheral voltage control circuits 135-1 to 135-4 are also spaced apart at equal intervals in the second direction Y. The first peripheral voltage control circuit 135-1 is located on one side of the first peripheral voltage generating circuit 133-1 in the first direction X and controls the level of the peripheral voltage VPERI generated by the first peripheral voltage generating circuit 133-1. The second peripheral voltage control circuit 135-2 is located on one side of the second peripheral voltage generating circuit 133-2 in the first direction X and controls the level of the peripheral voltage VPERI generated by the second peripheral voltage generating circuit 133-2. The third peripheral voltage control circuit 135-3 is located on one side of the third peripheral voltage generating circuit 133-3 in the first direction X, and controls the level of the peripheral voltage VPERI generated by the third peripheral voltage generating circuit 133-3. The fourth peripheral voltage control circuit 135-4 is located on one side of the fourth peripheral voltage generating circuit 133-4 in the first direction X, and controls the level of the peripheral voltage VPERI generated by the fourth peripheral voltage generating circuit 133-4.

[0037] The fifth peripheral voltage generation circuit 133-5 to the eighth peripheral voltage generation circuit 133-8 and the fifth peripheral voltage control circuit 135-5 to the eighth peripheral voltage control circuit 135-8 are located in the first edge region 131-2. The peripheral voltage generation circuits 133-5 to 133-8 are spaced apart at equal intervals in the second direction Y. The peripheral voltage control circuits 135-5 to 135-8 are also spaced apart at equal intervals in the second direction Y. The fifth peripheral voltage control circuit 135-5 is located on one side of the fifth peripheral voltage generation circuit 133-5 in the first direction X and controls the level of the peripheral voltage VPERI generated by the fifth peripheral voltage generation circuit 133-5. The sixth peripheral voltage control circuit 135-6 is located on one side of the sixth peripheral voltage generation circuit 133-6 in the first direction X and controls the level of the peripheral voltage VPERI generated by the sixth peripheral voltage generation circuit 133-6. The seventh peripheral voltage control circuit 135-7 is located on one side of the seventh peripheral voltage generation circuit 133-7 in the first direction X, and controls the level of the peripheral voltage VPERI generated by the seventh peripheral voltage generation circuit 133-7. The eighth peripheral voltage control circuit 135-8 is located on one side of the eighth peripheral voltage generation circuit 133-8 in the first direction X, and controls the level of the peripheral voltage VPERI generated by the eighth peripheral voltage generation circuit 133-8.

[0038] The ninth peripheral voltage generation circuit 133-9 to the twelfth peripheral voltage generation circuit 133-12 and the ninth peripheral voltage control circuit 135-9 to the twelfth peripheral voltage control circuit 135-12 are located in the second edge region 131-3. The peripheral voltage generation circuits 133-9 to 133-12 are spaced apart at equal intervals in the second direction Y. The peripheral voltage control circuits 135-9 to 135-12 are also spaced apart at equal intervals in the second direction Y. The ninth peripheral voltage control circuit 135-9 is located on one side of the ninth peripheral voltage generation circuit 133-9 in the first direction X and controls the level of the peripheral voltage VPERI generated by the ninth peripheral voltage generation circuit 133-9. The tenth peripheral voltage control circuit 135-10 is located on one side of the tenth peripheral voltage generation circuit 133-10 in the first direction X and controls the level of the peripheral voltage VPERI generated by the tenth peripheral voltage generation circuit 133-10. The eleventh peripheral voltage control circuit 135-11 is located on one side of the eleventh peripheral voltage generation circuit 133-11 in the first direction X, and controls the level of the peripheral voltage VPERI generated by the eleventh peripheral voltage generation circuit 133-11. The twelfth peripheral voltage control circuit 135-12 is located on one side of the twelfth peripheral voltage generation circuit 133-12 in the first direction X, and controls the level of the peripheral voltage VPERI generated by the twelfth peripheral voltage generation circuit 133-12.

[0039] Figure 1 Each of the core dies 121-2 to 121-L shown may include a central region and two edge regions, similar to core die 121-1. The thirty-two channels included in the four core dies 121-1 to 121-L are grouped together, and core dies 121-1 to 121-L exchange data with processor 19 through the thirty-two channels forming a group.

[0040] Figure 3 Embodiments according to this disclosure are shown (e.g., such as...). Figure 2 The peripheral voltage control circuit 135-1 (shown) is an external voltage control circuit.

[0041] like Figure 3 As shown, the peripheral voltage control circuit 135-1 includes a pull-up drive circuit (PU DRV) 21 and a pull-down drive circuit (PD DRV) 23.

[0042] The pull-up drive circuit 21 pulls up the external voltage VPERI based on the power-on signal PWR-BUP. The power-on signal PWR-BUP is activated during the power-on period according to the power supply voltage VDD and is deactivated synchronously with the termination of the startup operation. In this example, the power-on period is from when the power supply voltage VDD is applied at 0V to... Figure 1 The time interval from the time of storage device 17 to the time when the power supply voltage VDD reaches the preset voltage level. The startup operation refers to... Figure 1 The initialization process of storage system 1 includes setting up memory channels, setting the operating frequency of the clock signal used for signal timing, setting the voltage level of the operating voltage including the external voltage VPERI, and adjusting various operational parameters. Pulling up the external voltage VPERI involves driving the external voltage VPERI to the power supply voltage VDD. The pull-up drive circuit 21 pulls up the external voltage VPERI during the period when the power-on signal PWR-BUP is activated. During the period when the operation is initiated from the time the power supply voltage VDD reaches the preset voltage level, the pull-up drive circuit 21 pulls up the external voltage VPERI to the power supply voltage VDD.

[0043] The pull-down drive circuit 23 pulls down the external voltage VPERI based on the power-on signal PWR-BUP. Pulling down the external voltage VPERI includes, for example, driving the external voltage VPERI to ground voltage VSS when the charge or voltage at the VPERI terminal discharges. The external voltage VPERI terminal includes a terminal electrically connected to the external voltage VPERI. The pull-down drive circuit 23 pulls down the external voltage VPERI during a drive period after the startup operation terminates and when the power-on signal PWR-BUP is deactivated. The drive period can be predetermined or preset. The drive period is based on the oscillator (e.g., Figure 6 The oscillation pulse generated by the OSC (e.g.) Figure 6 The OPUL cycle is used to establish the voltage level. When the startup operation terminates, the pull-down drive circuit 23 pulls down the external voltage VPERI, causing the voltage level of the external voltage VPERI to quickly reach the target voltage level.

[0044] Figure 2 Each of the peripheral voltage control circuits 135-2 to 135-12 may include a configuration for pulling up and pulling down the peripheral voltage VPERI generated from each of the second peripheral voltage generation circuits 133-2 to twelfth peripheral voltage generation circuits 133-12 in the same manner as peripheral voltage control circuit 135-1.

[0045] Figure 4 Embodiments according to this disclosure are shown (e.g., such as...). Figure 3 An embodiment of the pull-up drive circuit 21 shown.

[0046] like Figure 4 As shown, the pull-up drive circuit 21 includes an inverter 211 and a PMOS transistor 213. The inverter 211 inverts and buffers the power-on signal PWR-BUP, and outputs the inverted buffered signal of the power-on signal PWR-BUP. The PMOS transistor 213 is turned on based on the output signal of the inverter 211 and operates as a pull-up device for the external voltage VPERI. During the time period from when the power supply voltage VDD reaches a preset voltage level, the inverter 211 inverts and buffers the power-on signal PWR-BUP, which is activated at a logic high level, thereby outputting the inverted buffered signal of the power-on signal PWR-BUP at a logic low level. When the output signal of the inverter 211 is at a logic low level, the PMOS transistor 213 is turned on to pull up the external voltage VPERI. The pull-up drive circuit 21 receives the power-on signal PWR-BUP, which is activated by a logic high level, and pulls up the external voltage VPERI to the power supply voltage VDD during the start-up operation period from the time when the power supply voltage VDD reaches the preset voltage level.

[0047] Figure 5 Embodiments according to this disclosure are shown (e.g., such as...). Figure 3 An embodiment of the pull-down drive circuit 23 (shown).

[0048] like Figure 5 As shown, the pull-down drive circuit 23 includes a leakage switching signal generation circuit (LEAK-SW GEN) 231 and a leakage drive circuit (LEAK DRV) 233.

[0049] The leakage current switching signal generation circuit 231 generates a leakage current switching signal LEAK-SW based on the power-on signal PWR-BUP, which is used to pull down the drive peripheral voltage VPERI during the drive period after the start-up operation ends. The leakage current switching signal generation circuit 231 receives the power-on signal PWR-BUP, which is deactivated after the start-up operation ends, and generates an oscillating pulse as a periodic signal (e.g., Figure 6 (OPUL). The leakage switching signal generation circuit 231 generates a leakage switching signal LEAK-SW based on the period or frequency of the oscillating pulse. This leakage switching signal is activated to pull down the drive peripheral voltage VPERI during the drive time period.

[0050] The leakage current drive circuit 233 is electrically connected to the leakage current switching signal generation circuit 231 and receives the leakage current switching signal LEAK-SW from the leakage current switching signal generation circuit 231. The leakage current drive circuit 233 pulls down the external driving voltage VPERI based on the leakage current switching signal LEAK-SW. The leakage current drive circuit 233 receives the leakage current switching signal LEAK-SW, which is activated during the drive period after the start-up operation terminates to pull down the external driving voltage VPERI.

[0051] Figure 6 Embodiments according to this disclosure are shown (e.g., such as...). Figure 5 An embodiment of the leakage current switching signal generation circuit 231 shown.

[0052] like Figure 6 As shown, the leakage switching signal generation circuit 231 includes an oscillator (OSC) 241, a latch 243, and a logic device 245.

[0053] Oscillator 241 generates an oscillation pulse OPUL based on a power-on signal PWR-BUP. Oscillator 241 generates the oscillation pulse OPUL when a deactivated power-on signal PWR-BUP is received after the startup operation has terminated. The oscillation pulse OPUL is a periodic signal, with a period of, for example, 1 ms; however, this disclosure is not limited to this example.

[0054] Latch 243 is electrically connected to oscillator 241 and receives the oscillation pulse OPUL from oscillator 241. Latch 243 generates an activated latch signal LAT when the oscillation pulse OPUL is generated. When the oscillation pulse OPUL is at a logic high level after a drive period has elapsed following the termination of the startup operation, latch 243 latches the power supply voltage VDD, thereby generating the latch signal LAT activated at a logic high level. The drive period is half a cycle of the oscillation pulse OPUL, for example, 0.5 ms, but this disclosure is not limited to this example. Latch 243 initializes the latch signal LAT based on the power-on signal PWR-BUP. When the power-on signal PWR-BUP, activated at a logic high level, is received during the period in which the startup operation is executed from the time the power supply voltage VDD reaches a preset voltage level, latch 243 initializes the latch signal LAT to a logic low level.

[0055] Logic device 245 is electrically connected to latch 243 and receives the latch signal LAT from latch 244. Logic device 245 receives the latch signal LAT and the power-on signal PWR-BUP, performs a NOR operation, and generates a leakage current switching signal LEAK-SW. Logic device 245 receives the latch signal LAT and the power-on signal PWR-BUP, both of which are deactivated during the drive period after the start-up operation terminates, and logic device 245 generates the activated leakage current switching signal LEAK-SW.

[0056] When a power-on signal PWR-BUP, activated at a logic high level, is received during the period from the time the power supply voltage VDD reaches a preset voltage level to the start operation execution time, latch 243 initializes the latch signal LAT to a logic low level, and logic device 245 generates a leakage switching signal LEAK-SW, deactivated at a logic low level. After the start operation terminates and the power-on signal PWR-BUP, deactivated at a logic low level, is received, oscillator 241 generates an oscillation pulse OPUL. During the drive period, i.e., from the time the start operation terminates until the time when the oscillation pulse OPUL is generated at a logic high level, the latch signal LAT remains at a logic low level, and the power-on signal PWR-BUP remains in a deactivated state at a logic low level. Therefore, logic device 245 generates a leakage switching signal LEAK-SW, activated at a logic high level. Because latch 243 latches the power supply voltage VDD to generate a logic-high latch signal LAT when the oscillation pulse OPUL is generated at a logic high level and the drive period ends, logic device 245 generates a leakage switching signal LEAK-SW that is deactivated to a logic low level. Leakage switching signal generation circuit 231 receives the power-on signal PWR-BUP, which is deactivated after the startup operation ends, to generate the oscillation pulse OPUL as a periodic signal, and generates the leakage switching signal LEAK-SW, which is activated at a logic high level, to pull down the drive peripheral voltage VPERI during the drive period based on the oscillation pulse period.

[0057] Figure 7 Embodiments according to this disclosure are shown (e.g., such as...). Figure 5 An embodiment of the leakage current drive circuit 233 shown.

[0058] like Figure 7 As shown, the leakage drive circuit 233 includes transistors 251 and 253 connected in series between the external voltage VPERI terminal and the ground voltage VSS terminal. The ground voltage VSS terminal includes a terminal electrically connected to the ground voltage VSS. NMOS transistor 251 operates as a driving device that receives the leakage switching signal LEAK-SW and is turned on. NMOS transistor 253 acts as a biasing device that receives the bias voltage BIAS and remains on. The leakage drive circuit 233 receives the activated leakage switching signal LEAK-SW and pulls down the driving external voltage VPERI during the drive period after the start-up operation terminates.

[0059] Figure 8 It is shown, for example, as Figure 1 and Figure 3 The timing diagram of the operation of the external voltage control circuit 135-1 is shown.

[0060] At time T11, when the power supply voltage VDD is applied to Figure 1 When the storage device 17 is activated, the voltage level of the power-on signal PWR-BUP rises together with the power supply voltage VDD. When the power supply voltage VDD reaches the preset voltage level, the power-on signal PWR-BUP is activated to a logic high level. Figure 3 The pull-up drive circuit 21 receives the power-on signal PWR-BUP activated by a logic high level to pull up the external voltage VPERI to the power supply voltage VDD.

[0061] At time T12, the startup operation is initiated. During the startup operation, the initialization process includes setting up memory channels, setting the operating frequency of the clock signal used for signal timing, setting the voltage level of the operating voltage, including the external voltage VPERI, and adjusting various operational parameters. During the startup operation, the power-on signal PWR-BUP remains active at a logic high level. During the startup operation, the external voltage VPERI remains pulled up to the power supply voltage VDD.

[0062] At time T13, after the startup operation terminates, the power-on signal PWR-BUP is deactivated with a logic low level. Oscillator 241 generates an oscillation pulse OPUL in response to receiving the power-on signal PWR-BUP, which is deactivated with a logic low level.

[0063] At time T14, when the oscillation pulse OPUL is generated at a logic high level... Figure 5 The leakage switching signal generation circuit 231 shown generates a leakage switching signal LEAK-SW, which is activated at a logic high level during the driving time period T13 to T14 from the termination of the start operation until the oscillation pulse OPOL is generated at a logic high level. Figure 5 The leakage current drive circuit 233 shown pulls down the external voltage VPERI according to the leakage current switching signal LEAK-SW activated during the drive period T13 to T14. At time T14, the external voltage VPERI is pulled down during the drive period, causing the external voltage VPERI to quickly reach the target voltage level.

[0064] Figure 9 An external voltage control circuit 135-1A according to an embodiment of the present disclosure is shown.

[0065] like Figure 9 As shown, the peripheral voltage control circuit 135-1A includes a pull-up drive circuit (PU DRV) 21, a first pull-down drive circuit (PD DRV1) 23-1, and a second pull-down drive circuit (PD DRV2) 23-2.

[0066] The pull-up drive circuit 21 pulls up the external voltage VPERI based on the power-on signal PWR-BUP. During the period when the power-on signal PWR-BUP is activated, the pull-up drive circuit 21 pulls up the external voltage VPERI to the power supply voltage VDD. During the period from the time the power supply voltage VDD reaches the preset voltage level to initiate the operation, the pull-up drive circuit 21 pulls the external voltage VPERI up to the power supply voltage VDD.

[0067] The first pull-down drive circuit 23-1 uses a first driving force to pull down the peripheral voltage VPERI based on the power-on signal PWR-BUP and the first mode signal MD1. The first mode signal MD1 is activated to use the first driving force to pull down the peripheral voltage VPERI. While the first mode signal MD1 is activated, during the drive period after the startup operation terminates and the power-on signal PWR-BUP is deactivated, the first pull-down drive circuit 23-1 uses the first driving force to pull down the peripheral voltage VPERI. After the startup operation terminates, the first pull-down drive circuit 23-1 uses the first driving force to pull down the peripheral voltage VPERI, causing the voltage level of the peripheral voltage VPERI to quickly reach the target voltage level.

[0068] The second pull-down driver circuit 23-2 uses a second driving force to pull down the external voltage VPERI based on the power-on signal PWR-BUP and the second mode signal MD2. The second mode signal MD2 is activated to use the second driving force to pull down the external voltage VPERI. While the second mode signal MD2 is activated, during the driving period after the startup operation terminates and the power-on signal PWR-BUP is deactivated, the second pull-down driver circuit 23-2 uses the second driving force to pull down the external voltage VPERI. In this example, the second driving force is greater than the first driving force. After the startup operation terminates, the second pull-down driver circuit 23-2 uses the second driving force to pull down the external voltage VPERI, causing the voltage level of the external voltage VPERI to reach the target voltage level faster than when driven by the first pull-down driver circuit 23-1.

[0069] For example, such as Figure 2 As shown, each of the peripheral voltage control circuits 135-2 to 135-12 may be similar to peripheral voltage control circuit 135-1A, including a configuration for pulling up the peripheral voltage VPERI generated by each peripheral voltage generation circuit 133-2 to 133-12 and multiple configurations for pulling down the peripheral voltage VPERI generated by each peripheral voltage generation circuit 133-2 to 133-12. According to an embodiment, the number of configurations for pulling down can be three or more.

[0070] Figure 10Embodiments according to this disclosure are shown (e.g., such as...). Figure 9 The first pull-down drive circuit 23-1 (shown) is as follows.

[0071] like Figure 10 As shown, the first pull-down drive circuit 23-1 includes a first leakage switching signal generation circuit (LEAK-SWGEN1) 261 and a first leakage drive circuit (LEAK DRV1) 263.

[0072] The first leakage switching signal generation circuit 261 generates a first leakage switching signal LEAK-SW1 based on the power-on signal PWR-BUP and the first mode signal MD1, to pull down the external voltage VPERI using a first driving force during the drive period after the startup operation terminates. The first leakage switching signal generation circuit 261 receives the power-on signal PWR-BUP, which is deactivated by a logic low level after the startup operation terminates, and generates an oscillating pulse as a periodic signal (e.g., Figure 11 (OPUL1 in the example). The first leakage switching signal generation circuit 261 generates a first leakage switching signal LEAK-SW1 that is activated at a logic high level during a drive time period based on the period of the oscillation pulse to pull down the external voltage VPERI using a first drive force.

[0073] The first leakage current driving circuit 263 is electrically connected to the first leakage current switching signal generation circuit 261 and receives the first leakage current switching signal LEAK-SW1 from the first leakage current switching signal generation circuit 261. The first leakage current driving circuit 243 uses a first driving force to pull down the external voltage VPERI based on the first leakage current switching signal LEAK-SW1. The first leakage current driving circuit 243 receives the first leakage current switching signal LEAK-SW1 activated during the driving time period after the start-up operation terminates and uses the first driving force to pull down the external voltage VPERI.

[0074] Figure 11 Embodiments according to this disclosure are shown (e.g., such as...). Figure 10 An embodiment of the first leakage current switching signal generation circuit 261 shown.

[0075] like Figure 11 As shown, the first leakage switching signal generation circuit 261 includes a first oscillator (OSC1) 271, a first latch 273, a first logic device 275, and a second logic device 277.

[0076] The first oscillator 271 generates a first oscillation pulse OPUL1 based on the power-on signal PWR-BUP. When the power-on signal PWR-BUP is received, the first oscillator 271 generates the first oscillation pulse OPUL1, which is deactivated after the startup operation terminates. The first oscillation pulse OPUL1 is a periodic signal, with a period of, for example, 1 ms; however, this disclosure is not limited to this example.

[0077] The first latch 273 is electrically connected to the first oscillator 271 and receives the first oscillation pulse OPUL1 from the first oscillator 271. When the first oscillation pulse OPUL1 is generated, the latch 273 generates an activated first latch signal LAT1. When the first oscillation pulse OPUL1 is at a logic high level after a drive period following the termination of the startup operation, the first latch 273 latches the power supply voltage VDD, thereby generating the first latch signal LAT1 activated at a logic high level. The first latch 273 initializes the first latch signal LAT1 based on the power-on signal PWR-BUP. When the power-on signal PWR-BUP, activated at a logic high level, is received during the period when the startup operation is executed from the time when the power supply voltage VDD reaches a preset voltage level, the first latch 273 initializes the first latch signal LAT1 to a logic low level.

[0078] A first logic device 275 is electrically connected to a first latch 273 and receives a first latch signal LAT1 from the first latch 273. The first logic device 275 receives the first latch signal LAT1 and a power-on signal PWR-BUP, and performs a NOR operation. A second logic device 277 is electrically connected to the first logic device 275 and receives the output signal of the first logic device 275. The second logic device 277 performs an AND operation on the output signal of the first logic device 275 and a first mode signal MD1 to generate a first leakage switching signal LEAK-SW1. When the first mode signal MD1 is activated, during the drive period after the start operation terminates, the second logic device 277 receives the first latch signal LAT1 and the power-on signal PWR-BUP, both deactivated at a logic low level, to generate the first leakage switching signal LEAK-SW1 activated at a logic high level.

[0079] When a power-on signal PWR-BUP, activated by a logic high level, is received during the period from the time the power supply voltage VDD reaches a preset voltage level to the start operation execution time, the first logic device 273 initializes the first latch signal LAT1 to a logic low level, the first logic device 275 outputs a logic low level signal, and the second logic device 277 generates a first leakage switching signal LEAK-SW1, which is deactivated by a logic low level. After the start operation terminates and the power-on signal PWR-BUP, which is deactivated by a logic low level, is received, the first oscillator 271 generates a first oscillation pulse OPUL1. During the drive period, i.e., the period from the termination of the start operation to the time when the first oscillation pulse OPUL1 is generated by a logic high level, the first latch signal LAT1 remains at a logic low level, and the power-on signal PWR-BUP remains deactivated by a logic low level. Therefore, the first logic device 275 outputs a logic high level signal, and the second logic device 277 generates the first leakage switching signal LEAK-SW1, which is activated by a logic high level. When the first oscillation pulse OPUL1 is generated at a logic high level and the drive period ends, the first latch 273 latches the power supply voltage VDD to generate a logic high first latch signal LAT1. Therefore, the first logic device 275 outputs a logic low signal, while the second logic device 277 generates a first leakage switching signal LEAK-SW1 that is deactivated at a logic low level. The first leakage switching signal generation circuit 261 receives the power-on signal PWR-BUP, which is deactivated after the startup operation terminates, to generate the first oscillation pulse OPUL1 as a periodic signal. When the first mode signal MD1 is activated, it generates the first leakage switching signal LEAK-SW1 activated at a logic high level during the drive period set based on the period of the first oscillation pulse OPUL1, to pull down the external voltage VPERI using the first driving force.

[0080] Figure 12 Embodiments according to this disclosure are shown (e.g., such as...). Figure 9 An embodiment of the second pull-down drive circuit 23-2 (shown).

[0081] like Figure 12 As shown, the second pull-down drive circuit 23-2 includes a second leakage switching signal generation circuit (LEAK-SWGEN2) 281 and a second leakage drive circuit (LEAK DRV2) 283.

[0082] The second leakage switching signal generation circuit 281 generates a second leakage switching signal LEAK-SW2 during the drive period after the startup operation terminates, based on the power-on signal PWR-BUP and the second mode signal MD2, to pull down the external voltage VPERI using the second driving force. The second leakage switching signal generation circuit 281 receives the power-on signal PWR-BUP, which is deactivated by a logic low level after the startup operation terminates, and generates an oscillating pulse as a periodic signal (e.g., Figure 13 (OPUL2). The second leakage switching signal generation circuit 281 generates a second leakage switching signal LEAK-SW2 that is activated at a logic high level during a drive time period set based on the period or frequency of the oscillation pulse, so as to pull down the external voltage VPERI using the second driving force.

[0083] The second leakage current driving circuit 283 is electrically connected to the second leakage current switching signal generation circuit 281 and receives the second leakage current switching signal LEAK-SW2 from the second leakage current switching signal generation circuit 281. Based on the second leakage current switching signal LEAK-SW2, the second leakage current driving circuit 283 uses a second driving force to pull down the external voltage VPERI. The second leakage current driving circuit 283 receives the second leakage current switching signal LEAK-SW2 activated during the driving time period after the start-up operation terminates and uses the second driving force to pull down the external voltage VPERI.

[0084] Figure 13 Embodiments according to this disclosure are shown (e.g., such as...). Figure 12 An embodiment of the second leakage current switching signal generation circuit 281 shown.

[0085] like Figure 13 As shown, the second leakage switching signal generation circuit 281 includes a second oscillator (OSC2) 291, a second latch 293, a third logic device 295, and a fourth logic device 297.

[0086] The second oscillator 291 generates a second oscillation pulse OPUL2 based on the power-on signal PWR-BUP. The second oscillator 291 generates the second oscillation pulse OPUL2 when the power-on signal PWR-BUP, which is deactivated by a logic low level after the startup operation has terminated, is received. The second oscillation pulse OPUL2 is a periodic signal, and its period is, for example, 1 ms; however, this disclosure is not limited to this example.

[0087] The second latch 293 is electrically connected to the second oscillator 291 and receives the second oscillation pulse OPUL2 from the second oscillator 2912. When the second oscillation pulse OPUL2 is generated, the second latch 293 generates a second latch signal LAT2 activated by a logic high level. When the second oscillation pulse OPUL2 is at a logic high level after a drive period following the termination of the startup operation, the second latch 293 latches the power supply voltage VDD, thereby generating the second latch signal LAT2 activated by a logic high level. The second latch 293 initializes the second latch signal LAT2 based on the power-on signal PWR-BUP. When the power-on signal PWR-BUP activated by a logic high level is received during the period in which the startup operation is executed from the time when the power supply voltage VDD reaches a preset voltage level, the second latch 293 initializes the second latch signal LAT2 to a logic low level.

[0088] The third logic device 295 is electrically connected to the second latch 293 and receives the second latch signal LAT2 from the second latch 293. The third logic device 295 receives the second latch signal LAT2 and the power-on signal PWR-BUP, and performs a NOR operation. The fourth logic device 297 is electrically connected to the third logic device 295 and receives the output signal of the third logic device 295. The fourth logic device 297 performs an AND operation on the output signal of the third logic device 295 and the second mode signal MD2 to generate the second leakage switching signal LEAK-SW2. When the second mode signal MD2 is activated at a logic high level, during the drive period after the start-up operation terminates, the fourth logic device 297 receives the second latch signal LAT2 and the power-on signal PWR-BUP, both of which are deactivated at a logic low level, and generates the second leakage switching signal LEAK-SW2 activated at a logic high level.

[0089] When a power-on signal PWR-BUP, activated by a logic high level, is received during the period from the time the power supply voltage VDD reaches a preset voltage level, the second latch 293 initializes the second latch signal LAT2 to a logic low level, the third logic device 295 outputs a logic low level signal, and the fourth logic device 297 generates a second leakage switching signal LEAK-SW2, deactivated by a logic low level. After the startup operation terminates and the power-on signal PWR-BUP, deactivated by a logic low level, is received, the second oscillator 291 generates a second oscillation pulse OPUL2. During the driving period from the termination of the startup operation until the second oscillation pulse OPUL2 is generated at a logic high level, the second latch signal LAT2 remains at a logic low level, and the power-on signal PWR-BUP remains in a deactivated state at a logic low level. Therefore, the third logic device 295 outputs a logic high level signal, and the fourth logic device 297 generates a second leakage switching signal LEAK-SW2, activated by a logic high level. When the second oscillation pulse OPUL2 is generated at a logic high level and the drive period ends, the second latch 293 latches the power supply voltage VDD to generate a logic high-level second latch signal LAT2. Therefore, the third logic device 295 outputs a logic low-level signal, while the fourth logic device 297 generates a logic low-level deactivated second leakage switching signal LEAK-SW2. The second leakage switching signal generation circuit 291 receives the power-on signal PWR-BUP, which is deactivated at a logic low level after the startup operation terminates, to generate the second oscillation pulse OPUL2 as a periodic signal. When the second mode signal MD2 is activated, it generates the logic high-level activated second leakage switching signal LEAK-SW2 during the drive period based on the period of the second oscillation pulse OPUL2 to pull down the external voltage VPERI using the second driving force.

[0090] Figure 14 This illustrates an embodiment according to the present disclosure (e.g., as shown in the example). Figure 9 The timing diagram of the operation of the external voltage control circuit 135-1A (shown) is shown.

[0091] At time T21, when the power supply voltage VDD is applied, for example as... Figure 1 When the storage device 17 is shown, the voltage level of the power-on signal PWR-BUP rises together with the power supply voltage VDD. When the power supply voltage VDD reaches a preset voltage level, the power-on signal PWR-BUP is activated at a logic high level. Figure 9 The pull-up drive circuit 21 receives the power-on signal PWR-BUP activated by a logic high level and pulls up the external voltage VPERI to the power supply voltage VDD.

[0092] After the startup operation terminates at time T23, the power-on signal PWR-BUP is deactivated at a logic low level. When the first mode signal MD1 is activated at a logic high level during the drive period T23 to T24 after the startup operation terminates, the first leakage switching signal LEAK-SW1 is generated and activated at a logic high level. Conversely, when the second mode signal MD2 is activated at a logic high level, the second leakage switching signal LEAK-SW2 is generated and activated at a logic high level. In the first mode MODE1, where the first mode signal MD1 is activated, the external voltage VPERI is pulled down using a first driving force during the drive period T23 to T24. In the second mode MODE2, where the second mode signal MD2 is activated at a logic high level, the external voltage VPERI is pulled down using a second driving force during the drive period T23 to T24. A greater driving force is used in the second mode MODE2 to drive the external voltage VPERI than in the first mode MODE1. Therefore, in the second mode MODE2, the external voltage VPERI reaches the target voltage level faster than in the first mode MODE1.

[0093] The concept has been disclosed in conjunction with various examples and embodiments. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and concept of this disclosure. The embodiments disclosed in this specification should be considered illustratively rather than restrictively. The scope of this disclosure is not limited to the specification, and all distinguishing features within the equivalent scope should be construed as included in this disclosure. All variations within the meaning and scope of the equivalents of the claims are included within its scope.

Claims

1. A storage system, comprising: An intermediate layer is disposed on the substrate; and Storage devices and processors are disposed on the intermediary layer and connected by wiring within the intermediary layer; The storage device includes a base die stacked on the interposer layer and a plurality of core dies; The substrate operates under input / output power supply voltage; Each of the plurality of core dies receives a power supply voltage through the base die to generate an external voltage with a voltage level lower than the power supply voltage, and operates under the external voltage.

2. The storage system according to claim 1, in, Each of the plurality of core dies includes an external voltage control circuit. The peripheral voltage control circuit pulls up the peripheral voltage based on the power supply voltage until the start-up operation terminates. Specifically, the peripheral voltage control circuit pulls down the peripheral voltage to the target voltage level during the driving period after the start-up operation terminates.

3. The storage system according to claim 2, wherein, The peripheral voltage control circuit includes: Pull-up drive circuit, which pulls up the external voltage based on the power-on signal; and A pull-down drive circuit that pulls down the external voltage based on the power-on signal.

4. The storage system according to claim 3, in, The pull-up drive circuit receives the power-on signal activated according to the power supply voltage during the power-on period, and The power-on signal is deactivated synchronously with the termination time of the startup operation.

5. The storage system according to claim 3, wherein, When the power-on signal is activated, the pull-up drive circuit drives the external voltage to the power supply voltage.

6. The storage system according to claim 3, wherein, The pull-down drive circuit drives the external voltage to ground during the drive period starting from the time the power-on signal is deactivated.

7. The storage system according to claim 3, wherein, The pull-down drive circuit includes: A leakage current switching signal generation circuit, which generates a leakage current switching signal based on the power-on signal; and The leakage current driving circuit pulls down the external voltage based on the leakage current switching signal.

8. The storage system according to claim 7, wherein, The leakage current switching signal generation circuit includes: An oscillator that generates oscillating pulses after the startup operation is terminated and the power-on signal is deactivated; A latch that latches the power supply voltage when the oscillation pulse is generated, and generates a latch signal; and A logic device that generates a leakage switching signal to pull down the external voltage during the drive time period based on the latch signal and the power-on signal.

9. The storage system according to claim 7, wherein, The leakage current driving circuit includes a driving device that is turned on based on the leakage current switching signal to pull down the external voltage to ground voltage.

10. The storage system according to claim 2, wherein, The peripheral voltage control circuit includes: The pull-up drive circuit pulls up the external voltage based on the power-on signal; A first pull-down drive circuit, wherein: when a first mode signal is activated, a first driving force is used to pull down the external voltage based on the power-on signal; and The second pull-down drive circuit, when the second mode signal is activated, uses a second driving force to pull down the external voltage based on the power-on signal.

11. The storage system according to claim 10, wherein, The peripheral voltage control circuit receives the power-on signal, which is activated during the power-on period according to the power supply voltage and deactivated synchronously with the end of the startup operation.

12. The storage system according to claim 10, wherein, The first pull-down drive circuit includes: A first leakage current switching signal generation circuit generates a first leakage current switching signal based on the power-on signal; and The first leakage current driving circuit uses the first driving force to pull down the external voltage based on the first leakage current switching signal.

13. The storage system according to claim 12, wherein, The first leakage current switching signal generation circuit includes: A first oscillator generates a first oscillation pulse after the startup operation is terminated and the power-on signal is deactivated. A first latch latches the power supply voltage to generate a first latch signal when the first oscillation pulse is generated. A first logic device performs a first logic operation based on the first latch signal and the power-on signal; and The second logic device, when the first mode signal is activated, generates the first leakage switching signal based on the output signal of the first logic device during the driving time period, so as to use the first driving force to pull down the peripheral voltage.

14. The storage system of claim 10, wherein the second pull-down drive circuit comprises: The second leakage current switching signal generation circuit generates a second leakage current switching signal based on the power-on signal. and The second leakage current driving circuit uses the second driving force to pull down the external voltage based on the second leakage current switching signal.

15. A storage device comprising: A base die that receives and operates under the input / output power supply voltage; and Multiple core dies are stacked on the base die; Each of the plurality of core dies receives a power supply voltage through the base die to generate an external voltage with a voltage level lower than the input / output power supply voltage, and operates under the external voltage.

16. The storage device according to claim 15, wherein, Each of the plurality of core dies includes an external voltage control circuit. Specifically, during the driving period after the start-up operation terminates, the peripheral voltage control circuit pulls the peripheral voltage down to the target voltage level. The peripheral voltage control circuit receives a power-on signal, which is activated during the power-on period based on the power supply voltage and deactivated synchronously with the termination time of the startup operation.

17. The storage device according to claim 16, wherein, The peripheral voltage control circuit includes: A pull-up drive circuit, which pulls up the external voltage based on the power-on signal; and A pull-down drive circuit that pulls down the external voltage based on the power-on signal.

18. The storage device according to claim 17, wherein, The pull-up drive circuit drives the external voltage to the power supply voltage when the power-on signal is activated.

19. The storage device according to claim 17, wherein, The pull-down drive circuit includes: A leakage current switching signal generation circuit, which generates a leakage current switching signal based on the power-on signal; and The leakage current driving circuit pulls down the external voltage based on the leakage current switching signal.

20. The storage device according to claim 16, wherein, The peripheral voltage control circuit includes: A pull-up drive circuit that pulls up the external voltage based on the power-on signal; A first pull-down drive circuit, wherein: when a first mode signal is activated, the peripheral voltage is pulled down using a first driving force based on the power-on signal; and The second pull-down drive circuit, when the second mode signal is activated, uses a second driving force to pull down the external voltage based on the power-on signal.

21. A method for controlling an operating voltage, the method comprising: When the power-on signal is activated, the external voltage supplied to the core die will be pulled up to the power supply voltage. and When the power-on signal is deactivated, the external voltage is pulled down to ground. The power-on signal is activated based on the power supply voltage and remains activated until the startup operation terminates. The power-on signal is deactivated synchronously with the termination time of the startup operation.

22. The method according to claim 21, wherein, The pull-down drive of the external voltage includes: An oscillation pulse is generated after the start-up operation terminates; and The driving time period is established based on the oscillation pulse.

23. The method according to claim 22, wherein, The pull-down driver's peripheral voltage also includes: Generate a leakage current switching signal that is activated during the driving time period; and The external voltage is driven by the leakage current switching signal.

24. The method according to claim 21, wherein, The pull-down drive of the external voltage includes: When the first mode signal is activated during the drive period following the termination of the startup operation, the peripheral voltage is pulled down using the first drive force; and When the second mode signal is activated during the driving time period after the start-up operation is terminated, the peripheral voltage is driven by the second driving force.

25. The method according to claim 21, wherein, The second driving force is greater than the first driving force.

26. A storage device comprising: The core die includes multiple peripheral voltage control circuits. Each peripheral voltage control circuit uses pull-up and pull-down drivers to generate the peripheral voltage. The core die operates under the external voltage, and The core die receives the power supply voltage and generates an external voltage with a voltage level lower than the power supply voltage.

27. The storage device according to claim 26, in, The external voltage control circuit pulls up the external voltage according to the power supply voltage until the start-up operation terminates, and Specifically, the peripheral voltage control circuit pulls down the peripheral voltage to the target voltage level during the driving period after the start-up operation terminates.

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