Self-timed circuit for semiconductor memory devices and memory devices

Abstract

Self-timed circuit for semiconductor memory device and memory device. A memory circuit (MEM) comprising: an array (ARR) of bit cells (BC) connected to a respective word line (WL) in rows and to one of a respective bit line (BL) in columns; a sense amplifier (S-Amp) circuit connected to the bit lines; an external clock input (In1) to receive an external clock signal (Ext-Clck) comprising external clock pulses having a first time length; and a timing circuit (T-Cntl) to track a time required to charge one of the bit lines, the time being a second time length, the timing circuit (T-Cntl) to generate an internal clock signal (Int-Clk) comprising internal clock pulses (Int-Clck Pulse ) and to transmit the internal clock signal to the sense amplifier circuit (S-Amp), a width of the internal clock pulses being defined as a longer one of the first time length and the second time length.

Description

Technical Field

[0001] The technical field of this invention relates to random access memory (RAM) cells, each containing an element whose state defines an information bit, which is read or written according to a timing operation sequence. Background Technology

[0002] In memories such as random access memory (RAM), precise timing of operations is crucial to ensuring the correct workflow of write and read operations. The timing and propagation of various signals directly affect the speed and reliability of data writing or retrieval.

[0003] During a typical read operation, the read word line is activated, causing the connected bit cells to transmit their stored data, or bits, as voltages to their respective bit lines. This data is sensed by sense amplifiers, which need to be enabled at a given time to ensure that the voltages on the bit lines are reliably detected and processed. For this purpose, the memory timing circuitry plays a crucial role, generating timing signals that determine when the sense amplifiers should be activated.

[0004] However, real-world factors such as variations in memory manufacturing and usage (known as process, voltage, and temperature variations, or PVT variations) introduce changes in signal propagation and word line and bit line charging, affecting memory operation, especially read operations.

[0005] Process variations originate from the manufacturing process of memory, which is formed from chips that are part of a semiconductor wafer. During wafer fabrication, variations inevitably occur depending on the chip's location on the wafer and the difficulty of accurately reproducing the same manufacturing parameters (especially considering lower manufacturing nodes). Examples include: ultraviolet wavelength, oxide thickness, charge carrier mobility, transistor channel length, metal thickness, and diffusion depth. Voltage variations arise from voltage drops on the power grid network within the memory, noise caused by parasitic inductance, and voltage irregularities provided by on-chip voltage regulators. Temperature variations may occur due to non-uniformity in transistor density or switching activity throughout the memory.

[0006] Therefore, the components of the circuitry forming the memory can be associated with their respective resistors R and capacitors C, causing each component to exhibit individual "RC characteristics." These RC characteristics control the propagation of signals throughout the memory, such as along bit lines and word lines. Among chips originating from the same wafer and thus undergoing nominally identical processing, some chips may propagate signals faster than others. The former are sometimes referred to as "fast angles," while the latter are sometimes called "slow angles." Considering the speed of signal propagation is essential for achieving high-performance memories, as they are heavily dependent on time-dependent operations.

[0007] To address the consequences of such uncontrolled changes in memory, timing circuits capable of withstanding PVT variations are needed. These circuits must maintain precise timing of operations under varying environmental and operational conditions. Timing circuits can be designed to track or simulate signals, potentially using virtual word lines and / or virtual bit lines to generate appropriate timing signals. Examples include patent documents US 6181626 B1, US 6646938 B2, US 20150063046 A1, EP 0422939 B1, US6388931, or US 2008205176 A1. These circuits are largely used to control circuits from both slow and fast angles in the same way, ensuring that differences in their effective characteristics do not affect how they are controlled, thus allowing them to be applied to each memory independently of whether it is "fast" or "slow".

[0008] However, there is still a need for better and simpler control of read operations in memory circuits, taking into account the individual characteristics of the memory, or even memory sharing the same design.

[0009] Against this backdrop, it is proposed to strengthen the control of the timing pulse width used to control the latching of the sense amplifier in the memory circuit. Summary of the Invention

[0010] Therefore, a first aspect of the present invention relates to a memory circuit comprising: a bit cell array arranged in rows and columns, each row of bit cells being connected to a respective word line, each column of bit cells being connected to one of its respective bit lines, the word lines being connected to a word line driver circuit, and the bit lines being connected to a multiplexer circuit; a sense amplifier circuit configured to be connected to the bit lines; an external clock input configured to receive an external clock signal comprising an external clock pulse having a first time length; a virtual word line; a virtual first line; and a timing circuit configured to track the time required to charge one of the bit lines, the time being a second time length, the timing circuit comprising: a reset signal generation circuit configured to generate and send a pulse reset signal when the voltage of the virtual first line reaches a given threshold; and a pulse generation circuit having a first input and a second input, the first input being connected to the external clock pulse. The system includes a clock input terminal, the second input terminal being configured to receive the pulse reset signal, the pulse generation circuit being configured to (i) generate and send a trigger signal in response to a pulse of an external clock signal to charge the virtual word line, and (ii) generate a pulse generation signal containing a pulse that begins with a pulse of an external clock signal and ends upon receiving the pulse reset signal; and a pulse width determination circuit being configured to receive (i) the external clock signal and (ii) the pulse generation signal, the selection circuit being further configured to generate and output the internal clock signal, and the timing circuit being configured to generate an internal clock signal containing an internal clock pulse and transmit the internal clock signal to the sense amplifier circuit, wherein the width of the internal clock pulse is defined as the longer of the first time length and the second time length.

[0011] Advantageously, this memory circuitry allows the internal clock signal to automatically adapt to variations in memories with the same design. This clock signal is used to determine the correct timing for enabling the sense amplifier circuitry, specifically when the bit lines are fully charged during a read operation.

[0012] This circuit is suitable for equipping memory circuits, whether they are "fast-angle" or "slow-angle," meaning that signals propagate faster or slower than the typical propagation speed. Furthermore, this circuit can be easily adapted to bit arrays with any number of rows and columns.

[0013] Furthermore, this circuit does not require user control of the clock signal or selection between different clock signals via additional control signals and additional circuitry dedicated to this function, because the circuit according to the invention automatically outputs a clock signal appropriate to the situation.

[0014] Other non-limiting features of the first aspect of the invention, whether used alone or in any technically feasible combination:

[0015] - The memory circuit can be configured to drive the respective voltages of the bit lines according to the data stored in the bit cells respectively connected to the bit lines during a read operation of the memory circuit;

[0016] - The timing circuit can track the time required to charge one of the bit lines by tracking the time required to charge the virtual bit line, where the time required to charge the virtual bit line represents the time required to charge the bit line.

[0017] - The memory circuit may include: a virtual word line; and a virtual first line; the timing circuit includes: a reset signal generation circuit configured to generate and send a pulse reset signal when the voltage of the virtual first line reaches a given threshold; the pulse generation circuit has a first input and a second input, the first input being connected to the external clock input, the second input being configured to receive the pulse reset signal, the pulse generation circuit being configured to (i) generate and send a trigger signal to charge the virtual word line in response to a pulse of the external clock signal, and (ii) generate a pulse generation signal containing a pulse that begins with a pulse of the external clock signal and ends upon receiving the pulse reset signal; and a pulse width determination circuit configured to receive (i) the external clock signal and (ii) the pulse generation signal, the selection circuit being further configured to generate and output the internal clock signal;

[0018] - The pulse width determination circuit can be configured to perform an OR logic gate function that takes an external clock signal and a pulse generation signal as inputs and an internal clock signal as output;

[0019] - The memory circuit may further include a virtual bit line emulation circuit connected to the virtual bit line and configured to emulate the environment of a bit line in the bit cell array, such that the time required to charge the virtual bit line is substantially the same as the time required to charge the bit line.

[0020] - The memory circuit may further include a virtual word line emulation circuit connected to the virtual word line and configured to emulate the environment of a word line in the bit cell array, such that the propagation of a signal along the virtual word line is substantially the same as the propagation along the word line.

[0021] - The memory circuit may further include a delay circuit configured to delay the pulse generation signal generated by the pulse generation circuit before the pulse generation signal reaches the pulse width determination circuit; and

[0022] - The memory circuit can be a resistive RAM.

[0023] The present invention extends to an embedded system (EmbSys) including memory circuitry according to the first aspect of the invention, the system being connected to a microprocessor. Attached Figure Description

[0024] Many other features and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, wherein:

[0025] Figure 1 A conventional memory is shown;

[0026] Figure 2 A circuit according to the present invention is shown. Figure 1 Conventional memory;

[0027] Figure 3 It shows the addition Figure 1 In memory Figure 2 Circuit block diagram;

[0028] Figure 4 The pulse width determination circuit is shown;

[0029] Figure 5 A portion of the bitline simulation circuit is shown;

[0030] Figure 6 This shows a portion of the word line simulation circuit;

[0031] Figure 7 Another part of the bitline simulation circuit is shown;

[0032] Figure 8 yes Figure 3 Timing diagram of the circuit's operation under slow-angle conditions;

[0033] Figure 9 yes Figure 3 The timing diagram of the circuit's operation under fast-angle conditions; and

[0034] Figure 10 An embedded system containing a resistive memory (MEM) is shown.

[0035] These diagrams are schematic and are not drawn to scale for clarity. Detailed Implementation

[0036] Figure 1Figure (A) illustrates a general architecture of random access memory (RAM) having an array of bit cells BC, each row-arranged bit cell BC connected to its respective word line WL, and each column-arranged bit cell BC connected to a corresponding pair of lines, designated in this specific example as a first line or bit line (labeled BL) and a second line or source line (labeled SL). The word line WL is connected to a word line driver WL-Drv circuit, and the bit line BL and source line SL are connected to a multiplexer circuit SL / BL-Mux. A sense amplifier circuit S-Amp is connected to the bit lines via the multiplexer circuit SL / BL-Mux. Figure 1 In the memory array shown in (A), a bit line is a circuit component that is strongly driven to the desired value when reading or writing data stored in the bit cell connected to it.

[0037] Set, reset, and read operations can be applied to bit cells in the array ARR of resistive RAM type memory MEM. Figure 1 (A) in the text represents a conventional structure of resistive random access memory, or ReRAM. This type of resistive RAM is described, for example, in patent US11735260B2.

[0038] exist Figure 1 In the RAM, each bit cell BC of the array ARR includes a ReRAM resistor Var formed by electrodes EL1 and EL2 sandwiching (for example) an oxide layer OL. R and a selection transistor Sel Tr Its source and drain are connected in series with the ReRAM resistor, such as Figure 1 As shown in (B) in the diagram.

[0039] The array of bit cells, ARR, comprises columns and rows of bit cells. Each column includes (i) a bit line BL, connected through a ReRAM resistor Var. R Transistor Sel connected to each bit cell in this column Tr (ii) a source line SL, through transistor Sel Tr The source and drain of the ReRAM resistor Var R Connected to the bit line BL. Each row of bit cells includes a word line WL, connected to the select transistor Sel of each bit cell in that row. Tr The gate of the [unclear - likely a specific type of ...

[0040] exist Figure 1 In (A), each intersection of word line WL and bit line BL corresponds to a bit cell BC. Figure 1(C) in the diagram shows two adjacent bit cells BC1 and BC2 that belong to the same row and are therefore connected to the same word line WL.

[0041] Figure 1 The general architecture shown cannot solve the problems related to PVT changes.

[0042] Figure 2 It shows Figure 1 The memory circuit MEM integrates a virtual bit line (DBL), a virtual word line (DWL), and a timing circuit T-Cntl. This timing circuit is connected to the virtual bit line, the virtual word line, and the sense amplifier circuit S-Amp. The timing circuit T-Cntl is also connected to the lines required for normal memory operation (clock signal transmission lines, high or low voltage lines, ground lines, control signal lines, etc.). Notably, an external clock signal is recognized as the external clock signal and contains pulses of a given constant width generated at constant intervals. Undoubtedly, the pulse interval and width represent their respective time lengths, which can be expressed in nanoseconds.

[0043] The virtual line and timing control circuitry are configured to (i) track the time required to charge one of the bit lines, and (ii) generate an internal clock signal Int-Clk containing an internal clock pulse, and transmit the internal clock signal to a sense amplifier circuit S-Amp and other clock-dependent signals, wherein the width of the internal clock pulse is defined as the longer of the pulse width of the external clock signal and the time required to charge one of the bit lines.

[0044] In practice, due to variations in PVT, the time required to charge the bit lines can differ from memory to memory. Therefore, it is necessary to assess the time required for effective bit line charging to reliably perform read operations. It is worth noting that operating the sense amplifier circuit before the bit lines are fully charged risks incompletely reading the memory contents. Conversely, if the clock signal is slowed down to prevent incomplete bit line charging, memory read speeds will often be slower than necessary.

[0045] The timing control circuit addresses this issue by extending the read operation time only when necessary; that is, when the pulse of the external clock line is too short to complete bit line charging (based on an assessment of the time required to effectively charge one bit line), the pulse of the internal clock signal is extended. In this embodiment, tracing is performed on a virtual bit line DBL, which is not connected to any bit cell of the memory bit cell array. This virtual bit line is charged via a virtual word line DWL, which is also not connected to any bit cell of the memory bit cell array. In other words, the operation of the virtual bit line and the virtual word line is independent of the bit cell, except that their operation depends on the external clock signal and the voltage supplying the bit cell array and its connecting circuitry.

[0046] Virtual bit lines and virtual word lines preferably behave similarly to the bit lines and word lines of a bit cell array in terms of signal propagation along these lines. To this end, the environments of the virtual lines are arranged to achieve this: the bit line emulation circuit Emul.BL is preferably connected to the virtual bit line DBL. Similarly, the word line emulation circuit Emul.WL is preferably connected to the virtual word line DWL. More specifically, these emulation circuits can reproduce any electrical capacitance connected in any circuit in an actual implementation, and represent, for example, the parasitic capacitance that needs to be charged when the bit lines and word lines are charged.

[0047] Therefore, the bit-line emulation circuit Emul.BL and the word-line emulation circuit Emul.WL simulate the capacitance of a bit line and a word line connected to the bit cell array, respectively. The capacitance depends on the components connected to the bit line (actual size, thickness, geometry, etc.), such as the interconnects and transistors. These capacitances can vary between memories due to minute variations that occur during manufacturing, even if their designs are strictly identical.

[0048] Figure 3 The timing control circuit T-Cntl is shown, along with the virtual bit line DBL, the virtual word line DWL, the sense amplifier circuit S-Amp (all clock-dependent circuits), the bit line emulation circuit Emul.BL, and the word line emulation circuit Emul.WL.

[0049] Bitline simulation circuits may include, for example, Figure 5 The virtual bit cell DBC shown BL Virtual bit unit DBC BL The number of virtual bit cells (BCs) is preferably matched to the number of bit cells (BCs) connected by a bit line (BL) in the array ARR, and is preferably connected along the virtual bit line (DBL) to match the connection between bit cells (BCs) and bit lines (BL). Virtual bit cell (DBC) BL Each can include a transistor Tr BL Transistor Tr BL Connect one of their source and drain terminals to the virtual bit line DBL to simulate the electrical environment of a bit line BL of the array ARR. The gate, as well as the other of the source and drain terminals, can be connected to ground. In this way, any capacitor that provides an effective connection to the bit line can be closely approximated, and an environment simulating the bit line environment is reproduced for the virtual bit line.

[0050] In addition, such as Figure 7 As shown, the virtual bitline simulation circuit may optionally include a pMOS transistor Tr Adj The virtual bit line DBL is selectively connected to the voltage Vdd. As shown in the figure, the virtual bit line DBL can be connected to each transistor Tr. Adj One of the source and drain of each transistor, and each transistor TrAdj The main body of the transistor, along with another of its source and drain terminals, can be connected to a line with a voltage of Vdd. All or part of the transistor Tr Adj This can be controlled by the user; in this example, it's achieved by inputting to the three inputs In1, In2, and In3 of their respective control logic gates LG (OR gates in this example). More generally, n inputs (where n is a natural number) can be used, depending on the transistor Tr to be controlled. Adj The quantity. Figure 7 The circuit includes a transistor Tr Adj Its gate is connected to the virtual word line DWL via an inverter INV to provide a reference capacitance for the virtual bit line DBL. The second input of each control logic gate LG, Dwl_neg, is connected to the virtual word line (not shown in the figure), in this example via an inverter INV. The output of the control logic gate is connected to the transistor Tr. Adj The gate. This allows control over the total capacitance effectively connected to the virtual bit line, thereby allowing adjustment of the bit line rise delay of any given memory and compensating for differences between memories, even if they have the same design.

[0051] Similar to bit-line emulation circuits, word-line emulation circuits can include, for example: Figure 6 The virtual bit cell DBC shown WL Virtual bit unit DBC WL The number of virtual bit cells (BCs) is preferably matched to the number of bit cells (BCs) connected by a word line (WL) in the array ARR, and is preferably connected along the virtual word line (DWL) to match the connection of bit cells (BCs) to word lines (WL). Virtual bit cells (DBCs) WL Each can include a transistor Tr WL Transistor Tr WL Their gates are connected to the virtual word line DWL to simulate the electrical environment of a word line WL of the array ARR. Transistor Tr WL The source and drain can be connected together. In this way, the capacitors effectively connected to any given word line can be closely approximated, and a simulated word line environment is recreated for the virtual word line.

[0052] The transistors Tr in the simulation circuits Emul.BL and Emul.WL BL and Tr WL Ideally, the transistors should be matched in characteristics (geometry, size, etc.) to the bit cells BC of the array ARR to better replicate the electrical environment of the bit lines and word lines.

[0053] More generally, the simulation circuit reproduces the RC characteristics of the bit lines and word lines as seen in the memory circuit when the bit lines are charged during a read operation.

[0054] In this example, the bit-line emulation circuit Emul.BL includes a control transistor Tr Cnt It can be an NMOS transistor, with one of its source and drain connected to ground (GND), the other connected to the virtual bit line (DBL), and its gate connected to the virtual word line (DWL) via an inverter (INV). When the virtual word line is at a low voltage, the NMOS control transistor Tr... Cnt Connecting the virtual word line to ground effectively allows it to discharge. When the virtual word line is at a high voltage, at least one PMOS transistor Tr... Adj Charge the virtual bit line to Vdd.

[0055] like Figure 3 As shown, the timing control circuit T-Cntl may include a reset signal generation circuit Reset-Gen, a pulse generation circuit Pulse-Gen, a pulse width determination circuit Pulse-Width, and a delay circuit Del.

[0056] The timing control circuit T-Cntl has an input terminal In1 for receiving the external clock signal Ext-Clck, an input terminal In2 for connecting to the virtual bit line DBL, and an output terminal Out1 for outputting the internal clock signal Int-Clck to the sense amplifier circuit S-Amp and other clock-dependent circuits.

[0057] The reset signal generation circuit Reset-Gen is connected to the virtual bit line DBL via input In2 and is configured to generate and send a pulse reset signal Pulse-Reset when the voltage of the virtual first line reaches a given threshold. This threshold can be predetermined and can be adjusted as is commonly known, for example, by the size of the transistor and / or by using a buffer circuit.

[0058] The Reset-Gen reset signal generation circuit can also be configured to connect the virtual bit line DBL to a line set to voltage Vdd during the charging operation of the virtual bit line DBL, for example, when the trigger signal Stp-Trig sent via the virtual word line DWL is at a high logic level. The Reset-Gen reset signal generation circuit can also be configured to connect the virtual bit line DBC to ground GND when the trigger signal Stp-Trig sent via the virtual word line DWL is at a low logic level. These functions can be implemented by connecting the virtual word line to the gate of a transistor that connects the virtual bit line to a line that is itself either at Vdd or connected to ground GND via its source and drain.

[0059] The pulse generation circuit Pulse-Gen has: a third input terminal In3, which is connected to an external clock input terminal In1; and a fourth input terminal In4, which is configured to receive a pulse reset signal Pulse-Reset generated by the reset signal generation circuit Reset-Gen. The pulse generation circuit can be configured to (i) charge a virtual word line in response to a pulse generation trigger signal Stp-Trig from an external clock signal, and (ii) generate a pulse generation signal Pulse-Gen-Clck, which contains a pulse that begins with a pulse from the external clock signal Ext-Clck and ends upon receiving the pulse reset signal Pulse-Reset. The trigger signal Stp-Trig and the pulse generation signal Pulse-Gen-Clck are output by the pulse generation circuit Pulse-Gen through second and third output terminals Out2 and Out3, respectively.

[0060] The Pulse Width determination circuit is configured to perform an OR logic gate function with an external clock signal Ext-Clck and a pulse generation signal Pulse-Gen-Clck as inputs and an internal clock signal Int-Clck as output. For this purpose, the Pulse Width determination circuit has a fifth input In5 connected to a third output Out3, and a sixth input In6 connected to a first input In1.

[0061] like Figure 4 As shown, the pulse width determination circuit Pulse-Width can be an OR logic gate, with the external clock signal Ext-Clck and the pulse generation signal Pulse-Gen-Clck as inputs, and the internal clock signal Int-Clck as output.

[0062] Based on the interaction between the above components, the pulse of the internal clock signal Int-Clck output by the pulse width determination circuit Pulse-Width begins at the rising edge of the external clock signal pulse and ends at the longer of the following two: (i) the duration of the external clock signal pulse ending, and (ii) the duration required for the virtual bit line to charge to a predetermined threshold.

[0063] The delay circuit Del is an optional component that can be inserted between the third output of the pulse generation circuit Pulse-Gen and the fifth input of the pulse width determination circuit Pulse-Width. The delay circuit Del includes inputs (not shown) that users can use to finely adjust the delay.

[0064] Nevertheless, the present invention is not limited to Figures 3 to 7The specific example shown illustrates that the functions of the various circuits constituting the timing control circuit can, of course, be implemented in various ways.

[0065] Figure 8 and Figure 9 This is a timing diagram illustrating the operation of the timing control circuit T-Cntl, which generates the internal clock signal Int-Clck by taking into account the effective charging time of the virtual bit line DBL (considered as the charging time representing bit line BL). In the graphs, voltage is expressed in volts (V) and time in nanoseconds (ns). These graphs are for... Figures 3 to 7 The simulation results show the functional operation of the circuit.

[0066] Figure 8 This illustrates the situation where the memory circuitry MEM originates from a slow angle. This means that the bit lines may not be fully charged by the end of an external clock pulse, which is supposed to control the charging time of the bit lines and the activation time of the sense amplifier circuit. In this case, without correction, the sense amplifier circuit may shut down prematurely (unable to sense when the clock is high), making it impossible to reliably evaluate the logic level of the bit cell (evaluated via the bit lines).

[0067] However, according to the present invention, the timing control circuit T-Cntl controls the length of the internal clock signal pulse to match the time required to charge the virtual bit line, thereby automatically shutting down the sensing amplifier circuit when the virtual bit line and the bit line of the array are fully charged.

[0068] As shown in the timing diagram, when the external clock signal Ext-Clck pulse Ext-Clck... Pulse During the rise, the pulse generation circuit Pulse-Gen generates the pulse of the trigger signal Stp-Trig and the pulse of the pulse generation signal Pulse-Gen-Clck. Pulse Pulse Ext-Clck Pulse It also initiated the pulse Int-Clck of the internal clock signal Int-Clk. Pulse .

[0069] The rise of the trigger signal Stp-Trig causes the voltage dwl-clk of the virtual word line DWL to rise, which is sent back to the timing control circuit T-Cntl, and more specifically to the reset signal generation circuit Reset-Gen.

[0070] The rise in the virtual word line DWL voltage dwl-clk causes the virtual bit line DBL voltage dbl to rise, which allows tracking the time required for the bit line to charge.

[0071] When the voltage dbl of the virtual bit line DBL reaches a given threshold, the reset signal generation circuit Reset-Gen generates a pulse in the pulse reset signal Pulse-Reset.

[0072] The pulse in the Pulse-Reset signal triggers the falling pulse of the Pulse-Gen-Clck pulse generation signal. At this time, since the external clock signal pulse has ended (under the assumption of a slow angle, the virtual bit line charging speed is slower than the time required for the external clock signal pulse to end), the external clock signal is at a low level, and only the Pulse-Gen-Clck pulse generation signal keeps the internal clock signal Int-Clck at a high level. Therefore, it is the falling pulse of the Pulse-Gen-Clck pulse that triggers the falling pulse of the internal clock signal Int-Clck, thus turning off the sense amplifier circuit S-Amp.

[0073] In this case, the timing control circuit T-Cntl extends the pulse that enables the sense amplifier circuit, providing the necessary time for the virtual bit line and the bit line to be read to be fully charged.

[0074] Figure 9 This illustrates that the memory circuit MEM originates from a fast angle, which means that the bit line is likely to be fully charged before the external clock pulse that controls the bit line charging time and senses the amplifier circuit's activation time ends.

[0075] As shown in the timing diagram, when the external clock signal Ext-Clck pulse Ext-Clck... Pulse During the rise, the pulse generation circuit Pulse-Gen generates the pulse of the trigger signal Stp-Trig and the pulse of the pulse generation signal Pulse-Gen-Clck. Pulse Pulse Ext-Clck Pulse It also initiated the pulse Int-Clck of the internal clock signal Int-Clk. Pulse .

[0076] The rise of the trigger signal Stp-Trig causes the voltage dwl-clk of the virtual word line DWL to rise, which is sent back to the timing control circuit T-Cntl, and more specifically to the reset signal generation circuit Reset-Gen.

[0077] The rise in the virtual word line DWL voltage dwl-clk causes the virtual bit line DBL voltage dbl to rise, which allows tracking the time required for the bit line to charge.

[0078] When the voltage dbl of the virtual bit line DBL reaches a given threshold, the reset signal generation circuit Reset-Gen generates a pulse in the pulse reset signal Pulse-Reset.

[0079] The pulse trigger pulse of the Pulse-Gen-Clck signal in the Pulse-Reset pulse reset signal falls. At this time, since the external clock signal pulse is still high (under the assumption of a fast angle, the virtual bit line charges faster than the time required for the external clock signal pulse to end), the external clock signal is high. Therefore, it is the falling of the external clock signal Ext-Clck pulse that triggers the pulse Int-Clck of the internal clock signal. Pulse The voltage dropped, and the sense amplifier circuit S-Amp was turned off.

[0080] In this case, the timing control circuit T-Cntl allows the external clock signal to define the timing of the enabled sense amplifier circuit S-Amp: the internal clock signal Int-Clck is essentially the same as the external clock signal Ext-Clck.

[0081] We see that the timing control circuit according to the present invention allows for automatic adaptation of the driving of the memory MEM, regardless of the exact characteristics of the memory in terms of bit line and / or word line charging times. More specifically, the pulses Int-Clck of the internal clock signal Int-Clk. Pulse The width is defined as (i) the pulse of the external clock signal Ext-Clck Pulse The length of (ii) the pulse generation clock signal Pulse-Gen-Clk and the pulse of Pulse-Gen Pulse The longer of the lengths.

[0082] In this instruction manual, Figure 1 (A) and Figure 2 The memory array shown is considered a resistive random access memory (RAM) array. However, the invention is not limited to this type of memory. Other examples of memories to which the memory circuitry according to the invention can be applied include static random access memory (SRAM). In this case, the two lines connecting a column of bit cells BC to the multiplexer circuit SL / BL-Mux are generally referred to as a bit line pair formed by the first bit line and the second bit line. Alternatively, embodiments of the invention can relate to a memory in which any data value stored for a positioning cell is determined by the voltage of the corresponding single bit line signal, or a memory that uses two bit line pairs to determine any data stored for a positioning cell, the data value being determined by detecting the voltage difference between the two bit lines. More generally, any architecture can be employed for the bit cell array ARR and the bit cells BC.

[0083] Each example mentioned in this document can be freely combined within the technological limits understood by those skilled in the art.

[0084] By studying the accompanying drawings, the disclosure, and the appended claims, those skilled in the art can understand and implement other variations of the disclosed embodiments in the course of practicing the claimed invention.

Claims

1. A memory circuit (MEM), the memory circuit comprising: An array (ARR) of bit cells (BC), with each bit cell arranged in a row connected to its respective word line (WL) and each bit cell arranged in a column connected to one of its respective bit lines (BL), the word lines being connected to word line driver circuitry (WL-Drv) and the bit lines being connected to multiplexer circuitry (SL / BL-Mux). - A sense amplifier (S-Amp) circuit configured to be connected to the bit line. - External clock input (In1), which is configured to receive an external clock signal (Ext-Clck) containing an external clock pulse having a first time length. - Virtual Word Line (DWL); and - Virtual First Line (DBL); and - A timing circuit (T-Cntl) configured to track the time required to charge one of the bit lines, the time being a second time length, and the memory circuitry includes: - Reset signal generation circuit (Reset-Gen), which is configured to generate and send a pulse reset signal (Pulse-Reset) when the voltage of the virtual first line reaches a given threshold. - A pulse generation circuit (Pulse-Gen) having a first input (In3) and a second input (In4), the first input (In3) being connected to the external clock input (In1), and the second input (In4) being configured to receive the pulse reset signal (Pulse-Reset). The pulse generation circuit is configured to (i) generate and send a trigger signal (Stp-Trig) in response to a pulse of the external clock signal to charge the virtual word line, and (ii) generate a pulse generation signal (Pulse-Gen-Clck) comprising a pulse that begins with a pulse of the external clock signal (Ext-Clck) and ends upon receiving the pulse reset signal (Pulse-Reset); and - A pulse width determination circuit (Pulse-Width) configured to receive (i) the external clock signal (Ext-Clck) and (ii) the pulse generation signal (Pulse-Gen-Clck), the selection circuit being further configured to generate and output the internal clock signal (Int-Clck). The timing circuit (T-Cntl) is configured to generate an internal clock pulse (Int-Clck). Pulse The internal clock signal (Int-Clk) is transmitted to the sense amplifier circuit (S-Amp), and the width of the internal clock pulse is defined as the longer of the first time length and the second time length.

2. The memory circuit of claim 1, wherein the memory circuit is configured to drive the respective voltages of the bit lines according to data stored in the bit cells respectively connected to the bit lines during a read operation of the memory circuit.

3. The memory circuit according to claim 1 or 2, wherein, The timing circuit (T-Cntl) is configured to track the time required to charge one of the bit lines by tracking the time required to charge the virtual bit line (DBL), the time required to charge the virtual bit line (DBL) representing the time required to charge the bit line.

4. The memory circuit according to claim 1, wherein, The pulse width determination circuit (Pulse-Width) is configured to perform an OR logic gate function with the external clock signal (Ext-Clck) and the pulse generation signal (Pulse-Gen-Clck) as inputs and the internal clock signal (Int-Clck) as outputs.

5. The memory circuit according to claim 1 or 4, further comprising a virtual bit line emulation circuit (Emul.BL) connected to the virtual bit line (DBL) and configured to emulate the environment of one of the bit lines (BL) of the array (ARR) of the bit cells (BC), such that the time required to charge the virtual bit line (DBL) is substantially the same as the time required to charge the single bit line (BL).

6. The memory circuit according to any one of claims 1 to 5, the memory circuit further comprising a virtual word line emulation circuit (Emul.WL), the virtual word line emulation circuit (Emul.WL) being connected to the virtual word line (DWL) and configured to emulate the environment of one word line (WL) of the array (ARR) of the bit cells (BC), such that the propagation of a signal along the virtual word line (DWL) is substantially the same as the propagation along the word line (WL).

7. The memory circuit according to any one of claims 1 to 6, the memory circuit further comprising a delay circuit (Del) configured to delay the pulse generation signal (Pulse-Gen-Clck) generated by the pulse generation circuit (Pulse-Gen) before the pulse generation signal (Pulse-Gen-Clck) reaches the pulse width determination circuit (Pulse-Width).

8. The memory circuit according to any one of claims 1 to 7, wherein, The memory circuit (MEM) is a resistive RAM.

9. An embedded system (EmbSys) including memory circuitry according to any one of claims 1 to 8, the embedded system (EmbSys) being connected to a microprocessor (CPU).

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