In-situ mixed multi-valued memory cell, array architecture and read / write method thereof

Abstract

This invention discloses an in-situ hybrid multi-value memory cell, array architecture, and read / write method thereof, belonging to the field of semiconductor memory technology. The memory cell of this invention includes a selection transistor and a ferroelectric capacitor; the first plate of the ferroelectric capacitor is connected to the source or drain of the selection transistor to form a memory node, and the second plate of the ferroelectric capacitor is connected to a plate line; the gate of the selection transistor is connected to a word line, and the drain or source of the selection transistor is connected to a bit line; wherein, the memory cell is configured to have four logical memory states, defined by a combination of a first data bit (F-bit) and a second data bit (D-bit); the first data bit is non-volatilely stored based on the ferroelectric polarization direction of the ferroelectric capacitor; the second data bit is volatilely stored based on the charge maintained by the potential difference between the memory node and the plate line; the memory cell simultaneously maintains the memory states of the first data bit and the second data bit within the same time period.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit storage technology, specifically relating to an in-situ hybrid multi-value memory cell, array architecture, and its read / write method. Background Technology

[0002] In the era of big data and artificial intelligence (AI), data-intensive applications such as deep neural networks (DNNs) place extremely high demands on storage systems. The existing memory hierarchy mainly consists of dynamic random access memory (DRAM) and flash memory, but both technologies are facing serious challenges. While DRAM is fast, its volatility necessitates frequent refresh operations, resulting in significant static power consumption. Furthermore, as process nodes shrink to below 10nm, the aspect ratio limitations of DRAM capacitors make maintaining their capacitance values ​​exceptionally difficult. On the other hand, emerging non-volatile memories (NVMs) such as resistive random access memory (ReRAM) and phase-change memory (PCM) have solved the data retention problem, but their write latency and endurance are far inferior to DRAM, making them unsuitable for use as primary working memory.

[0003] To combine the advantages of both, the industry has proposed the concept of "hybrid storage." Current hybrid solutions mainly fall into two categories: Component-level hybrid approach: Packaging DRAM chips and NVM chips together. This approach does not solve the problems of high power consumption and latency in data transfer between chips, and increases the overall chip area.

[0004] Cell-level hybrid: Utilizing the reconfigurability of the 1T1C FeRAM cell, it can be configured into either DRAM or FeRAM mode. A cell can only function as either DRAM or FeRAM at any given time; when switching modes is required, the ferroelectric polarization state must be changed, incurring additional latency and energy overhead. More importantly, this single-value storage (SLC) mode does not increase storage density in physical space, failing to meet the urgent need for high-density on-chip storage in AI edge computing.

[0005] Therefore, developing an "in-situ hybrid MLC" technology that can simultaneously store non-volatile weights and volatile activations without increasing cell area has become crucial to overcoming the memory wall bottleneck. However, superimposing two physical mechanisms (polarization and charge) within the same cell can lead to complex inter-bit interference problems, a challenge that current technologies have yet to solve. Summary of the Invention

[0006] To overcome the shortcomings of existing technologies, the present invention aims to provide an in-situ hybrid multi-valued memory cell (MLC FeRAM), an array architecture, and a read / write method therein, in order to solve the problems of low density and low mode switching efficiency in existing hybrid memory technologies. Furthermore, it reveals the physical mechanism of "inter-bit interference" in hybrid memory and proposes an anti-interference operation method based on voltage regulation, which significantly improves memory reliability.

[0007] To achieve the above objectives, the present invention adopts the following specific technical solutions: In a first aspect, the present invention provides an in-situ hybrid multi-value memory cell, comprising a selection transistor (1T) and a ferroelectric capacitor (1C); a first plate of the ferroelectric capacitor is connected to the source or drain of the selection transistor to form a memory node (SN), and a second plate of the ferroelectric capacitor is connected to a plate line (PL); the gate of the selection transistor is connected to a word line (WL), and the drain or source of the selection transistor is connected to a bit line (BL); wherein the memory cell is configured to have four logical memory states, the four logical memory states being defined by a combination of a first data bit (F-bit) and a second data bit (D-bit); the first data bit is non-volatilely stored based on the ferroelectric polarization direction of the ferroelectric capacitor; the second data bit is volatilely stored based on the amount of charge maintained by the potential difference of the memory node relative to the plate line; the memory cell simultaneously maintains the memory states of the first data bit and the second data bit within the same time period.

[0008] The first data bit (F-bit) is defined as the most significant bit, stored using the residual polarization direction of the ferroelectric capacitor. Positive polarization (+Pr) corresponds to logic "0", and negative polarization (-Pr) corresponds to logic "1". The second data bit (D-bit) is defined as the least significant bit, stored using the amount of free charge on the ferroelectric capacitor plates. A storage node voltage of 0V corresponds to logic "0", and a voltage of... The time corresponds to the logic "1".

[0009] Furthermore, the four logical storage states include: State "00": This corresponds to the ferroelectric capacitor being in a positive residual polarization state (+Pr) and the storage node being at a low voltage level; State "01": corresponds to the ferroelectric capacitor being in a positive residual polarization state (+Pr) and the storage node being at a high voltage level ( ); State "10": This corresponds to the ferroelectric capacitor being in a negative residual polarization state (-Pr) and the storage node being at a low voltage level; State "11": corresponds to the ferroelectric capacitor being in a negative residual polarization state (-Pr) and the storage node being at a high voltage level ( ); The first data bit is the most significant bit (MSB), and the second data bit is the least significant bit (LSB).

[0010] Secondly, the present invention provides a memory array architecture composed of in-situ hybrid multi-value memory cells as described above, comprising: Multi-line character lines (WL) and multi-line board lines (PL), wherein the character lines and the board lines are arranged parallel to each other; Multi-column bit lines (BLs), wherein the bit lines are perpendicular to the word lines and the board lines; A sensing amplifier module is connected to the bit line; wherein the sensing amplifier module includes a first sensing amplifier (SA_D) and a second sensing amplifier (SA_F) arranged in pairs; the first sensing amplifier is configured to sense the second data bit; and the second sensing amplifier is configured to sense the first data bit.

[0011] Thirdly, the present invention provides a read / write method for a storage array architecture composed of in-situ hybrid multi-value memory cells as described above, including a two-step write process and a four-stage read timing sequence. The two-step write process includes: First writing step: By controlling the voltage difference between the bit line and the plate line, the ferroelectric capacitor is set to positive polarization or negative polarization in order to write the first data bit; The second writing step is as follows: while maintaining the polarization state of the first data bit, the selection transistor is activated, and charge is applied to or released from the storage node through the bit line to write the second data bit.

[0012] Furthermore, the second write step also includes an inter-bit interference suppression operation, which is used to mitigate the effect of the reverse electric field generated when the second data bit is high and the first data bit is positively polarized on the ferroelectric domains; the interference suppression operation includes at least one or more combinations of the following strategies: Strategy 1: In the second write step, the high-level voltage used to write the second data bit ( It is set to a value higher than the standard logic level to compensate for charge loss caused by the nucleation-limited conversion mechanism; Strategy 2: In the first write step, the write voltage applied to the board line ( The voltage value is set to enable the ferroelectric material to operate in the local hysteresis loop (Minor Loop) in order to reduce the depolarization field; Strategy 3: In the second write step, when writing a high-level voltage to the storage node, a positive bias voltage is simultaneously applied to the board line. The bias voltage is less than the high-level voltage to reduce the net voltage drop across the ferroelectric capacitor.

[0013] Furthermore, by jointly adjusting the high-level voltage ( The write voltage ( ) and the bias voltage ( This ensures that the second data bit has a read voltage margin (SenseMargin) greater than 50mV after a preset hold time.

[0014] Furthermore, the four-stage read timing sequence includes: Phase 1 (D-bit Read): Ground the board line, activate the word line, and share the charge on the storage node with the parasitic capacitance of the bit line. Use the first sensing amplifier to amplify the bit line voltage difference and latch the second data bit. Phase 2 (F-bit Read): After Phase 1 is completed, keep the word line active, pull the board line voltage up to the read voltage, use the second sensing amplifier to sense the bit line voltage change and latch the first data bit; Phase 3 (F-bit write-back): The board line voltage is pulled down to ground, and the bit line is driven by the second sensing amplifier to restore the polarization state of the ferroelectric capacitor according to the latched first data bit. Phase 4 (D-bit write-back): Using the first sensing amplifier to drive the bit line, write back the charge to the storage node according to the latched second data bit.

[0015] Compared with the prior art, the present invention has the following advantages: (1) High density: This invention achieves a storage density of 2 bits per cell without changing the standard FeRAM process and cell area, which significantly reduces the cost per bit.

[0016] (2) High energy efficiency: Compared with the traditional method of storing all data in DRAM, this invention stores static data in F-bit (zero refresh power consumption) and only performs DRAM mode operation on dynamic data, which greatly reduces the overall power consumption of the system.

[0017] (3) High reliability: Through the synergistic application of three optimization strategies, the simulation results show that the sense margin of DRAM bits is improved by more than 50% without sacrificing the reliability of FeRAM bits, thus solving the key problem of practical application of hybrid memory. Attached Figure Description

[0018] Figure 1A schematic diagram of the hybrid MLC FeRAM cell structure and the mapping of four storage states on the QV hysteresis loop provided in the embodiments of the present invention; Figure 2 This is a circuit diagram showing the hybrid MLC FeRAM array architecture and dual sense amplifiers (SA_D, SA_F) proposed in this invention. Figure 3 Detailed timing waveform diagrams of the four-stage read operation provided in embodiments of the present invention; Figure 4 A schematic diagram of the physical mechanism of inter-bit interference in this invention: (a) shows the interference path in the QV loop; (b) shows the bit line read voltage as the hold time increases. The changing trend shows the attenuation of the D-bit signal; Figure 5 This is a schematic diagram illustrating the principles of the three optimization methods of this invention (strengthening D-bit, weakening F-bit, and balancing interference) and their specific effects on the QV curve; Figure 6 This is a 3D simulation heat map showing the improved sensing margin (SM) effect after combining three optimization methods according to the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0020] Example 1 like Figure 1 As shown, this embodiment provides an in-situ hybrid multi-value memory cell based on a standard 1T-1C (single transistor-single capacitor) structure, including a select transistor (1T) and a ferroelectric capacitor (1C). The first plate of the ferroelectric capacitor FeCAP is connected to the source or drain of the select transistor to form a memory node (SN), and the second plate of the ferroelectric capacitor is connected to the plate line (PL). The gate of the select transistor is connected to the word line (WL), and the drain or source of the select transistor is connected to the bit line (BL).

[0021] This design utilizes two physical characteristics of FeCAP to implement 2-bit data encoding: The first data bit (F-bit, high bit): Non-volatile storage is achieved using the residual polarization direction of FeCAP; polarization pointing to the bottom electrode (+Pr) is defined as logic "0", and polarization pointing to the top electrode (-Pr) is defined as logic "1". The second data bit (D-bit, low bit): Volatile storage is achieved using the free charge on the storage node (SN); logic "0" is defined when the storage node voltage is 0V, and logic "1" is defined when the voltage is... It is logical "1".

[0022] In this embodiment, the memory unit is configured to have four logical storage states, defined by a combination of a first data bit (F-bit) and a second data bit (D-bit). The first data bit is stored non-volatilely based on the ferroelectric polarization direction of the ferroelectric capacitor; the second data bit is stored volatilely based on the amount of charge maintained by the potential difference between the storage node and the plate line. The memory unit simultaneously maintains the storage states of the first data bit and the second data bit within the same time period. The four logical storage states include: State "00": This corresponds to the ferroelectric capacitor being in a positive residual polarization state (+Pr) and the storage node being at a low voltage level; State "01": corresponds to the ferroelectric capacitor being in a positive residual polarization state (+Pr) and the storage node being at a high voltage level ( ); State "10": This corresponds to the ferroelectric capacitor being in a negative residual polarization state (-Pr) and the storage node being at a low voltage level; State "11": corresponds to the ferroelectric capacitor being in a negative residual polarization state (-Pr) and the storage node being at a high voltage level ( ); The first data bit is the most significant bit (MSB), and the second data bit is the least significant bit (LSB).

[0023] Example 2 like Figure 2 As shown, this embodiment provides a memory array architecture based on the in-situ hybrid multi-value memory cell in Embodiment 1, including multiple word lines (WL), multiple board lines (PL), and multiple bit lines (BL), with word lines and board lines arranged in parallel; bit lines are perpendicular to word lines and board lines. In order to read the small charge signal of D-bit and the larger polarization switching signal of F-bit respectively, each column bit line is connected to a sensing amplifier module.

[0024] The sensing amplifier module includes a first sensing amplifier (SA_D) and a second sensing amplifier (SA_F) arranged in pairs; the first sensing amplifier is configured to sense the second data bit; and the second sensing amplifier is configured to sense the first data bit.

[0025] Example 3 This embodiment provides a read / write method based on the in-situ hybrid multi-value memory cell in Embodiment 1 and the memory array architecture in Embodiment 2, including a two-step write process and a four-stage read timing.

[0026] (1) The two-step write process includes: First writing step: By controlling the voltage difference between the bit line and the plate line, the ferroelectric capacitor is set to positive polarization or negative polarization in order to write the first data bit; The second writing step: While maintaining the polarization state of the first data bit, activate the selection transistor and charge or release charge to the storage node through the bit line to write the second data bit.

[0027] To address the inter-bit interference problem in hybrid memory, this invention, based on the nucleation-limited conversion theory, introduces an inter-bit interference suppression operation in the second write step. The inter-bit interference suppression operation mitigates the impact of the reverse electric field generated when the second data bit is high and the first data bit is positively polarized on the ferroelectric domains; the interference suppression operation includes at least one or more combinations of the following strategies: Strategy 1: In the second write step, the high-level voltage used to write the second data bit ( It is set to a value higher than the standard logic level to compensate for charge loss caused by the nucleation-limited conversion mechanism; Strategy 2: In the first write step, the write voltage applied to the board line ( The voltage value is set to enable the ferroelectric material to operate in the local hysteresis loop (Minor Loop) in order to reduce the depolarization field; Strategy 3: In the second write step, when writing a high-level voltage to the storage node, a positive bias voltage is simultaneously applied to the board line. The bias voltage is less than the high-level voltage to reduce the net voltage drop across the ferroelectric capacitor.

[0028] By jointly adjusting the high-level voltage ( ), write voltage ( ) and bias voltage ( This ensures that the second data bit has a read voltage margin (Sense Margin) greater than 50mV after a preset hold time.

[0029] This invention reveals a core challenge in hybrid storage models—inter-bit interference. For example... Figure 4 As shown in (a), when the memory cell is in state "01" (F=0, D=1), F-bit stores +Pr, while D-bit applies voltage to the memory node. At this point, the FeCAP is subjected to a reverse electric field. According to the theory of nucleation limited switching (NLS), although this electric field is smaller than the coercive field, it will induce accumulative switching of ferroelectric domains over time. This leads to two consequences: the remanent polarization of the F-bit weakens (shifts along the local loop); and the stored charge of the D-bit is used to shield the bound charge of the switched domains, resulting in losses and causing the storage node voltage to decay over time, such as... Figure 4 As shown in (b).

[0030] (2) such as Figure 3 As shown, the four-stage read timing includes: Phase 1 (D-bit read): Ground the board line, activate the word line, and enable charge sharing between the charge on the storage node and the parasitic capacitance of the bit line. Use the first sensing amplifier to amplify the voltage difference of the bit line and latch the second data bit.

[0031] Phase Two (F-bit Read): After Phase One is completed, the word line remains active, the board line voltage is pulled high to the read voltage, and the second sensing amplifier senses the change in bit line voltage and latches the first data bit. The F-bit is read via SA_F using the polarization switching current; this operation destroys the original F-bit data (i.e., destructive read).

[0032] Phase 3 (F-bit write-back): The board line voltage is pulled down to ground, and the bit line is driven by the second sensing amplifier to restore the polarization state of the ferroelectric capacitor based on the latched first data bit.

[0033] Phase 4 (D-bit write-back): Using the first sensing amplifier to drive the bit line, write back the charge to the storage node according to the latched second data bit.

[0034] This invention maps the F-bit to the polarization direction of a ferroelectric capacitor and the D-bit to the voltage of the storage node, and implements data access through a two-stage readout mechanism. Furthermore, addressing the inter-bit interference problem caused by polarization and electric field conflicts in hybrid storage, this invention proposes three optimization methods and their combinations: enhancing the D-bit voltage, adjusting the F-bit write voltage, and introducing a board line bias voltage. These methods significantly improve read margin and achieve high-density, high-reliability hybrid storage.

[0035] Example 4 The functions and effects of this invention are further illustrated and demonstrated through the following simulation experiments.

[0036] (1) Simulation conditions The experiments used physics-based, circuit-compatible SPECTRE and SPICE models for simulation. The basic transistors were designed using TSMC's 65nm process design kit (PDK). The FeCAP model employed a physics-based calibrated Monte Carlo model to accurately reflect the polarization reversal, saturation characteristics, and NLS time effects of ferroelectric materials. The key FeCAP technical parameters set for the simulation are shown in the table below.

[0037]

[0038] (2) Simulation results and analysis 1) Baseline performance and interference verification 1.1) The table below shows a performance comparison between the hybrid MLC mode and the traditional SLC mode. Simulation results show that, compared with the time-division multiplexing SLC mode, the MLC mode not only doubles the density but also achieves higher energy efficiency.

[0039]

[0040] However, as Figure 4 As shown in the simulation waveform in (b), in the unoptimized case, with the data holding time ( With the increase of ), the D-bit read voltage under state "01" A significant decrease. When the retention time reaches... When the sensing margin drops below 40mV, which is below the threshold for reliable sensing (typically 50mV), it confirms the severity of inter-bit interference caused by the NLS effect.

[0041] 2) Validation of the effects of the three optimization strategies To address the aforementioned interference, this invention proposes three optimization strategies, the results of which are verified through simulation: Strategy 1: Strengthen D-bit By increasing the write voltage of the D-bit (For example, increasing the voltage from 1.0V to 1.2V) increases the initial stored charge. Simulation results ( Figure 5 As shown in (a)-(c)), with The increase significantly improves the sensing margin of the D-bit. Although this slightly increases interference to the F-bit, the trade-off is worthwhile because the F-bit already has a large margin (>200mV).

[0042] Strategy 2: Weaken F-bit By reducing the board line voltage during F-bit writing (For example, reducing the voltage from 2.0V to 1.6V) causes the ferroelectric polarization to be in a local loop (minor loop). Simulation results ( Figure 5 The results (d)-(f) show that the polarization in the unsaturated state is more difficult to be reversed by the subsequent small electric field, thereby reducing the charge loss of D-bit caused by domain reversal and improving the retention characteristics of D-bit.

[0043] Strategy 3: Balance Disturbance When writing the D-bit, a positive bias voltage is applied to the board line. (e.g., 0.3V). This causes the net voltage drop across the FeCAP to be from... Reduced to Simulation results ( Figure 5 As shown in (g)-(i), this strategy utilizes the exponential relationship between the flip probability and the electric field in NLS theory to significantly suppress interference while improving the sensing margin of F-bit and D-bit.

[0044] 3) Overall performance after collaborative optimization Figure 6 A 3D simulated heatmap is shown after comprehensively applying the above three strategies. Under optimized parameter configurations (e.g.), The D-bit sensing margin was increased from the original 40mV to over 60mV, an improvement of more than 50%, meeting the requirements for reliable reading. The F-bit sensing margin remained at a high level of 0.28V, without being significantly negatively affected.

[0045] The simulation results above fully demonstrate that the FeFET-based hybrid MLC memory and its anti-interference optimization method proposed in this invention can effectively overcome the inter-bit interference bottleneck, significantly improve the sensing margin of volatile data without sacrificing the reliability of non-volatile data, and realize high-density, high-reliability on-chip hybrid memory.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An in-situ hybrid multi-value memory cell, characterized in that, The memory cell includes a selection transistor and a ferroelectric capacitor; the first plate of the ferroelectric capacitor is connected to the source or drain of the selection transistor to form a memory node, and the second plate of the ferroelectric capacitor is connected to a plate line. The gate of the selection transistor is connected to the word line, and the drain or source of the selection transistor is connected to the bit line; wherein, the memory cell is configured to have four logical storage states, the four logical storage states being defined by a combination of a first data bit and a second data bit; the first data bit is non-volatilely stored based on the ferroelectric polarization direction of the ferroelectric capacitor; the second data bit is volatilely stored based on the amount of charge maintained by the potential difference of the storage node relative to the plate line; the memory cell simultaneously maintains the storage states of the first data bit and the second data bit within the same time period.

2. The in-situ hybrid multi-value memory unit according to claim 1, characterized in that, The four logical storage states include: State "00": This corresponds to the ferroelectric capacitor being in a positive residual polarization state and the storage node being at a low voltage level; State "01": This corresponds to the ferroelectric capacitor being in a positive residual polarization state and the storage node being at a high voltage level; State "10": This corresponds to the ferroelectric capacitor being in a negative residual polarization state and the storage node being at a low voltage level. State "11": This corresponds to the ferroelectric capacitor being in a negative residual polarization state and the storage node being at a high voltage level; In this configuration, the first data bit is the most significant bit, and the second data bit is the least significant bit.

3. A memory array architecture composed of in-situ hybrid multi-value memory cells as described in claim 1 or 2, characterized in that, include: Multiple lines of text lines and multiple lines of board lines, wherein the text lines and the board lines are arranged in parallel; Multiple bit lines, wherein the bit lines are perpendicular to the word lines and the board lines; A sensing amplifier module is connected to the bit line; wherein the sensing amplifier module includes a first sensing amplifier and a second sensing amplifier arranged in pairs; the first sensing amplifier is configured to sense the second data bit; The second sensing amplifier is configured to sense the first data bit.

4. A read / write method for a storage array architecture composed of in-situ hybrid multi-value memory cells as described in claim 3, characterized in that, It includes a two-step write process and a four-stage read timing sequence. The two-step write process includes: First writing step: By controlling the voltage difference between the bit line and the plate line, the ferroelectric capacitor is set to positive polarization or negative polarization in order to write the first data bit; The second writing step is as follows: while maintaining the polarization state of the first data bit, the selection transistor is activated, and charge is applied to or released from the storage node through the bit line to write the second data bit.

5. The read / write method according to claim 4, characterized in that, The second write step further includes an inter-bit interference suppression operation, which is used to mitigate the effect of the reverse electric field generated when the second data bit is high and the first data bit is positively polarized on the ferroelectric domains; the interference suppression operation includes at least one or more combinations of the following strategies: Strategy 1: In the second write step, the high-level voltage used to write the second data bit is set to a value higher than the standard logic level to compensate for the charge loss caused by the nucleation-limited conversion mechanism; Strategy 2: In the first writing step, the writing voltage applied to the board line is set to the voltage value that makes the ferroelectric material work in the local hysteresis loop, so as to reduce the depolarization field. Strategy 3: In the second write step, when writing a high-level voltage to the storage node, a positive bias voltage is simultaneously applied to the board line. The bias voltage is less than the high-level voltage to reduce the net voltage drop across the ferroelectric capacitor.

6. The read / write method according to claim 5, characterized in that, By jointly adjusting the high-level voltage, the write voltage, and the bias voltage, the read voltage margin of the second data bit after a preset hold time is made greater than 50mV.

7. The read / write method according to claim 4, characterized in that, The four-stage read timing sequence includes: Phase 1: Ground the board line, activate the word line, so that the charge on the storage node and the parasitic capacitance of the bit line can share the charge, and use the first sensing amplifier to amplify the bit line voltage difference and latch the second data bit; Phase 2: After Phase 1 is completed, keep the word line active, pull the board line voltage up to the read voltage, use the second sensing amplifier to sense the bit line voltage change and latch the first data bit; Phase 3: Pull the plate line voltage down to ground, use the second sensing amplifier to drive the bit line, and restore the polarization state of the ferroelectric capacitor according to the latched first data bit; Phase 4: Using the first sensing amplifier to drive the bit line, write back the charge to the storage node according to the latched second data bit.

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