Semiconductor system and memory device for adjusting refresh operation period

Abstract

A semiconductor system and a memory device are provided. The semiconductor system includes a control device that generates input commands and input data from external commands and external data, generates commands and data from the input commands and the input data, and generates first refresh control signals and second refresh control signals, and a memory device that includes first and second channels, receives the commands and the data, and performs internal operations based on the commands and the data. The first channel performs a refresh operation at a first period based on the first refresh control signals. The second channel performs a refresh operation at a second period based on the second refresh control signals. The first channel is disposed in a heat path formed when the input commands and the input data are generated.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 730,239, filed December 10, 2024, and U.S. Application No. 19 / 318,707, filed September 4, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor system for adjusting the refresh operation cycle of each region based on temperature. Background Technology

[0004] With advancements in technologies for manufacturing semiconductor devices, packaging technologies for implementing multiple core chips in semiconductor devices have achieved high integration and performance. Among packaging technologies for implementing semiconductor devices, various advancements have been made in technologies related to three-dimensional structures where multiple core chips are vertically stacked, compared to two-dimensional structures where multiple core chips are laid flat on a printed circuit board (PCB). Semiconductor devices with three-dimensional structures can be implemented by stacking multiple core chips (such as high-bandwidth memory (HBM)) via through-silicon vias (hereinafter referred to as "TSVs"), or by stacking multiple core chips via wire bonding. Summary of the Invention

[0005] In an embodiment, the semiconductor system may include: a control device that generates input commands and input data from external commands and external data, generates commands and data from the input commands and input data, and generates a first refresh control signal and a second refresh control signal; and a storage device including a first channel and a second channel, and receiving commands and data, and performing internal operations based on the commands and data. The first channel performs a refresh operation in a first cycle based on the first refresh control signal. The second channel performs a refresh operation in a second cycle based on the second refresh control signal. The first channel is disposed in a hot path formed when the input commands and input data are generated.

[0006] In an embodiment, the semiconductor system may include: a control device that generates input commands and input data from external commands and external data, generates commands and data from the input commands and input data, and generates first refresh control signals to third refresh control signals; and a memory device that includes first channels to third channels, and receives commands and data, and performs internal operations based on the commands and data. The first channel may perform a refresh operation in a first cycle based on the first refresh control signal. The second channel may perform a refresh operation in a second cycle based on a second refresh control signal. The third channel may perform a refresh operation in a third cycle based on a third refresh control signal. The first channel may be disposed in a hot path formed when the input commands and input data are generated. The second channel may be disposed adjacent to the hot path. The third channel may be disposed spaced apart from the hot path, wherein the second channel is located between the third channel and the hot path.

[0007] In one embodiment, a storage device may include: a first channel that performs internal operations by receiving commands and data generated from input commands and input data, and performs a refresh operation at a first cycle based on a first refresh control signal; and a second channel that performs internal operations based on commands and data, and performs a refresh operation at a second cycle based on a second refresh control signal. The first channel may be disposed in a thermal path. The second channel may be disposed spaced apart from the thermal path. The thermal path may be the path along which heat generated when the input commands and input data are generated is transferred.

[0008] In an embodiment, a storage device may include: a first channel including a first memory cell and a second memory cell; and a second channel including a third memory cell and a fourth memory cell. The first and second memory cells may perform refresh operations at different periods based on a first refresh control signal and a second refresh control signal. The third and fourth memory cells may perform refresh operations at the same period based on a third refresh control signal. The first channel may be disposed in a thermal path along which heat is transferred. The second channel may be disposed spaced apart from the thermal path. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating the construction of a semiconductor system according to an embodiment of the present disclosure.

[0010] Figure 2 This is a block diagram illustrating the construction of a control device and a first storage device according to an embodiment of the present disclosure.

[0011] Figure 3 This is a block diagram illustrating the construction and connection of a control device, a first storage device, and a second storage device according to an embodiment of the present disclosure.

[0012] Figure 4 This is a view used to describe the refresh operation of a first storage device according to an embodiment of the present disclosure.

[0013] Figure 5 This is a view used to describe the refresh operation of a first storage device according to another embodiment of the present disclosure.

[0014] Figure 6 This is a view used to describe the refresh operation of a first storage device according to another embodiment of the present disclosure.

[0015] Figure 7 This is a table used to describe the heat generated from the thermal path of a semiconductor system according to embodiments of this disclosure.

[0016] Figure 8 This is a block diagram illustrating the construction of a semiconductor system according to another embodiment of the present disclosure. Detailed Implementation

[0017] In the description of the following embodiments, terms such as "first" and "second" are used to distinguish individual components, but are not limited to any particular component. For example, a first component may be referred to as a second component, and vice versa.

[0018] When a component is referred to as "coupled" or "connected" to another component, it should be understood that these components may be directly coupled or connected to each other, or coupled or connected to each other through another component in between. Conversely, when a component is referred to as "directly coupled" or "directly connected" to another component, it should be understood that these components are directly coupled or connected to each other without any other component in between.

[0019] The present disclosure will be described in more detail below through examples. These examples are for illustrative purposes only, and the scope of the disclosure is not limited to the examples.

[0020] Figure 1 This is a block diagram illustrating the construction of a semiconductor system 1 according to an embodiment of the present disclosure. Figure 1 As shown, the semiconductor system 1 may include a control device 110, a first storage device 210, a second storage device 220, a third storage device 230, and a fourth storage device 240.

[0021] Control device 110 can generate commands ( Figure 2 CMD and data (in the middle) Figure 2(DATA in the text). Control device 110 can output commands and data to first storage device 210, second storage device 220, third storage device 230, and fourth storage device 240. Control device 110 can receive data from first storage device 210, second storage device 220, third storage device 230, and fourth storage device 240. Control device 110 can generate multiple refresh control signals (DATA in the text). Figure 2 (RC in the image). The control device 110 can output multiple refresh control signals to the first memory device 210, the second memory device 220, the third memory device 230, and the fourth memory device 240. The control device 110 can be implemented using a basic chip that controls the operation of the first memory device 210, the second memory device 220, the third memory device 230, and the fourth memory device 240.

[0022] The control device 110 may include a physical region (D2D PHY) 111, a memory controller (MC) 112, and a basic TSV region (TSV PHY) 113.

[0023] Physical region 111 can generate input commands based on signals received from external devices (e.g., various devices such as a host, processor, and test equipment). Figure 2 INC in the input data ( Figure 2 (IND in the context). Physical region 111 can output input commands and input data to memory controller 112. Physical region 111 can be implemented using a physical layer PHY, which is responsible for the generation, transmission, reception, and physical connection of signals and data between external devices and control device 110.

[0024] The memory controller 112 can receive input commands and input data from the physical region 111. Based on the input commands and input data, the memory controller 112 can output commands controlling the operation of the first storage device 210, the second storage device 220, the third storage device 230, and the fourth storage device 240, and can also output data. The memory controller 112 can generate multiple refresh control signals controlling the refresh operations of the first storage device 210, the second storage device 220, the third storage device 230, and the fourth storage device 240. The refresh operation can be set to restore the data DATA within a retention time (i.e., the time during which the data DATA stored in the first storage device 210, the second storage device 220, the third storage device 230, and the fourth storage device 240 is stably maintained by sensing and amplifying the data DATA).

[0025] The basic TSV region 113 may include multiple TSVs. The basic TSV region 113 can receive commands and data from the memory controller 112. The basic TSV region 113 can output commands and data to the first memory device 210, the second memory device 220, the third memory device 230, and the fourth memory device 240 through multiple TSVs. The basic TSV region 113 can receive multiple refresh control signals from the memory controller 112. The basic TSV region 113 can output multiple refresh control signals to the first memory device 210, the second memory device 220, the third memory device 230, and the fourth memory device 240 through multiple TSVs.

[0026] When physical region 111 generates input commands and input data, a thermal path can be formed. A thermal path can be configured such that the heat generated during the generation of input commands and input data is transferred along it.

[0027] The first storage device 210 may include multiple channels ( Figure 2 (CH1 to CH8 in the first storage device 210). Multiple channels included in the first storage device 210 can perform internal operations by receiving commands and data. Multiple channels included in the first storage device 210 can store data after a write operation is initiated based on a command. Multiple channels included in the first storage device 210 can output the stored data after a read operation is initiated based on a command. Multiple channels included in the first storage device 210 can perform refresh operations by receiving multiple refresh control signals. The period of the refresh operation performed by the multiple channels included in the first storage device 210 can be adjusted based on the multiple refresh control signals. Among the multiple channels included in the first storage device 210, the refresh operation performed by the channel included in the hot path can have the shortest period.

[0028] The second storage device 220 may include multiple channels ( Figure 3 (CH1 to CH8 in the second storage device 220). Multiple channels included in the second storage device 220 can perform internal operations by receiving commands and data. Multiple channels included in the second storage device 220 can store data after a write operation is initiated based on a command. Multiple channels included in the second storage device 220 can output the stored data after a read operation is initiated based on a command. Multiple channels included in the second storage device 220 can receive multiple refresh control signals (CH1 to CH8 in the second storage device 220). Figure 3 The refresh operation is performed by the RC signal in the second storage device 220. The cycle of the refresh operation performed by the multiple channels included in the second storage device 220 can be adjusted based on multiple refresh control signals. Among the multiple channels included in the second storage device 220, the refresh operation performed by the channel included in the hot path can have the shortest cycle.

[0029] The third storage device 230 may include multiple channels. These channels can perform internal operations by receiving commands and data. They can store data after a write operation begins based on a command. They can output the stored data after a read operation begins based on a command. The channels can perform refresh operations by receiving multiple refresh control signals. The cycle of the refresh operations performed by the channels in the third storage device 230 can be adjusted based on the multiple refresh control signals. Among the multiple channels in the third storage device 230, the refresh operation cycle performed by the channel included in the hot path can be the shortest.

[0030] The fourth storage device 240 may include multiple channels. The multiple channels included in the fourth storage device 240 can perform internal operations by receiving commands and data. The multiple channels included in the fourth storage device 240 can store data after a write operation is initiated based on a command. The multiple channels included in the fourth storage device 240 can output the stored data after a read operation is initiated based on a command. The multiple channels included in the fourth storage device 240 can perform refresh operations by receiving multiple refresh control signals. The cycle of the refresh operation performed by the multiple channels included in the fourth storage device 240 can be adjusted based on the multiple refresh control signals. Among the multiple channels included in the fourth storage device 240, the cycle of the refresh operation performed by the channel included in the hot path can be the shortest.

[0031] The control device 110, the first storage device 210, the second storage device 220, the third storage device 230, and the fourth storage device 240 can be implemented horizontally in the XY plane. The first storage device 210 can be stacked vertically on the control device 110 along the Z direction. The second storage device 220 can be stacked vertically on the first storage device 210 along the Z direction. The third storage device 230 can be stacked vertically on the second storage device 220 along the Z direction. The fourth storage device 240 can be stacked vertically on the third storage device 230 along the Z direction.

[0032] A thermal path can be formed perpendicularly along the Z direction from a physical region 111 included in the control device 110. Heat generated from the thermal path can diffuse to the first storage device 210, the second storage device 220, the third storage device 230, and the fourth storage device 240.

[0033] The first storage device 210, the second storage device 220, the third storage device 230, and the fourth storage device 240 can each be implemented using a core chip or semiconductor device for storing data and outputting the stored data.

[0034] Figure 1 The semiconductor system 1 shown has four first to fourth memory devices 210, 220, 230 and 240 stacked on the control device 110; however, various numbers (such as 8, 12 and 16) of memory devices can be stacked on the control device 110.

[0035] As described above, the semiconductor system 1 according to embodiments of this disclosure can ensure data reliability by performing refresh operations on regions included in the memory device and in the thermal path formed from the control device 110 at short cycles. The reliability of data stored in the channels can be ensured by adjusting the refresh operation cycle differently based on the difference between the thermal path formed from the control device 110 and the location of the channels included in the memory device.

[0036] Figure 2 This is a block diagram illustrating the construction of a control device 110 and a first storage device 210 of a semiconductor system 1 according to an embodiment of the present disclosure. Figure 2 As shown, the control device 110 may include a physical region 111, a memory controller 112, and a basic TSV region 113.

[0037] Physical region 111 can be accessed from an external device (e.g., Figure 8 The physical region 111 receives external command EC from the processor in the device to generate input command INC. The physical region 111 can generate input command INC by buffering or decoding external command EC. External command EC and input command INC are each represented as a signal, but may each include multiple bits. The physical region 111 can generate input command INC from external devices (e.g., ...). Figure 8 The physical region 111 receives external data ED to generate input data IND. The physical region 111 can generate external data ED by receiving input data IND from the memory controller 112. The physical region 111 can output the external data ED to an external device. The external data ED and the input data IND are each represented as a signal, but may include multiple bits. The physical region 111 can be located in a hot path.

[0038] The memory controller 112 can receive input commands INC and input data IND from physical region 111. Based on the input commands INC and IND, the memory controller 112 can output commands CMD and data DATA to control the operation of the first memory device 210, the second memory device 220, the third memory device 230, and the fourth memory device 240. The memory controller 112 can generate multiple refresh control signals RC to control the refresh operation of the first memory device 210, the second memory device 220, the third memory device 230, and the fourth memory device 240. Each of the multiple refresh control signals RC can be set as a signal—the generation period of which is adjusted to adjust the refresh operation period. The memory controller 112 can generate input data IND by receiving data DATA from the base TSV region 113. The memory controller 112 can output the input data IND to physical region 111.

[0039] The basic TSV region 113 may include multiple TSVs. The basic TSV region 113 can receive commands (CMD) and data (DATA) from the memory controller 112. The basic TSV region 113 can output commands (CMD) and data (DATA) to the first memory device 210, the second memory device 220, the third memory device 230, and the fourth memory device 240 via multiple TSVs. The basic TSV region 113 can receive multiple refresh control signals (RC) from the memory controller 112. The basic TSV region 113 can output multiple refresh control signals (RC) to the first memory device 210, the second memory device 220, the third memory device 230, and the fourth memory device 240 via multiple TSVs. The basic TSV region 113 can receive data (DATA) from the first memory device 210, the second memory device 220, the third memory device 230, and the fourth memory device 240 via multiple TSVs and can output data (DATA) to the memory controller 112.

[0040] The base TSV region 113 may include a TSV T11 connecting microbumps B11 and B12. Microbump B11 may be configured such that it connects to an external device (e.g., Figure 8 The leads of the intermediate layer in the middle. Microbump B12 can be configured such that it is connected to microbump B13 connected to the first storage device 210. The base TSV region 113 has been shown as including three TSVs; however, the base TSV region 113 may include multiple TSVs connected to multiple microbumps.

[0041] The physical area 111, memory controller 112, and basic TSV area 113 of the control device 110 can be set along the X direction.

[0042] The first storage device 210 may include a memory control circuit (MEM CTR) 211 and a first channel CH1 to an eighth channel CH8.

[0043] The memory control circuit 211 may include multiple TSVs. The memory control circuit 211 can receive commands (CMD) and data (DATA) from the base TSV region 113. The memory control circuit 211 can output the commands (CMD) and data (DATA) received through the multiple TSVs to channels CH1 through CH8. The memory control circuit 211 can receive multiple refresh control signals (RC) from the base TSV region 113. The memory control circuit 211 can output the multiple refresh control signals (RC) received through the multiple TSVs to channels CH1 through CH8. The memory control circuit 211 can receive data (DATA) from channels CH1 through CH8 and can output the data (DATA) to the base TSV region 113.

[0044] The memory control circuit 211 may include a TSV T12 connected to the microbump B13. The microbump B13 may be configured such that it is connected to the microbump B12. The memory control circuit 211 has been shown as including three TSVs; however, the memory control circuit 211 may include multiple TSVs connected to multiple microbumps.

[0045] Channels CH1 through CH8 can each independently receive commands (CMD) and data (DATA) by performing internal operations. After a write operation based on command CMD, channels CH1 through CH8 can each store data (DATA). After a read operation based on command CMD, channels CH1 through CH8 can each output data (DATA). The refresh cycle performed by each of the channels CH1 through CH8 can be adjusted based on each of the multiple refresh control signals RC. For example, when the refresh control signal RC input to channel CH1 is twice as fast as the refresh control signal RC input to channel CH2, channel CH1 can perform a refresh operation at twice the cycle speed of channel CH2. Each of channels CH1 through CH8 can include multiple memory banks (…). Figure 6 (BK1 and BK2 in the middle).

[0046] The memory control circuit 211 of the first storage device 210 and the first channel CH1 to the eighth channel CH8 can be arranged along the X direction. Figure 2 The first storage device 210 shown can be electrically connected to a plurality of microbumps, such as microbumps B12 and B13, and can be stacked on the control device 110 along the Z direction.

[0047] Figure 1 The second storage device 220, the third storage device 230, and the fourth storage device 240 shown are stacked vertically on the first storage device 210 along the Z direction, and are implemented with the same components as the first storage device 210, and perform the same operations as the first storage device 210, therefore their detailed description is omitted.

[0048] Figure 3 This is a block diagram illustrating the construction and connection of the control device 110, the first storage device 210, and the second storage device 220 according to an embodiment of the present disclosure.

[0049] The physical area 111 of the control device 110 can be accessed from an external device (e.g., Figure 8 The processor in the control device 110 receives external commands EC to generate input commands INC. The physical area 111 of the control device 110 can generate input commands INC by buffering or decoding external commands EC. The physical area 111 of the control device 110 can generate input data IND by receiving external data ED from an external device. When the physical area 111 of the control device 110 generates input commands INC and input data IND by receiving external commands EC and external data ED, heat may be generated. In this case, the generated heat can diffuse vertically along the Z-direction, thus forming a thermal path.

[0050] Based on the input command INC and input data IND, the memory controller 112 of the control device 110 can output the command CMD to control the operation of the first memory device 210 and the second memory device 220, and can also output data DATA. The memory controller 112 of the control device 110 can output multiple refresh control signals RC to control the refresh operation of the first memory device 210 and the refresh operation of the second memory device 220.

[0051] The basic TSV area 113 of the control device 110 can receive commands (CMD) and data (DATA) from the memory controller 112. The basic TSV area 113 of the control device 110 can output commands (CMD) and data (DATA) to the first memory device 210 and the second memory device 220 via multiple TSVs. The basic TSV area 113 of the control device 110 can receive multiple refresh control signals (RC) from the memory controller 112. The basic TSV area 113 of the control device 110 can output multiple refresh control signals (RC) to the first memory device 210 and the second memory device 220 via multiple TSVs.

[0052] The memory control circuit 211 of the first storage device 210 can receive commands CMD and data DATA from the base TSV region 113. The memory control circuit 211 of the first storage device 210 can output the received commands CMD and data DATA to the first channel CH1 through the eighth channel CH8. The memory control circuit 211 of the first storage device 210 can receive multiple refresh control signals RC from the base TSV region 113. The memory control circuit 211 of the first storage device 210 can output multiple refresh control signals RC to the first channel CH1 through the eighth channel CH8. In this case, the first channel CH1 and the fifth channel CH5, included in the hot path, can perform refresh operations in the first cycle by receiving refresh control signals RC generated in the first cycle (i.e., the fastest cycle). The second channel CH2 and the sixth channel CH6, configured to be adjacent to the hot path, can perform refresh operations in the second cycle by receiving refresh control signals RC generated in the second cycle. The third channel CH3, the fourth channel CH4, the seventh channel CH7, and the eighth channel CH8 (these channels block heat generated from the thermal path through the second channel CH2 and the sixth channel CH6) can perform a refresh operation in a third cycle by receiving a refresh control signal RC generated in the third cycle. The first cycle can be shorter than the second cycle. The second cycle can be shorter than the third cycle. The first cycle can be half the second cycle. The second cycle can be half the third cycle. Therefore, the first cycle can be one-quarter of the third cycle. The first, second, and third cycles can be set differently according to the embodiments. The first storage device 210 is vertically stacked along the Z direction of the control device 110 by a plurality of microbumps.

[0053] The memory control circuit (MEM CTR) 221 of the second storage device 220 can receive commands (CMD) and data (DATA) from the base TSV region 113. The memory control circuit 221 of the second storage device 220 can output the received commands (CMD) and data (DATA) to the first channel CH1 through the eighth channel CH8. The memory control circuit 221 of the second storage device 220 can receive multiple refresh control signals (RC) from the base TSV region 113. The memory control circuit 221 of the second storage device 220 can output multiple refresh control signals (RC) to the first channel CH1 through the eighth channel CH8. In this case, the first channel CH1 and the fifth channel CH5, included in the hot path, can perform refresh operations in the first cycle by receiving refresh control signals (RC) generated in the first cycle (i.e., the fastest cycle). The second channel CH2 and the sixth channel CH6, configured to be adjacent to the hot path, can perform refresh operations in the second cycle by receiving refresh control signals (RC) generated in the second cycle. The third channel CH3, the fourth channel CH4, the seventh channel CH7, and the eighth channel CH8 (these channels block heat generated from the thermal path through the second channel CH2 and the sixth channel CH6) can perform refresh operations in the third cycle by receiving a refresh control signal RC generated in the third cycle. The second storage device 220 can be vertically stacked along the Z direction of the first storage device 210 by multiple microbumps.

[0054] As described above, the semiconductor system 1 can ensure the reliability of data stored in the channel by performing a refresh operation on the channel included in the storage device and in the thermal path formed from the control device 110 with a short cycle. The semiconductor system 1 can also ensure the reliability of data stored in the channel by adjusting the refresh operation cycle differently based on the difference between the thermal path formed from the control device 110 and the channel location included in the storage device.

[0055] Figure 4 This is a view used to describe the refresh operation of a first storage device 210 according to an embodiment of this disclosure. Reference Figure 4 The refresh operation of the first storage device 210 is described. In this case, the heat from the thermal path formed from the control device 110 is equally diffused to the first channel CH1 and the fifth channel CH5 as an example is described below.

[0056] The memory control circuit 211 of the first memory device 210 can receive a first refresh control signal RC1, a second refresh control signal RC2, and a third refresh control signal RC3 from the basic TSV region 113. The first refresh control signal RC1 can be generated in a first cycle and received by the corresponding channel. The second refresh control signal RC2 can be generated in a second cycle and received by the corresponding channel. The third refresh control signal RC3 can be generated in a third cycle and received by the corresponding channel. The first cycle can be shorter than the second cycle. The second cycle can be shorter than the third cycle. The first cycle can be half the length of the second cycle. The second cycle can be half the length of the third cycle. The first, second, and third cycles can be adjusted differently based on the heat generated from the thermal path.

[0057] The first channel CH1 and the fifth channel CH5 can be located within the first region AR1 included in the hot path. The memory control circuit 211 of the first memory device 210 can output a first refresh control signal RC1 generated in a first cycle to the first channel CH1 and the fifth channel CH5. The first channel CH1 and the fifth channel CH5 can perform refresh operations in a first cycle based on the first refresh control signal RC1.

[0058] The second channel CH2 and the sixth channel CH6 can be located in the second region AR2 adjacent to the hot path. The memory control circuit 211 of the first memory device 210 can output a second refresh control signal RC2 generated in a second cycle to the second channel CH2 and the sixth channel CH6. The second channel CH2 and the sixth channel CH6 can perform refresh operations in a second cycle based on the second refresh control signal RC2.

[0059] The third channel CH3, the fourth channel CH4, the seventh channel CH7, and the eighth channel CH8 can be located in the third region AR3, which is spaced apart from the first region AR1, wherein the second region AR2 is located between the third region AR3 and the first region AR1. The memory control circuit 211 of the first memory device 210 can output a third refresh control signal RC3 generated in a third cycle to the third channel CH3, the fourth channel CH4, the seventh channel CH7, and the eighth channel CH8. The third channel CH3, the fourth channel CH4, the seventh channel CH7, and the eighth channel CH8 can perform refresh operations in a third cycle based on the third refresh control signal RC3.

[0060] Because the data DATA is held stably for the shortest time based on the heat generated from the thermal path, the first channel CH1 and the fifth channel CH5, which are set within the first region AR1 included in the thermal path, can perform refresh operations in the first cycle (i.e., the fastest cycle).

[0061] Because the data DATA is held stably for a longer period of time compared to the first region AR1, based on the heat generated from the thermal path, the second channel CH2 and the sixth channel CH6 of the second region AR2, which is adjacent to the thermal path, can perform refresh operations in a second cycle that is slower than the first cycle.

[0062] Because the data DATA is held stably for a longer period of time compared to the second region AR2, based on the heat generated from the thermal path, the third channel CH3, the fourth channel CH4, the seventh channel CH7, and the eighth channel CH8 of the third region AR3 (which is separated from the first region AR1, with the second region AR2 located between the third region AR3 and the first region AR1) can perform refresh operations in the third cycle, which is slower than the second cycle.

[0063] The second storage device 220, the third storage device 230, and the fourth storage device 240 can each perform the same refresh operation as the first storage device 210, so their detailed description is omitted.

[0064] As described above, the semiconductor system 1 can ensure the reliability of the data stored in the channel by performing a refresh operation on the channel included in the storage device and in the thermal path formed from the control device 110 with a short cycle. The semiconductor system 1 can also ensure the reliability of the data stored in the channel by adjusting the refresh operation cycle differently based on the difference between the thermal path formed from the control device 110 and the channel location included in the storage device.

[0065] like Figure 4 As shown, the memory control circuit 211 of the first memory device 210 and the first channel CH1 to the eighth channel CH8 can be horizontally arranged on the XY plane.

[0066] Figure 5 This is a view used to describe the refresh operation of a first storage device 210 according to another embodiment of this disclosure. Reference Figure 5 The refresh operation of the first storage device 210 is described. In this case, the heat from the thermal path formed by the control device 110 is diffused at a high temperature to the fifth channel CH5 instead of the first channel CH1 as an example, as described below.

[0067] The memory control circuit 211 of the first memory device 210 can receive a first refresh control signal RC1, a second refresh control signal RC2, a third refresh control signal RC3, a fourth refresh control signal RC4, and a fifth refresh control signal RC5 from the basic TSV region 113. The first refresh control signal RC1 can be generated in a first cycle and received by the corresponding channel. The second refresh control signal RC2 can be generated in a second cycle and received by the corresponding channel. The third refresh control signal RC3 can be generated in a third cycle and received by the corresponding channel. The fourth refresh control signal RC4 can be generated in a fourth cycle and received by the corresponding channel. The fifth refresh control signal RC5 can be generated in a fifth cycle and received by the corresponding channel.

[0068] The first cycle can be shorter than the second cycle. The second cycle can be shorter than the third cycle. The third cycle can be shorter than the fourth cycle. The fourth cycle can be shorter than the fifth cycle. The first cycle can be half the length of the second cycle. The second cycle can be half the length of the third cycle. The third cycle can be half the length of the fourth cycle. The fourth cycle can be half the length of the fifth cycle. The first, second, third, fourth, and fifth cycles can be adjusted according to the heat generated from the thermal path.

[0069] The fifth channel CH5 can be located within the first region AR1 included in the hot path. The first channel CH1 can be located within the second region AR2 included in the hot path. The memory control circuit 211 of the first memory device 210 can output a first refresh control signal RC1 generated in a first cycle to the fifth channel CH5, and can output a second refresh control signal RC2 generated in a second cycle to the first channel CH1. The fifth channel CH5 can perform a refresh operation in the first cycle based on the first refresh control signal RC1. The first channel CH1 can perform a refresh operation in the second cycle based on the second refresh control signal RC2.

[0070] The sixth channel CH6 can be located in the third region AR3 adjacent to the hot path. The second channel CH2 can be located in the fourth region AR4 adjacent to the hot path. The memory control circuit 211 of the first memory device 210 can output a third refresh control signal RC3 generated in a third cycle to the sixth channel CH6, and can output a fourth refresh control signal RC4 generated in a fourth cycle to the second channel CH2. The sixth channel CH6 can perform a refresh operation in a third cycle based on the third refresh control signal RC3. The second channel CH2 can perform a refresh operation in a fourth cycle based on the fourth refresh control signal RC4.

[0071] The third channel CH3, the fourth channel CH4, the seventh channel CH7, and the eighth channel CH8 can be located in a fifth region AR5, which is spaced apart from the first region AR1 and the second region AR2, wherein the third region AR3 and the fourth region AR4 are located between the fifth region AR5 and the first region AR1 and the second region AR2. The memory control circuit 211 of the first memory device 210 can output a fifth refresh control signal RC5 generated in a fifth cycle to the third channel CH3, the fourth channel CH4, the seventh channel CH7, and the eighth channel CH8. The third channel CH3, the fourth channel CH4, the seventh channel CH7, and the eighth channel CH8 can perform refresh operations in a fifth cycle based on the fifth refresh control signal RC5.

[0072] Because the data DATA is held stably for the shortest time due to the heat generated from the thermal path, the fifth channel CH5 of the first region AR1 included in the thermal path can perform a refresh operation in the first cycle (i.e., the fastest cycle). Because the data DATA is held stably for a longer time due to the heat generated from the thermal path compared to the fifth channel CH5, the first channel CH1 of the second region AR2 included in the thermal path can perform a refresh operation in the second cycle, which is slower than the first cycle.

[0073] Because the retention time of data DATA is stably maintained increased due to the heat generated from the hot path compared to the second region AR2, the sixth channel CH6 of the third region AR3, which is adjacent to the hot path, can perform a refresh operation in the third cycle, which is slower than the second cycle. Similarly, because the retention time of data DATA is stably maintained increased due to the heat generated from the hot path compared to the third region AR3, the second channel CH2 of the fourth region AR4, which is adjacent to the hot path, can perform a refresh operation in the fourth cycle, which is slower than the third cycle.

[0074] Because the retention time of data DATA is stably maintained is increased according to the heat generated from the thermal path compared to the fourth region AR4, the third channel CH3, the fourth channel CH4, the seventh channel CH7, and the eighth channel CH8 of the fifth region AR5 (which is separated from the first region AR1 and the second region AR2, with the third region AR3 and the fourth region AR4 located between the fifth region AR5 and the first region AR1 and the second region AR2) can perform refresh operations in the fifth cycle, which is slower than the fourth cycle.

[0075] The second storage device 220, the third storage device 230, and the fourth storage device 240 can each perform the same refresh operation as the first storage device 210, so their detailed description is omitted.

[0076] like Figure 5As shown, the memory control circuit 211 of the first memory device 210 and the first channel CH1 to the eighth channel CH8 can be horizontally arranged on the plane formed by the X-axis and the Y-axis.

[0077] As described above, the semiconductor system 1 can ensure the reliability of the data stored in the channel by performing a refresh operation on the channel included in the storage device and in the thermal path formed from the control device 110 with a short cycle. The semiconductor system 1 can also ensure the reliability of the data stored in the channel by adjusting the refresh operation cycle differently based on the difference between the thermal path formed from the control device 110 and the channel location included in the storage device.

[0078] Figure 6 This is a view used to describe the refresh operation of a first storage device 210 according to another embodiment of this disclosure. Reference Figure 6 The refresh operation of the first storage device 210 is described. In this case, the following description will use the example of the heat from the thermal path formed by the control device 110 being diffused at high temperature to the fifth channel CH5 instead of the first channel CH1, and the heat being diffused at high temperature to the second storage cell BK2 of the first channel CH1 and the fifth channel CH5 instead of the first storage cell BK1 of the first channel CH1 and the fifth channel CH5.

[0079] The memory control circuit 211 of the first memory device 210 can receive a first refresh control signal RC1, a second refresh control signal RC2, a third refresh control signal RC3, a fourth refresh control signal RC4, a fifth refresh control signal RC5, a sixth refresh control signal RC6, a seventh refresh control signal RC7, an eighth refresh control signal RC8, and a ninth refresh control signal RC9 from the basic TSV region 113. The first refresh control signal RC1 can be generated in a first cycle and received by the corresponding channel. The second refresh control signal RC2 can be generated in a second cycle and received by the corresponding channel. The third refresh control signal RC3 can be generated in a third cycle and received by the corresponding channel. The fourth refresh control signal RC4 can be generated in a fourth cycle and received by the corresponding channel. The fifth refresh control signal RC5 can be generated in a fifth cycle and received. The sixth refresh control signal RC6 can be generated in a sixth cycle and received. The seventh refresh control signal RC7 can be generated in a seventh cycle and received by the corresponding channel. The eighth refresh control signal RC8 is generated in an eighth cycle and received by the corresponding channel. The ninth refresh control signal RC9 can be generated in a ninth cycle and received by the corresponding channel.

[0080] The first cycle can be shorter than the second cycle. The second cycle can be shorter than the third cycle. The third cycle can be shorter than the fourth cycle. The fourth cycle can be shorter than the fifth cycle. The fifth cycle can be shorter than the sixth cycle. The sixth cycle can be shorter than the seventh cycle. The seventh cycle can be shorter than the eighth cycle. The eighth cycle can be shorter than the ninth cycle.

[0081] The first cycle can be half of the second cycle. The second cycle can be half of the third cycle. The third cycle can be half of the fourth cycle. The fourth cycle can be half of the fifth cycle. The fifth cycle can be half of the sixth cycle. The sixth cycle can be half of the seventh cycle. The seventh cycle can be half of the eighth cycle. The eighth cycle can be half of the ninth cycle.

[0082] The first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth cycles can be adjusted differently based on the heat generated from the thermal path.

[0083] The fifth channel CH5 can be located in the first region AR1, which is included in the thermal path. The first channel CH1 can be located in the second region AR2, which is included in the thermal path.

[0084] The memory control circuit 211 of the first storage device 210 can output a first refresh control signal RC1 generated in a first cycle to the second memory bank BK2 of the fifth channel CH5, and can output a second refresh control signal RC2 generated in a second cycle to the first memory bank BK1 of the fifth channel CH5. The second memory bank BK2 of the fifth channel CH5 can perform a refresh operation in the first cycle based on the first refresh control signal RC1. The first memory bank BK1 of the fifth channel CH5 can perform a refresh operation in the second cycle based on the second refresh control signal RC2.

[0085] The memory control circuit 211 of the first storage device 210 can output a third refresh control signal RC3, generated in a third cycle, to the second memory bank BK2 of the first channel CH1, and can output a fourth refresh control signal RC4, generated in a fourth cycle, to the first memory bank BK1 of the first channel CH1. The second memory bank BK2 of the first channel CH1 can perform a refresh operation in a third cycle based on the third refresh control signal RC3. The first memory bank BK1 of the first channel CH1 can perform a refresh operation in a fourth cycle based on the fourth refresh control signal RC4.

[0086] The sixth channel CH6 can be located in the third region AR3, which is adjacent to the thermal path. The second channel CH2 can be located in the fourth region AR4, which is adjacent to the thermal path.

[0087] The memory control circuit 211 of the first storage device 210 can output a fifth refresh control signal RC5 generated in the fifth cycle to the second memory bank BK2 of the sixth channel CH6, and can output a sixth refresh control signal RC6 generated in the sixth cycle to the first memory bank BK1 of the sixth channel CH6. The second memory bank BK2 of the sixth channel CH6 can perform a refresh operation in the fifth cycle based on the fifth refresh control signal RC5. The first memory bank BK1 of the sixth channel CH6 can perform a refresh operation in the sixth cycle based on the sixth refresh control signal RC6.

[0088] The memory control circuit 211 of the first storage device 210 can output a seventh refresh control signal RC7, generated in the seventh cycle, to the second memory bank BK2 of the second channel CH2, and can output an eighth refresh control signal RC8, generated in the eighth cycle, to the first memory bank BK1 of the second channel CH2. The second memory bank BK2 of the second channel CH2 can perform a refresh operation in the seventh cycle based on the seventh refresh control signal RC7. The first memory bank BK1 of the second channel CH2 can perform a refresh operation in the eighth cycle based on the eighth refresh control signal RC8.

[0089] The third channel CH3, the fourth channel CH4, the seventh channel CH7, and the eighth channel CH8 can be located in the fifth region AR5, which is separated from the first region AR1 and the second region AR2, wherein the third region AR3 and the fourth region AR4 are located between the fifth region AR5 and the first region AR1 and the second region AR2.

[0090] The memory control circuit 211 of the first storage device 210 can output the ninth refresh control signal RC9, generated in the ninth cycle, to the third channel CH3, the fourth channel CH4, the seventh channel CH7, and the eighth channel CH8. The third channel CH3, the fourth channel CH4, the seventh channel CH7, and the eighth channel CH8 can perform refresh operations in the ninth cycle based on the ninth refresh control signal RC9.

[0091] Because the data DATA is held stably for the shortest time due to the heat generated from the hot path, the second memory bank BK2, included in the fifth channel CH5 of the hot path, can perform a refresh operation in the first cycle (i.e., the fastest cycle). Because the data DATA is held stably for a longer time due to the heat generated from the hot path compared to the second memory bank BK2 of the fifth channel CH5, the first memory bank BK1, included in the fifth channel CH5 of the hot path, can perform a refresh operation in the second cycle, which is slower than the first cycle.

[0092] Because the retention time of data DATA is stably maintained increased due to the heat generated from the hot path compared to the first memory bank BK1 of the fifth channel CH5, the second memory bank BK2 of the first channel CH1 included in the hot path can perform a refresh operation in a third cycle. Because the retention time of data DATA is stably maintained increased due to the heat generated from the hot path compared to the second memory bank BK2 of the first channel CH1, the first memory bank BK1 of the first channel CH1 included in the hot path can perform a refresh operation in a fourth cycle, which is slower than the third cycle.

[0093] Because the retention time for data DATA is stably maintained is increased due to the heat generated from the hot path compared to the first memory bank BK1 of the first channel CH1, the second memory bank BK2 of the sixth channel CH6 of the third region AR3, which is adjacent to the hot path, can perform a refresh operation in the fifth cycle, which is slower than the fourth cycle. Because the retention time for data DATA is stably maintained is increased due to the heat generated from the hot path compared to the second memory bank BK2 of the sixth channel CH6, the first memory bank BK1 of the sixth channel CH6 of the third region AR3 can perform a refresh operation in the sixth cycle, which is slower than the fifth cycle.

[0094] Because the retention time of data DATA is stably maintained increased due to the heat generated from the hot path compared to the first memory bank BK1 of the sixth channel CH6, the second memory bank BK2 of the second channel CH2 in the fourth region AR4 adjacent to the hot path can perform a refresh operation in the seventh cycle, which is slower than the sixth cycle. Because the retention time of data DATA is stably maintained increased due to the heat generated from the hot path compared to the second memory bank BK2 of the second channel CH2, the first memory bank BK1 of the second channel CH2 in the fourth region AR4 adjacent to the hot path can perform a refresh operation in the eighth cycle, which is slower than the seventh cycle.

[0095] Because the retention time of data DATA is stably maintained is increased due to the heat generated from the thermal path compared to the first storage BK1 of the second channel CH2, the third channel CH3, the fourth channel CH4, the seventh channel CH7, and the eighth channel CH8 of the fifth region AR5 (which is separated from the first region AR1 and the second region AR2, with the third region AR3 and the fourth region AR4 located between the fifth region AR5 and the first region AR1 and the second region AR2) can perform refresh operations in the ninth cycle, which is slower than the eighth cycle.

[0096] like Figure 6 As shown, the memory control circuit 211 of the first memory device 210 and the first channel CH1 to the eighth channel CH8 can be horizontally arranged on the XY plane.

[0097] The second storage device 220, the third storage device 230, and the fourth storage device 240 can each perform the same refresh operation as the first storage device 210, so their detailed description is omitted.

[0098] As described above, the semiconductor system 1 can ensure the reliability of the data stored in the channel by performing a refresh operation on the channel included in the storage device and in the thermal path formed from the control device 110 with a short cycle. The semiconductor system 1 can also ensure the reliability of the data stored in the channel by adjusting the refresh operation cycle differently according to the difference between the thermal path formed from the control device 110 and the channel location included in the storage device.

[0099] Figure 7 This is a table used to describe the heat generated from the thermal path of the semiconductor system 1 according to an embodiment of this disclosure.

[0100] Case 1 is as follows: the semiconductor system 1 operates at a speed of 10 Gbps and consumes 53 W. In Case 1, the thermal path temperature is 124 °C.

[0101] The second case (2CASE) is as follows: the semiconductor system 1 operates at a speed of 10 Gbps and consumes 58 W. In the second case (2CASE), the thermal path temperature (TEMP) is 163 °C.

[0102] The third case (3CASE) is as follows: the semiconductor system 1 operates at a speed of 12 Gbps and consumes 68 W. In the third case (3CASE), the thermal path temperature (THERMAL PATH TEMP) is 182 °C.

[0103] As shown in the table, it can be seen that when the operating speed of semiconductor system 1 is 10 Gbps and the power consumption increases from 53 W to 58 W, the thermal path temperature (THERMAL PATH TEMP) increases from 124 °C to 163 °C. That is, data reliability can only be ensured when refresh operations are performed at shorter intervals because the thermal path temperature (THERMAL PATH TEMP) increases.

[0104] Furthermore, as shown in the table, it can be seen that when the operating speed of semiconductor system 1 increases from 10Gbps to 12Gbps and the power consumption increases from 58W to 68W, the thermal path temperature (THERMAL PATH TEMP) increases from 163°C to 182°C. That is, data reliability can only be ensured when refresh operations are performed at shorter intervals because the thermal path temperature (THERMAL PATH TEMP) increases.

[0105] Figure 8 This is a block diagram illustrating the construction of a semiconductor system 3 according to another embodiment of the present disclosure. Figure 8 As shown, the semiconductor system 3 may include a PCB 11, a substrate 13, an interposer 15, an HBM device 17, and a processor 19.

[0106] PCB 11 connects several electronic components to form an electronic circuit (not shown). A copper layer, a solder mask layer, and a silkscreen layer can be formed on PCB 11. Circuit paths for transmitting signals or electricity can be formed in the copper layer. The solder mask layer prevents damage to the circuit and protects specific areas where components can be soldered. Furthermore, the silkscreen layer indicates the location or information of electronic components in the form of characters or symbols printed on the surface of PCB 11.

[0107] Substrate 13 is formed on PCB 11 via bump pads (e.g., 12) and can mechanically support interposer 15, HBM device 17, and processor 19. Substrate 13 can typically be used as an insulator, i.e., as the physical basis of PCB 11. Materials for substrate 13 include FR4 (i.e., an insulator made of glass fiber and epoxy resin), ceramics (which can withstand high temperatures due to their thermal conductivity and are typically used in high-frequency circuits or high-temperature environments), and polyimide (used as a base material for flexible PCBs due to its flexibility).

[0108] Intermediate layer 15 is formed on substrate 13 via bump pads and may include leads for connecting electronic components (e.g., HBM device 17 and processor 19) with mismatched form factors or pin arrangements. Intermediate layer 15 can convert signals in different interfaces.

[0109] HBM device 17 can be formed on interposer 15 via microbump pads (e.g., 16). Under the control of processor 19, HBM device 17 can store data applied by processor 19, or can output data stored in HBM device 17 to processor 19. HBM device 17 may include base chip 120 and multiple core chips 130-1 to 130-L. Multiple core chips 130-1 to 130-L can be stacked on or on base chip 120 via microbump pads. Base chip 120 and multiple core chips 130-1 to 130-L can be vertically connected via TSVs. Base chip 120 can generate command CMD by receiving external command EC from processor 19 via leads through interposer 15. Base chip 120 can generate data DATA by receiving external data ED from processor 19. Base chip 120 can output data DATA to processor 19 via leads through interposer 15. The base chip 120 can output commands (CMD) and data (DATA) to multiple core chips 130-1 to 130-L via TSV. The base chip 120 can generate multiple refresh control signals (RC), the generation period of each of which is adjusted to regulate the refresh operation period of the multiple core chips 130-1 to 130-L. The base chip 120 can also output these refresh control signals (RC) to the multiple core chips 130-1 to 130-L via TSV.

[0110] When the base chip 120 generates input commands INC and input data IND, a thermal path may be formed. The thermal path can be configured to follow the path along which heat generated during the generation of the input commands INC and input data IND is transferred. The thermal path can be formed vertically from the base chip 120.

[0111] The basic chip 120 can be used with, for example Figure 1 The control device 110 shown is used together.

[0112] Each of the multiple core chips 130-1 to 130-L may include multiple independently operating channel regions. Each channel region may be assigned as an independently operating channel capable of receiving or transmitting data. Each channel region may include a core region and can receive or transmit data. Some channels in the multiple channel regions of each core chip 130-1 to 130-L may be included and positioned in a hot path. Some channels in the multiple channel regions of each core chip 130-1 to 130-L may be positioned adjacent to the hot path. Some channels in the multiple channel regions of each core chip 130-1 to 130-L may be positioned spaced apart from the hot path. Channels included in the hot path may perform refresh operations at the fastest cycle based on multiple refresh control signals RC generated at the fastest cycle. Channels positioned adjacent to the hot path may perform refresh operations at a slower cycle than channels included in the hot path. Channels set to be separated from hot paths can perform refresh operations at a slower cycle than channels set to be adjacent to hot paths.

[0113] The number L of core chips 130-1 to 130-L can be 4, 8, 12, or 16. For example, when each of the core chips 130-1 to 130-12 includes 8 channels, each of the core chips 130-1 to 130-4, 130-5 to 130-8, and 130-9 to 130-12 can include 32 channel regions and can transfer data to and receive data from the processor 19 in units of memory comprising 32 channels.

[0114] The core chips 130-1 to 130-L can each be configured as follows: Figure 1 The storage devices 210, 220, 230 and 240 shown are implemented.

[0115] HBM device 17 can ensure the reliability of data stored in channels by performing refresh operations on channels included in the multiple core chips 130-1 to 130-L and included in the hot path formed from the base chip 120 at short cycles. HBM device 17 can ensure the reliability of data stored in channels by adjusting the refresh operation cycle differently based on the differences between the hot path formed from the base chip 120 and the channel positions included in the multiple core chips 130-1 to 130-L.

[0116] The processor 19 can control the operation of the base chip 120 via leads formed within the interposer layer 15. The processor 19 can control the base chip 120 such that commands (not shown) and signals (not shown) controlling the operation of the core chips 121-1 to 121-L are output to the core chips 121-1 to 121-L performing the operation.

Claims

1. A semiconductor system, comprising: Control device, which: Generate input commands and input data from external commands and external data; and Commands and data are generated from the input commands and the input data, and a first refresh control signal and a second refresh control signal are generated; and A storage device, comprising a first channel and a second channel, for receiving the command and the data, and for performing internal operations based on the command and the data. The first channel performs a refresh operation in a first cycle based on the first refresh control signal. The second channel performs the refresh operation in a second cycle based on the second refresh control signal, and The first channel is set in the hot path formed when the input command and the input data are generated.

2. The semiconductor system of claim 1, wherein, The first cycle is shorter than the second cycle.

3. The semiconductor system as described in claim 1, in, The first period is set to be 1 / 2N of the period of the second period, and Here, N is set to an integer greater than 0.

4. The semiconductor system as described in claim 1, in, The heat path is configured to be the path along which the heat generated when the input command and the input data are generated is transferred. The thermal path is formed vertically from the control device.

5. The semiconductor system of claim 1, wherein, The control device includes: A physical region that generates the input command and the input data by receiving the external command and the external data from an external device; A memory controller receives the input command and the input data from the physical region, and outputs the command and the data to control the internal operation of the memory device based on the input command and the input data, and outputs a first refresh control signal and a second refresh control signal; and The basic TSV region receives the command, the data, the first refresh control signal, and the second refresh control signal from the memory controller, and outputs the command, the data, the first refresh control signal, and the second refresh control signal to the memory device.

6. The semiconductor system of claim 5, wherein, The physical region is located within the thermal path.

7. The semiconductor system of claim 1, wherein, The storage device includes: A memory control circuit, electrically connected to the control device, wherein: Receive the command, the data, and the first refresh control signal, and output the command, the data, and the first refresh control signal to the first channel. The system receives the command, the data, and the second refresh control signal, and outputs the command, the data, and the second refresh control signal to the second channel. The first channel performs the internal operation based on the command and the data, and performs the refresh operation at the first cycle based on the first refresh control signal; and The second channel performs the internal operation based on the command and the data, and performs the refresh operation at the second cycle based on the second refresh control signal.

8. The semiconductor system as claimed in claim 7, in, The first channel is disposed in a first region included in the thermal path, and The second channel is located in a second region adjacent to the thermal path.

9. A semiconductor system, comprising: Control device, which: Generate input commands and input data from external commands and external data; and Commands and data are generated from the input commands and the input data, and a first refresh control signal, a second refresh control signal, and a third refresh control signal are generated; and A storage device, comprising a first channel, a second channel, and a third channel, which receives the command and the data, and performs internal operations based on the command and the data. The first channel performs a refresh operation in a first cycle based on the first refresh control signal. The second channel performs the refresh operation in a second cycle based on the second refresh control signal, and the third channel performs the refresh operation in a third cycle based on the third refresh control signal. The first channel is configured in the hot path formed when the input command and the input data are generated. Wherein, the second channel is configured to be adjacent to the thermal path, and The third channel is configured to be spaced apart from the thermal path, wherein the second channel is located between the third channel and the thermal path.

10. The semiconductor system as claimed in claim 9, in, The first period is shorter than the second period, and The second cycle is shorter than the third cycle.

11. The semiconductor system as claimed in claim 9, in, The first period is set to be 1 / 2N of the period of the second period. Wherein, the second period is set to be 1 / 2N of the period of the third period, and Here, N is set to an integer greater than 0.

12. The semiconductor system as claimed in claim 9, in, The heat path is configured to be the path along which the heat generated when the input command and the input data are generated is transferred. The thermal path is formed vertically from the control device.

13. The semiconductor system of claim 9, wherein, The control device includes: A physical region that generates the input command and the input data by receiving the external command and the external data from an external device; A memory controller receives the input command and the input data from the physical region, and outputs the command and the data to control the internal operation of the memory device based on the input command and the input data, and outputs the first refresh control signal to the third refresh control signal; and The basic TSV region receives the command, the data, and the first refresh control signal to the third refresh control signal from the memory controller, and outputs the command, the data, and the first refresh control signal to the third refresh control signal to the memory device.

14. The semiconductor system of claim 13, wherein, The physical region is located within the thermal path.

15. The semiconductor system of claim 9, wherein, The storage device includes: A memory control circuit, electrically connected to the control device, wherein: Receive the command, the data, and the first refresh control signal, and output the command, the data, and the first refresh control signal to the first channel; Receive the command, the data, and the second refresh control signal, and output the command, the data, and the second refresh control signal to the second channel; and Receive the command, the data, and the third refresh control signal, and output the command, the data, and the third refresh control signal to the third channel; The first channel performs the internal operation based on the command and the data, and performs the refresh operation at the first cycle based on the first refresh control signal; The second channel performs the internal operation based on the command and the data, and performs the refresh operation at the second cycle based on the second refresh control signal; and The third channel performs the internal operation based on the command and the data, and performs the refresh operation in the third cycle based on the third refresh control signal.

16. The semiconductor system of claim 15, in, The first channel is disposed in a first region included in the thermal path. The second channel is disposed in a second region adjacent to the thermal path, and The third channel is located in a third region spaced apart from the first region, wherein the second region is located between the third region and the first region.

17. A storage device comprising: The first channel performs internal operations by receiving commands and data generated from input commands and input data, and performs refresh operations in a first cycle based on a first refresh control signal; as well as The second channel executes the internal operations by receiving the commands and the data, and performs the refresh operation at a second cycle based on the second refresh control signal. The first channel is located in the hot path. Wherein, the second channel is configured to be spaced apart from the thermal path, and The thermal path is the path along which the heat generated when the input command and the input data are generated is transferred.

18. The storage device of claim 17, wherein, The first cycle is shorter than the second cycle.

19. The storage device as claimed in claim 17, in, The first period is set to be 1 / 2N of the period of the second period, and Here, N is set to an integer greater than 0.

20. The storage device of claim 17, wherein, The thermal path is configured such that the heat generated when the input command and the input data are generated travels along the path of their transmission, wherein the input command and the input data perform the internal operations of the first channel and the second channel.

21. A storage device comprising: A first channel, the first channel comprising a first storage cell and a second storage cell; as well as The second channel includes a third memory bank and a fourth memory bank. The first memory bank and the second memory bank perform refresh operations at different periods based on the first refresh control signal and the second refresh control signal. The third memory bank and the fourth memory bank perform the refresh operation at the same period based on the third refresh control signal. The first channel is positioned within the heat transfer path along which heat is transferred, and The second channel is configured to be spaced apart from the thermal path.

22. The storage device as claimed in claim 21, in, The thermal path is configured such that the heat generated during the generation of input commands and input data travels along the path along which it is transferred, wherein the input commands and input data perform internal operations of the first and second channels, and The thermal path is formed along the direction from the first memory cell to the second memory cell.

23. The storage device as claimed in claim 21, in, The first memory bank performs the refresh operation in a first cycle based on the first refresh control signal, and The second storage unit performs the refresh operation in a second cycle based on the second refresh control signal.

24. The storage device of claim 23, wherein, The first cycle is shorter than the second cycle.

25. The storage device as claimed in claim 23, in, The first period is set to be 1 / 2N of the period of the second period, and Here, N is set to an integer greater than 0.

26. The storage device as claimed in claim 25, in, The third storage bank performs the refresh operation in a third cycle based on the third refresh control signal, and The fourth storage bank performs the refresh operation in the third cycle based on the third refresh control signal.

27. The storage device of claim 26, wherein, The second period is set to be 1 / 2N of the period of the third period.

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