Semiconductor apparatus and manufacturing method therefor, storage apparatus, and electronic device

Abstract

The present application provides a semiconductor apparatus and a manufacturing method therefor, a storage apparatus, and an electronic device. The semiconductor apparatus comprises: a first transistor array; a second transistor array; a capacitor array; a first trace, connected to first terminals of a plurality of first transistors arranged in a first direction; a second trace, connected to second terminals of a plurality of first transistors arranged in a second direction; a first interconnection node, connected to a first driving terminal of one first transistor in the first transistor array; a third trace, connected to second driving terminals of a plurality of second transistors arranged in a third direction; a fourth trace, connected to fourth terminals of a plurality of second transistors arranged in a fourth direction; and a second interconnection node, connected to the first interconnection node, a third terminal of one second transistor in the second transistor array, and a first electrode structure of one capacitor in the capacitor array. The technical solution helps improve the performance of a memory.

Description

Semiconductor devices and their manufacturing methods, memory devices and electronic devices Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for manufacturing the same, a memory device, and an electronic device. Background Technology

[0002] Semiconductor memory, as an important branch of memory technology, has captured a large share of the memory market due to its advantages such as high-speed read / write, high integration, and low power consumption, and has promising development prospects. Semiconductor memory is formed from semiconductor devices, and the structure of these devices is closely related to the performance of the memory. How to optimize the structure of semiconductor devices to improve memory performance is a technical problem that urgently needs to be solved. Summary of the Invention

[0003] This application provides a semiconductor device and its manufacturing method, a storage device, and an electronic device, which are beneficial for improving the performance of memory.

[0004] In a first aspect, a semiconductor device is provided, comprising: a first transistor array; a second transistor array formed on the first transistor array; a capacitor array formed on the second transistor array; a first trace, a second trace, and a first interconnect node, wherein the first trace extends along a first direction and connects to first terminals of a plurality of first transistors arranged along the first direction in the first transistor array; the second trace extends along a second direction and connects to second terminals of a plurality of first transistors arranged along the second direction in the first transistor array; the first interconnect node is connected to a first driving terminal of a first transistor in the first transistor array; a third trace, a fourth trace, and a second interconnect node, wherein the third trace extends along a third direction and connects to second driving terminals of a plurality of second transistors arranged along the third direction in the second transistor array; the fourth trace extends along a fourth direction and connects to fourth terminals of a plurality of second transistors arranged along the fourth direction in the second transistor array; the second interconnect node is connected to the first interconnect node, a third terminal of a second transistor in the second transistor array, and a first electrode structure of a capacitor in the capacitor array.

[0005] The technical solution of this application combines two transistor arrays and one capacitor array in a vertical space within a semiconductor device. This not only facilitates three-dimensional (3D) process integration but also improves the accuracy and stability of data storage when the semiconductor device is used in a storage circuit. Layered stacking of different parts within the storage cell allows for higher space utilization and smaller size of the semiconductor device. This enables more stable and reliable data storage with a smaller footprint or area, improving the reliability of the storage system. Furthermore, the reduced size or area provides more usable space or area for other circuits within the chip, such as logic circuits, which is beneficial for improving logic circuit performance. The layered structure further enhances storage performance. Moreover, placing the capacitor array above the transistor array reduces the space constraints imposed by the transistor array on the capacitor array, allowing the capacitors in the capacitor array to expand in both the stacking and horizontal directions, thereby maximizing the capacitance value and further improving the storage performance of the storage system. This solution features a high degree of process integration in the semiconductor device, enabling denser stacking and facilitating better implementation of storage and in-memory computing functions. The array connection method of the above semiconductor devices can be applied to in-memory computing architectures to store weight data. This weight data can be used for in-memory computation or near-memory computation. The storage circuits / memories implemented using the above semiconductor devices can improve the accuracy and stability of weight data storage in the storage units, thereby improving the reliability of in-memory computing architectures. In addition, the above array structure can support efficient in-memory computation within the semiconductor devices.

[0006] In some implementations of the first aspect, the semiconductor device includes: a first device layer including a first transistor array; and a first interconnect layer formed on the first device layer, including a first trace, a second trace, and a first interconnect node, wherein the first trace and the second trace are located in different sublayers of the first interconnect layer, and either the first trace or the second trace and the first interconnect node are located in the same sublayer.

[0007] In a semiconductor device, a first transistor, a second transistor, and a capacitor are connected at a memory node. A first interconnect node can help realize the memory node. The first interconnect node is located on the same sublayer as either the first trace or the second trace, eliminating the need for a separate sublayer to house the first interconnect node. This reduces the number of sublayers in the interconnect layer, which helps to reduce the height of the semiconductor device and contributes to its miniaturization.

[0008] In some implementations of the first aspect, the semiconductor device includes: a second device layer including a second transistor array, wherein second drive terminals of a plurality of second transistors arranged along a third direction are integrally formed into a third trace extending along the third direction.

[0009] Compared to forming multiple second driving terminals and traces separately, forming traces by integrating multiple second driving terminals can reduce process steps, thereby greatly simplifying the process flow of the second transistor array. It can also reduce the space occupied by the trace structure of the second transistor array, which is beneficial for further miniaturizing the structure of semiconductor devices.

[0010] In some implementations of the first aspect, the semiconductor device further includes a second interconnect layer, comprising a second interconnect node. In the semiconductor device, the first transistor, the second transistor, and the capacitor are connected at a storage node, and the second interconnect node can facilitate the implementation of the storage node.

[0011] In some implementations of the first aspect, the second connection layer further includes a fourth trace, which is located on the same layer as the second interconnect node. Thus, since the second interconnect node and the fourth trace are located on the same sublayer, it is not necessary to set up a separate sublayer for the second interconnect node, thereby reducing the number of sublayers in the connection layer. This is beneficial for reducing the height of semiconductor devices and contributes to the miniaturization of semiconductor devices.

[0012] In some implementations of the first aspect, the semiconductor device includes: a third device layer including a capacitor array and at least one interlayer dielectric layer, the at least one interlayer dielectric layer including a first interlayer dielectric layer formed on a second interconnect layer, a fourth trace formed in the first interlayer dielectric layer, and at least a portion of the capacitors of the capacitor array formed in the first interlayer dielectric layer.

[0013] The fourth trace is formed in the first interlayer dielectric layer. With the same capacitance value, the overall height of the third device layer and the second interconnect layer can be reduced, which is beneficial for reducing the size of the semiconductor device and simplifying the manufacturing process of the semiconductor device. Alternatively, with the same overall height, more interlayer dielectric layers can be used to increase the height of the capacitor, thereby increasing the capacitance value and further improving the voltage stability and hold time at the storage node.

[0014] In some implementations of the first aspect, the first transistor array includes a plurality of first transistor pairs; wherein, in a first transistor pair, two first transistors share a first terminal, and the second terminals of the two first transistors are located on either side of the shared first terminal. This further improves the compactness of the semiconductor device, enabling it to further increase the storage density of the memory circuit when used in a memory circuit.

[0015] In some implementations of the first aspect, multiple pairs of first transistors are arranged along a second direction, and the second terminals of the two first transistors in a pair are located on both sides of a first terminal shared by the two first transistors along a first direction. This allows for layout that combines the directions of the first and second traces, further improving the compactness of the semiconductor device and enabling a further increase in the storage density of the memory circuit when the semiconductor device is used.

[0016] In some implementations of the first aspect, the semiconductor device includes a plurality of second trace pairs, one second trace pair corresponding to one first transistor pair, the second terminals of the first transistors in the first transistor pair being respectively connected to different second traces in the corresponding second trace pair, and electrical connection structure pairs being formed between the second traces in the second trace pair, corresponding to a first interconnect node pair, one electrical connection structure in the electrical connection structure pair being connected to the first driving terminal of the first transistor in the corresponding first transistor pair and the first interconnect node in the corresponding first interconnect node pair, and the other electrical connection structure being connected to the first driving terminal of the other first transistor in the corresponding first transistor pair and the other first interconnect node in the corresponding first interconnect node pair.

[0017] This technical solution can make full use of the space between the two second traces in the second trace pair to set up an electrical connection structure pair for connecting two first driving terminals and two first interconnect nodes of a first transistor pair. This is beneficial to make the layout of the semiconductor device more compact, thereby further reducing the size of the semiconductor device and increasing the storage density of the semiconductor device.

[0018] In some implementations of the first aspect, the semiconductor device includes a plurality of first trace pairs, wherein a first interconnect node pair is formed between two first trace pairs, and the two first interconnect nodes in the first interconnect node pair are respectively connected to the first drive terminals of different first transistors in a first transistor pair.

[0019] In some implementations of the first aspect, the second transistor array includes multiple pairs of second transistors; wherein two second transistors in a pair share a fourth terminal or a conductive structure corresponding to the fourth terminal, and the second driving terminals of the two second transistors are located on both sides of the shared fourth terminal or the conductive structure corresponding to the fourth terminal. This further improves the compactness of the semiconductor device, enabling it to further increase the storage density of the memory circuit when used in a memory circuit.

[0020] In some implementations of the first aspect, multiple pairs of second transistors are arranged along a third direction, and the second driving terminals of two second transistors in a pair are located along a fourth direction on both sides of a shared fourth terminal or a conductive structure corresponding to the fourth terminal. This allows for layout that combines the directions of the third and fourth traces, further improving the compactness of the semiconductor device and enabling a further increase in the storage density of the memory circuit when the semiconductor device is used.

[0021] In some implementations of the first aspect, the semiconductor device includes a third trace pair, wherein the second drive terminals of two second transistors in a second transistor pair are respectively connected to different third traces in the third trace pair, and in a plurality of second transistor pairs arranged along a third direction, the second drive terminals of second transistors located in the same row along the third direction are connected to the same third trace.

[0022] In some implementations of the first aspect, the semiconductor device includes a plurality of second interconnect node pairs, two of the second interconnect node pairs being respectively connected to the third terminals of different second transistors in a second transistor pair, and the plurality of second interconnect node pairs including a first row of second interconnect nodes and a second row of second interconnect nodes arranged in a fourth direction, with a fourth trace formed between the first row of second interconnect nodes and the second row of second interconnect nodes.

[0023] In a second aspect, a method for manufacturing a semiconductor device is provided, comprising: forming a first transistor array; forming a first trace, a second trace, and a first interconnect node, wherein the first trace extends along a first direction and connects to first terminals of a plurality of first transistors arranged along the first direction in the first transistor array, the second trace extends along a second direction and connects to second terminals of a plurality of first transistors arranged along the second direction in the first transistor array, and the first interconnect node is connected to a first driving terminal of a first transistor in the first transistor array; forming a second transistor array on the first transistor array; forming a third trace, a fourth trace, and a second interconnect node, wherein the third trace extends along a third direction and connects to second driving terminals of a plurality of second transistors arranged along the third direction in the second transistor array, the fourth trace extends along a fourth direction and connects to fourth terminals of a plurality of second transistors arranged along the fourth direction in the second transistor array, and the second interconnect node is connected to the first interconnect node and a third terminal of a second transistor in the second transistor array; and forming a capacitor array on the second transistor array, wherein a first electrode structure of a capacitor in the capacitor array is connected to the second interconnect node.

[0024] For a description of the beneficial effects of the second aspect, please refer to the description of the beneficial effects of the first aspect, which will not be repeated here.

[0025] Thirdly, a storage device is provided, comprising: a storage circuit including a semiconductor device provided in the first aspect or any implementation thereof; and a control circuit configured to control the operating state of the storage circuit.

[0026] Fourthly, an electronic device is provided, including the storage device provided in the third aspect. Attached Figure Description

[0027] Figure 1 shows a schematic diagram of a storage system according to an exemplary embodiment of this application.

[0028] Figure 2 shows a schematic diagram of another storage system according to an exemplary embodiment of this application.

[0029] Figure 3 shows a schematic diagram of a storage unit according to an exemplary embodiment of this application.

[0030] Figure 4 shows a schematic diagram of a semiconductor device according to an exemplary embodiment of this application.

[0031] Figure 5 shows a schematic diagram of a transistor layer according to an exemplary embodiment of this application.

[0032] Figures 6A to 6C show schematic diagrams of another transistor layer according to exemplary embodiments of this application.

[0033] Figure 7 shows a schematic diagram of yet another transistor layer according to an exemplary embodiment of this application.

[0034] Figures 8A and 8B show schematic diagrams of yet another transistor layer according to exemplary embodiments of this application.

[0035] Figure 9 shows a schematic diagram of yet another transistor layer according to an exemplary embodiment of this application.

[0036] Figures 10A, 10B, and 10C illustrate schematic diagrams of yet another transistor layer according to exemplary embodiments of this application.

[0037] Figure 11 shows a schematic diagram of a capacitor layer according to an exemplary embodiment of this application.

[0038] Figure 12 shows a schematic diagram of another capacitor layer according to an exemplary embodiment of this application.

[0039] Figure 13 shows a schematic diagram of yet another capacitor layer according to an exemplary embodiment of this application.

[0040] Figure 14 shows a schematic diagram of a semiconductor device according to an exemplary embodiment of this application.

[0041] Figures 15A to 15D show schematic diagrams of a partial structure of a semiconductor device according to an exemplary embodiment of the present application.

[0042] Figures 16A to 16D show schematic diagrams of a partial structure of another semiconductor device according to exemplary embodiments of this application.

[0043] Figures 17A to 17D show schematic diagrams of a partial structure of another semiconductor device according to an exemplary embodiment of the present application.

[0044] Figure 18 shows a schematic diagram of a partial structure of another semiconductor device according to an exemplary embodiment of this application.

[0045] Figure 19 shows a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment of this application.

[0046] Figure 20 shows a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment of this application.

[0047] Figures 21A to 21F illustrate schematic diagrams of the manufacturing process of a portion of a semiconductor device according to an exemplary embodiment of this application.

[0048] Figures 22A to 22E illustrate schematic diagrams of the manufacturing process of a portion of the structure of another semiconductor device according to exemplary embodiments of this application.

[0049] Figures 23A to 23G illustrate schematic diagrams of the manufacturing process of a portion of the structure of another semiconductor device according to an exemplary embodiment of this application.

[0050] Figures 24A to 24D illustrate schematic diagrams of the manufacturing process of a partial structure of another semiconductor device according to exemplary embodiments of this application.

[0051] Figures 25A to 25E illustrate schematic diagrams of the manufacturing process of a portion of the structure of another semiconductor device according to exemplary embodiments of this application.

[0052] Figures 26A to 26E illustrate schematic diagrams of the manufacturing process of a portion of the structure of another semiconductor device according to exemplary embodiments of this application.

[0053] Figure 27 shows a schematic diagram of a storage device according to an exemplary embodiment of this application.

[0054] Figure 28 shows a schematic diagram of an electronic device according to an exemplary embodiment of this application. Detailed Implementation

[0055] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0056] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0057] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0058] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0059] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0060] In this application, the elements of the material are represented by the element symbols in the chemical formula, and the subscripts of the elements in the chemical formula are omitted. The value of the subscript of the element in the chemical formula can be determined based on factors such as the valence of the element. Unless explicitly described in the context, this application does not limit the stoichiometry, near-stoichiometry, or impurity-doped materials of the material.

[0061] This application provides a storage system. The storage system may include a storage circuit and a readout circuit. The storage circuit stores data; the readout circuit converts the output signal of the storage circuit to achieve more accurate reading of the data stored in the storage circuit. In some embodiments, the storage system may further include a control device that can control one or more operations of the storage circuit, such as programming (or data writing), erasing, and reading. The control device can control the readout circuit to more accurately read the data stored in the storage circuit.

[0062] According to some embodiments, this storage system can be used in in-memory computing technology. This storage system can also be called an in-memory computing system or a computing system. The control device is used to control one or more operations of the storage circuit, such as programming, erasing, calculation, and reading. The reading can include reading stored data and / or reading (or sensing) calculation results. For example, the control device can be integrated with the storage circuit and call up data stored in the storage circuit, and perform calculations based on the called data; or, alternatively, the control device can control the in-memory calculations of the storage circuit and control the reading of the calculation results; optionally, the control device can also process the calculation results. This application does not limit the type of storage medium of the storage circuit, which may include, but is not limited to, non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, but is not limited to, static random access memory (SRAM) or dynamic random access memory (DRAM); non-volatile memory may include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric memory (FeRAM), or phase change memory (PCM). This application does not limit the structure of the control device. The control device may include one or more processing circuits. For example, a first processing circuit controls the operating state of the storage circuit and the operation of the read circuit; a second processing circuit processes the output of the storage circuit, such as performing calculations on the data stored in the storage circuit or processing the calculation results output by the storage circuit.

[0063] As an example, FIG1 shows a schematic diagram of a storage system according to an exemplary embodiment of the present application. As shown in FIG1, the storage system 100 may include a storage circuit 110, a control device 120, and a readout circuit 130. The control device 120 is connected to the storage circuit 110 and the readout circuit 130 to control one or more operations such as programming, reading, and erasing of the storage circuit 110. The storage circuit 110 may include multiple storage arrays, thereby increasing the storage capacity of the storage circuit. The readout circuit 130 is coupled to the output terminal of the storage circuit 110, receives the output signal S of the storage circuit 110, converts it into output data D, and provides it to the subsequent circuit (e.g., a processing circuit) so that the subsequent circuit can process the output data. The present application does not limit the processing content of the subsequent circuit, and different processing operations may be performed in different application systems. According to some embodiments, the storage system 100 can be used in a memory-computing architecture, and when used in a memory-computing architecture, the storage system 100 can also be called a memory-computing system or a computing system. The control device 120 is also used to control the computing operations of the storage circuit 110.

[0064] The output of storage circuit 110 may include the output of stored data or the output of calculation results. Control device 120's control of the output of storage circuit 110 may include controlling the following processes: establishing an output signal and performing at least one conversion on the output signal. This at least one conversion may include one or more of the following: signal type conversion, signal magnitude conversion, such as current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, control device 120 may control readout circuit 130 to perform a first conversion and a second conversion on the output signal S. The first conversion includes current-to-voltage conversion; for example, the output signal S of storage circuit 110 includes a current signal, and readout circuit 130 can convert the current signal into a voltage signal. The second conversion includes analog-to-digital conversion; for example, readout circuit 130 can convert the output of the first conversion into a digital signal. During the first conversion and / or the second conversion, the output signal may be amplified, or the output signal may be amplified after the first or second conversion. The readout circuit 130, which has an amplification function for the output signal, may also be called an inductive amplifier circuit.

[0065] Figure 2 shows a schematic diagram of another storage system according to an exemplary embodiment of this application.

[0066] As shown in Figure 2, the storage system 200 includes a storage circuit 210, a readout circuit 220, and a control device 230. The readout circuit 220 includes a first conversion circuit 221 and a second conversion circuit 222. The first conversion circuit 221 performs a first conversion on the output signal of the storage circuit 210 (e.g., readout current), for example, converting the current signal into a voltage signal. The second conversion circuit 222 performs a second conversion on the output of the first conversion, for example, converting the analog signal into a digital signal. The first conversion circuit 221 can also be called a sampling circuit; for example, the sampling circuit can be used to sample the current signal output by the storage circuit as a voltage signal. The second conversion circuit 222 can also be called a decision circuit; for example, the decision circuit can be used to convert the waveform parameters of the analog signal (e.g., voltage signal) into digital signals, for example, converting the amplitude, pulse width, or area of ​​the analog signal into digital signals through decision-making. This application does not limit the accuracy of this conversion or decision; for example, it can include 1-bit or multi-bit conversion accuracy. The control device 230 can control the operating state of the storage circuit 210.

[0067] The storage circuit 210 may include a storage array, such as storage array A1. Alternatively, the storage circuit 210 may include multiple storage arrays, such as storage arrays A1, A2, etc. A storage array includes multiple storage cells S. ij Where i ∈ [1, m], j ∈ [1, n], m is the number of rows in the storage array, and n is the number of columns in the storage array. Storage unit S ij It can store data W ij The control device 230 can control the storage array to be in a programming (or writing) state to send data to the storage cells S. ij Write data W ij The control device 230 can control the memory array to be in a read state, so as to put the memory cell S... ij Stored data W ij Read out. Storage unit S ij The conduction capability can be based on the stored data W ij Alternatively, the control device 230 can control the storage array to be in a computing state, and the data W... ij This can be referred to as weight data. In calculation mode, the control device 230 can send data to the storage unit S via the input terminal IN of the storage array. ij Provide an input signal; this input signal acts on the storage unit S ij The weight data stored in a storage cell enables the cell to have corresponding conduction capability, which generates current flowing to or into the output terminal. Multiple storage cells (e.g., S...) 1j -S mj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the current generated by multiple memory cells accumulates to obtain the output signal I.j Satisfy the following formula:

[0068] As can be seen, a storage array can be used to perform multiplication and accumulation calculations, and the calculation result can be output at the output terminal. The sensing output of the calculation result can be understood as reading the calculation result. The multiple storage cells with collinear outputs can be called a storage cell group.

[0069] The aforementioned storage unit may include a semiconductor device, and utilizes the conductivity of the semiconductor device, such as electrical conductance or transconductance, to store data. For example, the storage unit may include a resistive storage device or a transistor storage device. For instance, weight data can be stored by controlling the conductivity of the resistive storage device, or weight data can be stored by controlling the transconductance of the transistor storage device. Alternatively, the storage unit may utilize the energy stored in an energy storage element to store weight data, such as using the charge stored in a capacitor; this energy storage element may be connected to the semiconductor device, and the stored energy may act on the semiconductor device, causing the semiconductor device to generate a corresponding conductivity.

[0070] Figure 2 is only an example illustrating a connection method of memory cells in a memory cell array. Other connection methods can be used besides those shown in Figure 2. For example, the input terminals of the memory cells can be connected collinearly along columns, and the output terminals can be connected collinearly along rows. Furthermore, the input terminal of a memory cell may include the gate of a transistor memory device, or it may include the source or drain of a transistor memory device; this application does not limit the specific type of memory cell. This application also does not limit the type of memory cell; for example, a memory cell may include, but is not limited to, transistors, memristors, magnetic tunnel junctions (MTJs), or phase-change structures. This application also does not limit the type of transistor, including, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), floating-gate transistors (FGTs), ferroelectric field-effect transistors (FeFETs), and thin-film transistors.

[0071] In the example shown in Figure 2, the storage circuit 210 may include multiple output terminals OUT. For each output terminal OUT, an independent first sub-conversion circuit and / or second sub-conversion circuit can be set to improve readout bandwidth. For example, taking storage array A1 as an example, the first conversion circuit 221 may include multiple first conversion sub-circuits 2211, which are respectively connected to multiple output terminals and are used to perform a first conversion on the signal of the corresponding output terminal OUT. The second conversion circuit 222 may include multiple second conversion sub-circuits, which are respectively connected to multiple first conversion sub-circuits and are used to perform a second conversion on the output of the first conversion sub-circuit. However, this arrangement has a large overhead in the peripheral circuit, which is not conducive to chip miniaturization. In some other embodiments, multiple output terminals can share a first conversion circuit or a first conversion sub-circuit, and multiple first conversion sub-circuits can share a second conversion circuit or a second conversion circuit. For example, taking storage array A1 as an example, the first conversion circuit 221 may include multiple first conversion sub-circuits 2211, each connected to multiple output terminals, for time-division multiplexing of the signals from the multiple output terminals for a first conversion; the second conversion circuit 222 may include multiple second conversion sub-circuits 2221, each connected to multiple first conversion sub-circuits 2211, for time-division multiplexing of the outputs from the multiple first conversion sub-circuits 2211 for a second conversion. For ease of illustration, the output terminal of storage array A1 is used as an example above. When storage circuit 210 includes multiple storage arrays, the output terminals of other storage arrays or multiple storage arrays can use the above multiplexing method to multiplex the first conversion sub-circuits and the second conversion sub-circuits. This application does not limit the number of first conversion sub-circuits and the number of second conversion sub-circuits; or, it does not limit the number of multiplexed output terminals of the first conversion sub-circuits, nor does it limit the number of multiplexed first conversion sub-circuits of the second conversion sub-circuits.

[0072] In some embodiments of this application, the memory cell may include multiple transistors; for example, the memory cell may include a first transistor and a second transistor, wherein the gate of the first transistor (which may be referred to as a "read transistor" or "read tube") and the source or drain of the second transistor (which may be referred to as a "write transistor" or "write tube") are connected, and the charge stored at the gate of the first transistor can be used, for example, to characterize the stored data in a voltage-dependent form. Optionally, the gate of the first transistor may also be connected to a capacitor to increase the stability and duration of the voltage used to characterize the stored charge.

[0073] As an example, Figure 3 illustrates a storage unit S according to an exemplary embodiment of this application. ij A schematic diagram.

[0074] As shown in Figure 3, in storage unit S ijIn this configuration, transistor T1 can be a first transistor (also called a "read transistor"), with its non-control terminals referred to as first terminal T11 and second terminal T12, and its control terminal referred to as first drive terminal T13. Transistor T2 can be a second transistor (also called a "write transistor"), with its non-control terminals referred to as third terminal T21 and fourth terminal T22, and its control terminal referred to as second drive terminal T23. For example, the control terminal may include a gate, and the non-control terminals may include a source and a drain. For instance, first terminal T11 may include a source, and second terminal T12 may include a drain, or vice versa. Similarly, third terminal T21 may include a source, and fourth terminal T22 may include a drain, or vice versa.

[0075] The first driving terminal T13 of transistor T1 and the third terminal T21 of transistor T2 are connected. The first driving terminal T13 or any equipotential node connected to it can be understood as the memory cell S. ij Storage node (SN). Storage unit S ij The circuit may further include a capacitor C, which may comprise a capacitor with one end connected to the first drive terminal T13 of transistor T1 (or connected to the storage node SN), and the other end connected to a voltage signal, such as a positive voltage, a negative voltage, or a ground voltage. Grounding the other end of the capacitor simplifies the number of signals required for the circuit connection, simplifies circuit implementation, and reduces signal interference. The amount of charge stored in capacitor C can be used to characterize the charge at the storage node, and the presence of capacitor C increases the stability and duration of the charge at the storage node, thereby improving the stability of the storage cell S. ij The data stored in it is more stable.

[0076] The non-driving terminals of transistor T1 can be used to couple the input line IN. i and output line OUT j As an example, in Figure 3, the first terminal T11 of transistor T1 is used to couple the output line OUT. j The second terminal T12 is used to couple the input line IN. i In another example, the first terminal T11 of transistor T1 in Figure 3 can also be used to couple the input line IN. i The second terminal T12 is used to couple the output line OUT. j The second drive terminal T23 and the fourth terminal T22 of transistor T2 can be used to couple different control lines. As an example, in Figure 3, the second drive terminal T23 of transistor T2 is used to couple control line CON1. i The fourth terminal T22 is used to couple the control line CON2. j The control line CON1 i and control line CON2j The transmitted signal can be used to control the state of transistor T2, and thus control the memory cell S. ij The work status.

[0077] In some examples, in storage unit S ij When in programming or writing mode, control line CON1 i The control signal is used to turn on transistor T2. The fourth terminal T22 of transistor T2 is used to couple to the control line CON2. j The programming signal on the memory cell S can change the memory cell S ij The charge stored at the storage node (SN) controls the flow of charge to the storage cell S. ij Data written to storage unit S. ij When in calculation or readout state, control line CON1 i The control signal on the input is used to turn off transistor T2. The second terminal T12 of transistor T1 is used to couple to the input line IN. i The input signal is transmitted through the first terminal T11 of transistor T1 via the output line OUT. j The output transistor T1 generates an output signal based on the input signal and the stored data.

[0078] The storage unit shown in Figure 3 can achieve accurate, stable, and long-term storage of weight data. Furthermore, it can improve problems such as high leakage current, short data retention time, and destructive data retrieval.

[0079] This application provides a semiconductor device that, through structural design, implements a first transistor (read transistor), a second transistor (write transistor), a capacitor, and the connections and wiring between them in a memory cell. This improves the accuracy and stability of the memory cell's weighted data storage and enhances the reliability of the memory. Furthermore, when the memory is used in an in-memory computing architecture, it can improve the reliability of the in-memory computing architecture.

[0080] Figure 4 shows a schematic diagram of a semiconductor device according to an exemplary embodiment of this application.

[0081] As shown in Figure 4, the semiconductor device 400 includes a transistor layer 410, a transistor layer 420, and a capacitor layer 430. The transistor layer 410 includes a transistor T1, which has a first terminal T11, a second terminal T12, and a first driving terminal T13. A channel CH1 is formed between the first terminal T11 and the second terminal T12. The first driving terminal T13 is formed on the channel CH1 and has a dielectric layer D1 between it and the channel CH1. A transistor layer 420 is formed on transistor layer 410 and includes an oxide structure O1, a conductive structure CE1, a conductive structure CE2, and a conductive structure CE3. Conductive structure CE1 is connected to a first portion of oxide structure O1, where a third terminal T21 of transistor T2 is formed. Conductive structure CE2 is connected to a second portion of oxide structure O1, where a fourth terminal T22 of transistor T2 is formed. A channel CH2 is formed between the third terminal T21 and the fourth terminal T22 within oxide structure O1. Conductive structure CE3 is formed on channel CH2 and serves as a second driving terminal T23 of transistor T2. A dielectric layer D2 is present between CE3 and oxide structure O1. A capacitor layer 430 is formed on transistor layer 420 and includes a capacitor C. The capacitor C includes electrode structures E1 and E2, with a dielectric layer D3 between E1 and E2. The first driving terminal T13 of transistor T1, the third terminal T21 of transistor T2, and the electrode structure E1 of capacitor C are electrically connected. In some implementations, the electrode structure in capacitor C may also be referred to as the terminal structure.

[0082] To more clearly illustrate the structures of transistors T1 and T2, Figure 4 shows enlarged views of transistors T1 and T2 in different cross-sections. As shown in Figure 4, the first terminal T11 and the second terminal T12 of transistor T1 can be distributed along the x-direction on both sides of the first driving terminal T13; alternatively, the first terminal T11 and the second terminal T12 of transistor T1 can also be distributed along the y-direction on both sides of the first driving terminal T13. As shown in Figure 4, the third terminal T21 and the fourth terminal T22 of transistor T2 can be distributed along the y-direction on both sides of the second driving terminal T23; alternatively, the third terminal T21 and the fourth terminal T22 of transistor T2 can be distributed along the x-direction on both sides of the second driving terminal T23. The distribution directions of the non-driving terminals of transistors T1 and T2 on both sides of the driving terminals can be the same or different. In different cases, the dimensions of the semiconductor device 400 in the xy plane can be further reduced, and when used in the memory array structure of a memory device, the storage density of the memory circuit can be further improved.

[0083] The technical solution of this application combines two transistor layers and one capacitor layer in a vertical space in a semiconductor device. This not only facilitates three-dimensional (3D) process integration but also improves the accuracy and stability of data storage when the semiconductor device is used as a memory unit. Layered stacking of different parts within the memory unit allows for higher space utilization and smaller size of the semiconductor device. Therefore, it enables more stable and reliable data storage with a smaller space or area, improving the reliability of the storage system. Furthermore, the reduced space or area provides more usable space or area for other circuits in the chip, such as logic circuits, which is beneficial for improving the performance of logic circuits. The layered structure further enhances storage performance. Furthermore, placing the capacitor layer above the two transistor layers reduces the space restriction imposed by the transistor layers on the capacitor layer, allowing the capacitors in the capacitor layer to expand in the stacking and horizontal directions, thereby maximizing the capacitance value and further improving the storage performance of the storage system. This solution achieves high process integration of the semiconductor device, enabling denser stacking, which is beneficial for better implementation of storage and computing functions. The above semiconductor devices can be applied in in-memory computing architectures to store weight data. That is, the above data can include weight data, which can be used for in-memory computing or near-memory computing. By using the storage circuits / memory constructed from the above semiconductor devices, the accuracy and stability of weight data storage in the storage unit can be improved, thereby enhancing the reliability of the in-memory computing architecture in its application.

[0084] In this application embodiment, "layer" can refer to a spatial region containing multiple elements, features, or structures distributed along one or more directions. These directions can be any one or more directions parallel to the substrate, such as the x-direction, y-direction, or both x and y-directions. This application embodiment does not limit the distribution method; for example, elements, features, or structures can be distributed continuously, regularly, or irregularly at intervals. This application embodiment does not limit the height of the spatial region, which can have different heights based on the dimensions of the included elements, features, or structures. Layers may partially overlap, rather than being multiple spatially independent regions.

[0085] This application does not limit the electrical connection method of the first driving terminal T13 of transistor T1, the third terminal T21 of transistor T2, and the electrode structure E1 of capacitor C. For example, they can be electrically connected through at least one conductive node and / or at least one through-hole conductive structure. The electrical connection structures CO1, CO2, and CO3 marked by dashed boxes in Figure 4 illustrate the electrical connection relationship between them, but they do not represent the actual shape of their electrical connection structure.

[0086] In some embodiments, as shown in FIG4, the semiconductor device 400 may further include: interconnect node SN1, electrical connection structure CO1, interconnect node SN2, and electrical connection structure CO2. At least a portion of interconnect node SN1 is exposed to transistor layer 410, and electrical connection structure CO1 is formed between the first driving terminal T13 of transistor T1 and interconnect node SN1; at least a portion of interconnect node SN2 is exposed to transistor layer 420, and electrical connection structure CO2 is formed between the third terminal T21 of transistor T2 and interconnect node SN2. This application does not limit the form of electrical connection structure CO1, which may include one or more conductive via structures and / or one or more conductive nodes; similarly, this application does not limit the form of electrical connection structure CO2, which may include one or more conductive via structures and / or one or more conductive nodes. Furthermore, the form of electrical connection structure CO2 may be the same as or different from that of electrical connection structure CO1. For example, the number and size of conductive vias included in electrical connection structure CO2 and electrical connection structure CO1 may be the same as or different, and the number and size of conductive nodes included in electrical connection structure CO2 and electrical connection structure CO1 may be the same as or different.

[0087] A conductive node is, for example, an electrical connection structure formed by a conductive material in an interlayer dielectric layer. The embodiments of this application do not limit the material and shape of the conductive node, as long as it is a conductive structure that can be used to realize interlayer electrical connection.

[0088] In some embodiments of this application, the interconnect node is, for example, a conductive node corresponding to a memory node (SN). The interconnect node is used to realize the electrical connection between the first driving terminal T13 of transistor T1, the third terminal T21 of transistor T2, and the electrode structure E1 of capacitor C corresponding to the memory node. By setting the interconnect node, the electrical connection structure of the first driving terminal T13 of transistor T1, the third terminal T21 of transistor T2, and the electrode structure E1 of capacitor C can be simplified, and the manufacturing process can be simplified. The conductive structure CE1 can be used as the lead electrode of the third terminal T21 of transistor T2. The electrical connection structure CO2 can be formed between the conductive structure CE1 and the interconnect node SN2 to electrically connect the third terminal T21 of transistor T2 and the electrode structure E1 of capacitor C. The electrical connection structure CO3 can be formed between the conductive structure CE1 and the interconnect node SN1 to electrically connect the third terminal T21 of transistor T2 and the first driving terminal T13 of transistor T1.

[0089] In this implementation, the interconnect nodes facilitate the extraction of electrical connections within the device structure, simplify the manufacturing process, and enable reliable connections between the device structures of transistor layer 410, transistor layer 420, and capacitor layer 430, thereby facilitating the realization of semiconductor device processes.

[0090] In some implementations, transistor T1 may include a silicon-based transistor or an oxide semiconductor transistor. Transistor T2 may include an oxide semiconductor transistor.

[0091] The channel material of a silicon-based transistor can be silicon (Si). For example, the silicon-based transistor can include a metal-oxide-semiconductor field-effect transistor (MOSFET) or a bipolar junction transistor (BJT). MOSFETs can include planar transistors, fin field-effect transistors (FinFETs), tri-gate transistors, or gate-all-around (GAA) transistors. Additionally, MOSFETs can include N-type MOSFETs (NMOS) or P-type MOSFETs (PMOS). Silicon-based transistors have mature manufacturing processes, excellent and stable semiconductor performance, and high tunability, making them suitable for applications with high performance requirements.

[0092] The channel material of an oxide semiconductor transistor can be based on an oxide semiconductor material, such as a wide-bandgap oxide semiconductor material, for example, an oxide semiconductor with a bandgap greater than or equal to 1.65 eV. For example, the oxide semiconductor can include indium gallium zinc oxide (IGZO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin gallium zinc oxide (ITGZO), etc. Using this oxide semiconductor as a channel material can result in extremely low leakage current, leading to long data retention times in the transistor. Furthermore, this oxide semiconductor material has high compatibility with back-end circuit integration processes, which is beneficial for further optimizing the fabrication process of semiconductor devices.

[0093] In some embodiments of this application, transistor T1 may include a silicon-based transistor and transistor T2 may include a semiconductor oxide transistor (or an oxide semiconductor transistor). Transistor T1 can be located at the bottom layer of the semiconductor device. Using a silicon-based transistor allows for lower operating voltage and power consumption, and also helps reduce its area, thus facilitating the miniaturization of semiconductor devices and increasing storage density. Furthermore, using silicon as the bottom layer of the semiconductor device is compatible with the fabrication of transistor T1 and peripheral circuits, simplifying the process flow, reducing manufacturing complexity and costs, and improving the overall stability of the semiconductor device and system. Moreover, as a read transistor, transistor T1, being a silicon-based transistor, also offers superior performance and higher read accuracy, enabling accurate and rapid reading of data stored in the memory cell. Further, transistor T2, as a write transistor, uses a semiconductor oxide transistor, allowing for longer retention of data written to the transistor. This semiconductor oxide transistor T2 is fabricated after transistor T1, exhibiting high process compatibility and enabling better three-dimensional integration with transistor T1. The device structure in this application embodiment can be well applied to various fields such as neural network computing and in-memory computing, giving it many advantages such as high bandwidth and high performance.

[0094] The first transistor layer is described below with reference to the accompanying drawings.

[0095] Figure 5 shows a schematic diagram of a transistor layer according to an exemplary embodiment of this application. The transistor layer 500 may include the transistor T1 in the above embodiments. For ease of illustration, the embodiments of this application and the related embodiments below show a three-dimensional schematic diagram of the transistor layer or semiconductor device, and show the directions x, y, and z in three-dimensional space, wherein the multilayer structure in the transistor layer or semiconductor device may be arranged along the z direction, and a partial cross-section of the transistor layer 500 is shown in Figure 5.

[0096] As shown in Figure 5, the transistor layer 500 may include a substrate 510, and the first terminal T11 and the second terminal T12 of the transistor T1 may be formed in the substrate 510, and the first driving terminal T13 of the transistor T1 is formed on the substrate 510. Optionally, the material of the substrate 510 may be silicon-based, and may include a P-type substrate or an N-type substrate, and the transistor T1 may be a silicon-based transistor.

[0097] In some embodiments, the first terminal T11 and the second terminal T12 can be manufactured using doping processes or epitaxial technologies, etc., and this application is not limited thereto. This application does not limit the types of the first and second terminals; for example, they may include doping with group V or group III elements. Optionally, the first and second terminals may include materials such as silicon germanium or silicon germanide (SiGe), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), etc., thereby having higher carrier mobility to improve the performance of transistor T1. For example, the first and second terminals can generate stress on the channel, which can change the band structure of the channel, reduce carrier scattering, and thus improve the carrier mobility of the channel. Optionally, a lightly doped drain (LDD) technique can be applied between the first terminal T11 and / or the second terminal T12 and the channel CH1 to form a lightly doped region, thereby suppressing the short-channel effect of the transistor and reducing the hot carrier effect, further improving the performance of transistor T1. This application does not limit the material of the first driving terminal T13, and may include conductive materials with low resistivity, such as metals or metal compounds. In some examples, the material of the first driving terminal T13 may include, but is not limited to, one or more of the following: titanium nitride (TiN), tantalum (Ta), tungsten (W), aluminum (Al), or tantalum nitride (TaN), polycrystalline silicon, etc.

[0098] This application does not limit the material of dielectric layer D1. The material of dielectric layer D1 may include gate oxide. In some examples, the material of dielectric layer D1 may include silicon oxide (SiO), formed by oxidizing the substrate material. In other examples, dielectric layer D1 may include a high-k dielectric material, also known as a high-k material or HK material, which may be deposited on top of substrate 510. As an example, HK material may include, but is not limited to, one or more of the following: hafnium oxide (HfO), aluminum oxide (AlO), hafnium zirconium oxide (HfZrO), lutetium oxide (LuO), tantalum oxide (TaO), lanthanum oxide (LaO), or zirconium oxide (ZrO). In the embodiments of this application, the chemical formula of the compound material is omitted with subscripts, and the ratio of each element in the compound material can be the ratio of the compound material in a stable state. As an example, the hafnium oxide mentioned above may include hafnium dioxide, whose chemical formula is HfO2.

[0099] In the case where transistor layer 500 includes a plurality of transistors T1, the substrates of the plurality of transistors T1 may be isolated from each other by an isolation structure 520, which may include an insulating material. In some examples, the isolation structure 520 may include a shallow trench isolation (STI) structure formed between the transistors T1.

[0100] Referring again to Figure 5, the transistor layer 500 may further include electrical connection structures S11 to S13, which are respectively connected to the first terminal T11, the second terminal T12, and the first driving terminal T13 of the transistor T1, and are used to realize the electrical connection lead-out of the first terminal T11, the second terminal T12, and the first driving terminal T13. When the transistor layer 500 includes multiple transistors T1, these multiple transistors T1 can be arranged in an array. The first terminals T11 of the multiple transistors T1 arranged along one direction (e.g., either the x-direction or the y-direction) can be connected to a trace (which can be referred to as the first trace for distinction) through the corresponding electrical connection structure S11. This first trace can be used as the input line IN of the memory cell. i and output line OUT j One of them; the second terminal T12 of a plurality of transistors T1 arranged in another direction (e.g., the other of the x and y directions) can be connected to a trace (which can be referred to as the second trace for distinction) through a corresponding electrical connection structure S12. This second trace can be used as the input line IN of the memory cell. i and output line OUT j The other one. The first drive terminal T13 can be led out to the interconnect node SN1 through the electrical connection structure S13, which can be directly led out to the interconnect node SN1 or can be further connected to the interconnect node SN1 through other electrical connection structures. In some examples, the electrical connection structures S11 to S13 may include conductive via structures formed in at least one interlayer dielectric layer. For example, electrical connection structures S11 and S12 may include conductive via structures formed in the interlayer dielectric layers 530 and 540 shown in FIG. 5, and electrical connection structure S13 may include conductive via structures formed in the interlayer dielectric layer 540 shown in FIG. 5. The first drive terminal T13 is formed in the interlayer dielectric layer 530.

[0101] Figures 6A to 6C illustrate schematic diagrams of another transistor layer according to an exemplary embodiment of this application. The transistor layer 600 may include transistor T1. Figures 6A to 6C may be schematic cross-sectional views at different angles, and Figure 6C may be a schematic cross-sectional view of Figure 6A along the A-A' direction.

[0102] As shown in Figures 6A to 6C, the transistor layer 600 may include a device layer 610 and a connection layer 620. Devices, such as one or more transistors T1, may be formed within the device layer 610. The device layer 610 may include a substrate 611 and at least one interlayer dielectric layer, for example, an interlayer dielectric layer 612. Similar to the embodiment described in Figure 5, a first terminal T11 and a second terminal T12 of the transistor T1 may be formed within the substrate 611, and a first driving terminal T13 of the transistor T1 may be formed in the interlayer dielectric layer 612 on the substrate 611. The connection layer 620 may be formed on the device layer 610 and includes multiple interlayer dielectric layers, such as interlayer dielectric layers 622 and 624. Interconnect node SN1 and trace L1 (also referred to as the first trace) extending along one of the first and second directions (taking the x direction as an example in FIG. 6A) are formed in the interlayer dielectric layer 624. Interconnect node SN1 is electrically connected to the first driving terminal T13 of transistor T1, and trace L1 is electrically connected to the first terminal T11 of transistor T1. Trace L2 (also referred to as the second trace) extending along the other of the first and second directions (taking the y direction as an example in FIG. 6B) are formed in the interlayer dielectric layer 622. Trace L2 is electrically connected to the second terminal T12 of transistor T1.

[0103] This application does not limit the electrical connection method between interconnect node SN1 and the first driving terminal T13 of transistor T1. For example, it may include one or more via structures. Optionally, the via structures are connected through conductive structures within the interlayer dielectric layer. Similarly, this application does not limit the electrical connection method between trace L1 and the first terminal T11 of transistor T1. For example, it may include one or more via structures. Optionally, the via structures are connected through conductive structures within the interlayer dielectric layer. Similarly, this application does not limit the electrical connection method between trace L2 and the second terminal T12 of transistor T1. For example, it may include one or more via structures. Optionally, the via structures are connected through conductive structures within the interlayer dielectric layer.

[0104] Optionally, the interlayer dielectric layer 624 is located on the side of the interlayer dielectric layer 622 away from the substrate 611, and the interlayer dielectric layer 624 and the interlayer dielectric layer 622 may or may not include an interlayer dielectric layer. For example, the interlayer dielectric layer 623 is included between the interlayer dielectric layer 624 and the interlayer dielectric layer 622. Optionally, the interlayer dielectric layer 622 and the interlayer dielectric layer 612 may or may not include an interlayer dielectric layer. For example, the interlayer dielectric layer 612 and the interlayer dielectric layer 622 include an interlayer dielectric layer 621.

[0105] For the terminals T11 to T13 of transistor T1, and the related technical solutions for the electrical connection structures S11 to S13 for the electrical connection leads of the terminals, please refer to the relevant description in the embodiment shown in Figure 5 above.

[0106] In the examples shown in Figures 6A to 6C, traces L1 and L2 extend in different directions. For example, trace L1 extends along the x-direction, while trace L2 may extend along the y-direction. In other embodiments, trace L1 may extend along the y-direction, while trace L2 may extend along the x-direction. This application does not limit the specific extension direction of the traces. By intersecting the extension directions of the traces, interference can be reduced, and the storage density of the storage circuit containing the storage cell can be increased or the area of ​​the storage circuit can be reduced.

[0107] In the examples shown in Figures 6A to 6C, trace L1 can be connected to the first terminal T11 of transistor T1, and trace L2 can be connected to the second terminal T12 of transistor T1. In some other embodiments, trace L1 can be connected to the second terminal T12 of transistor T1, and trace L2 can be connected to the first terminal T11 of transistor T1.

[0108] In this embodiment, traces L1 and L2 can serve as the input and output lines of the memory cell, respectively. The descriptions of the input and output lines can be found in the embodiments described above. Optionally, the routing directions of traces L1 and L2 can intersect each other; for example, the routing directions can be perpendicular. This intersecting routing layout can reduce interference and improve the storage density of the memory circuit containing the memory cell, or reduce the area of ​​the memory circuit.

[0109] In this embodiment, the trace L1 and the interconnect node SN1 are disposed in the same interlayer dielectric layer 624, which helps to reduce the height of the transistor layer 600 and facilitates the miniaturization of semiconductor devices.

[0110] This application does not limit the number of interlayer dielectric layers included in transistor layer 600. In addition to interlayer dielectric layers 622 and 624 used for wiring layers, transistor layer 600 may also include more interlayer dielectric layers for redistributing electrical connection locations, such as redistributing the electrical connection locations of any one or more of the first terminal T11, second terminal T12, and first drive terminal T13 of transistor T1. For example, transistor layer 600 includes interlayer dielectric layer 621 located above interlayer dielectric layer 612; or, for instance, transistor layer 600 includes interlayer dielectric layer 623 located above interlayer dielectric layer 622. Thus, interlayer dielectric layers can be used to redistribute the electrical connection locations of one or more terminals of transistor T1 in connection layer 620, facilitating connections with transistor T2 and capacitor C, and improving the connection reliability between wiring or interconnect nodes and corresponding terminals of transistor T1. This approach helps reduce the area of ​​memory cells, improving the miniaturization of semiconductor devices while also ensuring reliable manufacturing processes, thereby enhancing the reliability and stability of semiconductor devices.

[0111] The second transistor layer is described below with reference to the accompanying drawings.

[0112] Figure 7 shows a schematic diagram of yet another transistor layer according to an exemplary embodiment of this application.

[0113] As shown in Figure 7, transistor layer 700 can be located above transistor layers 500 or 600. Transistor layer 700 may include an oxide structure O1, conductive structures CE1, CE2, and CE3, and a dielectric layer D2. Conductive structure CE1 is connected to a first portion of oxide structure O1, forming the third terminal T21 of transistor T2 in the first portion. Conductive structure CE2 is connected to a second portion of oxide structure O1, forming the fourth terminal T22 of transistor T2 in the second portion. A second channel CH2 is formed between the third terminal T21 and the fourth terminal T22 within oxide structure O1. Conductive structure CE3 is formed on the second channel CH2 and serves as the second driving terminal T23 of transistor T2, and is separated from oxide structure O1 by dielectric layer D2. The relevant technical solutions for transistor T2 can be found in the descriptions of the embodiments above, and will not be elaborated further here.

[0114] This application does not limit the materials of conductive structures CE1 to CE3, and the materials of conductive structures CE1 to CE3 may be the same or different. For example, conductive structure CE1 and conductive structure CE2 may use the same material; conductive structure CE3 may use the same or different material as conductive structures CE1 and CE2. In some embodiments of this application, conductive structure CE1, conductive structure CE2, or conductive structure CE3 may use conductive materials with low resistivity, such as, but not limited to, one or more of the following materials: titanium nitride (TiN), tungsten (W), copper (Cu), tantalum nitride (TaN), etc.

[0115] This application does not limit the material of the dielectric layer D2. For example, the dielectric layer D2 can be one or more materials selected from, but not limited to, silicon oxide, silicon nitride, silicon oxide oxynitride, hafnium oxide, and aluminum oxide. The dielectric layer D2 can use a dielectric material with a high dielectric constant (high-k), such as, but not limited to, one or more of the following: hafnium oxide (HfO), aluminum oxide (AlO), zirconium oxide (ZrO), or silicon oxynitride hafnium (HfSiON), to reduce the leakage current of transistor T2 and improve the charge retention time of the storage node. The above materials can also be doped as needed, for example, doped with lanthanide metals such as hafnium oxide.

[0116] Optionally, as shown in Figure 7, conductive structures CE1 and CE2 are formed on different sides of the oxide structure O1. For example, conductive structure CE3 is formed on the side of oxide structure O1 facing transistor layer 500 or 600, while conductive structures CE1 and CE2 are formed on the other side of oxide structure O1 away from transistor layer 500 or 600. During the manufacturing process of transistor T2, conductive structure CE3 can be formed first, followed by oxide structure O1 on top of conductive structure CE3, thereby realizing a bottom-gate structure or a back-gate structure for transistor T2. For transistor T2 with this structure, conductive structure CE3 is manufactured before oxide structure O1, and the manufacturing process of conductive structure CE3 will not affect oxide structure O1, thus avoiding the impact of etching processes on the channel, resulting in better stability for transistor T2. Therefore, the memory cell using the above transistor T2 structure has a simple manufacturing process, the gate and channel are less affected by subsequent processes, and the device has high stability, which is beneficial for optimizing the storage performance of the memory cell. When this memory cell is used for in-memory computation, it helps to provide stable computation results.

[0117] Optionally, as shown in FIG7, transistor layer 700 may include a device layer, which may include at least one interlayer dielectric layer, such as interlayer dielectric layer 710 shown in FIG7, which may be formed on transistor layer 500 / 600. Interlayer dielectric layer 710 may have interconnect node SN3 and conductive structure CE3 formed therein, wherein interconnect node SN3 penetrates interlayer dielectric layer 710 and electrically connects interconnect node SN1 and conductive structure CE1. Conductive structure CE3 is formed at a certain depth of interlayer dielectric layer 710 and is electrically isolated from transistor layer 500 / 600 through interlayer dielectric layer 710. Interlayer dielectric layer 710 may electrically isolate conductive structure CE3 from devices and / or traces in transistor layer 500 / 600, for example, electrically isolate conductive structure CE3 from transistor T1 in transistor layer 500 / 600. The interlayer dielectric layer 710 can electrically isolate the oxide structure O1 from the transistor layers 500 / 600. The conductive structure CE3 is formed at a certain depth of the interlayer dielectric layer 710, thereby eliminating the need to set an interlayer dielectric layer for the conductive structure CE3 above the transistor layers 500 / 600. This helps to reduce the number of interlayer dielectric layers in the transistor layer 700, thereby reducing the space occupied by the transistor layer 700 in the z-direction, such as the height space, and making the structure of the transistor layer 700 more miniaturized.

[0118] In some embodiments, transistor layer 700 may include a plurality of transistors T2, the conductive structure CE3 of which may be integrally formed as a trace extending in interlayer dielectric layer 710 along one of a third direction and a fourth direction (e.g., extending along the x-direction). (For distinction, this may be referred to as the third trace, and in subsequent figures, it may also be labeled L3). The portion of the trace formed on the channel CH2 of transistor T2 may be used for the conductive structure CE3. Compared to the case where the conductive structures and traces of the plurality of transistors T2 are formed separately, integrally forming the trace with the conductive structure reduces the number of process steps, thereby greatly simplifying the process flow of transistor layer 700, and reducing the space occupied by the trace structure in transistor layer 700, which is beneficial for further miniaturizing the structure of transistor layer 700.

[0119] In some embodiments, the dielectric layer D2 of the plurality of transistors T2 may be integrally formed on the interlayer dielectric layer 710, and the conductive structure CE1 of the plurality of transistors T2 may be exposed on the dielectric layer D2. For example, the integrally formed dielectric layer D2 of the plurality of transistors T2 may cover the traces formed by the conductive structure CE3. The conductive structure CE1 is exposed on the dielectric layer D2 and may pass through the dielectric layer D2 to connect to the underlying electrical connection structure, such as to the interconnect node SN1. The integral formation of the dielectric layer D2 of the plurality of transistors T2 can more reliably isolate the oxide structure O1 from the portion of the traces that does not form the conductive structure CE3, prevent undesirable short circuits between the oxide structure O1 and the traces, and improve the reliability of the device.

[0120] Referring again to Figure 7, in the transistor layer 700, the conductive structure CE1 may include a first portion CE11 and a second portion CE12. The first portion CE11 is formed on the first portion of the oxide structure O1, and the second portion CE12 penetrates the dielectric layer D2 and connects to the interconnect node SN3. The first portion CE11 can be used to form a third terminal T21 in the oxide structure O1, and the second portion CE12 can be directly connected to the interconnect node SN3, simplifying the connection between the conductive structure CE1 and the memory node. Furthermore, the second portion CE12 can be used to increase the connection area of ​​the conductive structure CE1, facilitating its extraction. Thus, the conductive structure CE1 can reliably and simply connect the third terminal T21 of transistor T2 (corresponding to the first portion of the oxide structure O1) to the interconnect node SN3 and / or other structures (e.g., electrical connection structures for connecting to capacitors). This approach further simplifies the semiconductor device manufacturing process.

[0121] Optionally, the conductive structure CE2 of the multiple transistors T2 can be exposed to the dielectric layer D2. Both conductive structures CE1 and CE2 are exposed to the dielectric layer D2 and can be formed simultaneously using the same process, thereby simplifying the manufacturing process of conductive structures CE1 and CE2.

[0122] Optionally, the conductive structure CE2 may include two parts: a first part CE21 formed on the second part of the oxide structure O1, and a second part CE22 that can penetrate the dielectric layer D2 and contact the interlayer dielectric layer 710, or the second part CE22 can be formed on the dielectric layer D2. The first part CE21 of the conductive structure CE2 can be used to form a fourth terminal T22 in the oxide structure O1, and the second part CE22 of the conductive structure CE2 can be used to increase the connection area of ​​the conductive structure CE2 for easier lead-out.

[0123] In some embodiments, the work function of the conductive structure CE3 can be matched to that of the oxide structure O1, which is more effective for threshold voltage adjustment of transistor T2 and can prevent performance degradation of transistor T2. In some examples, the material of the conductive structure CE3 may include, but is not limited to, one or more of the following materials: titanium nitride (TiN), tungsten (W), or tantalum nitride (TaN). In some embodiments, one or more of the conductive structures CE1, CE2, and CE3 may be a multilayer structure formed of more than one material, such as a double-layer structure. For example, it may include a first conductive layer with a work function matched to that of the oxide structure O1 and a second conductive layer with lower resistivity. The material of the first layer includes, but is not limited to, one or more of the following materials: titanium nitride (TiN), tungsten (W), tantalum (Ta), or tantalum nitride (TaN). The material of the second layer includes, but is not limited to, one or more of the following materials: copper (Cu), silver (Ag), gold (Au), aluminum (Al), or alloys containing the above elements.

[0124] For example, as shown in Figure 7, the conductive structure CE3 may include substructures CE31 and CE32, wherein substructure CE31 is located between the oxide structure O1 and substructure CE32. Substructures CE31 and CE32 of multiple transistors T2 can be integrally formed as a trace, or substructures CE32 of multiple transistors T2 can be integrally formed as a trace. Optionally, the work function of substructure CE31 can be matched to the oxide structure O1, facilitating the regulation of the threshold voltage of transistor T2 to the target threshold voltage and preventing performance degradation of transistor T2. In some examples, the material of substructure CE31 may include, but is not limited to, one or more of the following materials: titanium nitride (TiN), tungsten (W), tantalum (Ta), or tantalum nitride (TaN). Substructure CE32 can be a metal material or a metal compound material with low resistivity, which is beneficial for reducing the resistance of conductive structure CE3 and facilitating the formation of low-resistance traces. In some examples, the material of the substructure CE32 may include, for example, copper (Cu), silver (Ag), gold (Au), aluminum (Al), or a metal compound containing the above elements. In this embodiment, the conductive structure CE3 includes a substructure CE31 that matches the oxide structure O1 and a substructure CE32 with low resistivity, which can balance the performance of transistor T2 and the wiring requirements for connecting multiple transistors T2.

[0125] According to some embodiments, the interconnect node SN3 may include the same material / layer structure as the conductive structure CE3. For example, if the conductive structure CE3 includes two substructures, the interconnect node SN3 may also include two substructures, wherein the material of substructure SN31 may be the same as the material of substructure CE31 in the conductive structure CE3, and the material of substructure SN32 may be the same as the material of substructure CE32 in the conductive structure CE3. The interconnect node SN3 can be formed using the same process / process steps as the conductive structure CE3, thereby simplifying the process of forming the conductive structure in the interlayer dielectric layer 710.

[0126] In some embodiments, as shown in FIG7, transistor layer 700 may include a protective layer 720, which may be formed on at least one interlayer dielectric layer, such as on interlayer dielectric layer 710, with conductive structures CE1 and CE2 exposed to the protective layer 720. The protective layer 720 can reduce the probability of material degradation of oxide structure O1, reduce the corrosive effects of etching solution on oxide structure O1 in subsequent processes, and improve the stability and reliability of oxide structure O1. In some examples, the material of the protective layer 720 may include, but is not limited to, silicon nitride (SiN) or silicon oxide (SiO), etc. The protective layer 720 has a low or no hydrogen content, which can reduce the influence of hydrogen on the properties of oxide structure O1. Conductive structures CE1 and CE2 may be formed in the protective layer 720 and at least exposed to the protective layer 720. The protective layer 720 can provide better protection for the oxide structure O1 of transistor T2 and can expose conductive structures CE1 and CE2 without affecting the connection between conductive structures CE1 and CE2 and other structures in the layers.

[0127] Figures 8A and 8B illustrate schematic diagrams of yet another transistor layer according to an exemplary embodiment of this application. The transistor layer 800 may include transistor T2. Figure 8B may be a cross-sectional schematic diagram of Figure 8A along the B-B' direction.

[0128] Transistor layer 800 may include device layer 810 and interconnect layer 820. Device layer 810 may include at least one interlayer dielectric layer, for example, interlayer dielectric layer 811. Optionally, device layer 810 may also include more interlayer dielectric layers, which is not limited thereto. In some embodiments, device layer 810 may also include protective layer 812. As shown in Figures 8A and 8B, the conductive structure CE3 of transistor T2 may be formed in interlayer dielectric layer 811, and conductive structures CE1 and CE2 may be formed in protective layer 812. A dielectric layer D2 may be formed between interlayer dielectric layer 811 and protective layer 812. The relevant technical solutions for interlayer dielectric layer 811 and protective layer 812 can be found in the description of interlayer dielectric layer 710 and protective layer 720 in the above embodiments. The relevant technical solutions for each structure in transistor T2 can also be found in the description of the above embodiments.

[0129] In some embodiments, the interconnect layer 820 may include at least one interlayer dielectric layer, such as an interlayer dielectric layer 821, which is formed on the device layer 810 where transistor T2 is located. Interconnect node SN2 and a trace L4 (also called a fourth trace) extending along one of a third and a fourth direction (e.g., extending along the y-direction in FIG. 8A) are formed in the interlayer dielectric layer 821. Interconnect node SN2 is electrically connected to the third terminal T21 of transistor T2, and trace L4 is electrically connected to the fourth terminal T22 of transistor T2. For example, interconnect node SN2 extends through the interlayer dielectric layer 821 and is electrically connected to the third terminal T21 of transistor T2, or is electrically connected to the third terminal T21 of transistor T2 through a conductive via structure; trace L4 is formed at a portion of the depth of the interlayer dielectric layer 821 and is connected to the fourth terminal T22 of transistor T2 through a conductive via structure. For example, in the example shown in Figure 8B, interconnect node SN2 penetrates the interlayer dielectric layer 821 or is connected to the conductive structure CE1 through conductive via structure 822, thereby electrically connecting to the third terminal T21 of transistor T2; trace L4 is connected to the conductive structure CE2 through conductive via structure 823, thereby connecting to the fourth terminal T22 of transistor T2. The fact that trace L4 or interconnect node SN2 is formed at a partial depth of the interlayer dielectric layer 821 and connected to the terminal of transistor T2 through conductive via structure prevents undesirable connections to other terminals of transistor T2. Connecting interconnect node SN2 through the interlayer dielectric layer 821 to the terminal of transistor T2 increases the connection area of ​​interconnect node SN2 and reduces process complexity. Connecting interconnect node SN2 to the terminal of transistor T2 through conductive via structure improves the connection accuracy to the terminal of transistor T2 and can be formed using the same process / steps as trace L4, thereby simplifying the process of forming conductive structures in the interlayer dielectric layer 821.

[0130] In some embodiments, trace L4 and interconnect node SN2 can be formed using the same process / steps. The materials of trace L4 and interconnect node SN2 can be the same. Alternatively, in some alternative embodiments, trace L4 and interconnect node SN2 can also be formed using different processes / steps. The materials of trace L4 and interconnect node SN2 can be different. Optionally, the materials of trace L4 and / or interconnect node SN2 can refer to the descriptions of conductive structures CE1, CE2, or conductive structure CE3 above, and may include one or more layers of structure.

[0131] Optionally, trace L4 can be used as a control line for the memory cell, such as control line CON2. j This is used to control the data stored in the memory cell. The conductive structure CE3 of multiple transistors T2, and the integrally formed trace L3, can serve as the control line for the memory cell, such as control line CON1. iThis is used to control the state of transistor T2, such as whether it is on or off. In some examples, the direction of trace L3 can intersect the direction of trace L4; for example, the two trace directions can be perpendicular to each other. This application does not limit the specific extension direction of the traces. By setting the intersection of the trace extension directions, interference can be reduced, and the storage density of the storage circuit containing the memory cell can be increased or the storage circuit area can be reduced. Optionally, the third direction can be the same as one of the first and second directions, and the fourth direction can be the same as the other of the first and second directions.

[0132] Figure 9 shows a schematic diagram of yet another transistor layer according to an exemplary embodiment of this application. The transistor layer 900 may include transistor T2.

[0133] As shown in Figure 9, transistor layer 900 can be located above transistor layers 500 or 600. Transistor layer 900 may include an oxide structure O1, conductive structures CE1 and CE2, and a dielectric layer D2 formed on the oxide structure O1. The dielectric layer D2 is located between conductive structures CE1 and CE2. Conductive structures CE1 and CE2 are in contact with a first portion and a second portion of the oxide structure O1, respectively. The first and second portions are used to form the third terminal T21 and the fourth terminal T22 of transistor T2, respectively. The portion between the first and second portions of the oxide structure O1 is used to form a channel CH2. Conductive structure CE3 includes a portion formed on the channel CH2 and is used for the second driving terminal T23 of transistor T2. It has a dielectric layer D2 between it and the oxide structure O1. Conductive structures CE1, CE2, and CE3 can be located on the same side of the oxide structure O1, for example, on the side away from the transistor layer where transistor T1 is located.

[0134] Optionally, as shown in Figure 9, the transistor T2 in this embodiment may have a top-gate structure. The conductive structure CE3 can be used as the gate structure of the transistor T2. During the manufacturing process of the transistor T2, an oxide structure O1 can be formed first, and then the conductive structure CE3 can be formed on top of the oxide structure O1. The conductive structures CE1 and CE2 can be located on the same side of the oxide structure O1 as the conductive structure CE3. In the manufacturing process of the transistor T2, the conductive structures CE1 and CE2 can be formed first, and then the conductive structure CE3 can be formed. This approach reduces the manufacturing difficulty of the transistor T2, which is beneficial for reducing the manufacturing cost and yield of the transistor layer.

[0135] Optionally, the transistor layer 900 may include at least one interlayer dielectric layer, such as an interlayer dielectric layer 911, in which transistor T2 may be formed to isolate unwanted electrical connections between different transistors T2. Transistor T2 may also be formed in more interlayer dielectric layers; this application is not limited in this regard. One or more layers containing transistor T2 can be understood as the device layer of transistor layer 900. This device layer includes at least one interlayer dielectric layer; optionally, the at least one interlayer dielectric layer includes interlayer dielectric layer 911, in which conductive structures CE1, CE2, and CE3 are formed. This facilitates a reduction in the height of the semiconductor device and contributes to the miniaturization of semiconductor devices. Optionally, conductive structures CE1 and CE2 are formed in the same interlayer dielectric layer, and conductive structure CE3 is formed in another interlayer dielectric layer.

[0136] Optionally, the semiconductor device may further include an interlayer dielectric layer LA1, as shown in FIG. 9, formed between the interlayer dielectric layer 911 (or oxide structure O1) and the topmost interlayer dielectric layer of transistor layers 500 / 600. The interlayer dielectric layer LA1 may be part of transistor layers 420 / 900, or part of transistor layers 410 / 500 / 600, or independent of transistor layers 420 / 900 and 410 / 500 / 600. The provision of the interlayer dielectric layer LA1 can reduce the probability of short circuits between the oxide structure O1 in transistor T2 and conductive structures (e.g., interconnect node SN1 or trace L1) in transistor layers 500 / 600. In some embodiments, transistor layer 900 may include a plurality of transistors T2, the conductive structure CE3 of which may be integrally formed as a trace L3 extending in the interlayer dielectric layer (e.g., interlayer dielectric layer 911) along one of the third and fourth directions (e.g., extending along the x-direction). The L3 trace is formed in the device layer, which can simplify the semiconductor device’s need for other layers for setting the trace, which is beneficial to reducing the height of the semiconductor device and contributing to the miniaturization of the semiconductor device.

[0137] Optionally, the dielectric layer D2 can also be used to isolate the conductive structure CE3 from the conductive structures CE1 and CE2 to prevent unwanted short circuits between different conductive structures.

[0138] Optionally, as shown in Figure 9, to facilitate the interconnection of conductive structures CE1 and CE2 with other structures, the transistor layer 900 may further include electrical connection structures S21 and S22, which are respectively connected to conductive structures CE1 and CE2. Conductive structures CE1 and CE2 can be connected to other conductive structures, such as traces or interconnect structures, located above conductive structures CE1 and CE2 through the corresponding electrical connection structures S21 and S22.

[0139] In some embodiments, the electrical connection structure S21 may be formed within at least one interlayer dielectric layer. For example, the electrical connection structure S21 may be formed within interlayer dielectric layers 911 and LA1. As another example, the transistor layer 900 may further include an interlayer dielectric layer 921 formed above the interlayer dielectric layer 911, and the electrical connection structure S21 may be formed within interlayer dielectric layers 911, 921, and LA1. The electrical connection structure S21 is connected to the conductive structure CE1. Optionally, the electrical connection structure S21 may penetrate the transistor layer 900, connecting the third terminal T21 of transistor T2 to a conductive structure (e.g., interconnect node SN1) below the transistor layer 900 and a conductive structure (e.g., interconnect node SN2 or the first electrode structure of a capacitor) above the transistor layer 900. This can improve connection reliability and reduce the process complexity of forming the memory node, which can help reduce manufacturing costs and improve manufacturing yield. Optionally, the electrical connection structure S21 can connect the third terminal T21 of transistor T2 to a conductive structure (e.g., interconnect node SN1) below transistor layer 900 and a conductive structure (e.g., interconnect node SN2 or the first electrode structure of a capacitor) above transistor layer 900 through other electrical connection structures.

[0140] In some embodiments, the electrical connection structure S21 may be in contact with the side of the conductive structure CE1. The connection of the electrical connection structure S21 to the conductive structure CE1 on the side simplifies the electrical connection lead-out structure of the third terminal T21 of the transistor T2, allowing the electrical connection structure S21 to be formed through the transistor layer 900. This simplifies the manufacturing process, reduces the need for other layers for terminal electrical connection leads in the semiconductor device, helps reduce the height of the semiconductor device, and contributes to the miniaturization of semiconductor devices.

[0141] In some embodiments, the electrical connection structure S21 can not only contact and connect with the side of the conductive structure CE1, but also contact and connect with the top of the conductive structure CE1, thereby increasing the contact area between the electrical connection structure S21 and the conductive structure CE1 and improving the connection reliability.

[0142] Optionally, interconnect node SN1 is at least partially exposed on the transistor layer where transistor T1 is located, and the electrical connection structure S21 can be contacted and connected to interconnect node SN1. The contact connection between electrical connection structure S21 and interconnect node SN1 reduces the use of intermediate connection structures and the interlayer dielectric layer containing these intermediate connection structures, simplifies the connection method between the third terminal T21 of transistor T2 and the first driving terminal T13 of transistor T1, and facilitates the reduction of semiconductor device size and simplifies semiconductor device manufacturing processes.

[0143] In some embodiments, the electrical connection structure S22 may be formed within at least one interlayer dielectric layer. For example, the electrical connection structure S22 may be formed at a portion of the depth of the interlayer dielectric layer 911 and connected to the top of the conductive structure CE2; or the electrical connection structure S22 may pass through the interlayer dielectric layer 911 and connect to the side of the conductive structure CE2; or the electrical connection structure S22 may be formed at a portion of the depth of the interlayer dielectric layer 911 and connected to the side of the conductive structure CE2; or the electrical connection structure S22 may include a portion formed at a first depth of the interlayer dielectric layer 911 connected to the top of the conductive structure CE2 and a portion formed at a second depth of the interlayer dielectric layer 911 (including the case of passing through the interlayer dielectric layer 911) connected to the side of the conductive structure CE2. For example, the transistor layer 900 may also include an interlayer dielectric layer 921 formed above the interlayer dielectric layer 911, and the electrical connection structure S22 may also include a portion formed within the interlayer dielectric layer 921.

[0144] Figures 10A, 10B, and 10C illustrate schematic diagrams of yet another transistor layer according to exemplary embodiments of this application. The transistor layer 1000 may include transistor T2 (only a portion of the fourth terminal T22 of transistor T2 is shown in Figures 10A and 10B). Figures 10A to 10C may have more interlayer dielectric layers than Figure 9. Figures 10A and 10B may correspond to cross-sections of the transistor layer 900 shown in Figure 9 taken along the F-F' direction. Figure 10C may correspond to cross-sections of the transistor layer 900 shown in Figure 9 taken along the G-G' direction.

[0145] As shown in Figures 10A to 10C, transistor layer 1000 may include device layer 1010 and interconnect layer 1020. Device layer 1010 may include at least one interlayer dielectric layer, for example, interlayer dielectric layer 1011. Optionally, device layer 1010 may also include more interlayer dielectric layers, and this application is not limited thereto. The relevant technical solutions for interlayer dielectric layer 1011 can be found in the description of interlayer dielectric layer 911 in the above embodiments. The relevant technical solutions for each structure in transistor T2 can also be found in the description of each structure in the above embodiments.

[0146] In some embodiments, the interconnect layer 1020 may include at least one interlayer dielectric layer, such as interlayer dielectric layers 1021 and 1022 shown in the figure, which are formed on the device layer 1010 where transistor T2 is located. Interconnect nodes SN2 may be formed in the interlayer dielectric layer 1022, wherein the interconnect nodes SN2 may be connected to the electrical connection structure S21.

[0147] In some embodiments, the semiconductor device may further include an interlayer dielectric layer LA2, in which a trace L4 extending along one of a third and a fourth direction is formed (as an example, the trace L4 shown in FIG. 10B may extend along the y-direction). This trace L4 is electrically connected to the fourth terminal T22 of transistor T2, for example, by being connected to the electrical connection structure S22 via a conductive node CN1, thereby connecting to the fourth terminal T22 of transistor T2. This trace L2 serves as the control line CON2 of the memory cell. j Interconnect node SN2 is used for the electrical connection between the third terminal T21 of transistor T2 and the first electrode structure of the capacitor in the capacitor layer. In this embodiment, trace L4 and interconnect node SN2 can be located in different interlayer dielectric layers. In other embodiments, trace L4 and interconnect node SN2 can be located in the same interlayer dielectric layer, for example, both in interlayer dielectric layer 1022; or, for example, both in interlayer dielectric layer LA2. Forming trace L4 and interconnect node SN2 in different interlayer dielectric layers can help improve storage density and simplify routing complexity and interference.

[0148] The interlayer dielectric layer LA2 can belong to transistor layers 420 / 900 / 1000, or the interlayer dielectric layer LA2 can belong to capacitor layer 430, or the interlayer dielectric layer LA2 can be independent of transistor layers 420 / 900 / 1000 and capacitor layer 430.

[0149] In some embodiments, the interlayer dielectric layer LA2 is part of the capacitor layer 430, and at least a portion of the capacitor is formed within the interlayer dielectric layer LA2, with the first electrode structure of the capacitor in contact with the interconnect node SN2. For example, at least a portion of the capacitor extends through the interlayer dielectric layer LA2, allowing the first electrode structure E1 to contact the interconnect node SN2, thus achieving an electrical connection. The use of the interlayer dielectric layer LA2 by the capacitor layer 430 can reduce the overall height of the capacitor layer and transistor layer 420 while maintaining the same capacitance value, which is beneficial for reducing the size of the semiconductor device and simplifying the semiconductor device manufacturing process. Alternatively, with the same overall height, more interlayer dielectric layers can be used to increase the height of the capacitor, thereby increasing the capacitance value and further improving the voltage stability and hold time at the storage node.

[0150] In some embodiments, conductive node CN1 and interconnect node SN2 can be formed using the same process / process steps. The materials of conductive node CN1 and interconnect node SN2 can be the same. Alternatively, in some embodiments, conductive node CN1 and interconnect node SN2 can also be formed using different processes / process steps. The materials of conductive node CN1 and interconnect node SN2 can be different.

[0151] The material for oxide structure O1 can be found in the material description for oxide semiconductors in the above embodiments. The material for dielectric layer D2 can be found in the material description for dielectric layer D2 in the above embodiments. The materials for conductive structures CE1, CE2, and CE3 can be found in the material description for conductive structures CE1, CE2, and CE3 in the above embodiments.

[0152] Figure 11 shows a schematic diagram of a capacitor layer according to an exemplary embodiment of this application.

[0153] As shown in Figure 11, capacitor layer 1100 can be located above transistor layers 700 / 800 / 900 / 1000. Transistor layers 700 / 800 / 900 / 1000 may include transistor T2. The technical solution of transistor layers 700 / 800 / 900 / 1000 can be found in the relevant description of the embodiments above, and will not be elaborated further here for the sake of brevity.

[0154] As shown in Figure 11, the capacitor layer 1100 may include an electrode structure 1121, a dielectric layer 1122, and an electrode structure 1123. The capacitor C1 may also include the electrode structure 1121, the dielectric layer 1122, and the electrode structure 1123. Both electrode structures 1121 and 1123 may be made of conductive materials, and may be the same or different conductive materials. In some embodiments, electrode structure 1121 may include a metallic material, a metal compound material, or other conductive materials, and the material of electrode structure 1121 may be a material with better film formation quality. In some examples, the material of electrode structure 1121 may include, but is not limited to, one or more of the following: titanium nitride (TiN), tantalum nitride (TaN), etc. Electrode structure 1123 may be made of a metallic material, a metal compound material, or other conductive materials with low resistivity, etc. In some examples, the material of electrode structure 1123 may include, but is not limited to, one or more of the following: titanium nitride (TiN), tungsten (W), polycrystalline silicon (Poly-Si), tantalum nitride (TaN), etc. The dielectric layer 1122 may include a dielectric material, which may include, but is not limited to, one or more of the following: hafnium oxide (HfO), zirconium hafnium oxide (Zr-Hf-O), hafnium aluminum oxide (Hf-Al-O), or zirconium aluminum oxide (Zr-Al-O), silicon oxide (SiO), silicon nitride (SiN), aluminum oxide (AlO), zirconium oxide (ZrO), titanium oxide (TiO), or strontium titanate (STO / SrTiO). The dielectric layer D3 in the above embodiments may use one or more of the above dielectric materials. Any of the above dielectric layer materials may also be doped as needed, and this application does not impose any limitations.

[0155] In some embodiments of this application, capacitor layer 1100 may include opening 1101 and opening 1102. Opening 1101 is formed on the portion of interconnect node SN2 exposed above transistor layer 700 / 800 / 900 / 1000. Electrode structure 1121 includes a first portion 1121a formed on the bottom and inner wall of opening 1101. Opening 1102 is formed on opening 1101. Electrode structure 1121 includes a second portion 1121b formed on the bottom and inner wall of opening 1102. The bottom of opening 1102 communicates with opening 1101, and the size of opening 1102 is larger than the size of opening 1101. In this embodiment, by providing a smaller opening 1101, on the one hand, it facilitates more reliable alignment of the opening 1101 and the first portion 1121a of the electrode structure 1121 therein with the interconnect node SN2, allowing for good contact between the first portion 1121a of the electrode structure 1121 and the interconnect node SN2, thereby improving the connection reliability between the capacitor layer 1100 and the transistor layers 700 / 800 / 900 / 1000; on the other hand, it also helps reduce the alignment difficulty during the manufacturing process, improves alignment accuracy, and thus helps improve manufacturing efficiency. By providing a larger opening 1102, it is beneficial to increase the area of ​​the second portion 1121b of the electrode structure 1121 located in the opening 1102, thereby forming a capacitor with a larger capacitance value, improving the charge storage capacity of the capacitor, and further improving the storage performance and / or computing performance of the memory cell.

[0156] Referring again to Figure 11, the dielectric layer 1122 may be formed on the electrode structure 1121 and the non-opening region of the capacitor layer 1100. The electrode structure 1123 is formed on the dielectric layer 1122 and includes a portion corresponding to the electrode structure 1121 and a portion corresponding to the non-opening region of the capacitor layer 1100, for example, including portions formed in openings 1101 and 1102 and portions formed in the non-opening region of the capacitor layer 1100.

[0157] In some embodiments of this application, capacitor layer 1100 may include at least one interlayer dielectric layer formed above transistor layers 700 / 800 / 900 / 1000. At least a portion of capacitor C1 may be formed in the at least one interlayer dielectric layer; for example, one or both of openings 1101 and 1102 may be formed in the at least one interlayer dielectric layer. The non-opening region of capacitor layer 1100 may include the non-opening region of the at least one interlayer dielectric layer facing away from the surface of transistor layers 700 / 800 / 900 / 1000. Referring to FIG11, taking capacitor layer 1100 including interlayer dielectric layer 1103 as an example, its non-opening region may include the non-opening region on the surface of interlayer dielectric layer 1103. Capacitor layer 1100 may include multiple interlayer dielectric layers, openings 1101 and 1102 of capacitor C1 are formed in multiple interlayer dielectric layers, and the non-opening region of capacitor layer 1100 may include the non-opening region on the surface of the uppermost interlayer dielectric layer. The dielectric layer 1122 can be formed on the electrode structure 1121 in the openings 1101 and 1102, and also in the non-opening region of at least one interlayer dielectric layer facing away from the surface of the transistor layers 700 / 800 / 900 / 1000. The electrode structure 1123 can be further formed above the dielectric layer 1122, with a first portion located in the openings 1101 and 1102 and a second portion located above the dielectric layer 1122 in the non-opening region of the capacitor layer 1100. Thus, when the capacitor layer 1100 includes multiple capacitors, it facilitates the interconnection of the electrode structures 1123 of these multiple capacitors, thereby enabling the electrode structures 1123 of the multiple capacitors to be jointly connected to an external signal or ground (e.g., the voltage signal in the above embodiment), simplifying the manufacturing process complexity of the semiconductor device.

[0158] In some embodiments, the electrode structures 1123 of multiple capacitors can be integrally formed. Integrating the electrode structures 1123 can simplify the manufacturing process complexity of semiconductor devices.

[0159] Optionally, electrode structure 1123 may fill the areas in openings 1101 and 1102 excluding electrode structure 1121 and dielectric layer 1122. Completely filling the openings with electrode structure simplifies the capacitor formation process.

[0160] Optionally, referring to FIG11, the electrode structure 1123 may be formed in the form of a layer on the dielectric layer 1122 in the openings 1101 and 1102. At least one of the openings 1101 and 1102 may also include an unfilled region not filled by the electrode structure 1121, the dielectric layer 1122, and the electrode structure 1123. The capacitor layer 1100 may also include a filling structure 1124, which may include a first portion disposed in the unfilled region, thereby filling the unfilled regions of the openings 1101 and 1102. The filling structure 1124 may also include a second portion disposed in a non-opening region of the capacitor layer 1100, which may be disposed above the non-opening region of the capacitor layer 1100; the second portion of the filling structure 1124 may be disposed on a second portion of the electrode structure 1123.

[0161] The filling structure 1124 can be a capacitor. The filling structure 1124 can be integrally formed with the electrode structure 1123 or formed independently. When integrally formed, the filling structure 1124 and the electrode structure 1123 can be collectively understood as one electrode of the capacitor, i.e., electrode E2. Multiple capacitor filling structures 1124 can be integrally formed and connected to multiple integrally formed electrode structures 1123. The filling structure 1124 can be made of a conductive material to achieve electrical connection between one or more electrode structures 1123 and an external signal or ground. The filling structure 1124 can, for example, include a low-resistance conductive material, such as, but not limited to, one or more of the following materials: titanium nitride (TiN), tungsten (W), copper (Cu), tantalum nitride (TaN), etc.

[0162] In some embodiments of this application, the manufacturing process for the capacitor layer 1100 can be such that at least one interlayer dielectric layer can be formed above the transistor layers 700 / 800 / 900 / 1000. At least one of openings 1101 and 1102 can be formed in the at least one interlayer dielectric layer, with the larger opening 1102 communicating above the smaller opening 1101. An electrode material can be deposited in both openings to form the electrode structure 1121. Further deposition of dielectric and electrode materials on the electrode structure 1121 can form the dielectric layer 1122 and the electrode structure 1123. For example, the electrode structure 1123 can fill both openings. Alternatively, the electrode structure 1123 can be conformally fitted to the dielectric layer 1122, and the filling structure 1124 can fill one or both openings. Figure 12 shows a schematic diagram of another capacitor layer according to an exemplary embodiment of this application.

[0163] As shown in Figure 12, capacitor layer 1200 can be located above transistor layers 700 / 800 / 900 / 1000. Transistor layers 700 / 800 / 900 / 1000 may include transistor T2. The technical solution of transistor layers 700 / 800 / 900 / 1000 can be found in the relevant description of the embodiments above, and will not be elaborated further here for the sake of brevity.

[0164] As shown in Figure 12, the capacitor layer 1200 may include an electrode structure 1221, a dielectric layer 1222, and an electrode structure 1223. The capacitor C2 may also include an electrode structure 1221, a dielectric layer 1222, and an electrode structure 1223. The materials of these three components can be found in the description of the electrode structure 1121, dielectric layer 1122, and electrode structure 1123 in the embodiment shown in Figure 11 above.

[0165] The capacitor layer 1200 may include openings 1201 and 1202. Opening 1201 is formed on the portion of interconnect node SN2 exposed above transistor layers 700 / 800 / 900 / 1000. Electrode structure 1221 includes a first portion 1221a formed on the bottom and inner wall of opening 1201. Opening 1202 is formed above opening 1201. Electrode structure 1221 also includes a second portion 1221b formed on the bottom and inner wall of opening 1202. The bottom of opening 1202 communicates with opening 1201, and the size of opening 1202 is larger than the size of opening 1201. The region of opening 1201 may include the region occupied by the outer wall of the first portion 1221a of electrode structure 1221 and the region it surrounds. The region of opening 1202 may include the region occupied by the outer wall of the second portion 1221b of electrode structure 1221 and the region it surrounds.

[0166] A dielectric layer 1222 may be formed on the electrode structure 1221 and the non-opening region of the capacitor layer 1200. An electrode structure 1223 is formed on the dielectric layer 1222 and includes portions corresponding to the electrode structure 1221 and portions corresponding to the non-opening region of the capacitor layer 1200. For example, it includes portions formed on the inner and outer walls of the electrode structure 1221 (e.g., portions in openings 1201 and 1202 and portions on the outer wall of the electrode structure 1221) and portions formed on the non-opening region of the capacitor layer 1200. The outer wall of the second portion 1221b of the electrode structure 1221 may form the outer wall of the opening 1202. The dielectric layer 1222 may include portions surrounding the outer wall of the opening 1202. The electrode structure 1223 may include portions on the dielectric layer 1222 surrounding the outer wall of the opening 1202. The inner and outer walls of the electrode structure 1221 may both be opposite to the electrode structure 1223, such that the capacitor C2 may include a double-sided capacitor. With the same height in the stacking direction (z-direction), the capacitance of capacitor C2 can be increased compared to capacitor C1 shown in Figure 11; or, with the same capacitance, the height of capacitor C2 in the stacking direction can be reduced compared to capacitor C1. This allows for the formation of capacitors with larger capacitance values, improving their charge storage capacity and further enhancing the storage performance and / or computing performance of the memory cells; or, it can reduce the dimensions of the semiconductor device in the stacking direction, facilitating the miniaturization of the semiconductor device.

[0167] In some embodiments of this application, capacitor layer 1200 may include at least one interlayer dielectric layer, and at least a portion of capacitor C2 may be formed in the at least one interlayer dielectric layer. For example, capacitor layer 1200 may include an interlayer dielectric layer 1203 formed on transistor layers 700 / 800 / 900 / 1000; an opening 1201 may be formed in the interlayer dielectric layer 1203. The non-opening region of capacitor layer 1200 may include a portion of the non-opening region of the at least one interlayer dielectric layer that faces away from the surface of transistor layers 700 / 800 / 900 / 1000; for example, the non-opening region of capacitor layer 1200 may include the non-opening region on the surface of interlayer dielectric layer 1203.

[0168] Alternatively, the electrode structure 1223 can completely fill the areas in openings 1201 and 1202 except for the electrode structure 1221 and the dielectric layer 1222. Completely filling the openings with the electrode structure simplifies the capacitor forming process.

[0169] Optionally, referring to Figure 12, the electrode structure 1223 can be formed in layers on the dielectric layer 1222 within openings 1201 and 1202. At least one of the openings 1201 and 1202 may also include unfilled areas not filled by the electrode structure 1221, dielectric layer 1222, and electrode structure 1223. The capacitor layer 1200 may further include a filling structure 1224, which can be formed on the electrode structure 1223 to fill the area surrounding the electrode structure 1223, for example, filling the unfilled areas of openings 1201 and 1202, or filling the non-opening areas of the capacitor layer 1200. The filling structure 1224 may belong to the capacitor C2. The filling structure 1224 can be integrally formed with or independently of the electrode structure 1223. When integrally formed, the filling structure 1224 and the electrode structure 1223 can be collectively understood as one electrode of the capacitor, namely electrode E2. The filling structure 1224 of multiple capacitors can be integrally formed and connected to the integrally formed multiple electrode structures 1223. The relevant technical solutions for the filling structure 1224 can be found in the description of the embodiments above, and will not be elaborated further here. In some embodiments of this application, the semiconductor device may include multiple capacitors. Using the structure of the capacitor C2 described above, the electrode structure 1223 can be used to shield or reduce signal crosstalk between adjacent capacitors C2, thereby reducing interference between adjacent memory nodes.

[0170] Figure 13 shows a schematic diagram of yet another capacitor layer according to an exemplary embodiment of this application.

[0171] As shown in Figure 13, capacitor layer 1300 can be located above transistor layers 700 / 800 / 900 / 1000. Transistor layers 700 / 800 / 900 / 1000 may include transistor T2. The technical solution of transistor layers 700 / 800 / 900 / 1000 can be found in the relevant description of the embodiments above, and will not be elaborated further here for the sake of brevity.

[0172] The capacitor layer 1300 may include an electrode structure 1321, a dielectric layer 1322, and an electrode structure 1323. The capacitor C3 may include an electrode structure 1321, a dielectric layer 1322, and an electrode structure 1323. The materials of these three components can be found in the description of the electrode structure 1121, dielectric layer 1122, and electrode structure 1123 in the embodiment shown in Figure 11 above.

[0173] The capacitor layer 1300 may include openings 1301 and 1302. Opening 1301 is formed on the portion of interconnect node SN2 exposed above transistor layers 700 / 800 / 900 / 1000. Electrode structure 1321 includes a first portion 1321a formed on the bottom and inner wall of opening 1301. Opening 1302 is formed on opening 1301. Electrode structure 1321 also includes a second portion 1321b formed on the bottom or inner wall of opening 1302. The bottom of opening 1302 communicates with opening 1301, and the size of opening 1302 is larger than the size of opening 1301. The first portion 1321a may fill opening 1301, and the second portion 1321b may fill opening 1302.

[0174] The dielectric layer 1322 may be formed on the electrode structure 1321 and the non-opening region of the capacitor layer 1300. The electrode structure 1323 is formed on the dielectric layer 1322 and includes a portion corresponding to the electrode structure 1321 and a portion corresponding to the non-opening region of the capacitor layer 1300. For example, it includes a portion located on the outer wall of the opening 1302 (including a portion on the surface and outer wall of the transistor layer 700 / 800 / 900 / 1000) and a portion formed on the non-opening region of the capacitor layer 1300.

[0175] In some embodiments of this application, capacitor layer 1300 may include at least one interlayer dielectric layer, and at least a portion of capacitor C3 may be formed in the at least one interlayer dielectric layer. For example, capacitor layer 1300 may include an interlayer dielectric layer 1303 formed on transistor layers 700 / 800 / 900 / 1000; opening 1301 may be formed in interlayer dielectric layer 1303, and opening 1302 may be formed on interlayer dielectric layer 1303. Non-opening regions of capacitor layer 1300 may include portions of non-opening regions of the at least one interlayer dielectric layer that are away from the surface of transistor layers 700 / 800 / 900 / 1000; for example, non-opening regions of capacitor layer 1300 may include non-opening regions on the surface of interlayer dielectric layer 1303.

[0176] The dielectric layer 1322 may be formed on the second portion 1321b of the electrode structure 1321 and on a non-opening region of the surface of the dielectric layer 1303. Referring to FIG13, the dielectric layer 1322 may include a portion formed on the top surface of the second portion 1321b of the electrode structure 1321, a portion formed on the sidewall of the second portion 1321b of the electrode structure 1321, and a portion formed on the top surface of the dielectric layer 1303. The electrode structure 1323 is formed on the dielectric layer 1322. In some embodiments of this application, the capacitor layer 1300 may further include a filling structure 1324, which may be formed on the electrode structure 1323 to fill the area surrounding the electrode structure 1323, for example, filling the non-opening region of the capacitor layer 1300. The filling structure 1324 may belong to the capacitor C2. The filling structure 1324 may be integrally formed with the electrode structure 1323 or formed independently. When integrally formed, the filling structure 1324 and the electrode structure 1323 can be understood as a single electrode of a capacitor, namely electrode E2. Multiple capacitor filling structures 1324 can be integrally formed and connected to multiple integrally formed electrode structures 1323. The relevant technical solutions for the filling structure 1324 can be found in the descriptions of the embodiments above, and will not be elaborated upon here.

[0177] In some embodiments of this application, the semiconductor device may include multiple capacitors. Using the structure of the capacitor C3 described above, the electrode structure 1323 can be used to shield or reduce signal crosstalk between adjacent capacitors C3, thereby reducing interference between adjacent memory nodes.

[0178] As an example, in the embodiments shown in Figures 11 to 13 above, capacitors C1 / C2 / C3 can be cylindrical capacitors, and their cross-sections can include circles or ellipses. In other examples, capacitors C1 / C2 / C3 can also be other three-dimensional structures, such as prism structures. The embodiments of this application do not limit the cross-sectional shape of the capacitors.

[0179] In some embodiments of this application, at least one interlayer dielectric layer of capacitor layers 1100 / 1200 / 1300 includes an interlayer dielectric layer for the formation of other conductive structures, such as for the formation of traces connecting transistor T2, and may include the aforementioned interlayer dielectric layer LA2. This application does not limit the material of the interlayer dielectric layer, as long as it can be used for interlayer electrical isolation, and the materials of different interlayer dielectric layers can be the same or different. For example, the material of the interlayer dielectric layer may include, but is not limited to, at least one of the following: silicon carbide (SiC), silicon nitride (SiN), silicon oxide (SiO), etc. This application does not limit whether the material contains other elements; for example, the material of the interlayer dielectric layer may include nitrogen-containing silicon carbide (N-SiC).

[0180] This application does not limit the material of the electrical connection structure, as long as it can meet the requirements of electrical connection. The materials of different electrical connection structures can be the same or different. For example, the material of the electrical connection structure can refer to the description of interconnect nodes, conductive structures, etc. above. For example, it can include, but is not limited to, one or more of the following materials: titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN), copper (Cu), silver (Ag), gold (Au), aluminum (Al), or alloys containing the above elements. Any of the semiconductor devices shown in the above embodiments can be used as memory cells in a memory circuit. This application also provides a memory circuit that can include multiple memory cells, which can be arranged in an array and have the semiconductor device provided in any of the above embodiments. The memory circuit using the above semiconductor device can have a high storage density.

[0181] This application does not limit the connection method of the memory cells in the array. For example, the first terminal T11 of the transistor T1 of the memory cell can be connected to a first trace, and the first trace connects to the first terminals T11 of the transistors T1 of multiple memory cells arranged along its extension direction; the second terminal T12 of the transistor T1 of the memory cell can be connected to a second trace, and the second trace connects to the second terminals T12 of the transistors T1 of multiple memory cells arranged along its extension direction. The second driving terminal T23 of the transistor T2 of the memory cell can be connected to a third trace, and the third trace connects to the second driving terminal T23 of the transistors T2 of multiple memory cells arranged along its extension direction; the fourth terminal T22 of the transistor T2 of the memory cell can be connected to a fourth trace, and the fourth trace connects to the fourth terminal T22 of the transistors T2 of multiple memory cells arranged along its extension direction.

[0182] This application also provides a semiconductor device that can be used in a storage circuit or memory to improve the storage performance of the storage circuit or memory, such as storage density and storage reliability. The following description is in conjunction with the accompanying drawings.

[0183] As an example, Figure 14 shows a schematic diagram of a semiconductor device according to an exemplary embodiment of this application.

[0184] As shown in Figure 14, the semiconductor device 1400 includes a first transistor array 1410, a second transistor array 1420, and a capacitor array 1430. The second transistor array 1420 is formed on the first transistor array 1410; the capacitor array 1430 is formed on the second transistor array 1420. The semiconductor device 1400 may further include traces L1 and L2, and an interconnect node SN1. Traces L1 extend along a first direction (e.g., the x-direction shown in Figure 14) and connect to the first terminals of a plurality of transistors T1 arranged along the first direction in the first transistor array 1410. Traces L2 extend along a second direction (e.g., the y-direction shown in Figure 14) and connect to the second terminals of a plurality of transistors T1 arranged along the second direction in the first transistor array 1410. The interconnect node SN1 is connected to the first driving terminal of one of the transistors T1 in the first transistor array 1410. The semiconductor device 1400 may further include traces L3 and L4, and an interconnect node SN2. Trace L3 extends along a third direction (e.g., the x direction shown in FIG14) and connects to the second driving terminals of a plurality of transistors T2 arranged along the third direction in the second transistor array 1420. Trace L4 extends along a fourth direction (e.g., the y direction shown in FIG14) and connects to the fourth terminals of a plurality of transistors T2 arranged along the fourth direction in the second transistor array 1420. Interconnect node SN2 and interconnect node SN1, the third terminal of a transistor T2 in the second transistor array 1420, and the first electrode structure of a capacitor C in the capacitor array 1430 are connected.

[0185] The technical solution of this application combines two transistor arrays and one capacitor array in a vertical space within a semiconductor device. This not only facilitates three-dimensional (3D) process integration but also improves the accuracy and stability of data storage when the semiconductor device is used in a storage circuit. Layered stacking of different parts within the storage cell allows for higher space utilization and smaller size of the semiconductor device. This enables more stable and reliable data storage with a smaller footprint or area, improving the reliability of the storage system. Furthermore, the reduced size or area provides more usable space or area for other circuits within the chip, such as logic circuits, which is beneficial for improving logic circuit performance. The layered structure further enhances storage performance. Moreover, placing the capacitor array above the transistor array reduces the space constraints imposed by the transistor array on the capacitor array, allowing the capacitors in the capacitor array to expand in both the stacking and horizontal directions, thereby maximizing the capacitance value and further improving the storage performance of the storage system. This solution features a high degree of process integration in the semiconductor device, enabling denser stacking and facilitating better implementation of storage and in-memory computing functions. The array connection method of the above semiconductor devices can be applied to in-memory computing architectures to store weight data. This weight data can be used for in-memory computation or near-memory computation. The storage circuits / memories implemented using the above semiconductor devices can improve the accuracy and stability of weight data storage in the storage units, thereby improving the reliability of in-memory computing architectures. In addition, the above array structure can support efficient in-memory computation within the semiconductor devices.

[0186] In some embodiments of this application, the third direction may be the same as one of the first direction and the second direction, and the fourth direction may be the same as the other of the first direction and the second direction. In this way, the manufacturing process of the semiconductor device can be simplified and the storage density of the semiconductor device can be further improved.

[0187] In some embodiments of this application, the first transistor array 1410, the second transistor array 1420, and the capacitor array 1430 may be formed on different device layers, such as a first device layer, a second device layer, and a third device layer, with the second device layer located above the first device layer and the third device layer located above the second device layer. Optionally, at least one inter-dielectric layer (which may be referred to as a first interconnection layer) may be present between the first device layer and the second device layer for electrical connection and / or electrical isolation between the devices; at least one inter-dielectric layer (which may be referred to as a second interconnection layer) may be present between the second device layer and the third device layer for electrical connection and / or electrical isolation between the devices.

[0188] The layer structure of the semiconductor device 1400 described above will now be described with reference to the accompanying drawings.

[0189] Figures 15A to 15D illustrate a partial structural diagram of a semiconductor device according to an exemplary embodiment of this application. The semiconductor device 1500 may include a device layer 1510 (e.g., a first device layer in the above embodiments) and a connection layer 1520 (e.g., a first connection layer in the above embodiments). Figure 15B is a cross-sectional view of Figure 15A along the H-H' direction, Figure 15C is a cross-sectional view of Figure 15A along the I-I' direction, and Figure 15D is a cross-sectional view of Figure 15A along the J-J' direction.

[0190] As shown in Figures 15A to 15D, device layer 1510 may include a first transistor array, which may include a plurality of transistors T1 arranged in an array. A connection layer 1520 is formed on device layer 1510 and may include traces L1 and L2, and interconnection node SN1. Trace L1 may extend along one of a first direction and a second direction (e.g., the x-direction) and connect to the first terminal T11 of the plurality of transistors T1 arranged in device layer 1510 along one of the first and second directions. Trace L2 may extend along the other of the first and second directions (e.g., the y-direction) and connect to the second terminal T12 of the plurality of transistors T1 arranged in device layer 1510 along the other of the first and second directions. Interconnection node SN1 is connected to the first driving terminal T13 of one of the transistors T1 in device layer 1510. In this embodiment, the connection between interconnect node SN1 and the first driving terminal T13 of a transistor T1 in device layer 1510 can be referred to the description of the connection between interconnect node SN1 and the first driving terminal T13 in the above semiconductor device embodiments; the technical solutions of transistor T1 and its first terminal T11, second terminal T12 and first driving terminal T13 can be referred to the relevant descriptions in the above embodiments. For ease of distinction, trace L1 and trace L2 in this embodiment can also be referred to as the first trace and the second trace, respectively.

[0191] In this embodiment, traces L1 and L2 can serve as signal lines for the first transistor array in device layer 1510, such as the input and output lines of the memory circuit containing the first transistor array, to realize data input and output. The routing directions of traces L1 and L2 can intersect each other, for example, be perpendicular (e.g., the x and y directions shown in the figure). This intersecting routing layout can reduce interference and improve the storage density or reduce the area of ​​the memory circuit. The intersection of the input and output lines can facilitate matrix multiplication operations.

[0192] In some implementations, traces L1 and L2 can be located in different sublayers within the connection layer 1520, and either trace L1 or L2 can be located in the same sublayer as interconnect node SN1. For example, as shown in Figures 15A to 15D, interconnect node SN1 can be located in the same sublayer as trace L1. In other embodiments, interconnect node SN1 can be located in the same sublayer as trace L2. Having interconnect node SN1 in the same sublayer as either trace L1 or L2 eliminates the need for separate sublayers for interconnect node SN1 and traces L1 / L2, thereby reducing the number of sublayers in the connection layer 1520. This helps to reduce the height of the semiconductor device and contributes to the miniaturization of semiconductor devices.

[0193] In some implementations, interconnect node SN1 may also be located in a different sublayer from traces L1 and L2, thereby making the distribution of traces L1, traces L2 and interconnect node SN1 more flexible.

[0194] In some embodiments, the interconnect layer 1520 may include at least one interlayer dielectric layer, for example, multiple interlayer dielectric layers, which may be multiple sublayers of the interconnect layer 1520. As an example, Figures 15A to 15D show the interconnect layer 1520 including interlayer dielectric layers 1521 to 1524, where trace L2 may be formed on interlayer dielectric layer 1523 and trace L1 may be formed on interlayer dielectric layer 1524. Optionally, the interlayer dielectric layer 1522 may include other electrical connection structures for the electrical connection lead-out or redistribution of any one or more of the first terminal T11, second terminal T12, and first drive terminal T13 of transistor T1. For example, the electrical connection between the first terminal T11 and the second terminal T12 of transistor T1 can be led out through the interlayer dielectric layer 1511 of device layer 1510, and redistributed or led out through interlayer dielectric layers 1521 and 1522; the second terminal T12 of transistor T1 is then electrically connected to trace L2, and the electrical connection between the first terminal T11 of transistor T1 can be further redistributed or led out to trace L1 through interlayer dielectric layer 1523; the electrical connection between the first driving terminal T13 of transistor T1 can be redistributed or led out to interconnect node SN1 through interlayer dielectric layers 1521 to 1523. This facilitates the connection of transistor T1 with traces and / or interconnect nodes in subsequent interlayer dielectric layers 1523 and 1524, improving the reliability of electrical connections between one or more terminals of transistor T1 and other devices or traces. In some embodiments, the connection layer 1520 may not include interlayer dielectric layer 1522. The electrical connection between the first terminal T11 and the second terminal T12 of transistor T1 can be led out through the interlayer dielectric layer 1511 of device layer 1510, and its location can be redistributed or led out through the interlayer dielectric layer 1521. For example, the electrical connection of the first terminal T11 can be further redistributed or led out through the dielectric layer 1523 to trace L1, and the second terminal T12 can be redistributed or led out to trace L2. The electrical connection of the first drive terminal T13 can be redistributed or led out through the interlayer dielectric layer 1521, and further redistributed or led out through the interlayer dielectric layer 1523 to interconnect node SN1.

[0195] The above are merely examples. In this embodiment, traces L1 and L2 can be located in any two interlayer dielectric layers in the connection layer 1520. This embodiment does not specifically limit their location.

[0196] Trace L1 and trace L2 are located in different sub-layers of the connection layer 1520, which facilitates their extension and arrangement in different directions, thereby enabling them to be connected to the first terminals T11 and second terminals T12 of multiple transistors T1 in the first transistor array in the device layer 1510. Referring to Figures 15A to 15D, the interlayer dielectric layer 1524 can form multiple traces L1, which extend along a first direction (e.g., the x-direction) and are arranged along a second direction (e.g., the y-direction). One trace L1 can connect to the first terminals T11 of a row of transistors T1 arranged along the first direction, and multiple traces L1 can respectively connect to the first terminals T11 of multiple rows of transistors T1 arranged along the second direction. These multiple traces L1 can be used to form multiple input lines or multiple output lines of the memory circuit containing the first transistor array. Multiple traces L2 can be formed within the interlayer dielectric layer 1523, which extend along the second direction and are arranged along the first direction. A single trace L2 can connect to the second terminal T12 of a row of transistors T1 arranged along a second direction. Multiple traces L2 can connect to the second terminals T12 of multiple rows of transistors T1 arranged along a first direction. These multiple traces L2 can be used to form multiple output lines or multiple input lines of the memory circuit containing the first transistor array. In this embodiment, the molecular layer arrangement of traces L1 and L2 facilitates the simplification of semiconductor manufacturing processes and also improves the reliability of semiconductor devices.

[0197] In the embodiments shown in Figures 15A to 15D, trace L1 and interconnect node SN1 may be located in interlayer dielectric layer 1524, and trace L2 may be located in interlayer dielectric layer 1523. In other embodiments, trace L2 and interconnect node SN1 may be located in interlayer dielectric layer 1524, and trace L1 may be located in interlayer dielectric layer 1523. Interlayer dielectric layer 1524 is located above interlayer dielectric layer 1523. In these embodiments, interconnect node SN1 may be located in a sublayer of the connection layer 1520 near the second device layer, for example, it may be located in the uppermost interlayer dielectric layer among the multiple interlayer dielectric layers of the connection layer 1520, thereby providing interconnect nodes to devices in the second device layer and enabling electrical connections to desired device terminals in the second device layer.

[0198] In some embodiments, adjacent transistors T1 in the first transistor array can be configured as a common terminal structure, such as a common source or common drain structure. For example, the first terminals of adjacent transistors T1 can be configured as a common terminal structure. This can further improve the compactness of the semiconductor device, allowing for increased storage density when the semiconductor device is used in a storage circuit. Continuing to refer to Figures 15A to 15D, device layer 1510 may include a transistor pair TT1, which may include two transistors T1. In a transistor pair TT1, the two transistors T1 share a first terminal T11, and two second terminals T12 are located on either side of the first terminal T11.

[0199] In some embodiments, the first transistor array includes a plurality of first transistor pairs TT1 arranged along a second direction (e.g., the y-direction shown in FIG. 15B), and the second terminals T12 of two transistors T1 in the first transistor pairs TT1 are located on either side of the first terminal T11 along a first direction (e.g., the x-direction shown in FIG. 15B). In this way, the layout can be combined with the directions of traces L1 and L2, further improving the compactness of the semiconductor device and enabling a further increase in the storage density of the memory circuit when the semiconductor device is used in a memory circuit.

[0200] In some embodiments, the semiconductor device 1500 may include a plurality of trace pairs LL2, each trace pair LL2 corresponding to a transistor pair TT1. Two second terminals T12 in a transistor pair TT1 are respectively connected to different traces L2 in the corresponding trace pair LL2. Optionally, the device layer 1510 may include a plurality of transistor pairs TT1 arranged along a second direction, wherein transistors T1 located in the same row in the second direction may be connected to the same trace L2.

[0201] In this embodiment, two adjacent transistors T1 can form a transistor pair, and these two transistors T1 can share the first terminal T11. This facilitates a more compact layout of the first transistor array formed by multiple transistors T1, reducing the size of the first transistor array. Furthermore, by coordinating the routing direction in the interconnect layer 1520 with the terminal routing direction of the transistor pair TT1, the compactness of the semiconductor device 1500 can be further improved, and the process complexity reduced. Thus, this solution simplifies the manufacturing process of the semiconductor device while also increasing its storage density.

[0202] Optionally, device layer 1510 may include a plurality of transistor pairs TT1 arranged along a first direction, the first terminals T11 of the plurality of transistor pairs TT1 being connected to the same trace L1 extending along the first direction.

[0203] In some embodiments, an electrical connection structure pair CONN can be formed between the two traces L2 in the aforementioned trace pair LL2, corresponding to an interconnect node pair SNN1. One electrical connection structure in the CONN is connected to the first driving terminal T13 of a transistor T1 in the corresponding transistor pair TT1 and an interconnect node SN1 in the corresponding interconnect node pair SNN1, and the other electrical connection structure is connected to the first driving terminal T13 of another transistor T1 in the corresponding transistor pair TT1 and another interconnect node SN1 in the corresponding interconnect node pair SNN1. Multiple electrical connection structure pairs CONN arranged along a second direction can be formed between the two traces L2 in the trace pair LL2. Two electrical connection structures in one CONN are respectively connected to the first driving terminals T13 of two transistors T1 in a transistor pair TT1 and the two interconnect nodes SN1 in an interconnect node pair SNN1. The electrical connection structure pair CONN and the trace L2 can be formed in the same interlayer dielectric layer, for example, in the interlayer dielectric layer 1523 shown in Figures 15A to 15D.

[0204] This technical solution can make full use of the space between the two traces L2 in trace pair LL2 to set up an electrical connection structure pair CONN for connecting the two first drive terminals T13 of a transistor pair TT1 and the two interconnect nodes SN1 in an interconnect node pair SNN1. This helps to make the layout of the semiconductor device more compact, thereby further reducing the size of the semiconductor device and increasing the storage density of the semiconductor device.

[0205] In some embodiments, the semiconductor device 1500 may further include multiple trace pairs LL1. For example, the interconnect layer 1520 may include multiple trace pairs LL1, wherein multiple interconnect node pairs SNN1 are formed between two trace pairs LL1, and two interconnect nodes SN1 in one interconnect node pair SNN1 are respectively connected to the first drive terminal T13 of different transistors T1 in a transistor pair TT1. Optionally, the multiple interconnect node pairs SNN1 between two trace pairs LL1 may be arranged in an array. Multiple interconnect node pairs SNN1 arranged along at least one of a first direction and a second direction may be formed between two trace pairs LL1. For example, in the examples shown in Figures 15A to 15D, two rows of interconnect node pairs SNN1 arranged in the second direction may be formed between two trace pairs LL1. A row of interconnect node pairs SNN1 arranged along the first direction may include two or more interconnect node pairs SNN1.

[0206] In this implementation, multiple interconnect nodes SN1 and traces L1 are located in the same sub-layer of the connection layer 1540, and the space of the same sub-layer can be fully utilized to arrange the interconnect nodes SN1 more compactly, thereby further improving the compactness of the semiconductor device and further increasing the storage density of the semiconductor device.

[0207] Figures 16A to 16D show partial structural schematic diagrams of a semiconductor device according to an exemplary embodiment of this application. The semiconductor device 1600 includes a device layer 1610, a connection layer 1620, and a device layer 1630. The descriptions of device layer 1610 and connection layer 1620 can be found in the related descriptions of device layer 1510 and connection layer 1520 in Figures 15A to 15D above. Device layer 1630 may include a second transistor array, which includes a plurality of arrayed transistors T2. In some embodiments of this application, the transistors T2 in device layer 1630 may be bottom-gate structures. The technical solution of device layer 1630 can be found in the related descriptions of the embodiments shown in Figures 7, 8A, and 8B above. Figure 16B can be a cross-sectional schematic diagram of Figure 16A along the K-K' direction, Figure 16C can be a cross-sectional schematic diagram of Figure 16A along the L-L' direction, and Figure 16D can be a cross-sectional schematic diagram of Figure 16A along the O-O' direction.

[0208] As shown in Figures 16A to 16D, device layer 1630 can be formed on interconnect layer 1620. The technical solutions for interconnect layer 1620 and the underlying device layer 1610 can be found in the relevant descriptions of the embodiments above. Device layer 1630 may include a plurality of transistors T2, which can be arranged in an array as a second transistor array. In some embodiments, semiconductor device 1600 may further include interconnect layer 1640, which may include interconnect nodes SN2.

[0209] In the embodiments shown in Figures 16A to 16D, trace L3 may be formed in device layer 1630. In other embodiments, trace L3 may also be formed in interconnect layer 1640. Trace L3 may extend along one of a third direction and a fourth direction (taking the x-direction as an example), and connect to the second drive terminal T23 of a plurality of transistors T2 arranged in device layer 1630 along one of the third and fourth directions. Trace L4 may extend along the other of the third and fourth directions (taking the y-direction as an example), and connect to the fourth terminal T22 of a plurality of transistors T2 arranged in the other of the third and fourth directions in device layer 1630. Interconnect node SN2 is connected to interconnect node SN1 and the third terminal T21 of one transistor T2 in device layer 1630. In the device layer 1630 shown in Figures 16A to 16D, transistor T2 can be an oxide semiconductor transistor. The third terminal T21 and the fourth terminal T22 of transistor T2 are located in the oxide structure O1. The third terminal T21 is connected to the conductive structure CE1, and the fourth terminal T22 is connected to the conductive structure CE2. The conductive structure CE3 forms the second driving terminal T23 of transistor T2. A trace L3 can be connected to the second driving terminal T23. For example, the conductive structure CE3 can be used for the second driving terminal T23, and multiple conductive structures CE3 can be integrally formed into trace L3. Traces L4 can be connected to the conductive structure CE2, thereby connecting to the fourth terminal T22. Interconnect nodes SN2 and SN1 can be connected to the conductive structure CE1, thereby connecting to the third terminal T21.

[0210] In this embodiment, traces L3 and L4 can be used as signal lines for the second transistor array in device layer 1630, for example, as control lines CON1 of the memory circuit containing the second transistor array. i and CON2 j The routing directions of traces L3 and L4 can intersect or even be perpendicular to each other (e.g., the x and y directions shown in the figure). This intersecting routing layout reduces interference and can increase the storage density or reduce the area of ​​the memory circuit. The intersection of traces L3 and L4 also facilitates flexible control over data writing and programming.

[0211] According to some embodiments, the extension directions of traces L3 and L4 may be related to the extension direction of the oxide structure O1 of transistor T2. The extension direction of trace L3 may intersect the extension direction of oxide structure O1, and the extension direction of trace L4 may intersect the extension direction of trace L3. For example, the extension direction of oxide structure O1 may include the y-direction, the extension direction of trace L3 may include the x-direction, and the extension direction of trace L4 may include the y-direction.

[0212] Optionally, the routing directions of traces L3 and L4 can be related to the routing directions of traces L1 and L2 to simplify the manufacturing process. For example, trace L3 may have the same routing direction as one of traces L1 and L2 (e.g., trace L1), and trace L4 may have the same routing direction as the other of traces L1 and L2 (e.g., trace L2). The third direction may include one of the first and second directions, such as the x-direction; the fourth direction may include the other of the first and second directions, such as the y-direction. In this embodiment, the traces of the semiconductor device are more regular, which facilitates the design of the trace interface and simplifies the process implementation of the semiconductor device, thus improving the overall performance of the semiconductor device. In other embodiments, the routing directions of traces L1, L2, L3, and L4 may also be different from each other or partially the same.

[0213] In some embodiments, traces L3 and L4 can be located on different layers, and either trace L3 or L4 can be located on the same layer as interconnect node SN2. For example, as shown in Figures 16A to 16D, interconnect node SN2 can be located on the same layer as trace L4. In other embodiments, interconnect node SN2 can be located on the same layer as trace L3, and the second drive terminal T23 of transistor T2 can be led out to a sub-layer of interconnect layer 1640 through an electrical connection structure, and interconnect node SN2 is also formed in this sub-layer. Having interconnect node SN2 on the same sub-layer as either trace L3 or L4 reduces the number of sub-layers in the interconnect layer, which is beneficial for reducing the height of the semiconductor device and contributes to the miniaturization of semiconductor devices.

[0214] In some implementations, interconnect node SN2 may also be located in a different sublayer from traces L3 and L4, thereby making the distribution of traces L3, traces L4 and interconnect node SN2 more flexible.

[0215] In some embodiments, the interconnect layer 1640 may include at least one interlayer dielectric layer, which may be at least one sublayer of the interconnect layer 1640. As an example, Figures 16A to 16D show the interconnect layer 1640 including an interlayer dielectric layer 1641, on which trace L4 may be formed. Optionally, the interconnect layer 1640 may overlap with a portion of a sublayer in the device layer 1630, or in other words, a portion of a sublayer in the device layer 1630 may be reused as a sublayer in the interconnect layer 1640.

[0216] In some embodiments of this application, in the examples shown in Figures 16A to 16D, trace L3 may be formed in the interlayer dielectric layer 1631 of device layer 1630. In other embodiments, interconnect layer 1640 may include multiple interlayer dielectric layers, and traces L3 and L4 are respectively located in different interlayer dielectric layers of interconnect layer 1640.

[0217] Trace L3 and trace L4 are located on different sub-layers, which facilitates their extension and arrangement in different directions, thereby enabling them to be connected to the conductive structures CE2 of the fourth terminals T22 of multiple transistors T2 in the second transistor array in device layer 1630 and the conductive structures CE3 for the second driving terminals T23, respectively. Referring to Figures 16A to 16D, the interlayer dielectric layer 1641 can form multiple traces L4 extending in the fourth direction and arranged in the third direction. One trace L4 can connect to the conductive structures CE2 of a row of transistors T2 extending in the fourth direction, and multiple traces L4 can connect to the conductive structures CE2 of multiple rows of transistors T2 arranged in the third direction. These multiple traces L4 can be used to form multiple control lines CON2 of the memory circuit containing the second transistor array. j The interlayer dielectric layer 1631 can form multiple traces L3, which extend along a third direction and are arranged along a fourth direction. One trace L3 can connect to the conductive structure CE3 of a row of transistors T2 extending along the third direction, and multiple traces L3 can connect to the conductive structure CE3 of multiple rows of transistors T2 arranged along the fourth direction. These multiple traces L3 can be used to form multiple control lines CON1 of the memory circuit containing the second transistor array. i In this implementation, the layered arrangement of traces L3 and L4 simplifies the semiconductor manufacturing process and improves the reliability of the semiconductor device.

[0218] According to some embodiments, traces L3 and L4 can be located in sub-layers of the connection layer 1640, one above and one below the device layer 1630, respectively. Traces L3 and L4 are separated by the device layer 1630, which can reduce interference between them. According to some embodiments, a conductive structure CE3 can be used as the bottom gate of the transistor T2 in the device layer 1630 and integrally formed as trace L3, which can reduce the overall number of sub-layers of the device layer 1630 and the connection layer 1640.

[0219] According to some implementations, trace L3 is located on the side of device layer 1630 facing device layer 1610, and trace L4 is located on the side of device layer 1630 away from device layer 1610 (or the side facing the capacitor array). This can reduce interference between traces and facilitate the lead-out of trace L4 from device layer 1630 facing the capacitor array. This simplifies the lead-out structure of trace L4 and the manufacturing process of semiconductor devices, and is conducive to further improving the compactness of semiconductor devices and increasing storage density.

[0220] In the embodiments shown in Figures 16A to 16D, trace L4 and interconnect node SN2 can be located in interlayer dielectric layer 1641, and trace L3 can be located in interlayer dielectric layer 1631; wherein, interlayer dielectric layer 1641 is located above interlayer dielectric layer 1631. This facilitates electrical connection with devices (e.g., capacitors) located in layers above connection layer 1640.

[0221] Referring again to Figures 16A to 16D, device layer 1630 may include a pair of transistors TT2, in which the two transistors T2 share a fourth terminal T22 or the conductive structure CE2 corresponding to the fourth terminal T22, and the second driving terminals T23 of the two second transistors are located on both sides of the shared fourth terminal T22 or the conductive structure CE2 corresponding to the fourth terminal T22.

[0222] In some embodiments, the semiconductor device 1600 may include a transistor pair TT2, wherein the two transistors T2 in the transistor pair TT2 share a fourth terminal T22, and the second driving terminals T23 of the two transistors T2 are located on both sides of the shared fourth terminal T22 or the conductive structure CE2 corresponding to the fourth terminal T22. Multiple transistor pairs TT2 may be arranged along a third direction (e.g., the x-direction); in one transistor pair TT2, the two transistors T2 share the fourth terminal T22, and the two transistors T2 may also share the conductive structure CE2, and the two second driving terminals T23 (or the two conductive structures CE3) are located on both sides of the fourth terminal T22 or the conductive structure CE2 corresponding to the fourth terminal T22 along a fourth direction (e.g., the y-direction). The two second driving terminals T23 in one transistor pair TT2 may be connected to different traces L3 of a trace pair LL3. Optionally, among the multiple transistor pairs TT2 arranged along the third direction, the second driving terminals T23 (or conductive structures CE3) of transistors T2 located in the same row in the third direction can be connected to the same trace L3. For example, the second driving terminals T23 (or conductive structures CE3) of transistors T2 located in the same row in the third direction can be integrally formed into the same trace L3.

[0223] In this embodiment, two adjacent transistors T2 can form a transistor pair, and these two transistors T2 can share the fourth terminal T22. This facilitates a more compact layout of the second transistor array formed by multiple transistors T2, reducing the size of the second transistor array. Furthermore, by coordinating with the routing direction of trace L3 and the terminal routing direction of transistor pair TT2, the compactness of the semiconductor device 1600 can be further improved, and the process complexity reduced. Thus, this solution simplifies the semiconductor device manufacturing process while also increasing the storage density of the semiconductor device.

[0224] Optionally, device layer 1610 may include a plurality of transistor pairs TT2 arranged along a fourth direction, the fourth terminals T22 of the plurality of transistor pairs TT2 being connected to the same trace L4 extending along the fourth direction.

[0225] In some embodiments, the semiconductor device 1600 may include a plurality of interconnect node pairs SNN2, wherein two interconnect nodes SN2 in an interconnect node pair SNN2 are respectively connected to the third terminal T21 of different transistors T2 in a transistor pair TT2. The plurality of interconnect node pairs SNN2 may be arranged in an array, for example, along at least one of a third direction and a fourth direction. Two interconnect nodes SN2 in an interconnect node pair SNN2 are respectively connected to the third terminal T21 of different transistors T2 in a transistor pair TT2, and are connected to the first driving terminal T13 of transistor T1 in a transistor pair TT1 through a corresponding interconnect node SN1.

[0226] In some embodiments, the plurality of second interconnect nodes SNN2 include a first row of interconnect nodes SN1 and a second row of interconnect nodes SN2 arranged in a fourth direction (e.g., the y-direction), with a trace L4 formed between the first row of interconnect nodes SN1 and the second row of interconnect nodes SN2. This trace L4 connects to a common fourth terminal T22 (or conductive structure CE2) of the corresponding transistor pair TT2. Optionally, more traces L4 are formed between the first row of interconnect nodes SN1 and the second row of interconnect nodes SN2, thereby better utilizing the space of the interconnect layer 1640 and achieving a more compact layout of the semiconductor device 1600.

[0227] In this implementation, multiple interconnect nodes SN2 and traces L4 are located on the same sub-layer, and the space of the same sub-layer can be fully utilized. The multiple interconnect nodes SN2 are arranged in a regular manner, which facilitates the simplification of semiconductor device process implementation.

[0228] Referring to Figures 16A to 16D, the two interconnect nodes SN2 in the interconnect node pair SNN2 can be respectively set on both sides of the two traces L4. However, the embodiment is not limited to this; the interconnect node pair SNN2 can be set on both sides of a trace pair L4, or the interconnect node SN2 can be alternately set with the trace L4.

[0229] Figures 17A to 17D show partial schematic diagrams of another semiconductor device according to exemplary embodiments of this application. The semiconductor device 1700 may include a device layer 1710, an interconnect layer 1720, and a device layer 1730. Descriptions of device layer 1710 and interconnect layer 1720 can be found in the related descriptions of device layer 1510 and interconnect layer 1520 in Figures 15A to 15D above. Device layer 1730 may include a second transistor array, which includes a plurality of transistors T2. In some embodiments of this application, the transistors T2 in device layer 1730 may be top-gate structures. Technical solutions for device layer 1730 can be found in the related descriptions of the embodiments shown in Figures 9, 10A, and 10C above. Figure 17B is a perspective view of Figure 17A omitting the interlayer dielectric layer LA2; Figure 17C is a cross-sectional view of Figure 17A along the P-P' direction; and Figure 17D is a cross-sectional view of Figure 17A along the Q-Q' direction.

[0230] As shown in Figures 17A to 17D, device layer 1730 can be formed on top of interconnect layer 1720. The technical solutions for interconnect layer 1720 and the device layer 1710 below it can be found in the relevant descriptions of the embodiments above. Device layer 1730 may include multiple transistors T2, and may be arranged in an array as a second transistor array.

[0231] The semiconductor device 1700 may further include a trace L3. The trace L3 may extend along one of a third direction and a fourth direction (e.g., the x-direction) and connect to the second drive terminal T23 of a plurality of transistors T2 arranged in the device layer 1730 along one of the third direction and the fourth direction. For example, the conductive structure CE3 in the plurality of transistors T2 may be used for the second drive terminal T23, and the conductive structure CE3 of the plurality of transistors T2 arranged in the second transistor array along one of the third direction and the fourth direction may be integrally formed into the trace L3.

[0232] The semiconductor device 1700 may further include a connection layer 1740 in which an interconnect node SN2 is formed. The interconnect node SN2 is connected to the interconnect node SN1 and the third terminal T21 of a transistor T2 in the device layer 1730.

[0233] In some embodiments of this application, the semiconductor device 1700 may further include an interlayer dielectric layer LA2, and a trace L4 may be formed in the interlayer dielectric layer LA2. The interlayer dielectric layer LA2, for example, as described in the above embodiments, may belong to a second transistor layer or a capacitor layer. In some embodiments of this application, a trace L4 may also be formed within the connection layer 1740. The trace L4 may be formed in the same sublayer or a different sublayer as the interconnect node SN2, for example, in the same interlayer dielectric layer or a different interlayer dielectric layer. The trace L4 extends along another of a third direction and a fourth direction (e.g., the y-direction) and connects to the fourth terminal T22 of a plurality of transistors T2 arranged in the device layer 1730 along the other of a third direction and a fourth direction.

[0234] In the device layer 1730 shown in Figures 17A to 17D, transistor T2 can be an oxide semiconductor transistor. The third terminal T21 and the fourth terminal T22 of transistor T2 are located in the oxide structure O1. The third terminal T21 is connected to the conductive structure CE1 and the electrical connection structure S21, and the fourth terminal T22 is connected to the conductive structure CE2 and the electrical connection structure S22. Figures 17A to 17D illustrate the electrical connection structures S21 and S22 connecting transistor T2. Trace L4 can be connected to the electrical connection structure S22, thereby connecting to the fourth terminal T22. Interconnect nodes SN2 and SN1 can be connected to the electrical connection structure S21, thereby connecting to the third terminal T21.

[0235] According to some embodiments, the extension directions of traces L3 and L4 may be related to the extension direction of the oxide structure O1 of transistor T2. The extension direction of trace L3 may intersect the extension direction of oxide structure O1, and the extension direction of trace L4 may intersect the extension direction of trace L3. For example, the extension direction of oxide structure O1 may include the y-direction, the extension direction of trace L3 may include the x-direction, and the extension direction of trace L4 may include the y-direction.

[0236] Optionally, in the embodiments shown in Figures 17A to 17D, the semiconductor device 1700 may further include an interlayer dielectric layer LA1 disposed between the device layer 1730 and the interconnect layer 1720. The description of the interlayer dielectric layer LA1 can be referred to the above embodiments and will not be repeated here.

[0237] Optionally, in the embodiments shown in Figures 17A to 17D, the semiconductor device 1700 may further include an intermediate layer 1750 disposed between the device layer 1730 and the interconnect layer 1720. The intermediate layer 1750 may include an interconnect node SN4, which is at least partially exposed in the intermediate layer 1750 and connected to the electrical connection structure S21 and the interconnect node SN1. The intermediate layer 1750 can more reliably isolate the traces in the interconnect layer 1740 from the device layer 1730. For example, the intermediate layer 1750 can more reliably isolate the traces (e.g., trace L1) of the uppermost sublayer in the sublayer of the interconnect layer 1720 from the device layer 1730.

[0238] In some embodiments, the sublayer containing trace L4 may be located above the sublayer containing interconnect node SN2. Optionally, in the connection layer 1740, interconnect node SN2 may be formed in the interlayer dielectric layer 1741, and interlayer dielectric layer LA2 is located above interlayer dielectric layer 1741, in which trace L4 is formed. Interlayer node SN2 may be connected to the electrical connection structure S21 of device layer 1730. Optionally, interlayer dielectric layer LA2 may belong to capacitor layer, and at least a portion of the capacitor array of capacitor layer is formed in interlayer dielectric layer LA2. For example, a portion of the capacitor structure in capacitor layer may pass through interlayer dielectric layer LA2 and contact and connect with interconnect node SN2. The use of interlayer dielectric layer LA2 by capacitor layer can reduce the overall height of capacitor array and second transistor array for the same capacitance value, which is beneficial for reducing the size of semiconductor device and simplifying semiconductor device manufacturing process. Alternatively, with the same overall height, more interlayer dielectric layers can be used to increase the height of capacitor, thereby increasing capacitance value and further improving voltage stability and hold time at storage node.

[0239] In some other embodiments, the interlayer dielectric layer LA2 may belong to the interconnect layer 1740, and the capacitor layer may be formed on the interlayer dielectric layer LA2. The interlayer dielectric layer LA2 can better isolate the trace L4 from the capacitor layer. The interconnect node SN2 may be formed in a larger size in the interlayer dielectric layer 1741, which helps to achieve a more reliable connection with the capacitor in the capacitor layer. Alternatively, the interconnect node SN2 and the trace L4 may both be formed in the interlayer dielectric layer LA2.

[0240] Optionally, a conductive node CN1 may also be formed in the interlayer dielectric layer 1741. The trace L4 may be located at a certain depth of the interlayer dielectric layer LA2 and connected to the conductive node CN1 through an electrical connection structure. The conductive node CN1 is connected to the electrical connection structure S22.

[0241] In other embodiments, the interconnect node SN2 may be located in the same sublayer of the connection layer 1740 as the trace L4. For example, the connection layer 1740 includes an interlayer dielectric layer 1741, in which the interconnect node SN2 and the trace L4 are located.

[0242] In some embodiments, trace L3 may be formed in the connection layer 1740 and connected to the conductive structure CE3 via an electrical connection structure. Trace L3 and trace L4 may be located in different sublayers of the connection layer 1740.

[0243] Referring to Figures 17A to 17D, multiple traces L4 can be formed in the interlayer dielectric layer LA2, extending along a fourth direction (e.g., the y-direction). These multiple traces L4 can be arranged along a third direction (e.g., the x-direction). The traces L4 can connect to the fourth terminals T22 of a row of transistors T2 extending along the fourth direction. For example, the traces L4 can connect to the fourth terminals T22 of a row of transistors T2 extending along the fourth direction via multiple conductive nodes CN1, corresponding electrical connection structures S22 and CE2.

[0244] Optionally, multiple traces L3 may be formed in another interlayer dielectric layer or device layer 1730 of the connection layer 1740, extending along a third direction (e.g., the x-direction). The traces L3 may be arranged along a fourth direction (e.g., the y-direction). The traces L3 may connect to the second driving terminals of a row of transistors T2 extending along the third direction. For example, a conductive structure CE3 may be used for the second driving terminals of transistors T2, and the traces L3 may connect to the conductive structures CE3 of a row of transistors T2 extending along the third direction; alternatively, the traces L3 may include the conductive structures CE3 of a row of transistors T2 extending along the third direction.

[0245] Optionally, in some embodiments of this application, the second transistor array in device layer 1730 may also adopt a structure in which two transistors T2 share a fourth terminal. A description of the layout of the transistor pairs and their corresponding traces and interconnect nodes can be found in Figures 16A to 16D above, which describe the transistor pair TT2 and its corresponding traces L3, L4, and interconnect node SN2.

[0246] Based on the embodiments shown in Figures 16A to 16D or Figures 17A to 17D above, a capacitor layer can be further formed. As an example, Figure 18 shows a partial schematic diagram of a semiconductor device according to an exemplary embodiment of this application. The semiconductor device 1800 may include a device layer 1810, a connection layer 1820, a device layer 1830, a connection layer 1840, and a capacitor layer (or device layer) 1850. The device layer 1810 and connection layer 1820 can be referred to in the relevant descriptions of device layer 1510 and connection layer 1520 in Figures 15A to 15D above. The device layer 1830 and connection layer 1840 can be referred to in the relevant descriptions of device layer 1630 and connection layer 1640 in Figures 16A to 16D above, or the relevant descriptions of device layer 1730 and connection layer 1740 in Figures 17A to 17D.

[0247] As shown in Figure 18, the capacitor layer 1850 is formed on the interconnect layer 1840 and includes a capacitor array, and the electrode structure 1851 of one capacitor C of the capacitor array is connected to the interconnect node SN2 in the interconnect layer 1840.

[0248] The capacitor layer 1850 may include a plurality of openings 1801 arranged in an array, and a plurality of capacitors C are respectively formed in the plurality of openings 1801 to form a capacitor array. The capacitors C may include electrode structures 1851, dielectric layers 1852, and electrode structures 1853. The electrode structures 1851 are formed in the openings 1801, the dielectric layers 1852 may be formed on the electrode structures 1851 and in the non-opening regions of the capacitor layer 1850, and the electrode structures 1853 are formed on the dielectric layers 1852, including portions corresponding to the electrode structures 1851 and portions formed in the non-opening regions of the capacitor layer 1850. In some embodiments, the electrode structures 1853 of the plurality of capacitors C may be integrally formed. The electrode structures 1851 are connected to interconnect node SN2, and the electrode structures 1853 can be used as common electrodes. The integrally formed electrode structures 1853 can simplify the connection between the electrode structures 1853 of the plurality of capacitors, thereby simplifying the manufacturing process and increasing the storage density of the semiconductor device.

[0249] Optionally, referring to FIG18, the capacitor layer 1850 may further include a filling structure 1854 that can fill the remaining portion of the opening 1801 and is integrally formed between the plurality of capacitors C.

[0250] According to some embodiments, the electrode structure 1853 and the filling structure 1854 can be formed integrally. For example, the electrode structure 1853 can completely fill the opening 1801, thereby eliminating the need for other structures to fill the opening and simplifying the process.

[0251] Figure 18 is only an example, showing one implementation of capacitor layer 1850. The capacitor in capacitor layer 1850 can also adopt the technical solution provided in any of the embodiments in Figures 11 to 13.

[0252] This application also provides a method for manufacturing a semiconductor device, which can be used to manufacture the semiconductor devices of any of the above embodiments. As an example, FIG19 shows a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment of this application.

[0253] As shown in Figure 19, the semiconductor device manufacturing method 1900 may include the following steps.

[0254] S1910, forming a first transistor layer. The first transistor layer includes a first transistor, the first transistor includes a first terminal, a second terminal and a first driving terminal, a first channel is formed between the first terminal and the second terminal, the first driving terminal is formed on the first channel and has a first dielectric layer between it and the first channel.

[0255] S1920, a second transistor layer is formed. This second transistor layer is formed on top of the first transistor layer. The second transistor layer includes an oxide structure, a first conductive structure, a second conductive structure, and a third conductive structure. The second transistor includes an oxide structure. The first conductive structure is connected to a first portion of the oxide structure, forming a third terminal of the second transistor in the first portion. The second conductive structure is connected to a second portion of the oxide structure, forming a fourth terminal of the second transistor in the second portion. A second channel is formed between the third and fourth terminals within the oxide structure. The third conductive structure is formed on the second channel and serves as a second driving terminal of the second transistor, and a second dielectric layer is present between it and the oxide structure.

[0256] S1930, a capacitor layer is formed. This capacitor layer is formed on top of the second transistor layer. The capacitor layer includes a capacitor, which includes a first electrode structure and a second electrode structure. A third dielectric layer is provided between the first electrode structure and the second electrode structure. The first driving terminal of the first transistor, the third terminal of the second transistor, and the first electrode structure of the capacitor are electrically connected.

[0257] In this embodiment, the first transistor may include transistor T1, and the first transistor layer may be a transistor layer including transistor T1. The second transistor may include transistor T2, and the second transistor layer may be a transistor layer including transistor T2.

[0258] In some implementations, the first transistor layer may include a first transistor array, the second transistor layer may include a second transistor array, and the capacitor layer may include a capacitor array.

[0259] Figure 20 shows a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment of this application.

[0260] As shown in Figure 20, the semiconductor device manufacturing method 2000 may include the following steps.

[0261] S2010, forming the first transistor array.

[0262] S2020, a first trace, a second trace, and a first interconnect node are formed, wherein the first trace extends along a first direction and connects to the first terminals of a plurality of first transistors arranged along the first direction in the first transistor array, the second trace extends along a second direction and connects to the second terminals of a plurality of first transistors arranged along the second direction in the first transistor array, and the first interconnect node is connected to the first driving terminal of a first transistor in the first transistor array.

[0263] S2030 forms the second transistor array.

[0264] S2040, forming a third trace, a fourth trace, and a second interconnect node, wherein the third trace extends along a third direction and connects to the second driving terminals of a plurality of second transistors arranged along the third direction in the second transistor array, the fourth trace extends along a fourth direction and connects to the fourth terminals of a plurality of second transistors arranged along the fourth direction in the second transistor array, and the second interconnect node is connected to the first interconnect node and the third terminal of a second transistor in the second transistor array.

[0265] S2050, forming a capacitor array, wherein the first electrode structure of one capacitor in the capacitor array is connected to a second interconnect node.

[0266] In this embodiment, the first trace may include trace L1, the second trace may include trace L2, and the first interconnect node may include interconnect node SN1. The third trace may include trace L3, the fourth trace may include trace L4, and the second interconnect node may include interconnect node SN2. The related technical solutions for traces L1, L2, L3, and L4, as well as interconnect nodes SN1 and SN2, can be found in the descriptions of the embodiments above. The first direction may be, for example, the x-direction in the embodiments above, and the second direction may be, for example, the y-direction in the embodiments above. The third direction may include one of the first and second directions, such as the x-direction or the y-direction; the fourth direction may include the other of the first and second directions, such as the y-direction or the x-direction. In other embodiments, the first, second, third, and fourth directions may be different from each other.

[0267] To facilitate understanding of the manufacturing process described above, the following section, in conjunction with the accompanying drawings, introduces several implementation methods for each step in the above approach.

[0268] Figures 21A to 21F illustrate schematic diagrams of the manufacturing process of a portion of a semiconductor device according to an exemplary embodiment of this application. In this example, the first transistor includes, for example, a silicon-based transistor.

[0269] According to some embodiments, a plurality of active areas (AA) 2120 may be formed on the substrate 2110, and two first transistors may be formed based on one of the plurality of active areas 2120, the two first transistors sharing a first terminal or a second terminal. Alternatively, in some alternative embodiments, one first transistor may be formed based on one active area 2120. The substrate 2110 may include a silicon substrate.

[0270] As shown in Figure 21A, the substrate 2110 can be patterned. A portion of the substrate 2110 can be patterned to form an effective region 2120, which can form AA patterns. For example, the AA patterns can be defined first using photolithography, and then isolation trenches, such as shallow trench isolation (STI), can be formed between the AA patterns using etching (e.g., dry etching). The AA patterns can be arranged in an array along the x and y directions. In some embodiments, a silicon nitride film can be formed on the substrate 2110 before patterning. After etching to form the isolation trenches, the silicon nitride film remains patterned on the AA patterns. The silicon nitride film can be used to protect the substrate 2110 during the patterning process.

[0271] As shown in Figure 21B, filling the isolation trench with insulating material can form a shallow trench isolation structure. This insulating material may include, for example, oxides (which can be written as OX). The insulating material can be planarized to form an insulating layer 2130. According to some embodiments, the silicon nitride film above the effective region 2120 can be removed after planarization. Subsequently, ion implantation can be performed on the effective region 2120 to form a well, such as a P-type well or an N-type well. Optionally, the planarization process in this embodiment can employ a process such as chemical mechanical polishing (CMP). The removal of silicon nitride can be performed using an etching process, such as a wet etching process.

[0272] As shown in Figure 21C, an oxide (OX) layer 2121 can be formed on the surface of the effective region 2120. The oxide layer 2121 can be used to form a gate dielectric layer or a portion thereof. This oxide layer 2121 can be used to form a dielectric layer D1 or a portion thereof located between the first driving terminal T13 and the channel in the first transistor. In some examples, the oxide layer 2121 can be formed using an in-situ steam generation (ISSG) process, and the oxide layer 2121 may include, for example, silicon oxide. A gate structure 2140 can be formed over the effective region 2120. For example, the gate structure layer can be formed first, and then the gate structure 2140 can be formed by a patterning process (e.g., photolithography and etching). For example, the gate structure 2140 may include a sacrificial gate structure (or a dummy gate structure) for occupying a gate formed in a subsequent process. The material of the sacrificial gate structure may include, but is not limited to, silicon, such as polysilicon (polySi), which has lower manufacturing costs and a stable manufacturing process. According to some embodiments, the gate structure 2140 or the gate formed at the location of the gate structure 2140 can be used as a driving terminal of the first transistor. For example, when an effective region 2120 is used to form two first transistors (or a pair of first transistors), two gate structures 2140 can be correspondingly disposed on the effective region 2120, with the extending directions of the gate structures 2140 intersecting, for example, perpendicular to, the extending directions of the effective region 2120. As shown in FIG21C, the gate structure 2140 can extend along the y-direction, and the effective region 2120 can extend along the x-direction.

[0273] The dashed box d' in Figure 21D shows a cross-section along the R-R' direction. As shown in Figure 21D, in the effective region 2120, the source and drain regions of the transistor are located on both sides of the gate structure 2140. For example, the source and drain structure can be formed by an epitaxial process. The source and drain structure can include materials such as silicon germanium or silicon germanide (SiGe), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), etc., thereby having higher carrier mobility to improve transistor performance. For example, the source and drain structure can generate stress on the channel, which can change the band structure of the channel, reduce carrier scattering, and thus improve the carrier mobility of the channel. For example, the source and drain regions of the transistor can be etched to form a trench, and the source and drain structure can be formed in the trench. The first transistor may include transistor T1, and the source and drain structure of transistor T1 may include a first terminal T11 and a second terminal T12. In some examples, the first terminal T11 may include a source region and the second terminal T12 may include a drain region; or, in some examples, the first terminal T11 may include a drain region and the second terminal T12 may include a source region. According to some embodiments, two first transistors sharing the effective region 2120 may share the first terminal T11. Optionally, a lightly doped drain (LDD) technique can be applied between the first terminal T11 and the second terminal T12 and the channel to form a lightly doped region, thereby suppressing the short-channel effect of the first transistor and reducing the hot carrier effect, to further improve the performance of the first transistor. Optionally, a spacer structure can be formed on the sidewall of the gate structure 2140. Optionally, the first terminal T11 and the second terminal T12 can be heavily doped by ion implantation to reduce contact resistance and further improve transistor performance.

[0274] Furthermore, an interlayer dielectric layer 2150 can be formed on the insulating layer 2130, which can fill the gaps between the gate structures 2140. According to some embodiments, the gate structure 2140 can be removed to form a trench, and the trench can be filled with a dielectric layer material (e.g., HK material) and a gate material. The dielectric layer material and gate material are described with reference to the embodiments above and will not be repeated here. The dielectric layer material, together with the oxide layer 2121, can be used as the dielectric layer D1 between the driving terminal T13 of the first transistor corresponding to the gate structure 2124 and the channel.

[0275] As shown in Figure 21E, the dashed box e' on the right shows a cross-sectional view of the stacked structure on the left taken along the S-S' direction, and the dashed box e” shows a cross-sectional view of the stacked structure on the left taken along the W-W' direction. For the first transistor formed in the effective region 2120, an electrical connection structure can be formed to electrically connect the first terminal T11, the second terminal T12, and the first driving terminal T13. For example, an interlayer dielectric layer 2160 can be formed on the interlayer dielectric layer 2150. Contact holes are formed in the interlayer dielectric layer 2160 using photolithography and etching processes. After depositing conductive material in the contact holes, an electrical connection structure connecting to the three terminals of the transistor can be formed, such as an electrical connection structure S11 connected to the first terminal T11, an electrical connection structure S12 connected to the second terminal T12, and an electrical connection structure S13 connected to the first driving terminal T13. After depositing the conductive material, a planarization process can be further performed to facilitate reliable downstream processes.

[0276] As shown in Figure 21E, for example, contact holes are formed in at least one of the interlayer dielectric layers 2150 and 2160 using a patterning process (e.g., photolithography and etching). These contact holes can connect to the first terminal T11, the second terminal T12, or the first driving terminal T13, respectively. Conductive material can be deposited in the contact holes to form an electrical connection structure connecting to the three terminals of the transistor, for example, an electrical connection structure S11 connected to the first terminal T11, an electrical connection structure S12 connected to the second terminal T12, and an electrical connection structure S13 connected to the first driving terminal T13. After depositing the conductive material, the conductive material and the interlayer dielectric layer 2160 can be planarized to remove portions of the conductive material formed on the interlayer dielectric layer 2160, preventing undesirable connections caused by the conductive material. In some examples, in the electrical connection structures S11, S12, and S13 connecting two first transistors in a shared effective region 2120, electrical connection structure S12 is arranged on both sides of electrical connection structure S11 in the x-direction. Electrical connection structure S12 can be in the same row as electrical connection structure S11 in the x-direction, or it can be staggered. Electrical connection structure S13 is arranged in the x-direction and can be spaced apart from electrical connection structures S11 and S12 in the y-direction. For example, electrical connection structure S13 is alternately arranged with electrical connection structures S11 and S12 in the x-direction. The above arrangement of the electrical connection structures facilitates the connection between multiple first transistors and traces, as well as the connection with other devices.

[0277] Furthermore, multiple interlayer dielectric layers can be formed on the interlayer dielectric layer 2160. These multiple interlayer dielectric layers may belong to the first transistor layer or the first interconnect layer. The multiple interlayer dielectric layers may include traces connecting the first transistors in the first transistor array. The multiple interlayer dielectric layers may be multiple sublayers within the first interconnect layer. In some embodiments, the process of forming the first interconnect layer may include: forming a first sublayer of the first interconnect layer; forming a first trace in the first sublayer; forming a second sublayer of the first interconnect layer; forming a second trace in the second sublayer; and forming a first interconnect node in the first or second sublayer.

[0278] In some examples, as shown in FIG21F, the multilayer interlayer dielectric layers on interlayer dielectric layer 2160 may include interlayer dielectric layers 2170 and 2190, with interlayer dielectric layer 2190 formed on interlayer dielectric layer 2170. A trace L1 may be formed within interlayer dielectric layer 2190, extending in the x-direction and connecting to a first terminal T11 of a plurality of first transistors arranged in the x-direction. A trace L2 (not shown) may be formed within interlayer dielectric layer 2170, extending in the y-direction and connecting to a second terminal T12 of a plurality of first transistors arranged in the y-direction. An interconnect node SN1 may also be formed within interlayer dielectric layer 2190, connecting to a first drive terminal T13 of the plurality of first transistors. In other examples, trace L1 may be located in interlayer dielectric layer 2170, and trace L2 may be located in interlayer dielectric layer 2190. Optionally, the multilayer interlayer dielectric layer may further include an interlayer dielectric layer 2180, which is formed between interlayer dielectric layers 2170 and 2190. In other examples, trace L1 may be located in interlayer dielectric layer 2180 or 2190, and trace L2 may be located in interlayer dielectric layer 2170.

[0279] The technical solutions of the embodiments of this application can be found in the relevant descriptions of the embodiments shown in Figures 15A to 15D above, and will not be elaborated further here.

[0280] Figures 22A to 22E illustrate schematic diagrams of the manufacturing process of a partial structure of another semiconductor device according to exemplary embodiments of this application. In this example, the second transistor includes, for example, a semiconductor oxide transistor with a bottom gate structure.

[0281] As shown in FIG22A, other partial structures of the semiconductor device can be formed on the partial structure 2201 of the semiconductor device. Partial structure 2201 can be a partial structure formed in the embodiments shown in FIG22A to FIG22F above. For example, partial structure 2201 may include a first transistor layer. Partial structure 2201 can correspond to the cross-sectional view along the U-U' direction in FIG21F.

[0282] As shown in Figure 22A, an interlayer dielectric layer 2210 can be formed on a portion of the structure 2201. Interconnect nodes SN3 and traces L3 extending along the x-direction can be formed in this interlayer dielectric layer 2210. The interconnect nodes SN3 are connected to the interconnect nodes SN1 in the portion of the structure 2201, and the traces L3 can be used to form the second driving terminals T23 of a plurality of second transistors arranged along the x-direction.

[0283] For example, during the manufacturing process, the interlayer dielectric layer 2210 can be patterned. Regions for traces L3 and interconnect nodes SN3 can be defined in the interlayer dielectric layer 2210 using photolithography, and trenches can be etched in these regions using etching. Conductive material is then filled into the trenches to form the traces L3 and interconnect nodes SN3. This conductive material can be referred to the description in the above embodiments and will not be repeated here. The traces L3 may include a conductive structure CE3, which can be used as a driving terminal for the second transistor. This step, through a self-aligned process, simplifies the manufacturing of semiconductor devices or apparatuses and improves reliability.

[0284] In other embodiments, the interlayer dielectric layer 2210 may include multiple sublayers, and the traces L3 and interconnect nodes SN3 may include multiple substructures. For example, a first sublayer of the interlayer dielectric layer 2210 may be formed and patterned. Conductive material may be filled into the patterned trenches for the first substructures of the traces L3 and interconnect nodes SN3. A second sublayer of the interlayer dielectric layer 2210 may be formed on the first sublayer of the interlayer dielectric layer 2210 and patterned to form trenches. Patterning the second sublayer of the interlayer dielectric layer 2210 may also include overlaying the first sublayer of the traces L3 and interconnect nodes SN3, thereby thinning the first sublayer of the traces L3 and interconnect nodes SN3. Conductive material may be filled into the trenches for the second substructures of the traces L3 and interconnect nodes SN3. As shown in the dashed box a' of FIG22A, the trace L3 may include a sub-trace L31 of the first sublayer and a sub-trace L32 of the second sublayer. The interconnect node SN3 may include a substructure SN31 of the first sublayer and a substructure SN32 of the second sublayer. As an example, the materials of the first sublayer of the trace L3 and interconnect node SN3 include, but are not limited to, tungsten (W), copper (Cu), tantalum (Ta), or tantalum nitride (TaN). The second sublayer of the trace L3 and interconnect node SN3 can be used to match the work function of the oxide structure of the second transistor, and may include, but are not limited to, titanium nitride (TiN). Optionally, to improve process reliability, process yield, and semiconductor device performance, planarization can be performed after filling the trench with conductive material before proceeding with subsequent process steps.

[0285] As shown in Figure 22B, a gate dielectric layer 2220 and an oxide layer 2230 can be sequentially formed on the interlayer dielectric layer 2210. The gate dielectric layer 2220 may include the dielectric layer D2 in the embodiments described above. Optionally, a protective layer 2240 may also be formed on the oxide layer 2230. As an example, the material of the gate dielectric layer 2220 may include a gate oxide, such as silicon oxide (SiO) or HK material; the material of the oxide layer 2230 may include an oxide semiconductor with a band gap greater than or equal to 1.65 eV, such as ITGZO, IGZO, AZO, GZO, ITO, or IZO; the protective layer 2240 is used to protect the oxide layer 2230, for example, to prevent the oxide layer 2230 material from deteriorating and to reduce the corrosion of the etching solution in subsequent processes. The protective layer 2240 may include a hard mask material. The material of the protective layer 2240 may include silicon nitride (SiN) or oxides and other low-hydrogen or hydrogen-free materials to reduce or prevent the influence of hydrogen on the properties of the oxide layer 2230.

[0286] As shown in Figure 22C, a plurality of oxide structures 2231 can be formed in the oxide layer 2230. Optionally, one of the plurality of oxide structures can be used to form two second transistors, which can share a fourth terminal.

[0287] During the manufacturing process, the oxide layer 2230 can be patterned. The oxide structure region of the second transistor can be defined using photolithography, and then the oxide layer 2230 and the protective layer 2240 can be etched to form multiple oxide structures 2231. In some examples, an oxide structure 2231 can be stacked with two traces L3. The etched protective layer 2240 can have the same pattern as the oxide structure 2231. The etched protective layer 2240 can include multiple protective structures 2241. One protective structure 2241 can be superimposed on top of one oxide structure 2231. The gate dielectric layer 2220 can also be etched in the same process as the oxide layer 2230, thus having the same pattern as the oxide structure 2231. However, the embodiments are not limited to this; the gate dielectric layer 2220 may not be etched in the same process as the oxide layer 2230. The etching process of oxide layer 2230 can stop on gate dielectric layer 2220, which can isolate the second driving terminal, third terminal and fourth terminal in the second transistor, reduce the probability of short circuit between the second driving terminal and the third terminal and fourth terminal, and improve the reliability of the second transistor.

[0288] As shown in Figure 22D, a protective layer is formed above the gate dielectric layer 2220. This protective layer isolates and protects the oxide structure 2231, preventing, for example, degradation of the oxide structure 2231 and corrosion by etching solutions in subsequent processes. This protective layer can form a protective layer 2250 with the protective structure 2241. For example, the material of this protective layer can be the same as that of the protective layer 2240. The protective layer 2250 can be patterned. For example, the regions of the third and fourth terminals of the second transistor can be defined using photolithography, and then etched to form contact holes. Conductive material is filled into the contact holes to form conductive structures CE1 and CE2, which are respectively connected to the third and fourth terminals of the oxide structure 2231. Optionally, since the two second transistors formed based on one oxide structure 2231 can share a fourth terminal, one conductive structure CE2 can be correspondingly formed for each oxide structure 2231, and the conductive structure CE2 can connect to the shared fourth terminal of the two second transistors. Optionally, after filling the conductive material to form the conductive structure, a planarization process can be performed.

[0289] In some embodiments, the contact holes for the third and fourth terminals of the second transistor can be formed in a single etching process. In other examples, the contact holes for the third and fourth terminals of the second transistor can be formed in two etching processes, respectively; then, conductive structures CE1 and CE2 can be formed in the same process. The contact holes for the third terminal can be formed first, followed by the contact holes for the fourth terminal; or, the contact holes for the fourth terminal can be formed first, followed by the contact holes for the third terminal. In some examples, as shown in FIG22D, the contact holes for the third terminal of the second transistor can be formed in a single etching process, which can etch the protective layer 2250 and the gate dielectric layer 2220, exposing the interconnect node SN3. Thus, the conductive structure CE1 can connect to the third terminal in the oxide structure 2231 and also to the interconnect node SN3, thereby achieving interconnection with the first driving terminal of the first transistor in part of structure 2201. The contact hole for the fourth terminal of the second transistor can be formed through another etching process. This etching process can etch the protective layer 2250, thereby connecting the conductive structure CE2 to the fourth terminal in the oxide structure 2231. Optionally, in the example shown in FIG22D, the common fourth terminal of adjacent second transistors is located in the middle region of oxide structure 2231, the conductive structure CE2 is connected to the middle region of oxide structure 2231, the two third terminals of adjacent second transistors are located in the two end regions of oxide structure 2231, and the two conductive structures CE1 are respectively connected to the two end regions of oxide structure 2231. The materials of the above conductive structures CE1 and CE2 may include one or more of the following: titanium nitride (TiN), tungsten (W), copper (Cu), or tantalum nitride (TaN), etc. Through the above process steps, a second transistor array including multiple second transistors can be formed.

[0290] As shown in Figure 22E, at least one interlayer dielectric layer can be formed on the protective layer 2250. For example, an interlayer dielectric layer 2260 is illustrated in the figure. A trace L4 and an interconnect node SN2 can be formed in this interlayer dielectric layer 2260. The trace L4 can extend along the y-direction and connect to the fourth terminal of a plurality of second transistors arranged along the y-direction. Optionally, the interconnect node SN2 is connected to the conductive structure CE1 of the third terminal of the second transistor. This conductive structure CE1 can be connected to the interconnect node SN1 in the partial structure 2201 via interconnect node SN3. The number of interconnect nodes SN2 can be the same as the number of second transistors in the second transistor array, so that a plurality of second transistors in the second transistor array can be connected to a capacitor through the corresponding interconnect node SN2.

[0291] In this application embodiment, the partial structure 2202 formed by the above steps may include, for example, a second transistor layer. The technical solution of the partial structure 2202 can be found in the relevant description of the embodiments shown in Figures 16A to 16D above, and will not be elaborated further here.

[0292] Figures 23A to 23G illustrate schematic diagrams of the manufacturing process of a partial structure of another semiconductor device according to an exemplary embodiment of this application. In this example, the second transistor includes, for example, a semiconductor oxide transistor with a top-gate structure.

[0293] As shown in Figures 23A to 23G, other partial structures of the semiconductor device can be formed on partial structure 2301. Partial structure 2301 can be a partial structure formed in the embodiments shown in Figures 21A to 21F above. For example, partial structure 2201 may include a first transistor layer. Partial structure 2301 can correspond to the cross-sectional view along the V-V' direction in Figure 21F.

[0294] As shown in Figure 23A, an interlayer dielectric layer 2310 can be formed on a portion of structure 2301. This interlayer dielectric layer 2310 may include an insulating material, such as an oxide or nitride. The interlayer dielectric layer 2310 can be patterned. Interconnect regions can be defined in the interlayer dielectric layer 2310 using photolithography, and trenches can be etched in these interconnect regions using etching. Conductive material is filled into the trenches to form interconnect nodes SN4. The conductive material can include, but is not limited to, one or more of the following: tantalum nitride (TaN), copper (Cu), or tantalum (Ta). The interconnect node SN4 can be connected to the interconnect node SN1 in the portion of structure 2301, which is connected to the first driving terminal of the first transistor. In some alternative embodiments, the interlayer dielectric layer 2310 and its interconnect node SN4 can be omitted, and the second transistor can be connected to the first transistor via interconnect node SN1.

[0295] As shown in Figure 23B, an interlayer dielectric layer 2320, an oxide layer 2330, and a conductive layer 2340 can be sequentially formed on the interlayer dielectric layer 2310. Optionally, a protective layer 2350 can also be formed on the conductive layer 2340. The interlayer dielectric layer 2320 can be used to isolate the oxide layer 2330 from the layers below it (e.g., the interlayer dielectric layer 2310 or the first connection layer in part of structure 2301), preventing or reducing short circuits in the semiconductor device. The oxide layer 2330 is used to form the channel and part of the terminals of the second transistor. The conductive layer 2340 is used to form the first conductive structure (also referred to as conductive structure CE1 in the above embodiment) and the second conductive structure (also referred to as conductive structure CE2 in the above embodiment) of the second transistor. The protective layer 2350 is used to protect the conductive layer 2340 and the oxide layer 2330. In some examples, the interlayer dielectric layer 2320 may include an insulating material, such as silicon carbide (SiC), silicon nitride (SiN), silicon oxide (SiO), etc. The oxide layer 2330 may be made of materials such as ITGZO, IGZO, AZO, GZO, ITO, or IZO. The conductive layer 2340 may be made of a low-resistance material that has good work function matching with the oxide layer 2330, such as at least one of the following materials: titanium carbide (TiN), tungsten (W), gold (Au), molybdenum (Mo), or tantalum (Ta). The protective layer 2350 may be made of materials such as silicon nitride (SiN) or oxides.

[0296] As shown in Figure 23C, multiple oxide structures 2331 and multiple conductive structures 2341 can be formed in the oxide layer 2330 and the conductive layer 2340, with the multiple conductive structures 2341 correspondingly located on the multiple oxide structures 2331. Optionally, two second transistors can be formed on one of the multiple oxide structures 2331, and the two second transistors can share a fourth terminal. Optionally, as shown in Figure 23C, multiple protective structures 2351 are also correspondingly provided on the multiple conductive structures 2341.

[0297] During the manufacturing process, the oxide layer 2330 can be patterned. Multiple oxide structure regions for the second transistors can be defined using photolithography, followed by etching of the oxide layer 2330, conductive layer 2340, and protective layer 2350. The etching process stops at the interlayer dielectric layer 2320, which does not require etching. After etching, multiple stacked structures as shown in FIG23C can be formed, where any stacked structure can include a stacked oxide structure 2331, a conductive structure 2341, and a protective structure 2351. Optionally, two adjacent second transistors can share a single oxide structure 2331.

[0298] As shown in Figure 23D, a protective layer is formed above the interlayer dielectric layer 2320. This protective layer isolates and protects the surrounding oxide structure 2331, preventing deformation of the oxide material in the oxide structure 2331 and corrosion by the etching solution in subsequent processes. This protective layer can form a protective layer 2360 with the protective structure 2351. For example, the material of this protective layer can be the same as that of the protective layer 2350. The protective layer 2360 can be patterned. After defining the area of ​​the second driving terminal and the trace L3 of the second transistor using photolithography, a trench 2361 is formed by etching, exposing a portion of the oxide structure 2331 corresponding to the second driving terminal. This trench 2361 can correspond to the second driving terminals of multiple second transistors arranged along the x-direction. By etching, a portion of the conductive structure 2341 corresponding to the second driving terminal of the second transistor can be removed. The remaining portion of the conductive structure 2341 can form a conductive structure CE1 connected to the third terminal of the second transistor and a conductive structure CE2 connected to the fourth terminal of the second transistor. When the oxide structure 2331 is used to form two second transistors, a portion of the conductive structure 2341 on the oxide structure 2331 can be removed. The remaining portion of the conductive structure 2341 can be used to form the two conductive structures CE1 of the two second transistors and the shared conductive structure CE2. The removed portion can be used to form the two conductive structures CE3 of the two second transistors. Through this implementation, the three terminals of the second transistor can be defined using a single patterning process, which simplifies the process flow, reduces process complexity, and thus lowers the manufacturing cost of semiconductor devices.

[0299] As shown in Figure 23E, conductive material can be filled into trench 2361 to form trace L3. This trace L3 can be used to form the second driving terminals (or conductive structure CE3) of multiple second transistors arranged along the x-direction. The conductive material forming trace L3 can include one or more of the following: titanium nitride (TiN), tungsten (W), or tantalum nitride (TaN), etc. Optionally, planarization can be performed after filling the trench with conductive material. Optionally, a dielectric layer can also be filled into trench 2361 before filling it with conductive material, as a dielectric layer between the second driving terminals and oxide structure 2331. This dielectric layer can include dielectric layer D2.

[0300] As shown in Figure 23F, an interlayer dielectric layer 2370 is formed above the protective layer 2360. This interlayer dielectric layer 2370 may include an insulating material, such as an oxide. Electrical connection structures S21 and S22 may be formed in this interlayer dielectric layer 2370. Electrical connection structure S21 may be in contact with the side surface of the conductive structure CE1, and electrical connection structure S22 may be in contact with the top surface of the conductive structure CE2. In this embodiment, electrical connection structure S21 may be in contact with interconnect node SN1, or may be in contact with the top surface of interconnect node SN4 in the interlayer dielectric layer 2310, thereby connecting to interconnect node SN1 in the partial structure 2301.

[0301] During the manufacturing process, the interlayer dielectric layer 2370 can be patterned to form contact holes. After defining the regions of the electrical connection structures S21 and S22 of the second transistor using photolithography, contact holes for the electrical connection structures S21 and S22 are formed by etching. The contact holes of the electrical connection structure S21 can penetrate the interlayer dielectric layer 2320, the protective layer 2360, and the interlayer dielectric layer 2370, thereby exposing the top surface of the interconnect node SN1 or SN4, and exposing the sidewalls and / or top surface of the conductive structure CE1. The contact holes of the electrical connection structure S22 can penetrate the protective layer 2360 and the interlayer dielectric layer 2370, thereby exposing the top surface of the conductive structure CE2. The contact holes of the electrical connection structures S21 and S22 can be formed in the same patterning process or in different patterning processes. When the contact holes of the electrical connection structures S21 and S22 are formed in different patterning processes, the order in which they are formed is not limited. Conductive material is filled into the contact holes to form electrical connection structures S21 and S22 of the second transistor. The relevant technical solutions for these electrical connection structures S21 and S22 can be found in the descriptions of the embodiments shown in Figures 17A to 17D above.

[0302] As shown in Figure 23G, at least one interlayer dielectric layer can be formed on the interlayer dielectric layer 2370. For example, interlayer dielectric layers 2380 and 2390 are illustrated in the figure. Interlayer dielectric layer 2380 can be formed on interlayer dielectric layer 2370, and the interlayer dielectric layer 2380 is patterned to form trenches. Conductive material can be formed in the trenches to form interconnect nodes SN2 and conductive nodes CN1 (not shown). Interconnect node SN2 is connected to conductive structure CE1, and conductive node CN1 is used to connect to trace L4. Interlayer dielectric layer 2390 can be formed on interlayer dielectric layer 2380, and the interlayer dielectric layer 2390 is patterned to form trenches. Conductive material can be formed in the trenches to form trace L4. The trace L4 can extend along the y-direction and connect to the fourth terminal of a plurality of second transistors arranged along the y-direction. According to some embodiments, the conductive material filling the trenches of dielectric layer 2390 can also form interconnect nodes (not shown) connecting interconnect node SN2. Interconnect nodes SN2 are connected to the conductive structure CE1 of the third terminal of the second transistor. The number of interconnect nodes SN2 can be the same as the number of second transistors in the second transistor array, so that multiple second transistors in the second transistor array can be connected to the capacitor through the corresponding interconnect nodes SN2. According to some embodiments, the capacitor connected to the interconnect nodes SN2 can be formed directly in the interlayer dielectric layer 2390.

[0303] According to some embodiments, the layer used for connecting the traces of the second transistor may include a second connection layer. Partial structure 2302 may include the second connection layer, or the second connection layer may be used to connect the second transistor in partial structure 2302.

[0304] The technical solution of the partial structure 2302 formed by the above steps in the embodiments of this application may include, for example, a second transistor layer. The partial structure 2302 can be referred to the relevant description of the embodiments shown in Figures 17A to 17D above, which will not be elaborated here.

[0305] Figures 24A to 24D illustrate schematic diagrams of the manufacturing process of a partial structure of another semiconductor device according to exemplary embodiments of this application.

[0306] As shown in Figures 24A to 24D, other partial structures can be formed on partial structures 2401 and 2402. As an example, partial structures 2401 and 2402 can be partial structures 2301 and 2302 in the embodiment shown in Figure 23 above. In other examples, partial structures 2401 and 2402 can also be partial structures 2201 and 2202 in the embodiment shown in Figure 22 above.

[0307] As shown in Figure 24A, an interlayer dielectric layer 2410 can be formed on a portion of the structure 2402. This interlayer dielectric layer 2410 may include an insulating material, such as an oxide or nitride, which may have a low dielectric constant. An opening 2411 can be formed in the interlayer dielectric layer 2410, connecting to an interconnect node SN2 in the portion of the structure 2402. An opening 2412 is formed on the opening 2411, with its bottom communicating with the opening 2411, and the size of the opening 2412 being larger than the size of the opening 2411. The set of openings formed by the openings 2411 and 2412 can be used to form a capacitor.

[0308] During the manufacturing process, multiple sets of openings can be simultaneously formed in the interlayer dielectric layer 2410 to form multiple capacitors. These openings can also be referred to as trenches. Through a first photolithography and etching process, multiple openings 2411 can be formed in the interlayer dielectric layer 2410. Through a second photolithography and etching process, openings 2412 can be formed above the multiple openings 2411. The dimensions of openings 2411 in the x and / or y directions are smaller than the dimensions of openings 2412 in the x and / or y directions. A set of interconnected openings 2411 and 2412 can expose an interconnect node SN2 in a portion of the structure 2402, allowing the capacitors formed in the openings to connect with the interconnect node SN2. The smaller opening 2411 can be well aligned with the interconnect node SN2 in the portion of the structure 2402, while the larger opening 2412 can be used to form the main structure of the cap pillar. This method not only helps reduce alignment accuracy during manufacturing but also improves the charge storage capacity of the capacitor structure, thereby enhancing the storage and computing performance of the memory cell. In some alternative embodiments, the above steps can also utilize a single photolithography and etching process to form an opening, such as opening 2412, that aligns with interconnect node SN2, and the opening can directly expose interconnect node SN2. In this embodiment, the process steps are simple, which helps reduce manufacturing costs. The capacitor formed under this embodiment can be referred to the relevant description of the embodiment shown in FIG18. Opening 2411 or opening 2412 can penetrate the interlayer dielectric layer 2410 and further penetrate the underlying interlayer dielectric layer, such as interlayer dielectric layer 2390, to expose interconnect node SN2 formed in the lower interlayer dielectric layer, such as interlayer dielectric layer 2380.

[0309] Furthermore, the first electrode structure of the capacitor can be formed within the openings 2411 and 2412.

[0310] As shown in Figure 24B, during the process of fabrication, an electrode layer 2420 can be formed in the openings 2411 and / or 2412 and on the upper surface of the interlayer dielectric layer 2410.

[0311] As shown in Figure 24C, a sacrificial layer 2430 can be formed on the electrode layer 2420, for example, inside the openings 2411 and 2412 and above the interlayer dielectric layer 2410. The sacrificial layer 2430 is then planarized, thereby removing the sacrificial layer and electrode layer located on the upper surface of the dielectric layer 2410. The planarization process can be limited to the interlayer dielectric layer 2410. For example, a portion of the interlayer dielectric layer 2410 can be removed, or it can be left intact. After planarization, the sacrificial layer 2430 and electrode layer 2420 are located inside the openings 2411 and 2412, and this electrode layer 2420 located inside the openings 2411 and 2412 can form the first electrode structure of the capacitor.

[0312] Furthermore, a dielectric layer for forming a capacitor and a second electrode structure can be formed on the interlayer dielectric layer 2410 and the first electrode structure.

[0313] As shown in Figure 24D, during the process of manufacturing, after removing the sacrificial layer material inside the openings 2411 and 2412, a dielectric layer 2440 and an electrode layer 2450 can be formed sequentially inside the openings 2411 and 2412 and on the upper surface of the interlayer dielectric layer 2410.

[0314] Through the above steps, an electrode layer 2420, a dielectric layer 2440, and an electrode layer 2450 within a set of openings 2411 and 2412 can form a capacitor. Multiple sets of openings 2411 and 2412 can form multiple capacitors, thereby forming a capacitor array. The second electrode structure of the multiple capacitors in the capacitor array can be integrally formed through the electrode layer 2420. Optionally, a fill layer 2460 can be formed above the electrode layer 2450. The fill layer 2460 may include an insulating material. However, the embodiments are not limited to this; the fill layer 2460 may include a conductive material and be used to realize the electrical connection between the electrode layer 2450 of the multiple capacitors and an external power supply or ground. According to some embodiments, the electrode layer 2450 and the fill layer 2460 can be integrally formed. In the embodiments of this application, the structure of a single capacitor in the capacitor array can be referred to the relevant description of the embodiment shown in Figure 11 above, which will not be repeated here. The process of the capacitor structure under this embodiment is relatively simple and easy to implement, which is beneficial to improving process efficiency and manufacturing yield.

[0315] Figures 25A to 25E illustrate schematic diagrams of the manufacturing process of a portion of the structure of another semiconductor device according to exemplary embodiments of this application.

[0316] As shown in Figure 25A, a portion of structure 2501 may retain, for example, a second transistor layer. An interlayer dielectric layer 2510 may be formed on the portion of structure 2501. This interlayer dielectric layer 2510 may include an insulating material, such as an oxide or nitride, which may have a low dielectric constant. Multiple sets of openings may be formed in the interlayer dielectric layer 2510 through one or two photolithography and etching processes. Each set of openings may include interconnected openings 2511 and 2512, or only opening 2512. The technical solutions for openings 2511 and 2512 can be found in the descriptions of openings 2411 and 2412 in the embodiments shown in Figures 24A to 24D above.

[0317] As shown in Figure 25B, an electrode layer 2520 is formed within openings 2511 and 2512. This electrode layer 2520 can fill openings 2511 and 2512 and cover the upper surface of the interlayer dielectric layer 2510. The material of this electrode layer 2520 can be the same as the material of the electrode layer 2420 in the above embodiment.

[0318] As shown in Figure 25C, the electrode layer 2520 is planarized by removing part of the electrode layer located on the upper surface of the interlayer dielectric layer 2510, while retaining part of the electrode layer located in the openings 2511 and 2512.

[0319] As shown in Figure 25D, the interlayer dielectric layer 2510 is etched. The height of the etched portion in the stacking direction (e.g., the z-direction) can be the same as the height of the opening 2512 in the stacking direction. After etching, the height of the interlayer dielectric layer 2510 in the stacking direction can be the same as the height of the opening 2511 in the z-direction. In the current state, multiple electrode structures 2521 can be formed on the interlayer dielectric layer 2510.

[0320] As shown in Figure 25E, a dielectric layer 2530 and an electrode layer 2540 can be sequentially formed above multiple electrode structures 2521. The material of the dielectric layer 2530 can be the same as the material of the dielectric layer 2440 in the previous embodiment, and the material of the electrode layer 2540 can be the same as the material of the electrode layer 2450 in the previous embodiment. The multiple electrode structures 2521, dielectric layer 2530, and electrode layer 2540 can form a capacitor array consisting of multiple capacitors. Optionally, a filler layer 2550 can be further formed above the electrode layer 2540. The filler layer 2550 can be referred to the description of the filler layer 2460. In the embodiments of this application, the structure of a single capacitor in the capacitor array can be referred to the relevant description of the embodiment shown in Figure 13 above, and will not be elaborated further here.

[0321] The top electrodes (electrodes formed by electrode layer 2540) of adjacent capacitors are opposite each other. The top electrodes can be connected to the same power supply or ground through the filling layer 2550. The top electrodes are equivalent to shielding layers that can shield signal crosstalk between adjacent capacitors.

[0322] Figures 26A to 26E show schematic diagrams of a partial structure of another semiconductor device according to an exemplary embodiment of the present application.

[0323] As shown in Figure 26A, a portion of structure 2601 may retain, for example, a second transistor layer. An interlayer dielectric layer 2610 may be formed on the portion of structure 2601. Through one or two photolithography and etching processes, multiple sets of openings can be formed in the interlayer dielectric layer 2610. Each set of openings may include interconnected openings 2611 and 2612, or may only include opening 2612. The technical solution for this step can be found in the description of the embodiment shown above.

[0324] As shown in Figure 26B, an electrode layer 2620 can be formed inside the openings 2611 and 2612 and on the upper surface of the interlayer dielectric layer 2610. The material of the electrode layer 2620 can be the same as the material of the electrode layer 2420 in the above embodiment.

[0325] As shown in Figure 26C, after the electrode layer 2620 is formed, a sacrificial layer 2630 can be formed inside the openings 2611 and 2612 and above the interlayer dielectric layer 2610.

[0326] As shown in Figure 26D, planarizing the sacrificial layer 2630 removes a portion of the sacrificial layer and a portion of the electrode layer located on the upper surface of the interlayer dielectric layer 2610. After planarization, the sacrificial layer material is located inside openings 2611 and 2612. Etching the interlayer dielectric layer 2610 allows the height of the etched portion in the stacking direction (e.g., the z-direction) to be the same as the height of opening 2612 in the stacking direction. After etching, the height of the interlayer dielectric layer 2610 in the stacking direction is the same as the height of opening 2611 in the stacking direction. In the current state, multiple electrode structures 2621 can be formed on the interlayer dielectric layer 2610. Each electrode structure 2621 includes two interconnected groove substructures, the interior of which is filled with sacrificial material.

[0327] As shown in Figure 26E, after removing the sacrificial material inside the electrode structure 2621, a dielectric layer 2640 and an electrode layer 2650 can be sequentially formed above the multiple electrode structures 2621. The material of the dielectric layer 2640 can be the same as the material of the dielectric layer 2440 in the previous embodiment, and the material of the electrode layer 2650 can be the same as the material of the electrode layer 2450 in the previous embodiment. The multiple electrode structures 2621, dielectric layer 2640, and electrode layer 2650 can form a capacitor array consisting of multiple capacitors. Optionally, a fill layer 2660 can be further formed above the electrode layer 2650. The fill layer 2660 may include a conductive material and is used to realize the electrical connection between the electrode layer 2650 of the multiple capacitors and an external power supply or ground. In the embodiments of this application, the structure of a single capacitor in the capacitor array can be referred to the relevant description of the embodiment shown in Figure 12 above, and will not be repeated here.

[0328] The materials used in the structures described in the embodiments of this application can be applied to corresponding structures in other embodiments.

[0329] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0330] The positional relationships of the elements, features, or structures shown in the above-described embodiments are for illustrative purposes only. The elements, features, or structures shown in the figures do not necessarily mean that they are at substantially the same height in a certain direction in the device, or necessarily exist in a single cross section of the device, simply because they are shown in the figures.

[0331] This application also provides a storage device, as shown in FIG27. FIG27 illustrates a schematic diagram of a storage device according to an exemplary embodiment of this application. As shown in FIG27, the storage device 2700 includes a storage circuit 2710 and a control circuit 2720, wherein the control circuit 2720 is configured to control the operating state of the storage circuit 2710; wherein the storage circuit 2710 may include a semiconductor device in any of the embodiments described above, or the semiconductor device in the storage circuit 2710 may be manufactured using the manufacturing method of any of the embodiments described above.

[0332] This application also provides an electronic device, as shown in FIG28. FIG28 illustrates a schematic diagram of an electronic device according to an exemplary embodiment of this application. As shown in FIG28, the electronic device 2800 may include a storage device 2810 for storing / processing data of the electronic device. The storage device 2810 may include a semiconductor device in any of the embodiments described above, or the semiconductor device in the storage device 2810 may be manufactured using the manufacturing method of any of the embodiments described above.

[0333] The electronic device may further include an input / output device 2820 for receiving user input or outputting processing results. This application does not limit the input and output types; for example, input may include voice input, text input, image input, or video input. Output may include text output, voice output, image output, or video output. The electronic device may also include a processor 2830, which can process data provided to the storage device 2810 or process output data from the storage device 2810. The output of the input / output device 2820 may be based on the output of the processor 2830 or the output of the storage device 2810.

[0334] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0335] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A semiconductor device, characterized in that, include: First transistor array; A second transistor array is formed on top of the first transistor array; A capacitor array is formed on top of the second transistor array; A first trace, a second trace, and a first interconnect node, wherein the first trace extends along a first direction and connects to the first terminals of a plurality of first transistors arranged along the first direction in the first transistor array; the second trace extends along a second direction and connects to the second terminals of a plurality of first transistors arranged along the second direction in the first transistor array; and the first interconnect node is connected to the first driving terminal of a first transistor in the first transistor array. A third trace, a fourth trace, and a second interconnect node, wherein the third trace extends along a third direction and connects to the second driving terminals of a plurality of second transistors arranged along the third direction in the second transistor array; the fourth trace extends along a fourth direction and connects to the fourth terminals of a plurality of second transistors arranged along the fourth direction in the second transistor array; and the second interconnect node is connected to the first interconnect node, the third terminal of a second transistor in the second transistor array, and the first electrode structure of a capacitor in the capacitor array.

2. The semiconductor device according to claim 1, characterized in that, include: The first device layer includes the first transistor array; A first connection layer is formed on top of the first device layer and includes the first trace, the second trace, and the first interconnect node. The first trace and the second trace are located in different sub-layers of the first connection layer, and either the first trace or the second trace is located in the same sub-layer as the first interconnect node.

3. The semiconductor device according to claim 1 or 2, wherein include: The second device layer includes the second transistor array, wherein the second driving terminals of a plurality of second transistors arranged along the third direction are integrally formed into the third trace extending along the third direction.

4. The semiconductor device according to claim 3, wherein Also includes: The second connection layer includes the second interconnect node.

5. The semiconductor device according to claim 4, wherein The second connection layer also includes the fourth trace, which is located on the same layer as the second interconnect node.

6. The semiconductor device according to claim 4 or 5, wherein include: The third device layer includes the capacitor array and at least one interlayer dielectric layer, the at least one interlayer dielectric layer including a first interlayer dielectric layer formed on the second interconnect layer, the fourth trace formed in the first interlayer dielectric layer, and at least a portion of the capacitors of the capacitor array formed in the first interlayer dielectric layer.

7. The semiconductor device according to any one of Claims 1 to 6, wherein The first transistor array includes multiple first transistor pairs; wherein, in a first transistor pair, two first transistors share a first terminal, and the second terminals of the two first transistors are located on both sides of the shared first terminal.

8. The semiconductor device according to claim 7, wherein The plurality of first transistor pairs are arranged along the second direction, and the second terminals of the two first transistors in a first transistor pair are located on both sides of the first terminal shared by the two first transistors along the first direction.

9. The semiconductor device according to claim 7 or 8, characterized in that, The semiconductor device includes multiple second trace pairs, each second trace pair corresponding to a first transistor pair. The second terminals of the first transistors in a first transistor pair are respectively connected to different second traces in the corresponding second trace pairs. Electrical connection structure pairs are formed between the second traces in a second trace pair, corresponding to a first interconnect node pair. One electrical connection structure in the electrical connection structure pair connects the first driving terminal of the first transistor in the corresponding first transistor pair to the first interconnect node in the corresponding first interconnect node pair. The other electrical connection structure connects the first driving terminal of the other first transistor in the corresponding first transistor pair to the other first interconnect node in the corresponding first interconnect node pair.

10. The semiconductor device according to any one of claims 7 to 9, characterized in that, The semiconductor device includes a plurality of first trace pairs, wherein a first interconnect node pair is formed between two first trace pairs, and the two first interconnect nodes in the first interconnect node pair are respectively connected to the first driving terminals of different first transistors in a first transistor pair.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that, The second transistor array includes multiple second transistor pairs; In one pair of second transistors, the two second transistors share a fourth terminal or the conductive structure corresponding to the fourth terminal, and the second driving terminals of the two second transistors are located on both sides of the shared fourth terminal or the conductive structure corresponding to the fourth terminal.

12. The semiconductor device according to claim 11, characterized in that, The plurality of second transistor pairs are arranged along the third direction, and the second driving terminals of the two second transistors in a second transistor pair are located on both sides of the fourth terminal shared by the two second transistors or the conductive structure corresponding to the fourth terminal along the fourth direction.

13. The semiconductor device according to claim 11 or 12, wherein The semiconductor device includes a third trace pair, wherein the second drive terminals of two second transistors in a second transistor pair are respectively connected to different third traces in the third trace pair, and in a plurality of second transistor pairs arranged along the third direction, the second drive terminals of the second transistors located in the same row along the third direction are connected to the same third trace.

14. The semiconductor device according to any one of claims 11 to 13, characterized in that, The semiconductor device includes a plurality of second interconnect node pairs, wherein two second interconnect nodes in the second interconnect node pairs are respectively connected to the third terminals of different second transistors in a second transistor pair, and the plurality of second interconnect node pairs include a first row of second interconnect nodes and a second row of second interconnect nodes arranged in the fourth direction, wherein a fourth trace is formed between the first row of second interconnect nodes and the second row of second interconnect nodes.

15. A method of manufacturing a semiconductor device, characterized by include: Form the first transistor array; A first trace, a second trace, and a first interconnect node are formed, wherein the first trace extends along a first direction and connects to the first terminals of a plurality of first transistors arranged along the first direction in the first transistor array; the second trace extends along a second direction and connects to the second terminals of a plurality of first transistors arranged along the second direction in the first transistor array; and the first interconnect node is connected to the first driving terminal of a first transistor in the first transistor array. A second transistor array is formed on the first transistor array; A third trace, a fourth trace, and a second interconnect node are formed, wherein the third trace extends along a third direction and connects to the second driving terminals of a plurality of second transistors arranged along the third direction in the second transistor array; the fourth trace extends along a fourth direction and connects to the fourth terminals of a plurality of second transistors arranged along the fourth direction in the second transistor array; and the second interconnect node is connected to the first interconnect node and the third terminal of a second transistor in the second transistor array. A capacitor array is formed on the second transistor array, and the first electrode structure of one capacitor of the capacitor array is connected to the second interconnect node.

16. A memory device, comprising: include: The storage circuit includes the semiconductor device as described in any one of claims 1 to 14; The control circuit is configured to control the operating state of the storage circuit.

17. An electronic device, comprising: Includes the storage device as described in claim 16.

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