Non-volatile magnetoelectric spin-orbit memory with magnon current

Abstract

Described herein is a magnetoelectric spin-orbit device, comprising a first spin-orbit layer, a magnetoelectric layer positioned above the first spin-orbit layer, and a second spin-orbit layer positioned above the magnetoelectric layer. Also described herein is a memory array comprising a plurality of magnetoelectric spin-orbit devices.

Description

Attorney Docket No: 206595-0001-00WONON-VOLATILE MAGNETOELECTRIC SPIN-ORBIT MEMORY WITH MAGNON CURRENTCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U. S. Provisional Patent Application No. 63 / 727,485, filed on December 3, 2024, the contents of which are incorporated by reference herein in its entirety.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under Contract No. DE-AC02-05CH11231 awarded by the U. S. Department of Energy, Contract No. 2329111 awarded by the National Science Foundation and Grant No. W911NF2420100 awarded by the U. S. Department of Defense, Army Research Laboratory. The government has certain rights in the invention.BACKGROUND OF THE INVENTION

[0003] Spin-based devices such as spin transfer torque (STT) or spin-orbit torque (SOT) driven magnetic random-access memories (MRAMs) are examples of non-volatile memories, where the information can be stored for years without requiring power to refresh. In contrast, charge-based static or dynamic random-access memories (SRAM or DRAM) must remain powered on at all times, consuming significant amounts of energy (around 70% of its total energy). However, these charge-based memories are still popular due to their compatibility with today’s electronics and the perception that they have no viable alternatives. MRAMs, though non-volatile, still fall short in terms of energy consumption and information transfer speed compared to charge-based memories. To address this issue, a recently proposed device architecture known asAttorney Docket No: 206595-0001-00WOmagnetoelectric spin-orbit (MESO) logic based on magnetoelectric material such as BiFeO3, has shown significant potential for energy-efficient logic computation.

[0004] The scaling of CMOS energy efficiency is fundamentally limited by the Boltzmann tyranny (-0.4V thermal voltage barrier) and the slowdown of Moore’s Law, intensifying interest in spintronic devices for their low-power and non-volatility. By enabling in-memory computing, these devices have shown potential for reducing data transfer energy at the architectural level. However, most spintronic memories, including spin-transfer-torque (STT) and spin-orbit-torque (SOT)- Magnetic Random Access Memory (MRAM), still rely on current-driven magnetic switching, resulting in substantial energy loss due to Joule heating (Worledge, Daniel C. et al., ’’Spin-transfer torque magnetoresistive random access memory technology status and future directions,” Nature Reviews Electrical Engineering, vol. 1, no. 11, pp. 730-747, 2024.; Sato, Noriyuki et al., ”Two-terminal spin-orbit torque magnetoresistive random access memory,” Nature Electronics, vol. 1, no. 9, pp. 508-511, 2018.)

[0005] To overcome the energy-loss limitations of charge-driven spintronics, recent work has been relying on magnons (quantized spin waves) that carry angular momentum without charge motion, thereby avoiding Joule heating. Experiments demonstrate that magnons propagate with minimal dissipation in synthetic antiferromagnets (AFM) (Millo, F. et al., ’’Unidirectionality of spin waves in Synthetic Antiferromagnets,” Physical Review Applied, vol. 20, no. 5, pp. 054051, 2023.) and that their populations can be detected electrically via thermal spin-wave noise (Devolder, T. et al., ’’Measuring a population of spin waves from the electrical noise of an inductively coupled antenna,” Physical Review B, vol. 105, no. 21, pp. 214404, 2022.), confirming their promise for low-energy-loss information transfer. However, conventional magnonic devices are volatile (Balinskyy, Mykhaylo et al., ’’Magnonic combinatorial memory,” npj Spintronics, vol. 2, no. 1, pp. 1-11, 2024.), since information is encoded in the phase and amplitude of spin waves.

[0006] Voltage-controlled magnetoelectric spin-orbit (MESO) transducers, which use ferromagnetic (FM) composites and magnetoelectric (ME) thin films (Manipatruni, Sasikanth et al., ’’Scalable energy-efficient magnetoelectric spin-orbit logic,” Nature, vol. 565, no. 7737, pp.35-42, 2019.; Vaz, Diogo C. et al., ’’Functional Demonstration of a Fully Integrated Magneto-Attorney Docket No: 206595-0001-00WOElectric Spin-Orbit Device,” 2021 IEEE International Electron Devices Meeting (IEDM), pp. 32.4.1-32.4.4, 2021.), address volatility through the ferroelectricity of the ME layer, enabling non-volatile memory and logic operations. Moreover, electric-field-driven spin-wave excitation and detection render these devices compatible with CMOS platforms (Liao, Yu-Ching et al., ’’Evaluating the Performances of the Ultralow Power Magnetoelectric RandomAccess Memory With a Physics-Based Compact Model of the Antiferromagnet / Ferromagnet Bilayer,” IEEE Transactions on Electron Devices, vol. 69, no. 5, pp. 2331-2337, 2022.; Narla, Siri et al., ’’CrossLayer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search,” IEEE Transactions on Electron Devices, vol. 72, no. 1, pp. 240-246, 2025.). However, the complicated design, which includes ferromagnetic elements (limited by the spin polarization, leading to a 30-40% spin or energy loss at the input current), and the high error rate (due to weak antiferromagnetic exchange coupling between ferromagnet and antiferromagnetic BiFeO3) limit its efficiency for future integration into non-volatile memory (Nature, 565(7737), 2019, Nat Commun 15, 1902 (2024)). Thus, conventional MESO devices suffer from limited endurance at the FM-ME interface, restricting their practical use in logic circuits.

[0007] Thus, there is a need in the art for a novel magnetoelectric spin-orbit device that eliminates the need for ferromagnetic materials and uses the magnetic quasiparticle to encode the information in a non-volatile manner with an improved read / write process.SUMMARY OF THE INVENTION

[0008] Described herein is a magnetoelectric spin-orbit (MESO) device, comprising a first spinorbit layer, a magnetoelectric layer positioned above the first spin-orbit layer, and a second spinorbit layer positioned above the magnetoelectric layer. In some embodiments, the MESO device further comprises a first interconnect electrically connected to the first spin-orbit layer and a second interconnect electrically connected to the second spin-orbit layer. In some embodiments, the interconnects are configured to couple the first or second spin-orbit layers to a differential input voltage, a differential output voltage, a power supply, or a ground connection.Attorney Docket No: 206595-0001-00WO

[0009] In some embodiments, the first and second spin-orbit layer have a spin Hall angle ranging between 0.1 and 20. In some embodiments, the first and second spin-orbit layers comprise one or more heavy metals and one or more topological insulators. In some embodiments, the one or more heavy metals comprise platinum, tantalum, tungsten, palladium, tellurium, or iridium. In some embodiments, the one or more topological insulators comprise bismuth, antimony, selenium, or tellurium. In some embodiments, the magnetoelectric layer comprises an antiferromagnet. In some embodiments, the magnetoelectric layer comprises BiFeO3. In some embodiments, the magnetoelectric layer further comprises a rare earth ion selected from lanthanum, samarium or neodymium. In some embodiments, the first spin-orbit layer is configured to convert an electric current to a spin polarized current in the magnetoelectric layer. In some embodiments, the second spin-orbit layer is configured to convert a spin polarized current in the magnetoelectric layer to an electric current. In some embodiments, the magnetoelectric layer has an antiferromagnetic state. In some embodiments, the antiferromagnetic state is set or switched via the application of a differential input voltage across the magnetoelectric layer. In some embodiments, the MESO device is a non-volatile memory element.

[0010] Also disclosed herein is a memory device comprising a plurality of magnetoelectric spin-orbit (MESO) devices, each comprising a first spin-orbit layer, a magnetoelectric layer positioned above the first spin-orbit layer, and a second spin-orbit layer positioned above the magnetoelectric layer, a read line coupled to the first spin-orbit layer of a first subset of the MESO devices, a write line coupled to the second spin-orbit layer of a second subset of the MESO devices, and a source line coupled to the first spin-orbit layer of a third subset of MESO devices. In some embodiments, the memory device may have a 0T1R configuration, a 1T1R configuration, A 2T1R configuration, or be configured to have separate sets of read and write lines. In some embodiments, the memory device further comprises a plurality of transistors connected between the second spin-orbit layer and the read or write lines. In some embodiments, the memory device further comprises a second read line and a second write line.

[0011] Also disclosed herein is a method of writing a data bit to a magnetoelectric spin-orbit (MESO) memory, comprising providing a MESO memory, comprising a first spin-orbit layer, a magnetoelectric layer positioned above the first spin-orbit layer, and a second spin-orbit layerAttorney Docket No: 206595-0001-00WOpositioned above the magnetoelectric layer, applying a differential voltage input across the first and second spin-orbit layers to set the memory state of the magnetoelectric layer, applying a constant current across the first spin-orbit layer to generate a voltage output across the second spin-orbit layer, wherein the voltage output corresponds to the memory state of the magnetoelectric layer, and measuring the voltage output.BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The foregoing purposes and features, as well as other purposes and features, will become apparent with reference to the description and accompanying figures below, which are included to provide an understanding of the invention and constitute a part of the specification, in which like numerals represent like elements, and in which:

[0013] Fig 1 depicts a schematic of an exemplary magnetoelectric spin-orbit (MESO) device.

[0014] Fig. 2A depicts an equivalent circuit model illustrating the operating process of the exemplary MESO device.

[0015] Fig. 2B depicts an equivalent spin Hall effect circuit module, with a charge circuit (terminal 1 and terminal 2) and a spin circuit (terminal 3 to terminal 4).

[0016] Fig. 3 A depicts a schematic showing the writing operation for an exemplary 1T1R MESO memory array.

[0017] Fig. 3B depicts a schematic showing the reading operation for an exemplary 1T1R MESO memory array.

[0018] Fig. 4A depicts a schematic showing the writing and reading operations for an exemplary 0T1R MESO memory array.

[0019] Fig. 4B depicts a schematic showing an exemplary 2T1R MESO memory array.

[0020] Fig. 5A depicts a schematic showing the writing operation for an exemplary MESO memory array with separate read and write electrodes.Attorney Docket No: 206595-0001-00WO

[0021] Fig. 5B depicts a schematic showing the reading operation for an exemplary MESO memory array with separate read and write electrodes.

[0022] Fig. 6A depicts a plot showing the output voltage of a MESO device vs. spin Hall angles for different resistivities.

[0023] Fig. 6B depicts a plot showing the output voltage of a MESO device vs. resistivity for different spin Hall angles.

[0024] Fig. 7 depicts a plot showing resistivity vs. spin Hall angles of two exemplar spin-orbit materials, as well as a curve representing the required relation spin-Hall-angles vs. resistivity.

[0025] Fig. 8A depicts a schematic of an exemplary MESO device.

[0026] Fig. 8B depicts a plot showing ferroelectric (leakage current and polarization-electric field hysteresis) response of the BLFO layer.

[0027] Fig. 8C depicts a cross-sectional scanning transmission electron microscopy image of the different layers of the exemplary MESO device.

[0028] Fig. 8D depicts a cross-sectional scanning transmission electron microscopy image of the bottom interface between the SIO and the BLFO layer of an exemplary MESO device.

[0029] Fig. 8E depicts a cross-sectional scanning transmission electron microscopy image of the top interface between the SIO and the BLFO layer of an exemplary MESO device.

[0030] Fig. 8F depicts a schematic showing the spin-charge conversion response of the SIO and BLFO layers, and the magnon transport process in the BLFO layer.

[0031] Fig. 9A depicts a schematic showing the write process and measurement of inverse spin Hall voltage in the MESO device during the read process.

[0032] Fig. 9B depicts a plot showing the deterministic switching of the inverse spin-Hall voltage.Attorney Docket No: 206595-0001-00WO

[0033] Fig. 9C depicts a plot showing the non-volatile response of the MESO device in two opposite polar states.

[0034] Fig. 10A depicts a plot showing the inverse spin Hall effect (ISHE) voltage vs. time.

[0035] Fig. 10B depicts a plot showing the differential ISHE voltage as a function of injected AC pulse from the hysteresis data.

[0036] Fig. 10C depicts a plot showing the differential voltage recorded with varying pulse voltage width.

[0037] Fig. 11 depicts a plot showing the magnon output voltage as a function of spacing between the SIO injector and detector. The vertical device data is compared with the lateral devices and resonance-based measurements (triangles and spheres). The green (star) data points are taken from published MESO device data.

[0038] Fig. 12 depicts a plot showing the output current and output voltage when the aspect ratios of the layers are varied.

[0039] Fig. 13 depicts an exemplary computing environment in which aspects of the present disclosure may be practiced.

[0040] Fig. 14A depicts an exemplary device structure comprising an SO coupling layer, ME layer, and interconnections. Fig. 14B depicts an exemplary operating mechanism for the device. The device state is defined as S=1 for the low-resistance state (LRS) and S=0 for the high-resistance state (HRS). Fig 14C depicts the two operating modes of the device, reading the stored state and writing a new state by applying voltages.

[0041] Fig. 15A is a schematic of a SrIrO3 (SIO) / La-BiFeO3 (LBFO) / SrIrO3 (SIO) trilayer device and high resolution cross-sectional TEM image and vector polarization mapping. Fig. 15B is a plot showing the ferroelectric (polarization-electric field hysteresis) response of LBFO from the SIO / LBFO / SIO trilayer. Fig. 15C is a plot showing the first harmonic measurement of output voltage VISHEas a function of switch voltage.Attorney Docket No: 206595-0001-00WO

[0042] Fig. 16A depicts an equivalent circuit model illustrating the processes from bottom to top: spin Hall effect, magnon transport, and inverse spin Hall effect. Fig. 15b depicts a simplified circuit model showing the control signal VG, supply current ID, and output voltage V0. Fig. 16C depicts an equivalent small-signal circuit model.

[0043] Fig. 17A is a plot showing the comparison between simulation results and experimental data, extracted from the peak-to-peak voltage in the hysteresis loop. Fig. 17B is a plot showing the comparison of simulation results with previous studies.

[0044] Fig. 18A is a plot showing the spin Hall angle sweep for both the top and bottom layers, showing output voltage contours. Fig. 18B is a plot showing the electrical resistivity sweeping for bottom and top layers, showing output voltage contours. Fig. 18C is a plot showing the scalability analysis showing the impact of spin-orbit layer thickness on output voltage. Fig. 18D is a plot showing the relationship between ME layer thickness and output voltage. Fig. 18E is a plot showing the simulated switching energy results based on the model demonstrating the potential to achieve ultra-low energy operation, reaching the attajoule range.

[0045] Fig. 19A depicts a 1T1R memory array design. Fig. 19B depicts the writing and reading operating waveforms.

[0046] Fig. 20A depicts an inverter chain design for a logic gate. Fig. 20B depicts the operating waveforms for the inverter chain design. Fig. 20C depicts a majority gate logic realizing logic-inmemory.

[0047] Fig. 21A depicts an inverter chain design for a logic gate, each cell storing the same bit as the output. Fig. 21B depicts the operating waveforms. Fig. 21C depicts an OR / NAND gate logic.DETAILED DESCRIPTION

[0048] The following discussion omits or only briefly describes conventional features of magnetoelectric spin-orbit (MESO) devices and memory devices that are apparent to those skilled in the art. Those of ordinary skill in the pertinent arts may thus recognize that other elements may be desirable and / or necessary to implement the devices, systems, and / or methodsAttorney Docket No: 206595-0001-00WOdescribed herein. It is noted that various embodiments are described in detail with reference to the drawings. Reference to these various embodiments does not limit the scope of the claims attached hereto. Additionally, any embodiments set forth in this specification are intended to be non-limiting and merely set forth some of the many possible implementations for the appended claims. Further, particular features described herein can be used in combination with other described features in each of the various possible combinations and permutations. As such, it is understood that this detailed description is exemplary and explanatory only and is not restrictive of the broad inventive concepts upon which the embodiments disclosed herein are based.

[0049] Unless otherwise specifically defined herein, all terms are to be given their broadest reasonable interpretation. This includes meanings implied from the specification as well as meanings understood by those skilled in the art and / or as defined in dictionaries, treatises, etc.

[0050] It is noted that, as used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless otherwise specified. The term “includes” and / or “including,” when used in this specification, specify the presence of stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0051] Relative terms such as “horizontal,” “vertical,” “up,” “down,” “top,” and “bottom” as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then-described or as shown in the drawing figure under discussion. These relative terms are for convenience of description and normally are not intended to require a particular orientation in actuality. Terms including “inwardly” versus “outwardly,” “longitudinal” versus “lateral,” and the like are to be interpreted relative to one another or relative to an axis of elongation, or an axis or center of rotation, as appropriate. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise. The phrases “operatively” or “operably connected” indicates such an attachment, coupling, or connection that allows the pertinent structures to operate as intended by virtue of that relationship.Attorney Docket No: 206595-0001-00WO

[0052] Reference throughout the specification to “one embodiment,” “an embodiment,” or “some embodiments” means that a particular feature, structure, or characteristic described in connection with at least one example of the subject matter is included in at least one example of the subject matter disclosed. Thus, the appearance of the phrases “in one embodiment,” “in an embodiment,” or “in some embodiments” in various places throughout the specification is not necessarily referring to the same embodiment. Further, the particular features, structures, or characteristics of “one embodiment,” “an embodiment,” or “some embodiments” may be combined in any suitable manner with each other to form additional embodiments of such combinations. It is intended that embodiments of the disclosed subject matter cover modifications and variations thereof. Terms such as “first,” “second,” “third,” etc., merely identify one of a number of portions, components, steps, operations, functions, and / or points of reference as disclosed herein, and likewise to not necessarily limit embodiments of the present disclosure to any particular configuration or orientation.

[0053] Moreover, throughout this disclosure, various aspects can be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the disclosure. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as individual numbers within that range, for example, 1, 2, 2.7, 3, 4, 5, 5.3, 6, and any whole and partial increments therebetween. This applies regardless of the breadth of the range. As used herein, the term “about” in reference to a measurable value, such as an amount, a temporal duration, and the like, is meant to encompass the specified value variations of plus or minus 20%, plus or minus 10%, plus or minus 5%, plus or minus 1%, and plus or minus 0.1% of the specified value, as such variations are appropriate and fit within the confines of a functional system.

[0054] The terms “proximal,” “distal,” “anterior,” “posterior,” “medial,” “lateral,” “superior,” and “inferior” are defined by their standard usage indicating a directional term of reference. For example, “proximal” refers to a position that is situated nearer to the center of a body or point ofAttorney Docket No: 206595-0001-00WOattachment or interest. In another example, “anterior” refers to the front of a body or structure, while “posterior” refers to the rear of a body or structure, in relation to a relative viewpoint. In another example, “medial” refers to the direction towards the midline of a body or structure, and “lateral” refers to the direction away from the midline of a body or structure. In some embodiments, “lateral” or “laterally” may refer to any sideways direction. In another example, “superior” refers to the top of a body or structure, while “inferior” refers to the bottom of a body or structure. It should be understood, however, that the directional term of reference may be interpreted within the context of a specific body or structure, such that a directional term referring to a location in the context of the reference body or structure may remain consistent as the orientation of the body or structure changes.

[0055] Described herein is a magnetoelectric spin-orbit (MESO) device utilizing direct magnon-driven sensing in an insulating antiferromagnet. The disclosed device leverages the strong spinorbit coupling of spin Hall metals to achieve large output voltages through spin-charge conversion. The novel MESO device is a non-volatile magnetic memory capacitive element, employing a simple geometric configuration, and is therefore a promising alternative to existing memory technologies. Also described herein are memory arrays comprising the MESO devices. The novel MESO memory arrays are capable of reducing power consumption of memory devices, and are operable at lower voltages, reducing the energy and voltage requirements of conventional memory systems.

[0056] Referring now to Fig. 1, shown is an exemplary single-cell magnetoelectric spin-orbit (MESO) device 100 (also referred to herein as a magnetoelectric magnonic memory (MEMM) device). The device 100 comprises a first spin-orbit (SO) layer 102, a magnetoelectric (ME) layer 104 positioned above the first spin-orbit layer 102, and a second spin-orbit layer 106 positioned above the magnetoelectric layer 104. Referring now to Fig. 2A, each layer has a length 116, a width 118, and a thickness (a thickness 120 of the first spin-orbit layer is depicted in Fig. 2A), which may be the same for all layers, or which may differ for each layer. In some embodiments, the device 100 further comprises interconnects 108, 110 positioned at each end of the first SO layer 102, and interconnects 112, 114 positioned at each end of the second SO layer 106. The device 100 may further comprise any number of additional interconnects. The interconnects may be configured to couple any one of layers 102, and / or 106 to any one of aAttorney Docket No: 206595-0001-00WOsupply voltage, a differential input voltage, a differential output voltage, a power supply, a ground connection, a signal input, for example a write signal, a signal output, for example a read signal, and / or a clock signal, as would be understood by those skilled in the art.

[0057] In some embodiments, the first spin-orbit layer 102 has a length of about 10 - 150 pm, a width of about 0.1 - 5 pm, and a thickness of about 1 - 20 nm. In some embodiments, the second spin-orbit layer 106 has length of about 10 - 150 pm, a width of about 0.1 - 5 pm, and a thickness of about 1 -20 nm. In some embodiments, the magnetoelectric layer 104 has a length of about 10 - 150 pm, a width of about 0.1 - 5 pm, and a thickness of about 1 - 100 nm. In some embodiments, the lengths and widths of each layer may be the same, or each layer may have different lengths and widths. In some embodiments, the first spin-orbit layer 102, the second spin-orbit layer 106, and the magnetoelectric layer 104 have an aspect ratio, defined herein as length / width. In some embodiments, the aspect ratio may range between 0.01 and 100. Fig. 12 depicts the corresponding changes in output current and voltage when the aspect ratios of the layers 102, 104, and 106 (where the layers have equal aspect ratios) are varied.

[0058] In some embodiments, the first spin orbit layer 102 is configured to convert an electric current into a spin polarized current via the spin Hall effect (SHE). Fig. 2B depicts an equivalent circuit model showing the directions of electric current and the spin polarized current. In some embodiments, the magnetoelectric layer 104 is configured to transport the spin current across the magnetoelectric layer 104. At the interface between the first spin orbit layer 102 and the magnetoelectric layer 104, spin waves (or magnons) are generated which travel across the magnetoelectric layer 104 to the second spin-orbit layer 106. In some embodiments, the second spin orbit layer 106 is configured to convert a spin polarized current to an electric current via the inverse spin Hall effect (ISHE).

[0059] In some embodiments, when a differential input voltage is between the first spin-orbit layer 102 and the second spin-orbit layer 106 102 through interconnects 108 (or 110) and 112 (or 114), an electric field is generated in the vertical direction which sets or switches the antiferromagnetic state of the magnetoelectric layer 104 via magnetoelectric coupling. The antiferromagnetic state of the magnetoelectric layer 104 is retained even after the switch voltage is removed. In some embodiments, the differential voltage across the magnetoelectric layer mustAttorney Docket No: 206595-0001-00WOexceed a threshold value to set or switch the antiferromagnetic state of the magnetoelectric layer 104. In some embodiments, the differential input voltage may range between 50 mV and 2V.

[0060] In some embodiments, when a supply current is applied through the interconnects 108, 110 across the first SO layer 102, a spin polarized current is generated in first spin-orbit layer 102. The spin current is transported through the magnetoelectric layer 104 to the second spinorbit layer. At the interface between the magnetoelectric layer 104 and the second spin orbit layer 106, the spin current is converted to an electric charge current. An electric charge current is therefore produced in the transverse direction (e.g. parallel to length 116) towards or away from the interconnects 112, 114, which may therefore serve as an output of the MESO device 100. In some embodiments, the voltage output corresponds to the antiferromagnetic state of the magnetoelectric layer 104.

[0061] In some embodiments, the input voltage differential and a supply charge current may be provided during separate operations implemented at different times. For example, providing an input voltage differential may correspond to a write operation that sets the antiferromagnetic state of the magnetoelectric layer 104. In some embodiments, providing a supply charge current may correspond to a read operation that produces an output voltage differential associated with the antiferromagnetic state of the magnetoelectric layer 104 established during the write operation.

[0062] In some embodiments, the first and second spin-orbit (S-O) coupled metal layers 102, 106 may comprise any material known to those skilled in the art that have a high spin-to-charge conversion efficiency. This may include materials having a high spin Hall angle or a suitable electrical resistivity. In some embodiments, the first and S-0 metal layers may comprise heavy metals that may include platinum (Pt), tantalum (Ta), tungsten (W), palladium (Pd), silver (Au), tellurium (Te), iridium (Ir) or any alloys thereof (for example, W(O), Pt75Pd25, Pt75Au25, Pt3(MgO)3, Ta10Au9O, WTe2, or IrO2). In some embodiments, a topological insulator may be utilized, such as materials including bismuth, antimony, or alloys and combinations thereof. Other materials that are suitable may include perovskites or double perovskites (such as Sr2IrO4,YBCO, PrBCO), spinels (such as vanadates, Co3O4), pyrochlores (such as iridates, Tb2Ir2O7, Pb2Ir2O7, Bi2Ir2O7), hexaferrites (such as delafossite ABO2, PtCoO2), TMDs andAttorney Docket No: 206595-0001-00WOintermetallics (such as Fe-Ge-Te, Mn-Si, Fe-Si), amorphous alloys (such as Gd-BiSe, Fe-Si, Co-Si), perovskite topological insulators (such as YBiO3), and any combinations thereof. In some embodiments, orbital Hall metals may be utilized (such as RuO2, BaPbBiO3, or IrO2). In some embodiments, orbital Hall metals may help in the enhancement of the spin charge conversion effect. This may include low spin orbit coupled metals such as oxides BaBiPbO3. BaPbO3, BaBiO3, and metal multilayers including Cr, Cu, NiFe, Ir, V where the spin-charge interconversion process is governed by the orbital angular momentum. These materials have advantages that may include large spin-orbit coupling, orbital ordering, tunable conductivities, topological behavior, large spin Hall effects, or high spin-to-charge efficiency.

[0063] In some embodiments, the magnetoelectric layer 104 comprises an antiferromagnet. In some embodiments, the magnetoelectric layer 104 comprises bismuth, iron, and oxygen (for e.g. BiFeO3). In some embodiments, the magnetoelectric layer 104 further comprises a rare earth ion. Examples of rare earth ions may include, but are not limited to, lanthanum, samarium and neodymium.

[0064] In some embodiments, the MESO device 100 may be implemented as a memory array, for example comprising a plurality of MESO devices 100 arranged in an array or cascaded. It should therefore be understood that in some embodiments the output voltage difference between two states of one MESO device must be sufficiently high enough to exceed the noise margin of a sense amplifier or reading circuits to avoid misinterpretation of states. In some embodiments, the input voltage to the first spin-orbit layer may be about at least 50 mV, at least 60 mV, at least 70 mV, at least 80 mV, at least 90 mV, at least lOOmV, at least 200 mV, at least 500 mV, at least IV, at least 1.5V, at least 2V, or between about 50 mV and 2V. In some embodiments, the output voltage from the MESO device 100 may be greater than 50 mV, greater than 60 mV, greater than 70 mV, greater than 80 mV, greater than 90 mV, greater than 100 mV, greater than 120 mV, greater than 150 mV, or between about 50 mV and 150 mV.

[0065] In some embodiments, intermediate circuitry may be included in between the output of a first MESO device 100 and the input of a second MESO device 100 to amplify the output voltage of the first MESO device 100 to a level sufficient to drive the input of the second MESO device 100.Attorney Docket No: 206595-0001-00WO

[0066] Aspects of the present disclosure relate to a memory device comprising a plurality of magnetoelectric spin-orbit (MESO) devices (also referred to as cells). The memory device may further comprise any other component known to one of skill in the art. For example, the memory array may comprise electrodes, resistors, multiplexers, transistors, a power supply, and the like. In some embodiments, the memory array may be deposited on a substrate. In some embodiments, conductive traces may be utilized to electrically couple the components.

[0067] Generally, the memory array comprises a plurality of MESO devices (as described above), a constant current source connected to the first spin-orbit layer 102 of each device, a first electrode connected at one end of the second spin-orbit layer 106 of each device, and a second electrode connected at an opposing end of the second spin-orbit layer 106 of each device. In some embodiments, two sets of electrodes may be used. Generally, an input voltage differential exceeding a threshold is applied across the first spin-orbit layer 102 and the second spin-orbit layer 106 of a MESO cell to induce a voltage across the vertical direction of the magnetoelectric layer 104 and write to the cell. In some embodiments, a constant voltage is applied between the first spin-orbit layer 102 and the second spin-orbit layer 106 to alter the memory state of the cell, which may then be measured to read the memory state from the cell. The memory array may have various configurations, such as a one-transistor, one-resistor (1T1R) configuration, a 0T1R configuration, a 2T1R configuration, a configuration with separate read and write electrodes, or a vertical configuration.

[0068] In some embodiments, and referring now to Figs. 3A and 3B, shown is a memory device 200 with a 1T1R configuration. The memory device 200 comprises a plurality of MESO cells 202, each cell comprising a first SO layer 202a, a magnetoelectric layer 202b, and a second SO layer 202c, source lines 204, write bit lines (WBL) 206, and read bit lines (RBL) 208. The MESO cells 202 are arranged in a plurality of columns and rows. The source lines 204 are connected to the second SO layer 202c of each cell along the same row. The write bit lines 204 are connected to one end of the first SO layer 202a of each cell along the same column. The read bit lines 208 are connected to the opposing end of the top layer 202a of each cell along the same column. In some embodiments, transistors 210 are connected between the read bit lines 208 and the top layers 302a of each cell, with a gate connected to the source line, 204, a drain connected to the RBL 208 for the column, and a source connected to the first SO layer 202a. In someAttorney Docket No: 206595-0001-00WOembodiments, the transistor 210 may be an NMOS or a PMOS transistor. In some embodiments, the write bit line is connected to a multiplexer 212 configured to switch between voltages for different write-in functions.

[0069] To write to a specified cell and using the top right cell in Fig. 3A as an example, a voltage differential of Vo is applied to the write bit line 206, while the source line 204 is grounded. To make sure unselected cells are not being written to, a voltage differential of Vo / 2 is applied to the source lines 204 of the other cells, which is not sufficient to alter the memory state of the middle layer 202b. This configuration effectively differentiates between cells, ensuring correct write operations without interference from the other rows. Referring now to Fig 3B, the read operation is performed by applying a charge current to the source line 204 of the chosen cell, inducing an input current in the first SO layer 202c of the cell. Since the source line is at a high voltage, the transistor 210 is activated, thereby allowing the sense of an output voltage from the two ends of the second SO layer through the read bit line 208. Current flows from the first SO layer 202c to the read bit line 208. Since the read bit line 208 is connected to multiple cells along the same column, and the voltage from an individual cell is relatively small, it is important to prevent this voltage from being sensed by the other cells. To achieve this, the source lines 204 for the other rows are set to 0, thereby deactivating the transistors and preventing current flow into the other cells.

[0070] Referring now to Fig. 4A, shown is a 0T1R memory device, having a similar configuration to the 1T1R memory device described above. This configuration eliminates the transistors connected between the read bit line and the top layer. As a result of removing the transistors, the output voltage decreases by a factor of n (n being equal to the number of cells connected to the read bit line). Therefore, this configuration may not be suitable for very large memory arrays due to voltage degradation, but may significantly increase memory density, making this configuration ideal for highly compact memory devices. In some embodiments, and referring now to Fig. 4B, shown is a 2T1R memory device, comprising a first transistor 210 connected between the first SO layer and the read bit line, and a second transistor 410 connected between the first SO layer and the write bit line. The 2T1R embodiment shown in Fig. 4B is advantageous because the select line can better control current running from the write bit line into the first SO layer, but at the cost of additional complexity and lower cell density due to theAttorney Docket No: 206595-0001-00WOadded transistor. In some embodiments, the sense line does not require an additional voltage level V0 / 2 compared to the 1T1R structure, making it easier to implement peripheral circuits.

[0071] In some embodiments, and referring now to Fig. 5 A, shown is a memory cross-bar array 300 composed of a plurality of memory devices 302 with separate read and write electrodes. The memory device 300 comprises a plurality of MESO cells 302, each cell comprising a first SO layer 302a, a magnetoelectric layer 302b, and a second SO layer 302c, write bit lines (WBL) 304, write word lines (WWL) 306, read bit lines (RBL) 308, and read word lines (RWL) 310. The MESO cells 302 are arranged in a plurality of columns and rows. The write bit lines 304 are connected to one end of the magnetoelectric layer 302b of each cell along the same column. The write word lines 306 are connected to the opposite end of the magnetoelectric layer 302b of each cell along the same row. The read bit lines 308 are connected to one end of the first SO layer 302a of each cell along the same column. The read word lines 310 are connected to the same end of the second SO layer 302c of each cell along the same row. In some embodiments, transistors 312 are connected between the read bit lines 308 and the read word lines 310 and the first SO layers 302a of each cell.

[0072] In order to write to a particular cell (in this example setup, the top left cell is selected), a row is selected by applying half of the write-voltage, Vwrite / 2 to the write word line 306. Since this voltage is insufficient to alter the memory state of the magnetoelectric layer 302b, a negative half of the write-in voltage is applied to the write bit line 304, thereby introducing a voltage differential Vwrite across the ME layer and allowing the cell to be written. Since the other cells in the array have a maximum voltage difference of Vwrite / 2, any unintended change to their stored states is prevented. To read a chosen cell, and referring now to Fig. 5B, the corresponding row is selected by applying a Vread voltage to the read word line 310. This induces a charge current into the second SO layer 302c, which subsequently generates a corresponding charge current on the first SO layer 302a. Simultaneously, the transistor 312 is activated, allowing the current to flow into the read bit line 308, where external circuits can sense it. If Vread exceeds Vwrite, there is a risk of inadvertently writing to the MESO cell during the read operation. To mitigate this issue, the write word line 306 and write bit line 304 can be leveraged. By carefully controlling the electrical potential across both sides of the middle layer 302b, the electric field within the cellAttorney Docket No: 206595-0001-00WOcan be significantly reduced, effectively preventing accidental overwriting during the reading process.

[0073] It should be appreciated that configurations of a memory array utilizing the MESO device are not limited to the above-described configurations, and any memory array configuration known to one of skill in the art may be utilized.

[0074] Also described herein is a method of writing a data bit to a magnetoelectric spin-orbit (MESO) device, which may be any MESO device described above. The method generally comprises the steps of: applying a differential voltage input across the first and second spin-orbit layers to set the memory state of the magnetoelectric layer (step 602), applying a constant current across the first spin-orbit layer to generate a voltage output across the second spin-orbit layer, wherein the voltage output corresponds to the memory state of the magnetoelectric layer (step 604), and measuring the voltage output (step 606).

[0075] Aspects of the present disclosure relate to a logic gate comprising at least one pair of devices 100, each pair comprising a first and a second device 100. The first and second devices are generally configured to store complementary logic states. For example, when the logic gate stores a ‘ 1’ state, the first device 100 generates a positive voltage and the second device 100 generates a negative voltage. In some embodiments, the logic gate may comprise any number of pairs of devices 100, arranged in series and / or in parallel, and one or more inputs connected to at least one pair of devices 100. In some embodiments, the devices 100 may be arranged in any configuration such that the logic gate performs a desired logic function. The logic circuit of the present disclosure supports in-memory computing paradigms where data movement is minimized, and computation occurs directly within the memory array.

[0076] For example, and as shown in Fig. 20A, a logic gate comprises a C-MEMM unit comprising a first device 100 (P-MEMM cell) and a second device 100 (N-MEMM cell) storing complementary logic states, producing a robust differential output voltage suitable for driving subsequent logic stages. The P-MEMM cell generates a positive output voltage VSPI when storing a ‘ 1’ state, while the N-MEMM cell produces a corresponding negative voltage VSNI for the complementary operation. This differential signaling approach provides improved noise immunity compared to single-ended designs and enables rail-to-rail voltage swings for reliableAttorney Docket No: 206595-0001-00WOlogic operation. A single power transistor supplies current shared across multiple C-MEMM cells within the same logic block, thereby significantly reducing transistor overhead and area consumption.

[0077] The timing characteristics shown in Fig. 20B demonstrate the dynamic behavior during read and write operations. The propagation delay of each C-MEMM stage is approximately 60ps, primarily determined by the interconnection resistance and the charging time of the multiferroic capacitor (Manipatruni, Sasikanth et al., ’’Scalable energy-efficient magnetoelectric spin-orbit logic,” Nature, vol. 565, no. 7737, pp. 35-42, 2019.; Parsonnet, Eric et al., ’’Toward Intrinsic Ferroelectric Switching in Multiferroic BiFeO3”, Physical Review Letters, vol. 125, no. 6, pp. 067601, 2020.) During read operations, the differential voltage develops rapidly as the stored magnetic states modulate the spin current flow, while write operations require sufficient voltage duration to overcome the ferroelectric switching threshold and establish stable polarization states.

[0078] For more complex logic operations and referring now to Fig. 20C, a three-input majority gate design may be used which serves as a universal logic primitive for implementing arbitrary Boolean functions. In this architecture, three devices 100 (MEMM-A, MEMM-B, and MEMM-C) are interconnected such that the output voltages of devices A and B are combined and applied to the control port of cell C. The key principle relies on voltage summation: when both input cells A and B store a S = 1 state, their combined output voltage exceeds the switching threshold required to program cell C, whereas individual cell outputs or combinations involving S = 0 states generate insufficient voltage for switching.

[0079] The comprehensive truth table below (Table 1) illustrates all possible input combinations for the three-input majority gate, showing how the final state of cell C correctly implements majority logic functionality. For instance, when inputs A=l, B=l, and the initial state C=0, the combined voltage VP(C) = lOOmV exceeds the switching threshold, resulting in C transitioning to state ’ 1’. Conversely, when only one or no inputs are high, the generated voltage Vp(C) = 50mV remains below the threshold, preserving the existing state or switching to ‘0’ as appropriate. The majority gate output can be directly read from cell C and connected to subsequent logic stages, enabling the construction of complex computational circuits throughAttorney Docket No: 206595-0001-00WOcascaded majority operations, which form a functionally complete logic family capable of implementing any Boolean function.S(Co) S(A) S(B) Vp(C) VN(C) S(C) S(C) 0 0 0 0 lOOmV 0 10 0 1 50mV 50mV 0 10 1 0 50mV 50mV 0 10 1 1 lOOmV 0 1 01 0 0 0 lOOmV 0 01 0 1 50mV 50mV 1 01 1 0 50mV 50mV 1 01 1 1 lOOmV 0 1 1Table 1

[0080] In another example, a single-cell logic gate circuit is shown in Figs. 21 A - 21 C. In the inverter configuration, a bias voltage Vbias = 100 mV is utilized as an intermediate reference level, while input voltages are set to either 0 or 200 mV. This voltage scheme enables bidirectional electric field application, allowing the cell states to be switched between two distinct logic levels. The operating waveforms in Fig. 2 IB illustrate the temporal dynamics during read and write operations, demonstrating how input transitions at VIN propagate through successive stages with 30ps delays.

[0081] This single-cell architecture also enables simplified logic gate implementations. Fig. 21C presents a reconfigurable OR / NAND gate using two devices 100 (MEMM cells), where the logic function can be dynamically switched based on the input configuration. The truth table in Table 2 details the voltage-based logic operation, mapping different combinations of input voltages VA+and VB+to the corresponding output voltage VOUT. The green-highlighted rows demonstrate OR logic functionality, where the output is high (‘1’) when either input is high, while the orange-highlighted rows show NAND operation, where the output is low (‘0’) only when both inputs are high (‘1’). Notably, since NAND gates are functionally complete, this architecture canAttorney Docket No: 206595-0001-00WOtheoretically implement any arbitrary Boolean function, making it a versatile platform for general-purpose logic-in-memory computing.V_A^+(mV) V_B^+(mV) V_A^-(mV) V_B^-(mV) V_OUT(mV) Logic0 0 VBias V Bias 00 200 VBias VBias 200OR200 0 VBias V Bias 200200 200 VBias V Bias 400VBias VBias 0 0 400VBias VBias 0 200 200NAND VBias VBias 200 0 200VBias VBias 200 200 0Table 2

[0082] In some aspects of the present invention, software executing the instructions provided herein may be stored on a non-transitory computer-readable medium, wherein the software performs some or all of the steps of the present invention when executed on a processor.

[0083] Aspects of the invention relate to algorithms executed in computer software. Though certain embodiments may be described as written in particular programming languages, or executed on particular operating systems or computing platforms, it is understood that the system and method of the present invention is not limited to any particular computing language, platform, or combination thereof. Software executing the algorithms described herein may be written in any programming language known in the art, compiled or interpreted, including but not limited to C, C++, C#, Objective-C, Java, JavaScript, MATLAB, Python, PHP, Perl, Ruby, or Visual Basic. It is further understood that elements of the present invention may be executed on any acceptable computing platform, including but not limited to a server, a cloud instance, a workstation, a thin client, a mobile device, an embedded microcontroller, a television, or any other suitable computing device known in the art.Attorney Docket No: 206595-0001-00WO

[0084] Parts of this invention are described as software running on a computing device. Though software described herein may be disclosed as operating on one particular computing device (e.g. a dedicated server or a workstation), it is understood in the art that software is intrinsically portable and that most software running on a dedicated server may also be run, for the purposes of the present invention, on any of a wide range of devices including desktop or mobile devices, laptops, tablets, smartphones, watches, wearable electronics or other wireless digital / cellular phones, televisions, cloud instances, embedded microcontrollers, thin client devices, or any other suitable computing device known in the art.

[0085] Similarly, parts of this invention are described as communicating over a variety of wireless or wired computer networks. For the purposes of this invention, the words “network”, “networked”, and “networking” are understood to encompass wired Ethernet, fiber optic connections, wireless connections including any of the various 802.11 standards, cellular WAN infrastructures such as 3G, 4G / LTE, or 5G networks, Bluetooth®, Bluetooth® Low Energy (BLE) or Zigbee® communication links, or any other method by which one electronic device is capable of communicating with another. In some embodiments, elements of the networked portion of the invention may be implemented over a Virtual Private Network (VPN).

[0086] Fig. 13 and the following discussion are intended to provide a brief, general description of a suitable computing environment in which the invention may be implemented. While the invention is described above in the general context of program modules that execute in conjunction with an application program that runs on an operating system on a computer, those skilled in the art will recognize that the invention may also be implemented in combination with other program modules.

[0087] Generally, program modules include routines, programs, components, data structures, and other types of structures that perform particular tasks or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the invention may be practiced with other computer system configurations, including hand-held devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like. The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through aAttorney Docket No: 206595-0001-00WOcommunications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

[0088] Fig. 13 depicts an illustrative computer architecture for a computer 500 for practicing the various embodiments of the invention. The computer architecture shown in Fig. 13 illustrates a conventional personal computer, including a central processing unit 550 (“CPU”), a system memory 505, including a random access memory 510 (“RAM”) and a read-only memory (“ROM”) 515, and a system bus 535 that couples the system memory 505 to the CPU 550. A basic input / output system containing the basic routines that help to transfer information between elements within the computer, such as during startup, is stored in the ROM 515. The computer 500 further includes a storage device 520 for storing an operating system 525, application / program 530, and data.

[0089] The storage device 520 is connected to the CPU 550 through a storage controller (not shown) connected to the bus 535. The storage device 520 and its associated computer-readable media provide non-volatile storage for the computer 500. Although the description of computer-readable media contained herein refers to a storage device, such as a hard disk or CD-ROM drive, it should be appreciated by those skilled in the art that computer-readable media can be any available media that can be accessed by the computer 500.

[0090] By way of example, and not to be limiting, computer-readable media may comprise computer storage media. Computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data.Computer storage media includes, but is not limited to, RAM, ROM, EPROM, EEPROM, flash memory or other solid state memory technology, CD-ROM, DVD, or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by the computer.

[0091] According to various embodiments of the invention, the computer 500 may operate in a networked environment using logical connections to remote computers through a network 540, such as TCP / IP network such as the Internet or an intranet. The computer 500 may connect toAttorney Docket No: 206595-0001-00WOthe network 540 through a network interface unit 545 connected to the bus 535. It should be appreciated that the network interface unit 545 may also be utilized to connect to other types of networks and remote computer systems.

[0092] The computer 500 may also include an input / output controller 555 for receiving and processing input from a number of input / output devices 560, including a keyboard, a mouse, a touchscreen, a camera, a microphone, a controller, a joystick, or other type of input device. Similarly, the input / output controller 555 may provide output to a display screen, a printer, a speaker, or other type of output device. The computer 500 can connect to the input / output device 560 via a wired connection including, but not limited to, fiber optic, Ethernet, or copper wire or wireless means including, but not limited to, Wi-Fi, Bluetooth, Near-Field Communication (NFC), infrared, or other suitable wired or wireless connections.

[0093] As mentioned briefly above, a number of program modules and data files may be stored in the storage device 520 and / or RAM 510 of the computer 500, including an operating system 525 suitable for controlling the operation of a networked computer. The storage device 520 and RAM 510 may also store one or more applications / programs 530. In particular, the storage device 520 and RAM 510 may store an application / program 530 for providing a variety of functionalities to a user. For instance, the application / program 530 may comprise many types of programs such as a word processing application, a spreadsheet application, a desktop publishing application, a database application, a gaming application, internet browsing application, electronic mail application, messaging application, and the like. According to an embodiment of the present invention, the application / program 530 comprises a multiple functionality software application for providing word processing functionality, slide presentation functionality, spreadsheet functionality, database functionality and the like.

[0094] The computer 500 in some embodiments can include a variety of sensors 565 for monitoring the environment surrounding and the environment internal to the computer 500. These sensors 565 can include a Global Positioning System (GPS) sensor, a photosensitive sensor, a gyroscope, a magnetometer, thermometer, a proximity sensor, an accelerometer, a microphone, biometric sensor, barometer, humidity sensor, radiation sensor, or any other suitable sensor.Attorney Docket No: 206595-0001-00WOEXPERIMENTAL EXAMPLES

[0095] The invention is further described in detail by reference to the following experimental examples. These embodiments are provided for purposes of illustration only, and are not intended to be limiting unless otherwise specified. Thus, the invention should in no way be construed as being limited to the following embodiments, but rather, should be construed to encompass any and all variations which become evident as a result of the teaching provided herein.

[0096] Without further description, it is believed that one of ordinary skill in the art can, using the preceding description and the following illustrative embodiments, make and utilize the system and method of the present invention. The following working embodiments therefore, specifically point out the exemplary embodiments of the present invention, and are not to be construed as limiting in any way the remainder of the disclosure.Example 1: Equivalent Circuit Model for MESO

[0097] Referring now to Fig. 2A, shown is an equivalent circuit model illustrating the complete operating process of the MESO device. Fig. 2B depicts the geometry parameters and terminal annotations of the SO layer. For simplicity, the three layers were set to have the same width w and length 1. The magnetoelectric (ME) layer and the spin-orbit (SO) layer have thicknesses of tBFo and tso, respectively. The charge current is fed into the SO metal from the left terminal along the x direction. It excites a spin current along the z direction flowing out of the top terminal. Fig.2B shows the equivalent spin Hall effect circuit module, represented by a charge circuit and a spin circuit. The charge circuit for charge transport along x direction (between terminals 1 and 2). Inverse spin Hall effect (ISHE) is represented by two dependent sources with opposite polarity at two terminals. Spin circuit for spin transport along z and z-directions with y spin polarization (between terminals 3 and 4). Spin Hall effect (SHE) is represented by two dependent sources with opposite polarity at two terminals. The equivalent circuits for charge and spins are constructed using voltage-control current sources and conductance. The value of each component in the circuit is given by the following equations:Attorney Docket No: 206595-0001-00WOI0c= β1G0(V3z- V4z)G0= σtw / l, β1= θSHl / t, β2= θSHl / wEquation 1G1z= σlw / λ tanh(t / 2λ), G2z= σlw / λ (t / λ)Equation 2Example 2: Circuit Simulation Results

[0098] Based on the circuit model and real-world experimental data, the behavior of charge and spin current transport can be simulated using the SPICE circuit simulator to predict possible outputs. This approach allows us to overcome the limitations of physical experiments, which may be restricted by time, cost, or environmental conditions. By leveraging simulation, a wider range of conditions and configurations can be explored, potential performance bottlenecks can be identified, and subsequent experimental efforts can be guided more effectively. In line with this, simulations were first conducted for a single MESO cell, not only to verify the accuracy of the model but also to gain valuable insights that can optimize the system’s design and performance.

[0099] To ensure the simulation functions correctly, certain boundary conditions were established. The input nodes (terminals 1 and 2) are connected to a constant voltage source (Vsupply= 1V), providing the charge current. For the spin current circuit, terminal 4 in the SHE module and terminal 3 in the ISHE module are both grounded. Physically, this represents the need for a spin current sink to supply and absorb the spin current. The open-circuit voltage was then measured across the two sides of the ISHE module (VISHE) and its relationship with the material parameters was evaluated.Attorney Docket No: 206595-0001-00WOtSOtBFOw l15 nm 80 nm 2 μm 100 μmTable 3

[0100] The initial investigation examined how the spin Hall angle (θSHE) and electrical resistivity (pSo) influence the voltage output in the ISHE module. The geometric parameters for the SO metal and BFO layers are provided in Table 3. The results, illustrated in Fig. 6A, show the relationship between the output voltage of the ISHE module (VISHE) and the spin Hall angle (0SHE) under varying values of electric resistivity pso. The figure indicates that higher values of both 0SHEand psoresult in an increased VISHE. Notably, the VISHEvs. θSHEcurves demonstrate a saturation effect as 0SHEreaches high values, suggesting that the benefit of further increasing the spin Hall angle in certain materials is limited. By fixing the spin Hall effect at a specific value, the relationship between the output voltage of the ISHE module and the electrical resistivity of the SO metal layer was also evaluated. As shown in Fig. 6B, for a given spin Hall angle (0SHE=10), the output voltage VISHEreaches a maximum at a specific psovalue.

[0101] To assess whether the current material meets the standard for functioning as a memory or logic device, a minimum output requirement of 100 mV was set, which corresponds to the voltage necessary to alter polarization in the ferroelectric layer. Fig. 7 illustrates the potential output of various combinations of SO metal resistivity and theta values. The blue curve, moving from the bottom left to the top right, indicates the output values based on SrlrCh increase as the resistivity and theta values grow. The red line represents the minimum threshold necessary for a material to function as a logic device, which requires an output of at least 100 mV. Notably, both SrIrO3 and Bi2Ses surpass this threshold, indicating their potential suitability for use as logic devices. The parameters for materials are given in Table 4.Attorney Docket No: 206595-0001-00WOMaterial 0SH pso(Ohm.cm) CategoryPt 0.05 - 0.5 40u-100uTa 0.1 lOOuW 0.3 lOOuW(O) 0.03-0.8 50-180uPt75Pd250.2-0.3 80u Heavy metalsPt75Au250.2-0.3 80uPt3(MgO)3 0.26 240uTa10Au9O 0.5 lOOuSrlrCh 0.6-3 l-10mWTe20.09-0.15 130uBi2Se3 5-10 200uTopologicalInsulatorsBiSb 18 200uRu2Sn30.3 ImRUO20.1 l-10uBaPbBiO31.2-3.8 l-3m Orbital HallmetalsIrO20.5 220uTable 4Attorney Docket No: 206595-0001-00WOExample 3: Exemplar Illustration

[0102] Schematic illustration (Fig. 8A) of SIO / BLFO / SIO device structure side view shows how the top and bottom electrodes were to define the current and voltage paths. The bottom SIO layer serves as the current injector and top SIO as spin detector for inverse spin Hall effect transducer. BLFO functions as an antiferromagnetic magnon current source, controlled by an electric field via the magnetoelectric effect. To access the ferroelectric state, the electric field was applied to one of the top and bottom electrodes. Ferroelectric hysteresis and leakage current hysteresis are shown in Figure 7b. The leakage current values match those observed in small-sized capacitor, which is an indicative of good quality ferroelectric properties of used magnetoelectric layer. High angle annular dark field transmission electron microscopy (HAADF-STEM) imaging provides the layer-by-layer epitaxial growth of the trilayer shown in Fig. 8C. The bright spots in the SIO layers may result from a focus issue. However, the zoomed atomic imaging corresponding to the SIO / BLFO bottom and top BLFO / SIO interfaces are atomically sharp. Polar mapping (color arrows) within the BLFO layer indicates ferroelectric behavior, with the magnitude comparable to previous reports (Figs. 8D and 8E). The epitaxial quality is further confirmed by symmetric and asymmetric x-ray diffraction measurements. Since the BLFO and SIO lattice parameters are the same, the peaks overlapped and cannot be distinguished. A transduction mechanism in the SIO / BLFO / SIO trilayer is a working principle of new MESO design.

[0103] In this new MESO concept, BLFO multiferroic is sandwiched between the SIO layers. SIO is known for its high spin torque efficiency, where the charge-to-spin current conversion (known as spin Hall effect) is significantly greater than that of conventional heavy metals such as Pt and W. Thus, SIO is expected to generate a larger voltage via the inverse spin Hall effect (ISHE) in such materials. In the process of spin Hall effect (SHE), electrical current, carrying equal spin up / down electrons, is converted into a spin current (with only one direction of the spin) at the surface of the metal wire. Conversely, excited magnetization at the interface can produce a similar voltage via ISHE. In our new MESO concept, both SHE and ISHE processes are being used in the SIO / BLFO / SIO trilayer device.Attorney Docket No: 206595-0001-00WO

[0104] In the measurement scheme, electrical pulses are used to set the polarization (P) state which also sets the magnetization or antiferromagnetic state owing to the magnetoelectric coupling. In the next step, a constant current is injected in the bottom SIO (Fig. 9A) layer, which is converted to spin current via SHE and accumulated spins at the interface of the SIO / BLFO. The accumulated spins at the SIO / BLFO interface generate non-equilibrium spin accumulation, exciting spin waves or magnons in the antiferromagnetic BLFO layer. The excited magnons traveled through the thickness of BLFO and are converted to voltage due to the process of ISHE. The voltage response as a function of electrical pulses of BFO is shown in Fig. 9B. The output voltage (ImV) is generated via ISHE from the SIO metal, which gives access to read the memory state. The nonvolatile response is recorded for 200s in the up and down state of P (Fig.9C) is an indicative of the non-destructive readout of the non-volatile memory. This provides the freedom to design a new kind of memory using a magnetoelectric compound. The deterministic non-volatile switching response is shown in Fig. 9C. In this way, the memory state may be controlled electrically and a magnon current may be used to read it.

[0105] The output voltage exhibits a linear dependence on the input read current and does not show significant variations with changes in the write voltage pulse. When using the parameters from the vertical device configuration first the linear log-log data trend, demonstrating better performance compared to other configurations, as shown in Fig. 10. Interestingly, the output voltage from the ferromagnetic based MESO device (the green star in the data cloud) is significantly smaller than the magnon driven MESO device.Example 4: Device Circuit Modeling and Optimization

[0106] Magnon-based memory computing enables energy efficient data transfer through electric-field-controlled magnetization in magnetoelectric materials, positioning magnetoelectric spin-orbit logic-in-memory as a promising low-power alternative to conventional memory technologies. The present disclosure describes a non-volatile magnetoelectric magnonic memory (MEMM) device based on direct magnon-driven sensing in an insulating antiferromagnet. The fabricated SrlrCh / La-BiFeOi / SrlrOs trilayer device demonstrates ultra-fast switching below 100ps, endurance exceeding 1011cycles, and a remnant polarization of 20 pC / cm2. Experimental measurements show output voltage differences greater than 10 mV between high- and low-Attorney Docket No: 206595-0001-00WOresistance states, validating full electrical control of the memory state. A comprehensive circuit model capturing spin Hall effect and spin transport processes was developed and validated against experimental data. Circuit simulations reveal that with optimized material parameters, the device can generate output voltages exceeding 100 mV, sufficient for cascaded operation without amplification. Memory array and logic circuit designs demonstrate switching energies down to 1 aJ per operation, with logic gates achieving propagation delays of 30-60 ps. These quantitative results establish MEMM technology as a compelling solution for future energy-constrained computing applications.

[0107] Building on these advances, a magnetoelectric magnonic memory (MEMM) device is described herein, which leverages (1) electric-field control of magnetization via an ME material and (2) electron-free signal transport through magnon propagation in an insulating AFM. Fig. 14A illustrates the trilayer device structure, consisting of an ME layer, e.g. BiFeCh (BFO) and La-BiFeCh (LBFO), sandwiched between two spin-orbit (SO) layers, e.g. SrlrCh (SIO). The operating principle, shown in Fig. 14B, relies on voltage-controlled switching of the ferroelectric polarization in (L)BFO, which modulates the magnon transport resistance between high-resistance state (HRS, S=0) and low-resistance state (LRS, S=l). As shown in Fig. 14C, the device operates in two modes: reading the stored state through spin current, and writing a new state by applying switching voltages across the ME layer. The switch and read functionality of the device was experimentally demonstrated and a simulation model was developed and validated showing that with optimized parameters, the device can produce over 100 mV of output voltage, sufficient to drive subsequent MEMM cells. This scalable behavior was utilized to design memory arrays and logic circuits that exhibit the potential for low-power, high-density in-memory computing. Benefiting from its compact structure, the MEMM device switches in under 100ps and endures more than 1011cycles.

[0108] Fig. 15A presents a schematic side view of the trilayer structure and the associated write / read paths. The device was fabricated on a SrTiCh substrate using pulsed laser deposition to ensure high-quality epitaxial growth. High-angle annular dark field scanning transmission electron microscopy (HAADF-STEM), shown in Fig. 15A (right), confirms layer-by-layer epitaxial growth with sharp SIO / LBFO interfaces, which is crucial for efficient spin currentAttorney Docket No: 206595-0001-00WOinjection and detection. The absence of interfacial defects or interdiffusion ensures minimal spin scattering and maximum magnon transmission efficiency.

[0109] The device was tested in two steps: write and read. During the write operation, voltage pulses applied between the top and bottom SIO layers switch the ferroelectric polarization state of the LBFO layer, resulting in a LRS or HRS for magnon transport. Ferroelectric hysteresis loops (Fig. 15B) demonstrate robust polarization switching with a remnant polarization of approximately 20 pC / cm2consistent with high-quality LBFO films. The square-shaped hysteresis loops indicates well-defined bistable states suitable for digital memory applications.

[0110] For readout, a constant charge current Jc is injected into the bottom SIO electrode, generating a spin current via the spin Hall effect (SHE) in the vertical direction. The resulting spin accumulation at the SIO / LBFO interface excites magnons in the LBFO layer. These spin waves propagate through the AFM insulator and are converted into a measurable voltage VISHE at the top SIO layer via the inverse spin Hall effect (ISHE). Fig. 15C shows deterministic switching and magnon-mediated readout through first harmonic measurements of output voltage VISHE as a function of applied switching voltage. The hysteresis curve clearly demonstrates the correlation between ferroelectric switching and magnon transport resistance, with distinct high and low output voltage states corresponding to opposite polarization orientations. The switching occurs at voltages consistent with the coercive field observed in the ferroelectric hysteresis measurements, shown in Fig. 15B. The output voltage difference between the two states exceeds 10 mV for the demonstrated device design.

[0111] An equivalent spin circuit model (Fig. 16A) was developed for the MEMM device using vector spin circuit theory (Hong, Seokmin et al., ’’Spin Circuit Representation for the Spin Hall Effect,” IEEE Transactions on Nanotechnology, vol. 15, no. 2, pp. 225-236, 2016.), enabling SPICE-based analysis of its electrical behavior. For simplicity, all three layers are assumed to have the same width w and length / , and adjustable thicknesses / ME and / so. Material parameters include spin Hall angle OSH, spin diffusion length L, and charge conductivity G. Terminal voltages V1and currents I are defined on the surfaces of rectangular elements, where i = c denotes charge and r = z,x,y denotes spin, and i is the terminal index. The spin and charge current sources are:Attorney Docket No: 206595-0001-00WO / oz= P1GOW - v2c), I0c= - V4Z)Equation 3

[0112] With conductances:atw olw / t \Go0= ~ I ~ > Gi1— — — tanh I — I, G2Z=A \2A / Equation 4

[0113] And coupling parameters:OSHI GSH^wEquation 5

[0114] This model captures both the spin Hall effect (SHE) and inverse spin Hall effect (ISHE) that govern charge-spin conversion processes. As illustrated in Equation 3, charge current flows into the bottom layer, creating a voltage difference between Vf and V2, which triggers the voltage-controlled current source / Q. This current source described the spin current generated by SHE, establishing a voltage difference between V3and V4Z. This voltage difference subsequently activates the vol age-control led current source ZQ to generate charge current. The system reaches equilibrium with spin current flowing upward through the magnetoelectric (ME) layer.

[0115] Within the ME layer, the conductance values Gseand GSf are controlled by the ferroelectric capacitance CFE. For the two polarization states, state ‘1’ corresponds to high ME layer conductivity, resulting in negligible voltage drop from fl4zto V3r. Conversely, state ‘0’e exhibits extremely low conductivity, significantly impeding current flow. In the top spin-orbit (SO) layer, ISHE is modeled identically to SHE, where the spin current generates a charge voltage difference between V, and V2„ enabling electrical readout of the memory state.

[0116] Fig. 16A depicts an equivalent spin circuit model illustrating the processes from bottom to top: spin Hall effect, magnon transport, and inverse spin Hall effect. Fig. 16B depicts a simplified circuit model showing the control signal VG, supply current ID, and output voltage Vo.Attorney Docket No: 206595-0001-00WOEquation 6 and Table 5 below describe the relationship between output, control, and supply, where p is a material-dependent parameter and aVGis curve-fitted from the hysteresis loop, exhibiting a sharp increase near the threshold voltage VG. Fig. 16C and Equation 7 illustrate the equivalent small-circuit model.Vo = aV1■ ]IDR[SHE6 SHE IS HE t\ t1 — sech—] tanh —M 22 * l +£tanh (j)0s2H£Equation 6VG VG> +vcvc< -vcState LRS(l) HRS(l)v0~ Vsw- VorfTable 59m = anVG1■ gIDrISHEEquation 7

[0117] Table 6 below summarizes the demonstrated device parameters and target values required to achieve output voltages of 100 mV and above.Parameters Current Setup >100mV TargetsSpin Hall Angle (0) 1 >3Electric resistivity (p) 105(Q.m) >104(Q.m)Spin diffusion length (1) 1.4 m (SO), 0.17 pm (ME) >1.4 nm (SO), >0.17 pm (ME)Spin conductivity (o) 4*105(S / m) 2.5* 106(S / m)Attorney Docket No: 206595-0001-00WOThickness (tso, IME) 15 nm, 80 nm >10 nmWidth, Length (w, 1) 2 pm, 100 pm <10 nm, <100 nmTable 6Example 5: Simulation Results

[0118] To validate the modeling approach (Fig. 17A), the simulation results were compared with experimental data. The model verification demonstrates excellent agreement: Fig. 17A shows a linear relationship between read current and the output on / off voltage difference AVISHE, resembling the characteristic linear-region behavior of CMOS devices. Additionally, Fig. 17B shows the comparison of simulation results with previous studies (Huang, Xiaoxi et al., ’’Manipulating chiral spin transport with ferroelectric polarization,” Nature Materials, vol. 23, no.7, pp. 898- 904, 2024.) and the experimental data, revealing a consistent log-log relationship of voltage and spacing ( / so, the thickness of the top and bottom layers). Fig. 17B confirms promising device scalability, demonstrating that input-output spacing below 100 nm can achieve output voltage differences under 100 mV. These results were obtained using the parameters listed in Table 6, which represent the current experimental conditions.

[0119] The validated model was used to explore the design space by sweeping geometric and electrical parameters to map achievable device performance. As illustrated in Fig. 16B, optimizing key parameters, specifically increasing spin Hall angle and reducing switching voltage, enables switching energies to reach the attajoule regime. The final column in Table 6 presents targeted parameter specifications for achieving ideal low-power switching performance. Figs. 18A - 18E illustrate comprehensive parametric sweeps across key geometric and material properties.

[0120] Fig. 18A illustrates the relationship between the spin Hall angles of the bottom and top spin-orbit layers, 9SHE and OISHE respectively, with color contours indicating the achievable output voltage VISHE. The analysis reveals that increasing both spin Hall angles enables significantly higher output voltages, with optimal operating points occurring when OISHE isAttorney Docket No: 206595-0001-00WOaround 2.5. This suggest that materials with large spin Hall angles are essential for cascadable logic operation without requiring additional amplification stages.

[0121] The electrical resistivity analysis in Fig. 18B examines how the resistivities of both spinorbit layers affect device performance. The log-log plot demonstrates that maintaining output voltages above 100 mV requires careful optimization of both PSHE and PISHE, with a clear tradeoff between material conductivity and signal strength. Lower resistivity values generally correlate with higher output voltages due to reduced Joule heating losses and more efficient current flow, indicating that highly conductive spin Hall materials are preferred for energyefficient operation.

[0122] Fig. 18C investigates the scalability of MEMM devices by analyzing the impact of spinorbit layer thicknesses tsHE and tisHE on output voltage. The results show that output voltage decreases logarithmically with increasing layer thickness, suggesting that thinner spin-orbit layers (in the range of 1-10 nm) provide higher voltage outputs due to enhanced current density and more efficient spin-charge conversion. This scaling behavior provides important guidance for device miniaturization while maintaining adequate output signal levels.

[0123] Finally, Fig. 18D examines the relationship between magnetoelectric layer thickness tBFo and output voltage. The monotonically decreasing trend indicates that thinner LBFO layers yield higher output voltages, likely due to reduced magnon scattering and shorter transport distances. However, practical constraints such as ferroelectric stability and switching reliability impose a lower bound on the ME layer thickness. These comprehensive parametric studies collectively establish clear design rules for fabricating high-performance MEMM devices with minimal energy consumption and maximum output signal strength suitable for cascaded logic operations.Example 6: Memory Arrays

[0124] Leveraging ferroelectric polarization-modulated spin conductivity, MEMM devices are promising candidates for low-power memory applications. A compact 1T1R (one transistor, one resistor) memory array architecture, as shown in Fig. 19A, was designed, where each MEMM cell is accessed through a single transistor controlled by word bitlines (WBL) and read bitlines (RBL).Attorney Docket No: 206595-0001-00WO

[0125] The memory operation consists of three distinct phases illustrated in the timing waveforms of Fig. 19B. In the pre-charge phase (PCH), all MEMM cells across the array are uniformly initialized to logic state ‘0’ by biasing the sense lines (SL) to the switching threshold voltage VT = 200mV. This global initialization ensures a consistent starting state for subsequent operations while the supply voltage Vsuppiy remains at ground potential. During the write phase, data programming occurs row-by-row. The selected row is activated by setting the corresponding sense line pairs SL(2i) and SL(2i+l) to -VT / 2 = -100m V, creating a differential voltage configuration. Simultaneously, the target write bitline WBL(j) is biased to +VT / 2 = +100mV, establishing the full switching voltage VT across the selected MEMM cell. This differential addressing scheme ensures that only the targeted memory cell experiences the complete switching voltage, while non-selected cells in the same row see only half the switching voltage, thereby preventing unintended state changes and maintaining data integrity throughout the array.

[0126] The readout operation employs a two-phase sensing approach that exploits the differential spin conductivity between the ‘0’ and ‘1’ states. In phase 1, the read sensing cells are reset to a known reference state by appropriate biasing of the supply lines. Subsequently, in phase 2, the selected sense line SL(2i) is driven to the read voltage VR = 1 0mV, which is lower than the write threshold to ensure non-destructive readout. The stored magnetic state modulates the spin current flow through the MEMM cell, causing the read bitline (RBL) voltage to influence the state of the dedicated sensing cells at the bottom of the array. This sensing mechanism generates a robust differential voltage signal across the complementary bitline pairs (BLP and BLN), with the voltage difference directly proportional to the stored logic state. The differential readout signal can be directly interfaced with downstream logic circuits without requiring additional sense amplifiers, enabling seamless integration of memory and logic functions within the same array structure. The demonstrated 1T1R architecture is inherently scalable to large memory arrays while maintaining the differential addressing and sensing capabilities essential for reliable high-density storage applications.Example 7: Logic Gates

[0127] Complementary Logic Design: Unlike memory arrays, logic circuits benefit from a clear separation between control and power, achieved by using cells with side ports that enable directAttorney Docket No: 206595-0001-00WOswitching of the magnetoelectric (ME) layer without interfering with the main current path. By pairing two MEMM cells into a complementary configuration (C-MEMM), various logic functions can be efficiently implemented with enhanced noise margins and reduced power consumption.

[0128] To understand the potential of MEMM technology for sequential logic, consider a simple example: computing the Boolean function F — (( / I ■ B) + (C ■ D)) for multiple input sets. In a conventional CMOS implementation, we would use two AND gates followed by an OR gate. To process multiple operations concurrently and increase throughput, designers employ pipelining, by inserting registers between logic states to allow different inputs to be processed simultaneously at different states. However, each register in CMOS requires multiple transistors (typically 6-12 per bit), consumes both dynamic and static power, and occupies significant silicon area. As pipeline depth increase, the overhead of these registers quickly dominates the circuit, limiting how aggressively designers can partition logic operations.

[0129] The logic-in-memory feature of MEMM device fundamentally changes this trade-off. Because each MEMM cell is inherently non-volatile and stores its own state, every logic gate simultaneously acts as both a computational element and a storage register. There is no additional overhead, no extra transistors, no additional area, and crucially, no static power consumption to insert pipeline stages. This means that logic operations can be partitioned at an extremely fine granularity, placing a pipeline stage after every single logic gate if desired, without the penalties that make such aggressive pipelining impractical in CMOS.

[0130] To demonstrate this capability, a deeply pipelined 32-bit ripple carry adder was designed. Each full adder stage was constructed using MEMM-based INV, AND, and OR gates, implementing standard Boolean logic for sum and carry generation. The key distinction from CMOS is that immediate carry and sum results are stored directly within the MEMM cells themselves. Each gate’s output naturally holds its state between clock cycles. No additional register structures are required between pipeline stages. By partitioning the 32-bit in addition to individual bit-slice stages, the operational frequencies can be increased exceeding 16 GHz with appropriate clocking schemes.Attorney Docket No: 206595-0001-00WO

[0131] The energy efficiency of the pipelined MEMM adder is particularly compelling. The energy per addition operation remains nearly constate with increasing pipeline depth due to the near-zero leakage power of the non-volatile MEMM cells, allowing the operations-per-watt metric to scale linearly with frequency. In contrast, CMOS pipelines register dissipated substantial static power even when holding their state, resulting in energy overhead that grows with pipeline depth and ultimately limits the achievable OPs / W. A 400x advantage in energy efficiency, coupled with a 5x reduction in area, results in an area-normalized energy efficiency exceeding 1500 TOPS / W / mm2, making MEMM technology exceptionally attractive for power-constrained edge computing applications.

[0132] Beyond simple arithmetic units, the design methodology was extended to create a complete 32-bit MEMM-based arithmetic logic unit (ALU) capable of performing eight common operations: addition, subtraction, bitwise AND, OR, XOR, NOT, shift left, and shift right. The ALU architecture leverages the reconfigurability of MEMM logic gates where INV, AND, and OR gates can implement any Boolean function. The entire ALU consists of 512 MEMM cells organized into 32 bit-slices, with each slice containing 16 cells for arithmetic and logic operations. The total footprint is estimated to be under 10 pm2in a 7nm-equivalent technology node, representing a 5x area reduction compared to a standard CMOS ALU of similar functionality. Operating at 16 GHz with 64 aJ per operation, the MEMM ALU delivers 250 GOPS / mm2, demonstrating the technology’s potential for high-density, energy-efficient computing.

[0133] The deep pipelining capability of MEMM technology opens up architectural possibilities beyond traditional von Neumann computing. By eliminating the distinction between computation and storage, MEMM circuits naturally support in-memory computing paradigms where data movement is minimized, and computation occurs directly within the memory array. This spatial computing approach is particularly well-suited for data-intensive applications such as neural network inference, cryptographic operations, and signal processing, where the energy cost of data transfer often exceeds the energy required for computation itself.ReferencesAttorney Docket No: 206595-0001-00WO

[0134] Manipatruni, Sasikanth et al., ’’Scalable energy-efficient magnetoelectric spin-orbit logic,” Nature, vol. 565, no. 7737, pp. 35-42, 2019.

[0135] Vaz, Diogo C. et al., ’’Functional Demonstration of a Fully Integrated Magneto-Electric Spin-Orbit Device,” 2021 IEEE International Electron Devices Meeting (IEDM), pp. 32.4.1-32.4.4, 2021.

[0136] Worledge, Daniel C. et al., ’’Spin-transfer torque magnetoresistive random access memory technology status and future directions,” Nature Reviews Electrical Engineering, vol. 1, no. 11, pp. 730-747, 2024.

[0137] Sato, Noriyuki et al., ”Two-terminal spin-orbit torque magnetoresistive random access memory,” Nature Electronics, vol. 1, no. 9, pp. 508-511, 2018.

[0138] Millo, F. et al., ’’Unidirectionality of spin waves in Synthetic Antiferromagnets,” Physical Review Applied, vol. 20, no. 5, pp. 054051, 2023.

[0139] Devolder, T. et al., ’’Measuring a population of spin waves from the electrical noise of an inductively coupled antenna,” Physical Review B, vol. 105, no. 21, pp. 214404, 2022.

[0140] Balinskyy, Mykhaylo et al., ’’Magnonic combinatorial memory,” npj Spintronics, vol. 2, no. l, pp. 1-11, 2024.

[0141] Liao, Yu-Ching et al., ’’Evaluating the Performances of the Ultralow Power Magnetoelectric RandomAccess Memory With a Physics-Based Compact Model of the Antiferromagnet / Ferromagnet Bilayer,” IEEE Transactions on Electron Devices, vol. 69, no. 5, pp. 2331-2337, 2022.

[0142] Narla, Siri et al., ’’Cross-Layer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search,” IEEE Transactions on Electron Devices, vol. 72, no. 1, pp. 240-246, 2025.

[0143] Parsonnet, Eric et al., ’’Toward Intrinsic Ferroelectric Switching in Multiferroic BiFeO3”, Physical Review Letters, vol. 125, no. 6, pp. 067601, 2020.Attorney Docket No: 206595-0001-00WO

[0144] Husain, Sajid et al., ’’Non-volatile magnon transport in a single domain multiferroic,” Nature Communications, vol. 15, no. 1, pp. 5966, 2024.

[0145] Hong, Seokmin et al., ’’Spin Circuit Representation for the Spin Hall Effect,” IEEE Transactions on Nanotechnology, vol. 15, no. 2, pp. 225-236, 2016.

[0146] Manipatruni, Sasikanth et al., ’’Modeling and Design of Spintronic Integrated Circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 12, pp. 2801-2814, 2012.

[0147] Huang, Xiaoxi et al., ’’Manipulating chiral spin transport with ferroelectric polarization,” Nature Materials, vol. 23, no. 7, pp. 898- 904, 2024.

[0148] Rothe, Rohit et al., ’’Energy Efficient Logic and Memory Design With Beyond-CMOS Magnetoelectric Spin-Orbit(MESO) Technology Toward Ultralow Supply Voltage,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 9, no. 2, pp. 124-133, 2023.

[0149] Nikonov, Dmitri E. et al., ’’Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 1, pp. 3-11, 2015.

[0150] Vaz, Diogo C. et al., ’’Voltage-based magnetization switching and reading in magnetoelectric spin-orbit nanodevices,” Nature Communications, vol. 15, no. 1, pp. 1902, 2024.

[0151] Li, Hai and et al., ’’Differential Electrically Insulated Magnetoelectric Spin-Orbit Logic Circuits,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 7, no. 1, pp. 18–25, 2021.

[0152] Liu, Huichu et al., ’’Synchronous Circuit Design With Beyond-CMOS Magnetoelectric Spin-Orbit Devices Toward 100-mV Logic,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 5, no. 1, pp. 1-9, 2019.Attorney Docket No: 206595-0001-00WO

[0153] Huang, Tzuping et al., ’’MESO-CMOS Hybrid Circuits with Time-Multiplexing Technique for Energy and Area-Efficient Computing-In-Memory,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, pp. 1-1, 2025.

[0154] Li, Hai et al., ’’Physics-Based Models for Magneto-Electric Spin-Orbit Logic Circuits,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 8, no. 1, pp.10-18, 2022.

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[0156] The disclosures of each and every patent, patent application, and publication cited herein are hereby incorporated herein by reference in their entirety. While this invention has been disclosed with reference to specific embodiments, it is apparent that other embodiments and variations of this invention may be devised by others skilled in the art without departing from the true spirit and scope of the invention. The appended claims are intended to be construed to include all such embodiments and equivalent variations.

Claims

Attorney Docket No: 206595-0001-00WOCLAIMSWhat is claimed is:

1. A magnetoelectric spin-orbit device, comprising:a first spin-orbit layer;a magnetoelectric layer positioned above the first spin-orbit layer; and a second spin-orbit layer positioned above the magnetoelectric layer.

2. The device of claim 1, further comprising a first interconnect electrically connected to the first spin-orbit layer and a second interconnect electrically connected to the second spin-orbit layer.

3. The device of claim 2, wherein the interconnects are configured to couple the first or second spin-orbit layers to a differential input voltage, a differential output voltage, a power supply, or a ground connection.

4. The device of claim 1, wherein the first and second spin-orbit layer have a spin Hall angle ranging between 0.1 and 20.

5. The device of claim 1, wherein the first and second spin-orbit layers comprise one or more heavy metals and one or more topological insulators.

6. The device of claim 5, wherein the one or more heavy metals comprise platinum, tantalum, tungsten, palladium, tellurium, or iridium.

7. The device of claim 5, wherein the one or more topological insulators comprise bismuth, antimony, selenium, or tellurium.

8. The device of claim 1, wherein the magnetoelectric layer comprises an antiferromagnet.

9. The device of claim 1, wherein the magnetoelectric layer comprises BiFeO₃.Attorney Docket No: 206595-0001-00WO10. The device of claim 9, wherein the magnetoelectric layer further comprises a rare earth ion selected from lanthanum, samarium or neodymium.

11. The device of claim 1, wherein the first spin-orbit layer is configured to convert an electric current to a spin polarized current in the magnetoelectric layer.

12. The device of claim 1, wherein the second spin-orbit layer is configured to convert a spin polarized current in the magnetoelectric layer to an electric current.

13. The device of claim 1, wherein the magnetoelectric layer has an antiferromagnetic state.

14. The device of claim 13, wherein the antiferromagnetic state is set or switched via the application of a differential input voltage across the magnetoelectric layer.

15. The device of claim 1, wherein the device is a non-volatile memory element.

16. A memory device comprising:a plurality of magnetoelectric spin-orbit (MESO) devices, each comprising:a first spin-orbit layer;a magnetoelectric layer positioned above the first spin-orbit layer; and a second spin-orbit layer positioned above the magnetoelectric layer; a read line coupled to the first spin-orbit layer of a first subset of the MESO devices;a write line coupled to the second spin-orbit layer of a second subset of the MESO devices; anda source line coupled to the first spin-orbit layer of a third subset of MESO devices.

17. The memory array of claim 16, wherein the memory device may have a 0T1R configuration, a 1T1R configuration, A 2T1R configuration, or be configured to have separate sets of read and write lines.

18. The memory device of claim 16, wherein the device further comprises a plurality of transistors connected between the second spin-orbit layer and the read or write lines.Attorney Docket No: 206595-0001-00WO19. The memory array of claim 16, further comprising a second read line and a second write line.

20. A method of writing a data bit to a magnetoelectric spin-orbit (MESO) memory, comprising:providing a MESO memory, comprising:a first spin-orbit layer;a magnetoelectric layer positioned above the first spin-orbit layer; and a second spin-orbit layer positioned above the magnetoelectric layer. applying a differential voltage input across the first and second spin-orbit layers to set the memory state of the magnetoelectric layer;applying a constant current across the first spin-orbit layer to generate a voltage output across the second spin-orbit layer;wherein the voltage output corresponds to the memory state of the magnetoelectric layer; andmeasuring the voltage output.

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