Verification and read control techniques for memory devices

Abstract

A memory device includes a memory block including memory cells arranged in word lines and memory holes having varying diameters. The word lines are grouped into a first group and a second group based on memory hole diameter. Circuitry is configured to determine whether a selected word line is in the first group or the second group. In response to the selected word line being in the first group, the circuitry is configured to perform a memory operation using a first set of reference voltages. In response to the selected word line being in the second group, the circuitry is configured to perform a memory operation using a second set of reference voltages. The first set of reference voltages and the second set of reference voltages are different for a plurality of data states and similar for at least one data state at a highest threshold voltage range.

Description

Background Technology 1. Technical Field

[0002] This topic discloses information about memory devices in general, and more specifically about improved read and verification techniques for improving reliability.

[0003] 2. Related Technologies

[0004] Semiconductor memories are widely used in a variety of electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memories can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0005] NAND flash memory devices include chips having multiple memory blocks, each of which includes an array of memory cells arranged in multiple word lines. The memory cells can be programmed to have a threshold voltage associated with a data state. During a sensing operation, a reference voltage is applied to a selected word line, and the threshold voltage of the memory cell is compared to the reference voltage. By repeating this process with a set of reference voltages, the data states of the memory cells on the selected word line can be determined. Summary of the Invention

[0006] One aspect of this disclosure relates to a method of operating a memory device. The method includes the steps of: preparing a memory block having an array of memory cells arranged in a plurality of word lines. The memory block also includes a plurality of memory holes extending through the plurality of word lines and having varying diameters. The word lines are grouped into a first group and a second group based on the diameter of the memory holes. The method continues with the step of: determining whether a selected word line among the plurality of word lines is in the first group or the second group. In response to the selected word line being in the first group, the method continues with the step of: performing a memory operation using a first set of reference voltages. In response to the selected word line being in the second group, the method continues with the step of: performing the memory operation using a second set of reference voltages. The first set of reference voltages and the second set of reference voltages are different for multiple data states and similar for at least one data state at a maximum threshold voltage range.

[0007] According to another aspect of this disclosure, the memory operation is a three-bit memory operation per memory cell, and each of the first set of reference voltages and the second set of reference voltages includes seven reference voltages associated with seven programmed data states at different threshold voltage ranges.

[0008] According to another aspect of this disclosure, the memory operation is a programming operation, and the reference voltage of the first set of reference voltages and the second set of reference voltages is a verification voltage.

[0009] According to another aspect of this disclosure, for the first six programming data states, the reference voltage of the second set of reference voltages is greater than the reference voltage of the first set of reference voltages, such that programming the memory cells of the word lines of the second region results in an increased margin between the erase data state and the first programming data state compared to programming the memory cells of the word lines of the first region.

[0010] According to a further aspect of this disclosure, for each programmed data state other than the last data state, the reference voltage of the second set of reference voltages is a first offset greater than the reference voltage of the first set of reference voltages.

[0011] According to a further aspect of this disclosure, the memory hole has a larger diameter at the word line of the first region and a smaller diameter at the word line of the second region.

[0012] According to a further aspect of this disclosure, the memory operation is a read operation.

[0013] According to another aspect of this disclosure, for each of the multiple data states other than the last data state, the reference voltage is equal to the verification voltage used for the data state plus a first offset plus a second offset. For the last data state, the reference voltage is equal to the verification voltage used for the last data state plus a first offset.

[0014] Another aspect of this disclosure relates to a memory device. The memory device includes a memory block comprising an array of memory cells arranged in a plurality of word lines. The memory block also includes a plurality of memory holes extending through the plurality of word lines and having varying diameters. The word lines are grouped into a first group and a second group based on the diameter of the memory holes. The memory device also includes circuitry for performing a memory operation on a selected word line among the plurality of word lines. The circuitry is configured to determine whether the selected word line is in the first group or the second group. In response to the selected word line being in the first group, the circuitry is configured to perform a memory operation using a first set of reference voltages. In response to the selected word line being in the second group, the circuitry is configured to perform a memory operation using a second set of reference voltages. The first set of reference voltages and the second set of reference voltages are different for a variety of data states and similar for at least one data state within a maximum threshold voltage range.

[0015] According to another aspect of this disclosure, the memory operation is a three-bit memory operation per memory cell, and each of the first set of reference voltages and the second set of reference voltages includes seven reference voltages associated with seven programmed data states at different threshold voltage ranges.

[0016] According to another aspect of this disclosure, the memory operation is a programming operation, and the reference voltage of the first set of reference voltages and the second set of reference voltages is a verification voltage.

[0017] According to another aspect of this disclosure, for the first six programmed data states, the reference voltage of the second set of reference voltages is greater than the reference voltage of the first set of reference voltages, such that programming the memory cells of the word lines of the second region results in an increased margin between the erase data state and the first programmed data state compared to programming the memory cells of the word lines of the first group.

[0018] According to a further aspect of this disclosure, for each programmed data state other than the last data state, the reference voltage of the second set of reference voltages is a first offset greater than the reference voltage of the first set of reference voltages.

[0019] According to a further aspect of this disclosure, the memory hole has a larger diameter at the word line of the first region and a smaller diameter at the word line of the second region.

[0020] According to a further aspect of this disclosure, the memory operation is a read operation.

[0021] According to another aspect of this disclosure, for each of the multiple data states other than the last data state, the reference voltage is equal to the verification voltage used for the data state plus a first offset plus a second offset. For the last data state, the reference voltage is equal to the verification voltage used for the last data state plus a first offset.

[0022] Another aspect of this disclosure relates to an apparatus comprising a memory block having an array of memory cells arranged in a plurality of word lines. The memory block also includes a plurality of memory holes extending through the plurality of word lines and having varying diameters. The plurality of word lines includes bottom-layer word lines and other word lines. The apparatus also includes a sensing element configured to perform a sensing operation on a selected word line among the plurality of word lines. The sensing element is configured to determine whether the selected word line is a bottom-layer word line among the bottom-layer word lines or another word line among the other word lines. In response to the selected word line being another word line among the other word lines, the sensing element is configured to perform the sensing operation using a first set of reference voltages. In response to the selected word line being a bottom-layer word line among the bottom-layer word lines, the sensing element is configured to perform the sensing operation using a second set of reference voltages. The first set of reference voltages and the second set of reference voltages are different for multiple data states and similar for at least one data state within a maximum threshold voltage range.

[0023] According to another aspect of this disclosure, the sensing operation is a verification operation, and the reference voltage of the first set of reference voltages and the second set of reference voltages is the verification voltage.

[0024] According to another aspect of this disclosure, the sensing operation is a reading operation.

[0025] According to another aspect of this disclosure, the sensing operation is a three-bit sensing operation per memory cell, and each of the first set of reference voltages and the second set of reference voltages includes seven reference voltages associated with seven programmed data states at different threshold voltage ranges. Attached Figure Description

[0026] A more detailed description is set forth below with reference to the exemplary embodiments depicted in the accompanying drawings. It should be understood that these drawings depict only exemplary embodiments of this disclosure and are therefore not intended to be limiting of its scope. This disclosure is described and explained with added specificity and detail by using the drawings, in which:

[0027] Figure 1A This is a block diagram of an example memory device.

[0028] Figure 1B This is a block diagram of an example control circuit;

[0029] Figure 1C yes Figure 1A A block diagram of an example circuit for a memory device;

[0030] Figure 2 Depicting Figure 1A A block of memory cells in an example two-dimensional configuration of a memory array.

[0031] Figure 3A and Figure 3B A cross-sectional view of an example floating gate memory cell in a NAND string is depicted;

[0032] Figure 4A and Figure 4B A cross-sectional view of an example charge-trapping memory cell in a NAND string is depicted;

[0033] Figure 5 An example block diagram of the sensing block SB1 in Figure 1 is depicted;

[0034] Figure 6A This is a perspective view of a set of blocks in an example three-dimensional configuration of the memory array in Figure 1;

[0035] Figure 6B Depicting Figure 6A An example cross-sectional view of a portion of a block.

[0036] Figure 6C Depicting Figure 6B A drawing of the diameter of memory holes in a stack.

[0037] Figure 6D Depicting Figure 6B A close-up view of the stacked area 622.

[0038] Figure 7A Depicting Figure 6B A top view of an example stacked wordline layer WL0.

[0039] Figure 7B Depicting Figure 6B A top view of the top dielectric layer DL116, an example of a stacked structure.

[0040] Figure 8 It is a cross-sectional view of a part of a memory block and passing through a pair of memory holes;

[0041] Figure 9 The threshold voltage distribution of pages programmed into memory cells with three bits per memory cell (TLC) is depicted.

[0042] Figure 10 This is a schematic diagram of an exemplary NAND string during a sensing operation;

[0043] Figure 11 The threshold voltage distribution of pages in memory cells programmed to TLC but subjected to True Temperature Data Retention (TTDR) is depicted.

[0044] Figure 12 The threshold voltage distribution of pages in memory cells programmed to TLC but subjected to read disturbance (RD) is depicted;

[0045] Figure 13 It is a plot of voltages in a memory block versus word lines, and shows the verification voltages applied during programming of different word lines;

[0046] Figure 14 It is a threshold voltage distribution plot of two pages of a memory cell, including a first page programmed with a first set of verification voltages and a second page programmed with a different second set of verification voltages;

[0047] Figure 15 This is a flowchart depicting the steps of programming a memory cell for a selected word line according to an exemplary embodiment of the present disclosure; and

[0048] Figure 16 This is a flowchart depicting the steps of reading a memory cell of a selected word line according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0049] This disclosure relates to an operational technique for memory devices that improves True Temperature Data Retention (TTDR) without degrading Read Disturbance (RD). This is achieved by introducing layer-bottom verification and read voltages for at least one data state, separate from the verification and read voltages for other data states. Improved TTDR and RD enhance reliability.

[0050] Figure 1A This is a block diagram of an example memory device 100 configured to sense (read and verify) memory cells of a memory block according to the read and verification techniques disclosed in this subject matter. The memory die 108 includes a memory structure 126 (such as an array of memory cells), control circuitry 110, and read / write circuitry 128. The memory structure 126 is addressable via word lines through a row decoder 124 and via bit lines through a column decoder 132. The read / write circuitry 128 includes a plurality of sensing blocks SB1, SB2, ..., SBp (sensing circuitry) and allows for parallel reading or programming of pages of memory cells. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable memory card) as the one or more memory dies 108. Commands and data are transmitted between the host 140 and the controller 122 via a data bus 120 and between the controller and the one or more memory dies 108 via line 118.

[0051] Memory structure 126 can be two-dimensional or three-dimensional. Memory structure 126 may include one or more arrays of memory cells, including three-dimensional arrays. Memory structure 126 may include a monolithic three-dimensional memory structure in which multiple memory stages are formed on (and not in) a single substrate (such as a wafer) without an intervening substrate. Memory structure 126 may include any type of non-volatile memory, integrally formed as one or more physical stages of an array of memory cells having active regions disposed on a silicon substrate. Memory structure 126 may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, regardless of whether the associated circuitry is on or within the substrate.

[0052] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126, and includes state machine 112, on-chip address decoder 114, and power control module 116. State machine 112 provides chip-level control of memory operations.

[0053] Storage region 113 may be provided, for example, for programming parameters. Programming parameters may include programming voltage, programming voltage bias, location parameters indicating the location of memory cells, contact connector thickness parameters, verification voltage, and / or the like. Location parameters may indicate the location of memory cells within the entire array of NAND strings, the location of memory cells within a specific group of NAND strings, the location of memory cells on a specific plane, and / or the like. Contact connector thickness parameters may indicate the thickness of the contact connector, the substrate or material included with the contact connector, and / or the like.

[0054] On-chip address decoder 114 provides an address interface used by the host or memory controller between the hardware addresses used by decoders 124 and 132. Power control module 116 controls the power and voltage supplied to word lines and bit lines during memory operation. It may include drivers for word lines, SGS transistors and SGD transistors, and source lines. In one approach, a sensing block may include bit line drivers. The SGS transistor is a select-gate transistor at the source terminal of the NAND string, and the SGD transistor is a select-gate transistor at the drain terminal of the NAND string.

[0055] In some implementations, some of the components may be combined. In various designs, one or more components (alone or in combination) other than memory structure 126 may be considered as at least one control circuit configured to perform the actions described herein. For example, the control circuit may include any or a combination of control circuit 110, state machine 112, decoder 114 / 132, power control module 116, sensing blocks SBb, SB2, ..., SBp, read / write circuit 128, controller 122, etc.

[0056] The control circuit 150 may include a programming circuit 151 configured to perform programming and verification operations on a set of memory cells, wherein the set of memory cells includes memory cells assigned to represent one of a plurality of data states and memory cells assigned to represent another of the plurality of data states; the programming and verification operations include a plurality of programming and verification iterations; and in each programming and verification iteration, the programming circuit performs programming on a selected word line, after which the programming circuit applies a verification signal to the selected word line. The control circuit 150 may also include a counting circuit 152 configured to obtain a count of memory cells that have passed the verification test for the one data state. The control circuit 150 may also include a determining circuit 153 configured to determine whether the programming operation is complete based on the amount by which the count exceeds a threshold.

[0057] For example, Figure 1B This is a block diagram of an example control circuit 150, including a programming circuit 151, a counting circuit 152, and a determining circuit 153.

[0058] The off-chip controller 122 may include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, an error correction code (ECC) engine 245, and a reference voltage engine 246. The ECC engine can correct the number of read errors caused when the upper tail of the Vt distribution becomes too high. However, in some cases, uncorrectable errors may exist. The techniques presented herein reduce the likelihood of uncorrectable errors.

[0059] Storage devices 122a and 122b include code such as an instruction set, and processor 122c is operable to execute the instruction set to provide the functionality described herein. Alternatively or otherwise, processor 122c may access the code from storage device 126a of memory structure 126 (such as a reserved area of ​​memory cells in one or more word lines). For example, the code may be used by controller 122 to access memory structure 126, such as to perform programming, reading, and erasing operations. The code may include boot code and control code (e.g., an instruction set). Boot code is software that initializes controller 122 during a boot or startup process and enables controller 122 to access memory structure 126. The code may be used by controller 122 to control one or more memory structures 126. Upon power-up, processor 122c retrieves boot code from ROM 122a or storage device 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM 122b, it is executed by processor 122c. The control code includes drivers for performing basic tasks such as controlling and allocating memory, determining the priority of instruction processing, and controlling input and output ports.

[0060] Typically, control code may include instructions for performing the functions described herein (including the steps in the flowcharts discussed further below) and providing voltage waveforms (including those discussed further below). For example, as Figure 1C As shown, control circuitry 110, controller 122, control circuitry 150, and / or any other circuitry are configured / programmed during memory operation to determine at step 160 whether the selected word line WLn is a bottom-of-layer word line in the memory block or one of other word lines in the memory block. At step 161, in response to the selected word line WLn being one of other word lines, a set of reference voltages to be used for subsequent sensing operations is set to a first set of reference voltages, and in response to the selected word line WLn being a bottom-of-layer word line, the set of reference voltages is set to a second set of reference voltages. At step 162, a sensing operation is performed. In some embodiments, the sensing operation is a verification operation. In some other embodiments, the sensing operation is a read operation. These techniques are discussed in more detail below.

[0061] In one embodiment, the host is a computing device (e.g., a laptop, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0062] Other types of non-volatile memory besides NAND flash memory can also be used.

[0063] Semiconductor memory devices include volatile memory devices (such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices), non-volatile memory devices (such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which can be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”)), as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured with NAND or NOR.

[0064] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements (such as antifuse or phase-change materials) and optional manipulation elements (such as diodes or transistors). Further, as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0065] Multiple memory elements can be configured such that they are connected in series or that each element is individually accessible. As a non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically contains memory elements connected in series. A NAND string is an example of a group of transistors and SG transistors connected in series, comprising memory cells.

[0066] NAND memory arrays can be configured such that the array consists of multiple memory strings, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, for example, a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional memory structures or three-dimensional memory structures.

[0067] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single planar level or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane extending substantially parallel to the main surface of the substrate supporting the memory elements (e.g., in an xy-direction plane). The substrate can be a wafer on which or in which the memory element layer is formed, or the substrate can be a carrier substrate attached to the memory element after it has been formed. As a non-limiting example, the substrate can include a semiconductor, such as silicon.

[0068] Memory elements can be arranged in an ordered array (such as in multiple rows and / or columns) within a single memory device level. However, memory elements can be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0069] The three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y and z directions, where the z direction is substantially perpendicular to the main surface of the substrate, and the x and y directions are substantially parallel to the main surface of the substrate).

[0070] As a non-limiting example, a three-dimensional memory structure can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate (i.e., in the y-direction), with each column having multiple memory elements. The columns can be arranged in a two-dimensional configuration (e.g., in the xy-plane), resulting in a three-dimensional arrangement of memory elements having elements on multiple vertically stacked memory planes. Other configurations of the three-dimensional memory elements can also constitute a three-dimensional memory array.

[0071] As a non-limiting example, in a three-dimensional array of NAND strings, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0072] Typically, in a monolithic three-dimensional memory array, one or more memory device classes are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers located at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic three-dimensional array, the layer constituting each memory device class of the array is typically formed on the layer of the lower memory device class of the array. However, the layers of adjacent memory device classes in a monolithic three-dimensional memory array may be shared or intermediate layers may be present between memory device classes.

[0073] Similarly, two-dimensional arrays can be formed independently and then packaged together to form a non-monolithic memory device with multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Alternatively, multiple (monolithic or non-monolithic) two-dimensional or three-dimensional memory arrays can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0074] Figure 2Memory blocks 200, 210 of memory cells in an example two-dimensional configuration of memory array 126 of FIG1 are shown. Memory array 126 may contain a plurality of such blocks 200, 210. Each example block 200, 210 includes multiple NAND strings and corresponding bit lines, such as BL0, BL1, ..., which are shared between blocks. Each NAND string is connected at one end to a drain-side select gate (SGD), and the control gate of the drain-side select gate is connected via a common SGD line. The NAND string is connected at its other end to a source-side select gate (SGS), which is in turn connected to a common source line 220. One hundred and twelve word lines (e.g., WL0 to WL111) extend between the SGS and the SGD. In some embodiments, a memory block may include more or fewer than one hundred and twelve word lines. For example, in some embodiments, a memory block includes one hundred and sixty-four word lines. In some cases, virtual word lines without user data may also be used in the memory array adjacent to the select gate transistor or between certain data word lines. Such virtual word lines can shield edge data word lines from certain edge effects.

[0075] One type of non-volatile memory that can be set in a memory array is a floating-gate memory, such as... Figure 3A and Figure 3B The type shown. However, other types of non-volatile memory can also be used. As discussed in further detail below, in... Figure 4A and Figure 4B In another example shown, the charge-trapping memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A three-layer dielectric composed of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is sandwiched between the surface of a semi-conductive substrate and the conductive control gate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where these electrons are trapped and stored in a limited area. The stored charge then detectably alters a threshold voltage of a portion of the cell channel. The cell is erased by injecting a hot hole into the nitride. A similar cell can be provided in a split-gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate selection transistor.

[0076] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends across a channel diffused between the source and drain. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for another data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is achieved by independently reading the binary states of spatially independent charge storage regions within the dielectric. Other types of non-volatile memories are also known.

[0077] Figure 3A Cross-sectional views of example floating-gate memory cells 300, 310, and 320 in a NAND string are shown. In this figure, bit lines or NAND string directions enter the page, and word line directions are from left to right. For example, word line 324 extends across a NAND string including corresponding channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and a channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and a channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and a channel region 326. Each memory cell 300, 310, and 320 is in a different corresponding NAND string. A polysilicon interlayer dielectric (IPD) layer 328 is also shown. Control gates 302, 312, and 322 are portions of word lines. Figure 3B A cross-sectional view along the contact line connector 329 is provided.

[0078] Control gates 302, 312, and 322 are wrapped around floating gates 304, 314, and 321, thereby increasing the surface contact area between control gates 302, 312, and 322 and floating gates 304, 314, and 321. This results in higher IPD capacitance, leading to a higher coupling ratio, which makes programming and erasing easier. However, as NAND memory devices are miniaturized, the spacing between adjacent cells 300, 310, and 320 becomes smaller, so there is almost no space between two adjacent floating gates 302, 312, and 322 for control gates 302, 312, and 322 and the IPD layer 328.

[0079] As an alternative form, such as Figure 4A and Figure 4BAs shown, planar or flat memory cells 400, 410, and 420 have been developed, wherein control gates 402, 412, and 422 are planar or flat; that is, the control gate is not enclosed on the floating gate, and the control gate only contacts the charge storage layer 428 from above it. In this case, having a high floating gate offers no advantage. Instead, the floating gate is fabricated to be thinner. Furthermore, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This method avoids the problem of ballistic electron transport, where electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0080] Figure 4A A cross-sectional view of example charge-trapping memory cells 400, 410, and 420 in a NAND string is shown. As a two-dimensional example of memory cells 400, 410, and 420 in the memory cell array 126 of FIG. 1, this view is in the word line direction of the memory cells 400, 410, and 420, which include a flat control gate and charge-trapping regions. Charge-trapping memory can be used in NOR and NAND flash memory devices. This technology uses an insulator (such as a SiN film) to store electrons, compared to floating-gate MOSFET technology which uses conductors (such as doped polysilicon) to store electrons. As an example, word line 424 extends across a NAND string including corresponding channel regions 406, 416, and 426. A portion of the word line provides control gates 402, 412, and 422. Below the word line are IPD layers 428, charge-trapping layers 404, 414, and 421, polysilicon layers 405, 415, and 425, and tunneling layers 409, 407, and 408. Each charge trapping layer 404, 414, 421 extends continuously within its respective NAND string. The flat configuration of the control gate can be manufactured thinner than a floating gate. Furthermore, memory cells can be placed more closely together.

[0081] Figure 4B It shows Figure 4A The structure is shown in a cross-sectional view along the contact connector 429. The NAND string 430 includes an SGS transistor 431, example memory cells 400, 433, ... 435, and an SGD transistor 436. Passages in the IPD layer 428 of the SGS transistor 431 and SGD transistor 436 allow communication between the control gate layer 402 and the floating gate layer. For example, the control gate layer 402 and the floating gate layer can be polysilicon, and the tunnel oxide layer can be silicon oxide. The IPD layer 428 can be a stack of nitride (N) and oxide (O), such as in a NONON configuration.

[0082] NAND strings can be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. The channel voltage Vch can be directly applied to the channel region of the substrate.

[0083] Figure 5 An example block diagram of the sensing block SB1 of Figure 1 is shown. In one approach, the sensing block includes multiple sensing circuits. Each sensing circuit is associated with a data latch. For example, example sensing circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different corresponding sensing blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sensing circuits to be partitioned and processed by a corresponding processor in each sensing block. For example, a sensing circuit controller 560 in SB1 can communicate with this group of sensing circuits and latches. The sensing circuit controller 560 may include a precharge circuit 561 that provides a voltage to each sensing circuit to set a precharge voltage. In one possible approach, the voltage is provided independently to each sensing circuit, for example, via a data bus and a local bus. In another possible approach, a common voltage is provided to each sensing circuit simultaneously. The sensing circuit controller 560 may also include the precharge circuit 561, a memory 562, and a processor 563. Memory 562 may store code that can be executed by a processor to perform the functions described herein. These functions may include: reading latches 550b, 551b, 552b, and 553b associated with sensing circuits 550a, 551a, 552a, and 553a; setting bit values ​​in the latches; and providing voltage to set the precharge level in the sensing nodes of sensing circuits 550a, 551a, 552a, and 553a. Further example details of the sensing circuit controller 560 and sensing circuits 550a, 551a, 552a, and 553a are provided below.

[0084] In some embodiments, a memory cell may include a tag register comprising a set of latches storing tag bits. In some embodiments, a number of tag registers may correspond to a number of data states. In some embodiments, one or more tag registers may be used to control the type of verification technique used when verifying a memory cell. In some embodiments, the output of the tag bits may modify associated logic of the device (e.g., address decoding circuitry) such that a designated block of the cell is selected. Tag settings in the tag registers, or combinations of tag registers and address registers (e.g., in implicit addressing), or alternatively, batch operations (e.g., erase operations, etc.) may be performed using direct addressing with address registers alone.

[0085] Figure 6A This is a perspective view of a set of blocks 600 in an example three-dimensional configuration of the memory array 126 of FIG1. ​​On the substrate are example blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements) and a peripheral region 604 having circuitry used by blocks BLK0, BLK1, BLK2, and BLK3. For example, the circuitry may include a voltage driver 605 connectable to a control gate layer of blocks BLK0, BLK1, BLK2, and BLK3. In one approach, the control gate layer at a common height in blocks BLK0, BLK1, BLK2, and BLK3 is driven. The substrate 601 may also carry circuitry beneath blocks BLK0, BLK1, BLK2, and BLK3, and one or more lower metal layers patterned in the conductive paths of signals carrying the circuitry. Blocks BLK0, BLK1, BLK2, and BLK3 are formed in a middle region 602 of the memory device. In an upper region 603 of the memory device, one or more upper metal layers are patterned in the conductive paths of signals carrying the circuitry. Each block BLK0, BLK1, BLK2, BLK3 includes a stacked region of memory cells, where alternating levels of the stack represent word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has opposing layered sides, from which vertical contacts extend upwards to an upper metal layer to form connections to conductive paths. Although four blocks BLK0, BLK1, BLK2, BLK3 are shown as an example, two or more blocks extending in the x and / or y directions can be used.

[0086] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends within the one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends within the one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0087] Figure 6B It shows Figure 6A An example cross-sectional view of a portion of one of blocks BLK0, BLK1, BLK2, and BLK3. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, in addition to data word line layers (word lines) WL0 to WL111, the conductive layers include two SGD layers, two SGS layers, and four virtual word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL116. Additionally, a region of stack 610 including NAND strings NS1 and NS2 is shown. Each NAND string encompasses a memory cavity 618 or 619 filled with material forming memory cells adjacent to the word lines. Region 622 of stack 610 is shown... Figure 6D This is illustrated in more detail below and discussed further. The dielectric layer can have a variable thickness, allowing some conductive layers to be closer to or further away from adjacent conductive layers. The thickness of the dielectric layer affects the "ON pitch," which is a factor in memory density. Specifically, a smaller ON pitch allows for more memory cells in a given area but may compromise reliability.

[0088] Stack 610 includes a substrate 611, an insulating film 612 on the substrate 611, and a portion of a source line SL. NS1 has a source terminal 613 at the bottom 614 of the stack and a drain terminal 615 at the top 616 of the stack 610. Contact line connectors (e.g., slots, such as metal-filled slots) 617, 620 may be periodically provided across the stack 610 as interconnects extending through the stack 610, such as to connect source lines to lines above the stack 610. Contact line connectors 617, 620 may be used during word line formation and subsequently metal-filled. A portion of a bit line BL0 is also shown. A conductive via 621 connects the drain terminal 615 to BL0.

[0089] Figure 6C It shows Figure 6B A drawing of the diameter of memory holes in a stack. The vertical axis is... Figure 6B The stack alignment is shown, and the width (wMH) (e.g., diameter) of memory holes 618 and 619 is shown. Figure 6A Word line layers WL0 to WL111 are repeated as examples, and at corresponding heights z0 to z111 in the stack. In such memory devices, the memory holes etched through the stack have very high aspect ratios. For example, depth-to-diameter ratios of approximately 25 to 30 are common. The memory holes may have a circular cross-section. Due to the etching process, the width of the memory hole can vary along the length of the hole. Typically, the diameter gradually decreases from the top to the bottom of the memory hole. That is, the memory hole is tapered, narrowing at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the hole near the select gate, making the diameter slightly wider before it gradually decreases from the top to the bottom of the memory hole.

[0090] Figure 6D It shows Figure 6BA close-up view of region 622 of the stack 610. Memory cells are formed at different levels of the stack at the intersection of word line layers and memory holes. In this example, SGD transistors 680, 681 are disposed above virtual memory cells 682, 683 and data memory cells MC. Multiple layers may be deposited along the sidewalls (SW) of memory holes 630 and / or within each word line layer, for example, using atomic layer deposition. For example, each column (e.g., a pillar formed by material within memory holes 630) may include a charge trapping layer or film 663 (such as SiN or other nitrides), a tunneling layer 664, a polysilicon body or channel 665, and a dielectric core 666. The word line layer may include a blocking oxide / blocking high-k material 660, a metal barrier 661, and a conductive metal (such as tungsten) as a control gate. For example, control gates 690, 691, 692, 693, and 694 are disposed. In this example, all layers except the metal are disposed within the memory cavity 630. In other methods, some layers may be located within the control gate layer. Similarly, additional pillars are formed in different memory cavities. These pillars may form columnar active regions (AA) of the NAND string.

[0091] When a memory cell is programmed, electrons are stored in a portion of the charge-trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge-trapping layer and then through the tunneling layer. The threshold voltage Vt of the memory cell increases proportionally to the amount of charge stored. During sensing operations, the threshold voltage Vt is detected or measured. During erasing operations, the electrons return to the channel.

[0092] Each memory cavity in memory cavity 630 may be filled with multiple annular layers, including a blocking oxide layer, a charge trapping layer 663, a tunneling layer 664, and a channel layer. The core region of each memory cavity in memory cavity 630 is filled with a host material, and the multiple layers are located between the core region and the word line layer in each memory cavity of memory cavity 630. In some cases, the charge trapping layer 663 and the tunneling layer 664 are annular in shape. In other cases, as discussed in further detail below, these layers are semi-circular in shape.

[0093] NAND strings can be considered to have floating body channels because the length of the channels is not formed on the substrate. Furthermore, NAND strings are provided by multiple word line layers stacked one on top of the other and separated from each other by dielectric layers.

[0094] Figure 7A It shows Figure 6BA top view of an example word line layer WL0 of the stack 610. As mentioned, a three-dimensional memory device may include a stack of alternating conductive and dielectric layers. The conductive layers provide the control gates for SG transistors and memory cells. The layer for the SG transistors is the SG layer, while the layer for the memory cells is the word line layer. Additionally, memory holes are formed in the stack and filled with charge trapping material and channel material. Thus, vertical NAND strings are formed. Source lines are connected to the NAND strings below the stack, and bit lines are connected to the NAND strings above the stack.

[0095] In a three-dimensional memory device, a block BLK can be divided into sub-blocks, each sub-block comprising a group of NAND strings sharing a common SGD control line. See, for example, the SGD lines / control gates SGD0, SGD1, SGD2, and SGD3 in sub-blocks SBBa, SBb, SBc, and SBd, respectively. Additionally, the word line layer within the block can be divided into regions. Each region is within a corresponding sub-block and can extend between contact line connectors (e.g., slots) periodically formed in the stack to process the word line layer during the manufacturing process of the memory device. This processing may include replacing the sacrificial material of the word line layer with metal. Generally, the distance between the contact line connectors should be relatively small to account for limitations on the distance that etchant can travel laterally to remove the sacrificial material and that metal can travel to fill the gaps created by the removal of the sacrificial material. For example, the distance between the contact line connectors may allow for several rows of memory holes between adjacent contact line connectors. The layout of the memory holes and contact line connectors should also consider limitations on the number of bit lines that can extend across the region when each bit line is connected to a different memory cell. After processing the word line layer, contact line connectors can optionally be filled with metal to provide interconnects via stacking.

[0096] In this example, four rows of memory holes exist between adjacent contact line connectors. Here, a row is a set of memory holes aligned in the x-direction. Furthermore, the rows of memory holes are staggered to increase the density of the memory holes. Word line layers, or word lines, are divided into regions WL0a, WL0b, WL0c, and WL0d, each connected by contact line 713. In one method, the last region of a word line layer in a block can be connected to the first region of a word line layer in the next block. Contact line 713 is then connected to a voltage driver for the word line layer. Region WL0a has example memory holes 710, 711 along contact line 712. Region WL0b has example memory holes 714, 715. Region WL0c has example memory holes 716, 717. Region WL0d has example memory holes 718, 719. Memory holes are also... Figure 7BAs shown in the diagram, each memory hole can be a portion of the corresponding NAND string. For example, memory holes 710, 714, 716, and 718 can be portions of the NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, respectively.

[0097] Each circle represents a cross-section of a memory cavity at a word line layer or SG layer. Example circles shown in dashed lines represent the material within the memory cavity and the memory cells provided by adjacent word line layers. For example, memory cells 720 and 721 are in WL0a, memory cells 724 and 725 are in WL0b, memory cells 726 and 727 are in WL0c, and memory cells 728 and 729 are in WL0d. These memory cells are at a common height in the stack.

[0098] Contact line connectors (e.g., slots, such as metal-filled slots) 701, 702, 703, 704 may be located between and adjacent to the edges of regions WL0a to WL0d. Contact line connectors 701, 702, 703, 704 provide a conductive path from the bottom to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductive line above the stack, wherein the conductive line connects to a voltage driver in a peripheral region of the memory device.

[0099] Figure 7B It shows Figure 6B A top view of the top dielectric layer DL116 in an example stack. The dielectric layer is divided into regions DL116a, DL116b, DL116c, and DL116d. Each region can be connected to a corresponding voltage driver. This allows a group of memory cells in a region of the word line layer to be programmed simultaneously, with each memory cell in a corresponding NAND string connected to a corresponding bit line. A voltage can be set on each bit line during each programming, sensing, or erasing operation.

[0100] Region DL116a has example memory holes 710, 711 along contact line 712 coinciding with bit line BL0. Multiple bit lines extend over and connect to the memory holes, as indicated by the "X" symbol. BL0 is connected to a set of memory holes including memory holes 711, 715, 717, and 719. Another example bit line BL1 is connected to a set of memory holes including memory holes 710, 714, 716, and 718. Figure 7A Contact line connectors (e.g., slots, such as metal-filled slots) 701, 702, 703, 704 are also shown as extending vertically through the stack. Bit lines may span the DL116 layers in the x-direction, numbered sequentially from BL0 to BL23.

[0101] Different subsets of the bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to memory cells in the first row of cells at the right edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to memory cells in the adjacent row of cells adjacent to the first row at the right edge. BL3, BL7, BL11, BL15, BL19, and BL23 are connected to memory cells in the first row of cells at the left edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to memory cells in the adjacent row of cells adjacent to the first row at the left edge.

[0102] Turn now Figure 8 In an exemplary embodiment, each memory hole in the memory block includes an upper memory hole 800 (upper layer) and a lower memory hole 802 (bottom layer). Each of the upper memory hole 800 and the lower memory hole 802 is truncated conical in shape, having a larger diameter at its upper end and a smaller diameter at its lower end. Therefore, for each of the upper and lower memory holes, there exists an upper word line with a relatively large diameter and a bottom word line with a relatively small diameter.

[0103] According to exemplary embodiments of this disclosure, word lines are divided into pairs of regions, groups, or clusters based on the diameter of the memory holes, and the word lines of each region or group may be discontinuous. More specifically, the bottom word lines of both the upper and lower memory holes are hereinafter referred to as "layer bottom word lines 804". In an exemplary embodiment, for each of the upper memory hole 800 and the lower memory hole 802, the ten word lines having the smallest memory hole are the layer bottom word lines 804, for example, WL0 to WL9 and WL81 to 90. In some other embodiments, the layer bottom word lines 804 may include more or fewer than ten word lines. In some further embodiments, the number of layer bottom word lines for the upper memory hole may differ from the number for the lower memory hole. In still further embodiments, the number of layers in the memory block may be more or fewer than two (e.g., three or more layers including one or more intermediate layers).

[0104] In this exemplary embodiment, both the bottom word line 804 itself and the dielectric layer DL between the bottom word lines 804 are thicker than the non-bottom word line 806 and the dielectric layer DL between the non-bottom word lines 806 (hereinafter referred to as "other word lines"). Therefore, the ON spacing between adjacent bottom word lines is greater than the ON spacing in other parts of the memory block.

[0105] The memory cells of a memory block can be programmed to store one or more data bits in multiple data states, each of which is associated with a corresponding threshold voltage Vt range and with a corresponding bit or bit series. For example, Figure 9 The threshold voltage Vt distribution of a set of memory cells programmed according to a three-bit-per-cell (TLC) memory scheme is depicted. In the TLC memory scheme, there are a total of eight data states: an erase state (Er) and seven programming data states (S1, S2, S3, S4, S5, S6, and S7). Each programming data state (S1 to S7) is associated with a corresponding verification voltage, which is applied during the verification portion of the programming operation. Other memory schemes are also available, such as one-bit-per-cell (SLC) with two data states, two-bit-per-cell (MLC) with four data states, four-bit-per-cell (QLC) with sixteen data states, or five-bit-per-cell (PLC) with thirty-two data states. However, the following discussion focuses primarily on the TLC memory scheme.

[0106] Programming memory cells occurs on a word-line basis, proceeding from one side of the memory block towards the opposite side. Typically, programming memory cells on a selected word line to maintain multiple bits per memory cell (e.g., MLC, TLC, or QLC) begins with the memory cell in an erase data state Er and includes multiple program cycles, each consisting of both a programming pulse and a verification operation. During the programming pulse, the threshold voltage Vt of the memory cell being programmed increases, while the threshold voltage Vt of memory cells already in their final data state is suppressed. During the verification operation, the threshold voltage Vt of the memory cell being programmed is compared to a verification voltage Vv associated with its final data state during a sensing operation.

[0107] Turn now Figure 10 The sensing operation (verification or read) begins when the sensing node SEN on the drain side of the memory block is charged to a predetermined charging voltage. Simultaneously, a selected memory cell in a selected NAND string containing a selected word line WLn is connected by a voltage VREAD, except for the selected memory cell. A reference voltage VCG (e.g., ...) is then applied. Figure 9 Any of Vv1 to Vv7 described in the text (depending on which data state is being verified) is applied to the control gate of the selected word line WLn.

[0108] The sensing node SEN then discharges through the NAND string. Since all memory cells in the memory cell except the selected memory cell are turned on by the increased pass voltage VREAD, the discharge current Icell through the NAND string is mainly determined by whether the selected memory cell is turned on or off by the reference voltage VCG (i.e., whether the threshold voltage Vt of the memory cell is lower or higher than the reference voltage VCG).

[0109] At discharge time T_sense, the voltage on the SEN node is sensed by the sensing circuit and compared with V_sense (which is the threshold voltage Vt of the ΔVPGM sensing transistor). If the threshold voltage Vt of the selected memory cell being sensed is higher than the reference voltage VCG, the selected memory cell is not turned on by the reference voltage VCG and conducts a very small / negligible current, resulting in only a small discharge of the SEN node voltage. Therefore, the SEN node voltage will remain higher than V_sense. On the other hand, if the threshold voltage Vt of the selected memory cell being sensed is lower than the reference voltage VCG, the reference voltage VCG will turn on the selected memory cell and a larger discharge current will cause the SEN node to have a voltage lower than V_sense. This process is performed for each memory cell of the selected word line WLn to read the data stored in the memory cell of the selected word line WLn.

[0110] Return to Figure 9 Generally speaking, the larger the voltage gap or margin between two adjacent data states, the higher the reliability. More specifically, a larger margin makes it easier for memory devices to distinguish data states. However, two issues that can affect the margin between data states and compromise reliability are True Temperature Data Retention (TTDR) and Read Disturbance (RD).

[0111] TTDR occurs when electrons leak from the charge trapping layer in a memory cell, thereby reducing the threshold voltage Vt of the affected memory cell. Memory cells in the highest data state S7, which is associated with the highest threshold voltage range, are particularly susceptible to TTDR. Figure 11 The threshold voltage Vt distribution of multiple memory cells that have experienced significant TTDR is depicted. As shown, the lower tail of the S7 data state has been shifted downwards, thereby reducing the margin between the S6 and S7 data states. Furthermore, some memory cells in the S7 data state now have a threshold voltage Vt lower than the reference voltage Vr7 associated with the S7 data state. These memory cells are misread as being in the S6 data state, resulting in failure bits.

[0112] Conversely, RD occurs when a memory cell is unintentionally programmed by an elevated pass voltage VREAD, which is applied to an unselected word line during a sensing operation (read or verify). Memory cells in the erase data state Er are particularly susceptible to RD because they have the lowest threshold voltage Vt. Figure 12 The threshold voltage Vt distribution of multiple memory cells that have undergone significant RD is depicted. As shown in the figure, the upper tail of the erase data state Er has been shifted upwards, thereby reducing the margin between the Er data state and the S1 data state. Furthermore, some memory cells in the erase data state Er now have a threshold voltage Vt higher than the reference voltage Vr1 associated with the S1 data state. These memory cells may be misread as being in the S1 data state, resulting in failure bits.

[0113] One way to mitigate the impact of TTDR is to increase the margin between the S6 and S7 data states, and another way to mitigate the impact of RD is to increase the margin between the Erase data state and the S1 data state. However, the available margins for these adjustments are limited without significantly impairing programming performance. Therefore, these methods lead to a trade-off between mitigating TTDR and RD.

[0114] One aspect of this disclosure relates to techniques for operating memory devices that mitigate both TTDR and RD while maintaining high programming performance. According to these techniques, the verification voltage Vv applied to the word lines during programming is specifically optimized across memory blocks based on whether the memory cells of those word lines are susceptible to either TTDR or RD.

[0115] Move to Figure 13During programming of memory cells on "other word lines" (excluding bottom-level word lines), a first set of verification voltages Vv1 to Vv7 is used. Conversely, during programming of memory cells on bottom-level word lines, a different second set of verification voltages Vv1_Bottom to Vv7_Bottom is used. The verification voltages Vv7 and Vv7_Bottom associated with the S7 data state are the same in both sets. However, for other data states S1 to S6, the verification voltages of the second set are greater than those of the first set. In other words, Vv1_Bottom > Vv1, Vv2_Bottom > Vv2, Vv3_Bottom > Vv3, Vv4_Bottom > Vv4, Vv5_Bottom > Vv5, and Vv6_Bottom > Vv6. More specifically, for data states S1 to S6, the verification voltage of the second group is offset from the bottom of the layer for a specific data state compared to the verification voltage of the first group, i.e., Vvn_Bottom = Vvn + Sn_Bottom_Offset. For example, Vv1_Bottom = Vv1 + S1_Bottom_Offset, Vv2_Bottom = Vv2 + S2_Bottom_Offset, and so on.

[0116] Figure 14 The threshold voltage Vt distributions for multiple memory cells programmed using the first set of verification voltages (solid lines) and the second set of verification voltages (dashed lines) are shown. Compared to other word lines, the second set of verification voltages Vv1_Bottom to Vv7_Bottom provides an increased margin between the erase data state Er and the S1 data state of memory cells in the bottom-layer word line. In other words, the margin M1_Bottom is greater than the margin M1. It has been found that memory cells in the bottom-layer word line are more susceptible to RD and less susceptible to TTDR compared to other word lines. Therefore, the larger margin M1_Bottom provides protection against the increase in failure bits due to RD for memory cells in the bottom-layer word line.

[0117] Therefore, memory cells on other word lines are more susceptible to TTDR and less susceptible to RD than those on the bottom word line. Because the first and second set of verification voltages have the same verification voltage for the S7 data state (Vv7 = Vv7_Bottom), the margin between the S6 and S7 data states in other word lines (M7) is greater than the same margin in the bottom word line (M7_Bottom). This increased margin between the S6 and S7 data states provides protection for the memory cells on other word lines against the increase in failure bits due to TTDR.

[0118] The technology disclosed herein thus optimizes the protection of failure bits in memory cells for both bottom-layer word lines and other word lines. Therefore, reliability is improved without performance loss or with minimal performance loss. If the optimal settings for the bottom-layer word line can be different, we can also consider using different S7 verifications (Vv7).

[0119] According to some techniques, the reference voltage Vrn used during the read operation is compared with the reference voltage Vvn used during the verification operation for a specific read offset of the big data state, that is, Vrn = Vvn + Sn_Read_Offset.

[0120] According to another aspect of this disclosure, the reference voltage Vrn used during the reading of a memory cell on a bottom-layer word line is offset from both the verification voltage and the state-specific bottom-layer offset. Therefore, during the reading of one of the data states S1 to S7 in one of the bottom-layer word lines, the reference voltage VCG applied to the selected word line is equal to Vrn = Vvn + Sn_Bottom_Offset + Sn_Read_Offset. For example, for the reading of data state S1, the reference voltage Vr1 is set to Vv1 + S1_Bottom_Offset + S1_Read_Offset. By offsetting the read voltage Vr from both the verification voltage Vv and the data state-specific bottom offset, the number of failure bits is further reduced during the read operation. The read offset S7_Read_Offset for the S7 data state can be any suitable value, including 0V in some embodiments.

[0121] Another aspect of this disclosure relates to a method for programming memory cells of selected word lines of a memory device. Figure 15 This is a flowchart 1500 depicting the steps of performing the operation according to an exemplary embodiment of this disclosure. These steps may be performed by: a controller; a processor or processing device or any other circuitry that executes instructions stored in memory; and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0122] At step 1502, programming begins on the memory cell of the selected word line WLn. At step 1504, the memory device determines whether the selected word line WLn is a bottom-of-layer word line or one of other word lines. At decision step 1506, it is determined whether the selected word line WLn is a bottom-of-layer word line. If the answer at decision step 1506 is "no", then at step 1508, the set of verification voltages to be used for subsequent programming operations is the first set of verification voltages Vv1 to Vv7. If the answer at decision step 1506 is "yes", then at step 1510, the set of verification voltages to be used for subsequent programming operations is the second set of verification voltages Vv1_Bottom to Vv7_Bottom. After steps 1508 or 1510, at step 1512, the memory cell of the selected word line WLn is programmed in multiple program loops using either the first set of verification voltages Vv1 to Vv7 or the second set of verification voltages Vv1_Bottom to Vv7_Bottom. In either case, the verification voltage used during the verification of the S7 data state is the same, i.e., Vv7 = Vv7_Bottom.

[0123] Another aspect of this disclosure relates to a method for reading memory cells of a selected word line of a memory device. Figure 16 This is a flowchart 1600 depicting the steps of performing the operation according to an exemplary embodiment of this disclosure. These steps may be performed by: a controller; a processor or processing device or any other circuitry that executes instructions stored in memory; and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0124] At step 1602, a read instruction for the selected word line WLn is received. At step 1604, the memory device determines what type of word line the selected word line WLn is, i.e., a bottom-of-layer word line or another word line. At decision step 1606, it is determined whether the selected word line WLn is a bottom-of-layer word line. If the answer at decision step 1606 is "no", then at step 1608, for each of data states S1 to S7, the read voltage Vrn is set to the verification voltage Vvn plus the read offset Sn_Read_Offset, i.e., Vrn = Vvn + Sn_Read_Offset. If the answer at decision step 1606 is "yes", then at step 1610, for data states S1 to S7, the read voltage Vrn is set to the verification voltage Vvn plus the read offset Sn_Read_Offset and the bottom-of-layer offset Sn_Bottom_Offset, i.e., Vrn = Vvn + Sn_Read_Offset + Sn_Bottom_Offset. In some implementations, S7_Read_Offset can be set to zero volts (0V). At step 1612, a read operation is performed on the selected word line WLn using read voltages Vr1 to Vr7.

[0125] This document uses various terms to refer to specific system components. Different companies may use different names to refer to the same or similar components, and this description is not intended to distinguish components with different names rather than different functions. With regard to the various functional units described in the following disclosure being referred to as “modules,” such characterization is intended not to unduly limit the scope of possible specific implementation mechanisms. For example, a “module” may be implemented as hardware circuitry including custom-designed very large-scale integration (VLSI) circuitry or gate arrays, or as off-the-shelf semiconductors including logic chips, transistors, or other discrete components. In further examples, modules may also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, etc. Furthermore, modules may also be implemented in software, at least in part, by various types of processors. For example, a module may include executable code segments that constitute one or more physical or logical blocks of computer instructions that translate into objects, processes, or functions. Moreover, it is not required that the executable portions of such modules be physically located together, but rather that they may include different instructions stored in different locations, and that these instructions, when executed together, may include the identified module and achieve the stated purpose of the module. Executable code may include a single instruction or a set of instructions, and may be distributed across different code segments, different programs, or across several memory devices. In specific implementations of software or portions of software or modules, the software portions may be stored on one or more computer-readable and / or executable storage media, including but not limited to electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based systems, apparatuses, or devices, or any suitable combination thereof. Generally, for the purposes of this disclosure, computer-readable and / or executable storage media may include any tangible and / or non-transitory medium capable of containing and / or storing programs for use by or in conjunction with an instruction execution system, apparatus, processor, or device.

[0126] Similarly, for the purposes of this disclosure, the term "component" can include any tangible, physical, and non-transitory device. For example, a component can be in the form of hardware logic circuitry, including custom VLSI circuitry, gate arrays, or other integrated circuits, or including off-the-shelf semiconductors (including logic chips, transistors, or other discrete components), or any other suitable mechanical and / or electronic equipment. Furthermore, components can also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, etc. Additionally, a component can include one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages) or other discrete electrical devices that are in an electrically communicative configuration with one or more other components via electrical conductors such as printed circuit boards (PCBs). Therefore, modules as defined above can be embodied in or implemented as components in some embodiments, and in some cases, the terms module and component can be used interchangeably.

[0127] As used herein, the term "circuit" includes one or more electrical and / or electronic components that form one or more conductive paths that allow current to flow. A circuit can be in the form of a closed-loop configuration or an open-loop configuration. In a closed-loop configuration, the circuit components provide a return path for current. In contrast, in an open-loop configuration, the circuit components are still considered to form a circuit, although a return path for current is not included. For example, an integrated circuit is referred to as a circuit regardless of whether it is grounded (as a return path for current). In some exemplary embodiments, a circuit may include a set of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit may include custom VLSI circuitry, gate arrays, logic circuitry, and / or other forms of integrated circuits, and may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In another example, a circuit may include one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages) or other discrete electrical devices that are in an electrically communicative configuration with one or more other components via electrical conductors, such as a printed circuit board (PCB). A circuit may also be implemented as a composite circuit relative to programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, and / or programmable logic devices. In other exemplary embodiments, the circuit may include a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Therefore, modules as defined above may be embodied in or implemented as circuits in some embodiments.

[0128] It should be understood that the exemplary embodiments disclosed herein may include one or more microprocessors and specifically stored computer program instructions that control one or more microprocessors in combination with certain non-processor circuitry and other elements to implement some, most, or all of the functions disclosed herein. Alternatively, some or all of the functions may be implemented by a state machine without stored program instructions, or in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), wherein each or some combinations of the functions are implemented as custom logic. Combinations of these methods may also be used. Furthermore, the reference to “controller” below should be defined as including individual circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), field-programmable gate arrays (FPGAs) and / or processors with control software, or combinations thereof.

[0129] Additionally, as may be used herein, the term "coupled / couples" is intended to refer to direct or indirect connections. Thus, if a first device is coupled to or is coupled to a second device, the connection can be either a direct connection or an indirect connection via other devices (and components).

[0130] Regarding the use of terms such as “implementation,” “an implementation,” “exemplary implementation,” “specific implementation,” or other similar terms herein, these terms are intended to indicate that a specific feature, structure, function, operation, or characteristic described in connection with that implementation exists in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as “in one implementation,” “in an implementation,” “in an exemplary implementation,” etc., may, but not necessarily, refer to the same implementation, but rather means “one or more, but not all, implementations,” unless otherwise expressly stated. Furthermore, the terms “comprising,” “having,” “including,” and variations thereof are used in an open-ended manner and should therefore be construed as meaning “including, but not limited to…,” unless otherwise expressly stated. Moreover, an element preceded by “comprising…” does not exclude the presence of additional identical elements in the subject matter process, method, system, article, or apparatus that includes that element, unless further construed.

[0131] The terms “a,” “an,” and “the” also mean “one or more” unless otherwise explicitly stated. By way of example, a “processor” programmed to perform various functions means a processor programmed to perform each function, or more than one processor collectively programmed to perform each of the various functions. Furthermore, the phrase “at least one of A and B” (where A and B are variables indicating a particular object or attribute) used herein and / or in the appended claims indicates a choice of A or B, or a choice of both A and B, similar to the phrase “and / or.” Where there are more than two variables in such a phrase, the phrase is thereby defined as including only one variable, any one variable, any combination (or sub-combination) of any variables, or all variables.

[0132] Additionally, as used herein, the terms “about” or “approximately” apply to all numerical values, whether explicitly stated or not. These terms generally refer to a range of numerical values ​​that a person skilled in the art would consider equivalent to the listed values ​​(e.g., having the same function or result). In some cases, these terms may include numerical values ​​rounded to the nearest significant figure.

[0133] Furthermore, any list of items presented herein does not imply that any or all of the listed items are mutually exclusive and / or mutually inclusive, unless otherwise expressly stated. Additionally, as used herein, the term "group" should be interpreted as meaning "one or more," and in the case of "group," it should be interpreted as meaning a multiple (or many) of "one or more," "ones or more," and / or "ones or mores" according to the established theory, unless otherwise expressly stated.

[0134] The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise forms disclosed. Many modifications and variations are possible based on the foregoing description. The described embodiments were chosen to best explain the principles of the technology and its practical application, thereby enabling others skilled in the art to best utilize the technology in various embodiments and with various modifications suitable for the particular intended use. The scope of this technology is defined by the appended claims.

Claims

1. A method for operating a memory device, the method comprising the following steps: A memory block is prepared, the memory block comprising an array of memory cells arranged in a plurality of word lines and including a plurality of memory holes, the plurality of memory holes extending through the plurality of word lines and having varying diameters, the word lines being grouped into a first group and a second group based on the diameter of the memory holes; Determine whether the selected word line among the multiple word lines belongs to the first group or the second group; In response to the selected word line being in the first group, a memory operation is performed using the first group of reference voltages; In response to the selected word line being in the second group, the memory operation is performed using the second group of reference voltages; and The first set of reference voltages and the second set of reference voltages are different for multiple data states, and are similar for at least one data state at the highest threshold voltage range.

2. The method of claim 1, wherein the memory operation is a three-bit memory operation per memory cell, and each of the first set of reference voltages and the second set of reference voltages includes seven reference voltages associated with seven programmed data states at different threshold voltage ranges.

3. The method of claim 2, wherein the memory operation is a programming operation, and the reference voltage of the first set of reference voltages and the second set of reference voltages is a verification voltage.

4. The method of claim 3, wherein for the first six programmed data states, the reference voltage of the second set of reference voltages is greater than the reference voltage of the first set of reference voltages, such that programming the memory cells of the word lines of the second group results in an increased margin between the erase data state and the first programmed data state compared to programming the memory cells of the word lines of the first group.

5. The method of claim 4, wherein for each programmed data state of the programmed data states other than the last data state, the reference voltage of the second set of reference voltages is a first offset greater than the reference voltage of the first set of reference voltages.

6. The method of claim 4, wherein the memory cavity has a larger diameter at the word lines of the first group and a smaller diameter at the word lines of the second group.

7. The method of claim 2, wherein the memory operation is a read operation.

8. The method of claim 6, wherein for each of the plurality of data states other than the last data state, the reference voltage is equal to the verification voltage for the data state plus a first offset plus a second offset, and For the last data state, the reference voltage is equal to the verification voltage used for the last data state plus the first offset.

9. A memory device, the memory device comprising: A memory block comprising an array of memory cells arranged in a plurality of word lines and including a plurality of memory holes extending through the plurality of word lines and having varying diameters, the word lines being grouped into a first group and a second group based on the diameter of the memory holes; Circuitry for performing memory operations on selected word lines among the plurality of word lines, the circuitry being configured to: Determine whether the selected word line is in the first group or the second group; In response to the selected word line being in the first group, a memory operation is performed using the first group of reference voltages; In response to the selected word line being in the second group, the memory operation is performed using the second group of reference voltages; and The first set of reference voltages and the second set of reference voltages are different for multiple data states, and are similar for at least one data state at the highest threshold voltage range.

10. The memory device of claim 9, wherein the memory operation is a three-bit memory operation per memory cell, and each of the first set of reference voltages and the second set of reference voltages includes seven reference voltages associated with seven programmed data states at different threshold voltage ranges.

11. The memory device of claim 10, wherein the memory operation is a programming operation, and the reference voltage of the first set of reference voltages and the second set of reference voltages is a verification voltage.

12. The memory device of claim 11, wherein for the first six programmed data states, the reference voltage of the second set of reference voltages is greater than the reference voltage of the first set of reference voltages, such that programming the memory cells of the word lines of the second group results in an increased margin between the erase data state and the first programmed data state compared to programming the memory cells of the word lines of the first group.

13. The memory device of claim 12, wherein for each programmed data state of the programmed data states other than the last data state, the reference voltage of the second set of reference voltages is a first offset greater than the reference voltage of the first set of reference voltages.

14. The memory device of claim 12, wherein the memory holes have a larger diameter at the word lines of the first group and a smaller diameter at the word lines of the second group.

15. The memory device of claim 10, wherein the memory operation is a read operation.

16. The memory device of claim 15, wherein for each of the plurality of data states other than the last data state, the reference voltage is equal to the verification voltage for the data state plus a first offset plus a second offset, and For the last data state, the reference voltage is equal to the verification voltage used for the last data state plus the first offset.

17. An apparatus comprising: A memory block comprising an array of memory cells arranged in a plurality of word lines and including a plurality of memory holes extending through the plurality of word lines and having varying diameters, the plurality of word lines including bottom-layer word lines and other word lines; A sensing component, configured to perform a sensing operation on a selected word line among the plurality of word lines, wherein the sensing component is configured to: Determine whether the selected character line is one of the bottom character lines or another character line among the other character lines; In response to the selected word line being one of the other word lines, a sensing operation is performed using the first set of reference voltages; In response to the selected word line being one of the bottom word lines, the sensing operation is performed using a second set of reference voltages; and The first set of reference voltages and the second set of reference voltages are different for multiple data states, and are similar for at least one data state at the highest threshold voltage range.

18. The apparatus of claim 17, wherein the sensing operation is a verification operation, and the reference voltage of the first set of reference voltages and the second set of reference voltages is a verification voltage.

19. The apparatus of claim 17, wherein the sensing operation is a reading operation.

20. The apparatus of claim 17, wherein the sensing operation is a three-bit sensing operation per memory cell, and each of the first set of reference voltages and the second set of reference voltages comprises seven reference voltages associated with seven programmed data states at different threshold voltage ranges.

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