Method for testing memory devices

Abstract

A test method for a memory device is provided. The memory device includes a memory array and a decoder circuit. The decoder circuit operates in accordance with a first reference voltage. The memory array operates in accordance with a second reference voltage. The test method includes partitioning the memory array into a plurality of memory blocks, adjusting a voltage value of at least one of the first reference voltage and the second reference voltage to sequentially perform access operations on the plurality of memory blocks, and receiving a plurality of failed bit counts (FBCs) of the plurality of memory blocks after the access operations, and counting a number of memory blocks corresponding to a plurality of different voltage values of the first reference voltage and / or the second reference voltage and the plurality of FBCs.

Description

Technical Field

[0001] This invention relates to a testing method for electronic devices, and more particularly to a testing method for memory devices. Background Technology

[0002] Current testing methods for memory devices can obtain the failed bit count (FBC) of the memory array. However, these methods do not analyze the faulty bit condition of the memory array based on the FBC. Therefore, providing a testing method that utilizes the FBC to analyze the faulty bit condition of a memory array is a key research focus for those skilled in the art. Summary of the Invention

[0003] This invention provides a testing method. The testing method can analyze the fault bit status of a memory array using the failed bit count (FBC).

[0004] In one embodiment of the present invention, the testing method is applicable to a memory device. The memory device includes a memory array and a decoder circuit. The decoder circuit operates based on a first reference voltage. The memory array operates based on a second reference voltage. The testing method includes: dividing the memory array into a plurality of memory blocks; adjusting the voltage value of at least one of the first reference voltage and the second reference voltage to sequentially perform access operations on the plurality of memory blocks, and receiving a plurality of File Cross-Blocks (FBCs) of the plurality of memory blocks after the access operations; and counting the plurality of different voltage values ​​corresponding to at least one of the first reference voltage and the second reference voltage, and the plurality of memory blocks corresponding to the plurality of FBCs.

[0005] Based on the above, the test method adjusts the voltage value of at least one of the first reference voltage and the second reference voltage to sequentially perform access operations on the plurality of memory blocks to receive multiple FBCs (Fault-Blocked Cells) after the access operations. The test method also counts the number of memory blocks corresponding to multiple different voltage values ​​of the first reference voltage and / or the second reference voltage, as well as the number of FBCs. In this way, the test method can utilize the FBCs to analyze the fault bit condition of the memory array. Attached Figure Description

[0006] Figure 1 This is a test schematic diagram of a memory device illustrated according to an embodiment of the present invention.

[0007] Figure 2 This is a flowchart illustrating a test method according to an embodiment of the present invention.

[0008] Figure 3This is a schematic diagram of a memory block according to an embodiment of the present invention.

[0009] Figure 4 This is a flowchart illustrating a test method according to an embodiment of the present invention.

[0010] Figure 5 This is a flowchart illustrating a test method according to an embodiment of the present invention.

[0011] Figure 6 This is a statistical chart of the number of memory blocks illustrated according to an embodiment of the present invention.

[0012] Figure 7 This is a flowchart illustrating a test method according to an embodiment of the present invention.

[0013] Figure 8 This is a flowchart illustrating a test method according to an embodiment of the present invention.

[0014] Figure 9 This is a flowchart illustrating a test method according to an embodiment of the present invention.

[0015] Figure 10 This is a flowchart illustrating a test method according to an embodiment of the present invention.

[0016] Figure 11 This is a flowchart illustrating a test method according to an embodiment of the present invention.

[0017] Figure 12 This is a flowchart illustrating a test method according to an embodiment of the present invention.

[0018] [Symbol Explanation]

[0019] 100: Memory device

[0020] 110: Memory Array

[0021] 120: Decoder Circuit

[0022] 121: Column Decoder

[0023] 122: Line Decoder

[0024] 200: Controller

[0025] a, b: Step value

[0026] BK, BK0~BKn: Memory blocks

[0027] BL0~BLx: Bit lines

[0028] I1: First current value

[0029] I2: Second current value

[0030] MC: Memory Cell

[0031] NBK0~NBKm: Number of memory blocks

[0032] P1, P2: Positions

[0033] R1, R2, R3: FBC range

[0034] S100, S200, S300, S400, S500, S600, S700, S800, S900, S1000: Test Methods

[0035] S110~S130, S210~S250, S310~S350, S410~S450, S510~S560, S610~S650, S710~S760, S810~S850, S910~S950, S1010~S1050: Steps

[0036] VDD: First reference voltage

[0037] VDD0, VDDC0: Initial voltage values

[0038] VDDh, VDDCh: Set voltage values

[0039] VDDmax: First maximum test voltage value

[0040] VDDC: Second reference voltage

[0041] VDDCmax: Second maximum test voltage value

[0042] VDDCt: Target voltage value

[0043] VR: Read voltage

[0044] VDDread, VDDwrite, VDDCwrite: Operating voltage values

[0045] Vs0, Vs1, Vs2: Step voltage values

[0046] VW: Write voltage

[0047] WL0~WLy: Word lines Detailed Implementation

[0048] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description, when appearing in different drawings, are considered to be the same or similar components. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples within the scope of the present invention's patent application.

[0049] Please refer to Figure 1 as well as Figure 2 , Figure 1 This is a test schematic diagram of a memory device illustrated according to an embodiment of the present invention. Figure 2 This is a flowchart illustrating a test method according to an embodiment of the present invention. In this embodiment, the memory device 100 includes a memory array 110 and a decoder circuit 120. For example, the memory device 100 is a static random-access memory (SRAM), but the present invention is not limited thereto. In this embodiment, the memory array 110 includes a plurality of memory cells. The decoder circuit 120 includes a column decoder 121 and a row decoder 122. The decoder circuit 120 operates based on a first reference voltage VDD. The first reference voltage VDD can be a reference power supply for the column decoder 121 and the row decoder 122. The memory array 110 operates based on a second reference voltage VDDC. The second reference voltage VDDC can be a reference power supply for the memory array 110.

[0050] In this embodiment, the test method S100 is applicable to the memory device 100. For example, the test method S100 may be executed by a controller 200. For example, the controller 200 may be a memory controller in the memory device 100 or a test circuit located outside the memory device 100.

[0051] In this embodiment, the test method S100 includes steps S110 to S130. In step S110, the memory array 110 is divided into memory blocks BK0 to BKn. For example, taking a memory array 110 with 64Mb as an example, the memory array 110 can be divided into 256 memory blocks BK0 to BKn (that is, n equals "255").

[0052] In step S120, the controller 200 adjusts the voltage value of at least one of the first reference voltage VDD and the second reference voltage VDDC to sequentially perform access operations on memory blocks BK0 to BKn, and receives multiple FBCs of memory blocks BK0 to BKn after the access operations.

[0053] For example, controller 200 fixes the voltage value of the second reference voltage VDDC. Controller 200 increments or decrements the voltage value of the first reference voltage VDD to sequentially perform access operations on memory blocks BK0 to BKn, and receives multiple FBCs of memory blocks BK0 to BKn after the access operations.

[0054] For another example, controller 200 fixes the voltage value of the first reference voltage VDD. Controller 200 increments or decrements the voltage value of the second reference voltage VDDC to sequentially perform access operations on memory blocks BK0 to BKn, and receives multiple FBCs of memory blocks BK0 to BKn after the access operations.

[0055] For another example, controller 200 sets the voltage value of the first reference voltage VDD to a first voltage value. Controller 200 increments or decrements the voltage value of the second reference voltage VDDC to sequentially perform access operations on memory blocks BK0 to BKn, and receives multiple first FBCs (Fragments by Content Frames) for memory blocks BK0 to BKn after the access operations. Next, controller 200 increments or decrements the voltage value of the first reference voltage VDD to a second voltage value. Controller 200 resets the voltage value of the second reference voltage VDDC. Next, controller 200 increments or decrements the voltage value of the second reference voltage VDDC to sequentially perform access operations on memory blocks BK0 to BKn, and receives multiple second FBCs for memory blocks BK0 to BKn after the access operations, and so on.

[0056] In step S130, the controller 200 counts multiple different voltage values ​​corresponding to at least one of the first reference voltage VDD and the second reference voltage VDDC, as well as the number of memory blocks NBK0 to NBKm of the multiple FBCs.

[0057] It is worth mentioning that, in test method S100, the voltage value of at least one of the first reference voltage VDD and / or the second reference voltage VDDC is adjusted to sequentially perform access operations on memory blocks BK0 to BKn to receive multiple FBCs (Error Buffers) of memory blocks BK0 to BKn after the access operations. Test method S100 also counts the number of memory blocks NBK0 to NBKm corresponding to multiple different voltage values ​​of the first reference voltage VDD and / or the second reference voltage VDDC and different FBCs. In this way, test method S100 can use the FBCs to analyze the error bit status of the memory array 110.

[0058] Please refer to Figure 1 , Figure 2 as well as Figure 3 , Figure 3This is a schematic diagram of a memory block according to an embodiment of the present invention. In this embodiment, the memory block BK includes word lines WL0 to WLy, bit lines BL0 to BLx, and a plurality of memory cells MC. During access operations, one of the bit lines BL0 to BLx is selected as the selected bit line. The decoder circuit 120 performs write operations on the memory cells MC connected to the selected bit line and the plurality of selected bit addresses on different word lines, and performs read operations on the memory cells MC connected to the selected bit line and the plurality of selected bit addresses on different word lines.

[0059] For example, bit line BL0 is selected as the selected bit line. Therefore, the decoder circuit 120 performs write operations on all memory cells MC (or memory rows) connected to bit line BL0 and then read operations. The decoder circuit 120 does not perform access operations on memory cells MC connected to bit lines BL2 to BLx. In this way, access operations on memory rows connected to bit line BL0 are not interfered with by access operations on other memory rows.

[0060] Next, bit line BL1 is selected as the selected bit line. Therefore, decoder circuit 120 performs write operations on all memory cells MC connected to bit line BL1 and subsequently performs read operations.

[0061] In this embodiment, during a write operation, the decoder circuit 120 provides a write voltage VW to the memory cell MC connected to the selected bit line. During a read operation, the decoder circuit 120 pumps the write voltage VW to a read voltage VR and provides the read voltage VR to the memory cell MC connected to the selected bit line. After the write operation, the decoder circuit 120 adjusts at least one of the first reference voltage VDD and / or the second reference voltage VDDC to perform read operations on the memory cells MC of multiple selected bit addresses connected to the selected bit line and different word lines.

[0062] Please refer to Figure 1 as well as Figure 4 , Figure 4 This is a flowchart illustrating a test method according to an embodiment of the present invention. In this embodiment, the controller 200 also obtains a first maximum test voltage value VDDmax of the first reference voltage VDD and a second maximum test voltage value VDDCmax of the second reference voltage VDDC. Taking this embodiment as an example, the controller 200 uses test method S200 to obtain the first maximum test voltage value VDDmax and uses test method S300 to obtain the second maximum test voltage value VDDCmax.

[0063] In this embodiment, the test method S200 includes steps S210 to S250. In step S210, the controller 200 resets the voltage value of the first reference voltage VDD. For example, the voltage value of the first reference voltage VDD is equal to the initial voltage value VDD0 plus the product of the step voltage value Vs0 and the step value a (i.e., VDD = VDD0 + Vs0 × a). In step S210, the step value a is reset to "0". Therefore, the voltage value of the first reference voltage VDD is equal to the initial voltage value VDD0. Furthermore, in step S210, the voltage value of the second reference voltage VDDC is also reset to the initial voltage value VDDC0.

[0064] In step S220, the controller 200 provides a first reference voltage VDD to the decoder circuit 120 and a second reference voltage VDDC to the memory array 110 to receive a first current value I1 (or first operating current value) from the memory device 100.

[0065] In step S230, the controller 200 determines whether the first current value I1 is less than the maximum current value. For example, the maximum current value may be the maximum test current value (e.g., 160mA). The maximum test current value is lower than the maximum operating current value of the memory device 100 (e.g., 200mA). In step S230, when the first current value I1 is less than the maximum current value, the controller 200 increments the step value a (e.g., a = a + 1) in step S240 and returns to the operation in step S220. Therefore, the voltage value of the first reference voltage VDD is incremented. The first current value I1 is also incremented. In step S230, when the first current value I1 reaches the maximum current value, the controller 200 uses the voltage value of the first reference voltage VDD as the first maximum test voltage value VDDmax in step S250. In other words, the first maximum test voltage value VDDmax corresponds to the voltage value of the maximum current value.

[0066] In this embodiment, the test method S300 includes steps S310 to S350. In step S310, the voltage value of the second reference voltage VDDC is reset. For example, the voltage value of the second reference voltage VDDC is equal to the initial voltage value VDDC0 plus the product of the step voltage value Vs0 and the step value b (i.e., VDDC = VDDC0 + Vs0 × b). In step S310, the step value b is reset to "0". Therefore, the voltage value of the second reference voltage VDDC is equal to the initial voltage value VDDC0. Furthermore, in step S310, the voltage value of the first reference voltage VDD is also reset to the initial voltage value VDD0.

[0067] In step S320, the controller 200 provides a first reference voltage VDD to the decoder circuit 120 and a second reference voltage VDDC to the memory array 110 to receive the second current value I2 (or second operating current value) of the memory device 100.

[0068] In step S330, the controller 200 determines whether the second current value I2 is less than the maximum current value. In step S330, when the second current value I2 is less than the maximum current value, the controller 200 increments the step value b (e.g., b = b + 1) in step S340 and returns to the operation in step S320. Therefore, the voltage value of the second reference voltage VDDC is incremented. The second current value I2 is also incremented. In step S330, when the second current value I2 reaches the maximum current value, the controller 200 uses the voltage value of the second reference voltage VDDC as the second maximum test voltage value VDDCmax in step S350. In other words, the second maximum test voltage value VDDCmax corresponds to the voltage value of the maximum current value.

[0069] Please refer to Figure 1 , Figure 5 as well as Figure 6 , Figure 5 This is a flowchart illustrating a test method according to an embodiment of the present invention. Figure 6 This is a statistical chart illustrating the number of memory blocks according to an embodiment of the present invention. The chart is presented, for example, in a table format. The chart is for illustrative purposes only, and the invention is not limited to the chart. In this embodiment, Figure 5 Test method S400 can be used to count the number of memory blocks NBK0 to NBKm. Test method S400 includes steps S410 to S450. In step S410, during a read operation, the voltage value of the first reference voltage VDD is reset. For example, the voltage value of the first reference voltage VDD is equal to the initial voltage value VDD0 plus the product of the step voltage value Vs1 and the step value a (i.e., VDD = VDD0 + Vs1 × a). In step S410, the step value a is reset to "1". Therefore, the voltage value of the first reference voltage VDD is equal to the initial voltage value "VDD0 + Vs1". In step S410, during a read operation, the voltage value of the second reference voltage VDDC is set to the second maximum test voltage value VDDCmax. During a write operation, the voltage value of the first reference voltage VDD is set to the set voltage value VDDh. The voltage value of the second reference voltage VDDC is set to the set voltage value VDDCh.

[0070] In step S420, controller 200 counts the number of memory blocks with an FBC range R1 based on the voltage values ​​of the first reference voltage VDD and the second reference voltage VDDC, and records the number of memory blocks in step S430. The FBC range R1 indicates that the FBC equals "0". For example, when the step value a equals "1", controller 200 counts 255 memory blocks with an FBC range R1 in step S420 (i.e., NBK0 = "255"). Therefore, in step S430, controller 200 records the number of memory blocks. For example, in step S430, controller 200 records the number of memory blocks NBK0 at position P1 on the statistics chart.

[0071] In step S440, the controller 200 determines whether the voltage value of the first reference voltage VDD is greater than or equal to the first maximum test voltage value VDDmax. When the voltage value of the first reference voltage VDD is less than the first maximum test voltage value VDDmax, the controller 200 increments the step value a (e.g., a = a + 1) in step S450 and returns to the operation in step S420. For example, when a equals "2", the controller 200 counts 254 memory blocks with FBC range R1 in step S420 (i.e., NBK1 = "254"). Therefore, in step S430, the controller 200 records the number of memory blocks. For example, in step S430, the controller 200 records the number of memory blocks NBK1 at position P2 on the statistics chart.

[0072] In this embodiment, in step S440, when the voltage value of the first reference voltage VDD is greater than or equal to the first maximum test voltage value VDDmax, the controller 200 completes the counting of the number of memory blocks in the FBC range R1.

[0073] The controller 200 can execute test method S400 based on FBC range R2 (e.g., FBC ≤ “5”) and test method S400 based on FBC range R3 (e.g., FBC ≤ “10”), and so on.

[0074] Please refer to Figure 1 , Figure 6 as well as Figure 7 , Figure 7 This is a flowchart illustrating a test method according to an embodiment of the present invention. In this embodiment, Figure 7The test method S500 can be used to determine the operating voltage value VDDread of the first reference voltage VDD when the voltage value of the second reference voltage VDDC is equal to the second maximum test voltage value VDDCmax during a read operation. The controller 200 sequentially obtains multiple memory block numbers by subtracting the voltage value of the first reference voltage VDD from the first maximum test voltage value VDDmax based on the same FBC range. When the number of memory blocks NBK(m-1) is greater than or equal to the current number of operating memory blocks NBKm, the controller 200 modifies the number of operating memory blocks to the number of memory blocks NBK(m-1). Furthermore, the controller 200 uses the voltage value of the first reference voltage VDD corresponding to the number of memory blocks NBK(m-1) as the operating voltage value VDDread.

[0075] On the other hand, when the number of memory blocks NBK(m-1) is less than the number of memory blocks NBKm, the controller 200 continues to decrease the voltage value of the first reference voltage VDD to sequentially obtain the number of memory blocks NBK(m-2). When the number of memory blocks NBK(m-2) is greater than or equal to the number of operating memory blocks NKBm, the controller 200 modifies the number of operating memory blocks to the number of memory blocks NBK(m-2). Furthermore, the voltage value of the first reference voltage VDD corresponding to the number of memory blocks NBK(m-2) is used as the operating voltage value VDDread.

[0076] In this embodiment, the test method S500 further includes steps S510 to S560. In step S510, the controller 200 selects the FBC range and sets the step value a to the maximum value corresponding to the first maximum test voltage value VDDmax. The controller 200 sets the current operating voltage value VDDread to an initial value (e.g., "0"). In addition, the controller 200 resets the previously received number of memory blocks to an initial value (i.e., "0").

[0077] In step S520, controller 200 receives the number of memory blocks corresponding to step value a, and in step S530, determines the received number of memory blocks. For example, in the FBC range R1, when step value a is at its maximum value, the number of memory blocks is equal to "7". That is, when the voltage value of the first reference voltage VDD is equal to the first maximum test voltage value VDDmax, there are a total of 7 memory blocks that conform to the FBC range R1. When the voltage value of the first reference voltage VDD is equal to the first maximum test voltage value VDDmax, controller 200 determines that the received number of memory blocks is greater than the number of operating memory blocks (e.g., the initial value of the number of operating memory blocks). Therefore, in step S540, controller 200 modifies the number of operating memory blocks to the currently received number of memory blocks "7", and uses the voltage value of the first reference voltage corresponding to the number of memory blocks as the operating voltage value VDDread. Next, in step S550, the controller 200 decrements the step value a (e.g., a = a - 1) and in step S560 determines whether the step value a has reached the minimum value (e.g., a = 0). When the step value a has not reached the minimum value (e.g., a > 0), the controller 200 returns to the operation of step S520.

[0078] In step S530, when the number of received memory blocks is less than the number of operating memory blocks, the controller 200 does not modify the operating voltage value VDDread or the number of operating memory blocks, and decrements the step value a in step S550. In step S530, the selected FBC range can be adjusted or shifted. In other words, during the execution of test method S500, the selected FBC range can be changed based on a patch value. In other words, based on the same FBC range and patch value, the controller 200 decrements the voltage value of the first reference voltage VDD from the first maximum test voltage value VDDmax to sequentially obtain multiple memory block numbers. The patch value can be 0 or any non-zero real number.

[0079] In step S560, when the step value a reaches its minimum value, the controller 200 terminates test method S500. Therefore, based on test methods S400 and S500, the controller 200 determines the operating voltage value VDDread of the first reference voltage VDD. It should be noted that after test method S500 ends, the number of memory blocks operated is the highest number of memory blocks corresponding to the selected FBC range and the operating voltage value VDDread corresponding to the aforementioned highest number of memory blocks. In other words, the operating voltage value VDDread of the first reference voltage VDD is the optimal read voltage value for the selected FBC range.

[0080] Please refer to Figure 1 , Figure 6 as well as Figure 8, Figure 8 This is a flowchart illustrating a test method according to an embodiment of the present invention. In this embodiment, Figure 8 Test method S600 can be used to count the number of memory blocks NBK0 to NBKm. Test method S600 includes steps S610 to S660. In step S610, during a write operation, the voltage value of the second reference voltage VDDC is reset. For example, the voltage value of the second reference voltage VDDC is equal to the initial voltage value VDDC0 plus the product of the step voltage value Vs2 and the step value b (i.e., VDDC = VDDC0 + Vs2 × b). In step S610, the step value b is reset to "1". Therefore, the voltage value of the second reference voltage VDDC is equal to the initial voltage value "VDDC0 + Vs2". In step S610, during a write operation, the voltage value of the first reference voltage VDD is set to the first maximum test voltage value VDDmax. During a read operation, the voltage value of the first reference voltage VDD is set to the set voltage value VDDh. The voltage value of the second reference voltage VDDC is set to the set voltage value VDDCh.

[0081] In step S620, controller 200 counts the number of memory blocks with an FBC range R1 based on the voltage values ​​of the first reference voltage VDD and the second reference voltage VDDC, and records the number of memory blocks in step S630. The FBC range R1 indicates that the FBC equals "0". For example, when the step value b equals "1", controller 200 will count 255 memory blocks with an FBC range R1 in step S620 (i.e., NBK0 = "255"). Therefore, in step S630, controller 200 records the number of memory blocks NBK0.

[0082] In step S640, the controller 200 determines whether the voltage value of the second reference voltage VDDC is greater than or equal to the second maximum test voltage value VDDCmax. When the voltage value of the second reference voltage VDDC is less than the second maximum test voltage value VDDCmax, the controller 200 increments the step value b (e.g., b = b + 1) in step S650 and returns to the operation in step S620. For example, when b equals "2", the controller 200 counts 254 memory blocks with the FBC range R1 in step S620 (i.e., NBK1 = "254"). Therefore, in step S630, the controller 200 records the number of memory blocks NBK1.

[0083] In this embodiment, in step S640, when the voltage value of the second reference voltage VDDC is greater than or equal to the second maximum test voltage value VDDCmax, the controller 200 completes the statistics of the number of memory blocks in the FBC range R1.

[0084] The controller 200 can execute test method S600 based on FBC range R2 (e.g., FBC ≤ “5”) and test method S600 based on FBC range R3 (e.g., FBC ≤ “10”), and so on.

[0085] Please refer to Figure 1 , Figure 6 as well as Figure 9 , Figure 9 This is a flowchart illustrating a test method according to an embodiment of the present invention. In this embodiment, Figure 9 The test method S700 can be used to determine the operating voltage value VDDCwrite of the second reference voltage VDDC when the voltage value of the first reference voltage VDD is equal to the first maximum test voltage value VDDmax during a write operation. The controller 200 sequentially obtains multiple memory block numbers by subtracting the voltage value of the second reference voltage VDDC from the second maximum test voltage value VDDCmax based on the same FBC range. When the number of memory blocks NBKm is less than the number of memory blocks NBK(m-1), the controller 200 uses the voltage value of the second reference voltage VDDC corresponding to the number of memory blocks NBK(m-1) as the operating voltage value VDDCwrite.

[0086] On the other hand, when the number of memory blocks NBKm is greater than or equal to the number of memory blocks NBK(m-1), the controller 200 continues to decrease the voltage value of the second reference voltage VDDC to sequentially obtain the number of memory blocks NBK(m-2). When the number of memory blocks NBKm is less than the number of memory blocks NBK(m-2), the controller 200 uses the voltage value of the second reference voltage VDDC corresponding to the number of memory blocks NBK(m-2) as the operating voltage value VDDCwrite.

[0087] In this embodiment, the test method S700 further includes steps S710 to S750. In step S710, the controller 200 selects the FBC range and sets the step value b to the maximum value corresponding to the second maximum test voltage value VDDCmax. The controller 200 sets the current operating voltage value VDDCwrite to an initial value (e.g., "0"). Furthermore, the controller 200 resets the previously received number of memory blocks to an initial value (i.e., "0").

[0088] In step S720, controller 200 receives the number of memory blocks corresponding to the step value b and in step S730, determines the received number of memory blocks. For example, in the FBC range R1, when the step value b is the maximum value, the number of memory blocks is equal to "7". That is, when the voltage value of the second reference voltage VDDC is the second maximum test voltage value VDDCmax, there are a total of 7 memory blocks that conform to the FBC range R1. When the voltage value of the second reference voltage VDDC is the second maximum test voltage value VDDCmax, controller 200 determines that the received number of memory blocks is greater than the initial value (i.e., the initial value of the number of operating memory blocks). Therefore, in step S740, controller 200 modifies the number of operating memory blocks to the currently received number of memory blocks "7" and uses the voltage value of the second reference voltage corresponding to the number of memory blocks as the operating voltage value VDDCwrite. Next, in step S750, the controller 200 decrements the step value b (e.g., b = b - 1) and in step S760 determines whether the step value b has reached the minimum value (e.g., b = 0). If the step value b has not reached the minimum value (e.g., b > 0), the controller 200 returns to the operation of step S720.

[0089] In step S730, when the number of received memory blocks is less than the number of operating memory blocks, the controller 200 does not modify the operating voltage value VDDCwrite or the number of operating memory blocks, and decrements the step value b in step S750. In step S730, the selected FBC range can be adjusted or shifted. In other words, the selected FBC range can be changed during the execution of test method S700.

[0090] In step S760, when the step value b reaches its minimum value, the controller 200 terminates test method S700. Therefore, based on test methods S600 and S700, the controller 200 determines the operating voltage value VDDCwrite of the second reference voltage VDDC. It should be noted that after test method S700 ends, the number of memory blocks operated is the highest number of memory blocks corresponding to the selected FBC range and the corresponding operating voltage value VDDCwrite. The operating voltage value VDDCwrite of the second reference voltage VDDC is the optimal write voltage value for the selected FBC range.

[0091] Please refer to Figure 1 , Figure 6 as well as Figure 10 , Figure 10This is a flowchart illustrating a test method according to an embodiment of the present invention. In this embodiment, the controller 200 uses test method S800 to determine the target voltage value VDDCt of the second reference voltage VDDC. Test method S800 includes steps S810 to S850. In step S810, the voltage value of the second reference voltage VDDC is reset. For example, similar to Figure 4 In step S310, the voltage value of the second reference voltage VDDC is equal to the initial voltage value VDDC0 plus the product of the step voltage value Vs0 and the step value b. In step S810, the step value b is reset to "0". Therefore, the voltage value of the second reference voltage VDDC is equal to the initial voltage value VDDC0. Furthermore, in step S810, the voltage value of the first reference voltage VDD is also reset to the initial voltage value VDD0.

[0092] In step S820, the controller 200 provides a first reference voltage VDD to the decoder circuit 120 and a second reference voltage VDDC to the memory array 110 to receive the second current value I2 of the memory device 100.

[0093] In step S830, the controller 200 determines whether the second current value I2 is less than a target current value. In step S830, if the second current value I2 is less than the target current value, the controller 200 increments the step value b (e.g., b = b + 1) in step S840 and returns to the operation in step S820. Therefore, the voltage value of the second reference voltage VDDC is incremented. The second current value I2 is also incremented. In step S830, when the second current value I2 reaches the target current value, the controller 200 uses the voltage value of the second reference voltage VDDC as the target voltage value VDDCt in step S850.

[0094] Please refer to Figure 1 , Figure 6 as well as Figure 11 , Figure 11 This is a flowchart illustrating a test method according to an embodiment of the present invention. Figure 11 Test method S900 can be used to count the number of memory blocks NBK0 to NBKm. Test method S900 includes steps S910 to S950. In step S910, during a read operation, the voltage value of the first reference voltage VDD is reset. For example, similar to Figure 5In step S410, the voltage value of the first reference voltage VDD is equal to the initial voltage value VDD0 (i.e., VDDmin) plus the product of the step voltage value Vs1 and the step value a. In step S910, the step value a is reset to "1". Therefore, the voltage value of the first reference voltage VDD is equal to the initial voltage value "VDD0 + Vs1". In step S910, unlike step S410, in the read operation, the voltage value of the second reference voltage VDDC is set to the target voltage value VDDCt. Furthermore, in the write operation, the voltage value of the first reference voltage VDD is set to the set voltage value VDDh. The voltage value of the second reference voltage VDDC is set to the set voltage value VDDCh.

[0095] In step S920, the controller 200 counts the number of memory blocks with FBC range R1 and records the number of memory blocks in step S930.

[0096] In step S940, the controller 200 determines whether the voltage value of the first reference voltage VDD is greater than or equal to the first maximum test voltage value VDDmax. When the voltage value of the first reference voltage VDD is less than the first maximum test voltage value VDDmax, the controller 200 increments the step value a (e.g., a = a + 1) in step S950 and returns to the operation in step S920. In this embodiment, in step S940, when the voltage value of the first reference voltage VDD is greater than or equal to the first maximum test voltage value VDDmax, the controller 200 completes the counting of the number of memory blocks in the FBC range R1.

[0097] The operational examples for steps S920 to S940 can be found in the examples in steps S420 to S440, so they will not be repeated here.

[0098] Furthermore, the controller 200 may execute test method S900 based on FBC range R2 (e.g., FBC ≤ “5”) and test method S900 based on FBC range R3 (e.g., FBC ≤ “10”), and so on.

[0099] After completing test method S900, controller 200 can be based on Figure 7 Test method S500 determines the operating voltage value VDDread of the first reference voltage VDD. It should be noted that, based on test method S900 and test method S500, when the voltage value of the second reference voltage VDDC is equal to the target voltage value VDDCt, the controller 200 can determine that the operating voltage value VDDread of the first reference voltage VDD is the optimal reading voltage value during the reading operation.

[0100] Please refer to Figure 1 , Figure 6 as well as Figure 12, Figure 12 This is a flowchart illustrating a test method according to an embodiment of the present invention. In this embodiment, Figure 12 Test method S1000 can be used to count the number of memory blocks NBK0 to NBKm. Test method S1000 includes steps S1010 to S1050. In step S1010, during a write operation, the voltage value of the first reference voltage VDD is reset. For example, the voltage value of the first reference voltage VDD is equal to the first maximum test voltage value VDDmax minus the product of the step voltage value Vs1 and the step value a (i.e., VDD = VDDmax - Vs1 × a). In step S1010, the step value a is reset to "1". Therefore, the voltage value of the first reference voltage VDD is equal to the initial voltage value "VDDmax - Vs1". In step S1010, during a write operation, the voltage value of the second reference voltage VDDC is set to the target voltage value VDDCt. During a read operation, the voltage value of the first reference voltage VDD is set to the set voltage value VDDh. The voltage value of the second reference voltage VDDC is set to the set voltage value VDDCh.

[0101] In step S1020, the controller 200 counts the number of memory blocks with FBC range R1 and records the number of memory blocks in step S1030.

[0102] In step S1040, the controller 200 determines whether the voltage value of the first reference voltage VDD is less than or equal to the first minimum test voltage value. When the voltage value of the first reference voltage VDD is greater than the first minimum test voltage value, the controller 200 increments the step value a (e.g., a = a + 1) in step S1050 and returns to the operation in step S1020.

[0103] In this embodiment, in step S1040, when the voltage value of the first reference voltage VDD is less than or equal to the minimum test voltage value, the controller 200 completes the counting of the number of memory blocks in the FBC range R1.

[0104] The controller 200 can execute test method S1000 based on FBC range R2 (e.g., FBC ≤ “5”), and execute test method S1000 based on FBC range R3 (e.g., FBC ≤ “10”), and so on.

[0105] After completing test method S1000, controller 200 can be based on Figure 7Test method S500 determines the operating voltage value VDDwrite of the first reference voltage VDD. It should be noted that, based on test methods S1000 and S500, when the voltage value of the second reference voltage VDDC equals the target voltage value VDDCt, the controller 200 can determine that the operating voltage value VDDwrite of the first reference voltage VDD is the optimal write voltage value during the write operation. Therefore, based on test methods S900, S1000, and S500, the controller 200 can obtain the optimal write operation voltage value and the optimal read operation voltage value of the first reference voltage VDD corresponding to the target voltage value VDDCt of the second reference voltage VDDC.

[0106] In this embodiment, when the operating voltage value VDDread (i.e., the read operating voltage value) is determined first, the controller 200 stores the operating voltage value VDDread. During a write operation, the controller 200 adjusts the first reference voltage VDD to obtain the operating voltage value VDDwrite (i.e., the write operating voltage value). In some embodiments, when the operating voltage value VDDwrite (i.e., the write operating voltage value) is determined first, the controller 200 stores the operating voltage value VDDwrite. During a read operation, the controller 200 adjusts the first reference voltage VDD to obtain the operating voltage value VDDread (i.e., the read operating voltage value).

[0107] Furthermore, the operating voltage value VDDread (i.e., the read operation voltage value) is less than the target voltage value VDDCt. The operating voltage value VDDwrite (i.e., the write operation voltage value) is less than the target voltage value VDDCt. Once the operating voltage values ​​VDDread and VDDwrite are determined, the operating parameters of the memory block can be determined based on these values. In other words, when the voltage value of the second reference voltage VDDC is equal to the target voltage value VDDCt, memory blocks NBK0 to NBKm can perform access operations based on the operating voltage values ​​VDDread and VDDwrite.

[0108] In summary, the test method adjusts at least one of the first reference voltage and the second reference voltage to sequentially perform access operations on the plurality of memory blocks to receive multiple File Cross-Blocks (FBCs) after the access operations. The test method also counts the number of memory blocks corresponding to multiple different voltage values ​​of the first reference voltage and / or the second reference voltage, as well as the number of FBCs. In this way, the test method can utilize FBCs to analyze the error bit status of the memory array. Furthermore, the test method can also obtain the write operation voltage values ​​and read operation voltage values ​​of the first reference voltage and / or the second reference voltage.

[0109] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A testing method for a memory device, wherein the memory device includes a memory array and a decoder circuit, wherein the decoder circuit operates according to a first reference voltage, wherein the memory array operates according to a second reference voltage, wherein the testing method includes: The memory array is divided into multiple memory blocks; The voltage values ​​of at least one of the first reference voltage and the second reference voltage are adjusted to sequentially access the memory block, and multiple error bit counts of the memory block are received after the access operation. as well as The system counts the number of memory blocks corresponding to at least one of the first reference voltage and the second reference voltage, as well as the number of error bits.

2. The test method as described in claim 1, further comprising: Obtain the first maximum test voltage value of the first reference voltage and the second maximum test voltage value of the second reference voltage.

3. The test method as described in claim 2, wherein the step of obtaining the first maximum test voltage value of the first reference voltage and the second maximum test voltage value of the second reference voltage includes: Set the voltage value of the second reference voltage; The voltage value of the first reference voltage is increased and the first current value of the memory device is received; as well as When the first current value reaches the maximum current value, the voltage value of the first reference voltage is taken as the first maximum test voltage value.

4. The test method as described in claim 2, wherein the step of obtaining the first maximum test voltage value of the first reference voltage and the second maximum test voltage value of the second reference voltage includes: Set the voltage value of the first reference voltage; The voltage value of the second reference voltage is increased and the second current value of the memory device is received; as well as When the second current value reaches the maximum current value, the voltage value of the second reference voltage is taken as the second maximum test voltage value.

5. The test method as described in claim 4, further comprising: Based on the same error bit count and repair count, the voltage value of the first reference voltage is subtracted from the first maximum test voltage value to sequentially obtain the first memory block number and the second memory block number among the memory block numbers; as well as When the number of the second memory blocks is greater than or equal to the number of the first memory blocks, the number of operating memory blocks is modified to the number of the second memory blocks, and the voltage value of the first reference voltage corresponding to the number of the second memory blocks is used as the first operating voltage value. The number of repairs can be any real number.

6. The test method of claim 5, wherein the first operating voltage value is a read operation voltage value generated by the read operation in the access operation, and wherein the test method further comprises: When the second current value reaches the target current value, the voltage value of the second reference voltage is taken as the target voltage value; as well as When the voltage value of the second reference voltage is equal to the target voltage value, the read operation voltage value is determined to be the optimal read voltage value.

7. The test method of claim 6, wherein the first operating voltage value is the write operation voltage value generated by the write operation in the access operation, and wherein the test method further comprises: When the second current value reaches the target current value, the voltage value of the second reference voltage is taken as the target voltage value; as well as When the voltage value of the second reference voltage is equal to the target voltage value, the write operation voltage value is determined to be the optimal write voltage value.

8. The test method as described in claim 7, wherein: The read operation voltage value is less than the target voltage value, and The write operation voltage value is greater than the target voltage value.

9. The test method as described in claim 7, further comprising: The operating parameters of the memory block are determined based on the write operation voltage value and the read operation voltage value.

10. The test method as described in claim 7, further comprising: When the read operation voltage value is determined first, the read operation voltage value is maintained, and the first reference voltage is adjusted during the write operation to obtain the write operation voltage value; as well as Once the write operation voltage value is determined, the write operation voltage value is maintained, and the first reference voltage is adjusted during the read operation to obtain the read operation voltage value.

11. The test method as described in claim 5, further comprising: When the number of the second memory blocks is less than the number of the operating memory blocks, the voltage value of the first reference voltage continues to decrease to sequentially obtain the number of the third memory blocks among the number of memory blocks; as well as When the number of the third memory blocks is greater than or equal to the number of the operating memory blocks, the number of operating memory blocks is modified to the number of the third memory blocks, and the voltage value of the first reference voltage corresponding to the number of the third memory blocks is used as the first operating voltage value.

12. The test method as described in claim 2, further comprising: Based on the same error bit count, the voltage value of the second reference voltage is subtracted from the second maximum test voltage value to sequentially obtain the first memory block number and the second memory block number among the memory block numbers; as well as When the number of the second memory blocks is greater than or equal to the number of the first memory blocks, the number of operating memory blocks is modified to the number of the second memory blocks, and the voltage value of the second reference voltage corresponding to the number of the second memory blocks is used as the second operating voltage value.

13. The test method as described in claim 12, further comprising: When the number of the second memory blocks is less than the number of the operating memory blocks, the voltage value of the second reference voltage continues to decrease to sequentially obtain the number of the third memory blocks among the number of memory blocks; as well as When the number of the third memory blocks is greater than or equal to the number of the operating memory blocks, the number of the operating memory blocks is modified to the number of the third memory blocks, and the voltage value of the second reference voltage corresponding to the number of the third memory blocks is used as the second operating voltage value.

14. The testing method of claim 1, wherein the access operation includes: Write operations are performed on multiple memory cells connected to multiple selected bit addresses on the selected bit line and different word lines, and read operations are performed on the memory cells connected to the multiple selected bit addresses on the selected bit line and different word lines.

15. The testing method of claim 1, wherein the access operation includes: Write operations are performed on multiple memory cells connected to multiple selected bit addresses on the selected bit line and different word lines, and at least one of the first reference voltage and the second reference voltage is adjusted to perform read operations on the memory cells connected to the multiple selected bit addresses on the selected bit line and different word lines.

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