Sram test structure and monitoring method

By setting adjacent test structures in the SRAM memory cell, electrically leading out the drain and gate of the pull-up transistor, and obtaining the standard deviation of the electrical parameter difference, the problem of pull-up transistor mismatch in the SRAM memory cell is solved, improving the accuracy of monitoring and the yield.

CN122201399APending Publication Date: 2026-06-12QINGDAO AUCMA YUNLIAN INFORMATION TECHNOLOGY CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
QINGDAO AUCMA YUNLIAN INFORMATION TECHNOLOGY CO LTD
Filing Date
2024-12-11
Publication Date
2026-06-12

AI Technical Summary

⚠Technical Problem

Existing technologies make it difficult to accurately monitor and test the mismatch of pull-up transistors in SRAM memory cells, resulting in reduced yield.

⚗Method used

An SRAM test structure is provided, including at least M adjacent SRAM memory cells. The drain and gate of pull-up transistors are electrically led out through an interconnect structure. The standard deviation of the electrical parameter difference between adjacent memory cells is obtained to monitor the mismatch of the pull-up transistors.

🎯Benefits of technology

It reduces the impact of factors such as random doping fluctuations, improves the accuracy of mismatch monitoring, and provides a solid foundation for process adjustment.

✦ Generated by Eureka AI based on patent content.

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Abstract

The application provides an SRAM test structure and a monitoring method. The test structure comprises at least M adjacent SRAM memory units, each of which comprises a first pull-up transistor and a second pull-up transistor; an interconnection structure arranged on the SRAM memory unit, which electrically leads out the drain and gate of at least part of the first pull-up transistor and the second pull-up transistor; and a test unit connected with the interconnection structure. The test unit is configured to: take two adjacent SRAM memory units as a pair of memory units, obtain the electrical parameters of the first pull-up transistor of one SRAM memory unit and the second pull-up transistor of the other SRAM memory unit in each pair of memory units, and obtain the standard deviation of the difference between the two electrical parameters of N pairs of memory units to monitor the mismatch between the pull-up transistors in the SRAM memory units. The application can accurately monitor the mismatch of the SRAM memory units in the manufacturing process.
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