Test circuit and semiconductor device comprising the same

Abstract

The present disclosure relates to a test circuit and a semiconductor device including the same. A test circuit includes a data compression circuit and an output control circuit. The data compression circuit compresses read data transmitted through a plurality of first signal lines to generate a plurality of test result signals, and outputs the plurality of test result signals through a plurality of second signal lines. The output control circuit selects one of the plurality of test result signals and the read data according to die identification information and a test mode signal, and sequentially outputs the selected signal through a pre-assigned pad among a plurality of pads.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0183877, filed on December 11, 2024, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention generally relate to a semiconductor circuit, and more specifically, to a test circuit and a semiconductor device including the test circuit. Background Technology

[0004] A stacked semiconductor device includes multiple semiconductor dies in a package. The multiple semiconductor dies are electrically connected by bonding leads. Accordingly, when multiple semiconductor dies are connected by bonding leads, the number of pads is limited due to physical constraints.

[0005] Semiconductor devices are needed to perform test operations, and for this purpose, the semiconductor devices include test-related circuitry. Therefore, it is necessary to develop a technique that can efficiently output test results for wire-bonded stacked semiconductor devices using a limited number of pads. Summary of the Invention

[0006] In one embodiment, the test circuit may include a data compression circuit and an output control circuit. The data compression circuit may be configured to compress read data transmitted via a first signal line to generate multiple test result signals, and may be configured to output the multiple test result signals via a second signal line. The output control circuit may be configured to select one of the multiple test result signals and read data based on die identification information and a test mode signal, and may be configured to sequentially output the selected signal via pre-assigned pads among multiple pads.

[0007] In one embodiment, the semiconductor device may include multiple unit memory areas, multiple normal global lines, data compression circuitry, and output control circuitry. The multiple normal global lines may be coupled to the multiple unit memory areas. The data compression circuitry may be configured to compress read data transmitted through the multiple normal global lines to generate multiple test result signals, and may be configured to output the multiple test result signals through the multiple test global lines. The output control circuitry may be configured to select one of the multiple test result signals and read data based on die identification information and a test mode signal, and may be configured to sequentially output the selected signal through pre-assigned pads in a plurality of pads.

[0008] In one embodiment, a semiconductor device may include a plurality of semiconductor dies, each semiconductor die having a plurality of pads coupled to each other by bonding leads, and may be configured such that when a test read command is input, the plurality of semiconductor dies simultaneously output test results through some of the plurality of pads in different orders. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating the configuration of a stacked semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2 This is a diagram illustrating the configuration of a semiconductor die according to an embodiment of the present disclosure.

[0011] Figure 3 It is shown Figure 2 A diagram showing the configuration of the memory cores.

[0012] Figure 4 This is a diagram illustrating the configuration of a test circuit according to an embodiment of the present disclosure.

[0013] Figure 5 It is shown Figure 4 A diagram showing a partial configuration of the test circuit.

[0014] Figure 6 It is shown Figure 5 A diagram showing the configuration of the control unit.

[0015] Figure 7 This is a diagram illustrating a test method according to an embodiment of the present disclosure.

[0016] Figure 8 This is a diagram illustrating a method for outputting test results according to an embodiment of the present disclosure. Detailed Implementation

[0017] Various embodiments not only enable efficient testing of semiconductor devices with wire-bonded structures without adding pads, but also reduce test time by initiating test result output using only a single read command for parallel testing.

[0018] In the following, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0019] Figure 1 This is a diagram illustrating the configuration of a stacked semiconductor device 10 according to an embodiment of the present disclosure.

[0020] See Figure 1 The stacked semiconductor device 10 may include a package 100 and a plurality of external terminals 110. The package 100 may include a plurality of semiconductor dies DIE0 to DIE3 mounted on a printed circuit board (PCB) 120.

[0021] Multiple external terminals 110 can be implemented in the form of multiple packaged balls.

[0022] Multiple semiconductor dies DIE0 to DIE3 can be electrically connected to each other via bonding leads 150 and can be electrically connected to multiple external terminals 110 via a printed circuit board 120. Although Figure 1 Not shown, but each of the multiple semiconductor dies DIE0 to DIE3 includes multiple pads that can be electrically connected to each other via bonding leads 150.

[0023] Multiple semiconductor dies DIE0 to DIE3 may each include volatile memory or non-volatile memory.

[0024] When a test read command is input to the stacked semiconductor device 10, multiple semiconductor dies DIE0 to DIE3 can simultaneously output test results by passing through some of the multiple pads in different orders.

[0025] Figure 2 This is a diagram illustrating the configuration of a semiconductor die 200 according to an embodiment of the present disclosure. Figure 2 The semiconductor die 200 can be Figure 1 Any one of the multiple semiconductor dies DIE0 to DIE3.

[0026] See Figure 2 The semiconductor die 200 may include: a memory core 201, an address decoder 202, a data input / output circuit 203, a memory control circuit 204, and an input / output pad circuit 205.

[0027] The memory core 201 may include multiple memory cells, and these memory cells may include at least one of volatile memory and non-volatile memory. The volatile memory may include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM), while the non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically erasable and programmable read-only memory (EEPROM), electrically programmable ROM (EPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). The memory core 201 may be divided into multiple unit memory areas, such as multiple memory banks BK0 to BKn-1.

[0028] The memory core 201 can compress read data from each of the multiple memory banks BK0 to BKn-1 in a test operation (e.g., a parallel test operation) to generate multiple test result signals, and can output multiple test result signals through multiple global lines GIO.

[0029] Address decoder 202 can be coupled to memory control circuit 204 and memory core 201. Address decoder 202 can decode address signals provided by memory control circuit 204 and can access memory core 201 in response to the decoding result.

[0030] The data input / output circuit 203 can be coupled to the memory core 201 via the global line GIO. The data input / output circuit 203 can exchange data with external systems or the memory core 201.

[0031] The data input / output circuit 203 can select one of the multiple test result signals and read data transmitted through multiple global lines GIO based on the die identification information and test mode signal, and can output it sequentially through one of the pre-assigned pads of multiple pads included in the input / output pad circuit 205.

[0032] The memory control circuit 204 can be coupled to the memory core 201, the address decoder 202, and the data input / output circuit 203. The memory control circuit 204 can provide the address decoded by the address decoder 202 to the data input / output circuit 203. The memory control circuit 204 can control the testing operations of the semiconductor die 200, as well as data input and output related operations. Data input and output related operations can include normal read operations and normal write operations.

[0033] The input / output pad circuit 205 may include multiple pads 206 for receiving command, address and clock signals, inputting and outputting data, and outputting test result signals.

[0034] Figure 3 It is shown Figure 2 A diagram showing the configuration of the memory core 201.

[0035] See Figure 3 The memory core 201 may include multiple memory banks BK0 to BKn-1 and a data compression circuit 210.

[0036] Multiple memory banks BK0 to BKn-1 can be coupled to the first signal line, i.e., multiple normal global lines NGIO. <n:0>.

[0037] The data compression circuit 210 can compress data passing through multiple normal global lines NGIO. <n:0>The transmitted read data generates multiple test result signals, and these signals can be transmitted via a second signal line (i.e., multiple test global lines TGIO). <n:0>It outputs multiple test result signals.

[0038] Data compression circuit 210 can compress read data from each of the multiple memory banks BK0 to BKn-1 to generate multiple test result signals in parallel test operations, and can transmit data through multiple test global lines TGIO. <n:0>Each of the multiple test result signals is output by each signal bit. More specifically, the data compression circuit 210 can compress the read data output from the first memory bank BK0 to generate the test result signal, and can output the generated test result signal to the test global line TGIO. <0> The data compression circuit 210 can compress the read data output from the second memory bank BK1 to generate a test result signal, and can output the generated test result signal to the test global line TGIO. <1> In the manner described above, the data compression circuit 210 can compress the read data output from the sixteenth memory bank BK15 to generate a test result signal, and can output the generated test result signal to the test global line TGIO. <15> .

[0039] Multiple normal global lines NGIO <n:0>and multiple test global lines TGIO <n:0>It can be included in Figure 2 In multiple global lines of GIO.

[0040] Figure 4 This is a diagram illustrating the configuration of a test circuit 300 according to an embodiment of the present disclosure.

[0041] See Figure 4 The test circuit 300 may include output control circuits 300A-1 to 300N-1 in each of a plurality of semiconductor dies 300A to 300N. The test circuit 300 may also include a data compression circuit 210. Figure 4 (not shown in the image), but refer to Figure 3 It has been described.

[0042] The output control circuits 300A-1 to 300N-1 can be coupled to the input / output pad circuits 300A-2 to 300N-2 respectively via the third signal line GIO-DQ<m:0><n:0>.

[0043] The output control circuit 300A-1 of the semiconductor die 300A can be controlled via the third signal line GIO-DQ. <m:0><0> Coupled with the input / output pad circuit 300A-2, the output control circuit 300B-1 of the semiconductor die 300B can be connected via the third signal line GIO-DQ. <m:0><1> The input / output pad circuit 300B-2 is coupled to the output control circuit 300N-1 of the semiconductor die 300N, while the output control circuit 300N-1 of the semiconductor die 300N can be connected via the third signal line GIO-DQ. <m:0> <n>Coupled to the input / output pad circuit 300N-2.

[0044] The multiple pads included in each of the input / output pad circuits 300A-2 to 300N-2 can be coupled to each other in the same order by multiple bonding leads 400A to 400N-1.

[0045] The multiple pads included in the input / output pad circuit 300A-2 of semiconductor die 300A can be coupled to each other via multiple bonding leads 400A in the same order as the multiple pads included in the input / output pad circuit 300B-2 of semiconductor die 300B. More specifically, the first pad of the multiple pads included in the input / output pad circuit 300A-2 can be coupled to the first pad of the multiple pads included in the input / output pad circuit 300B-2 of semiconductor die 300B via one of the multiple bonding leads 400A, and the second pad of the multiple pads included in the input / output pad circuit 300A-2 can be coupled to the second pad of the multiple pads included in the input / output pad circuit 300B-2 of semiconductor die 300B via another of the multiple bonding leads 400A. In the same manner, the nth pad among the multiple pads included in the input / output pad circuit 300A-2 can be coupled to the nth pad among the multiple pads included in the input / output pad circuit 300B-2 of the semiconductor die 300B via another of the multiple bonding leads 400A.

[0046] The multiple pads included in the input / output pad circuit 300B-2 of the semiconductor die 300B can be coupled to each other via multiple bonding leads 400B in the same order as the multiple pads included in the input / output pad circuit of the higher-level semiconductor die, and the multiple pads included in the output / input pad circuit of the second higher-level semiconductor die can be coupled to each other via multiple bonding leads 400N-1 in the same order as the multiple pads 300N-2 included in the input / output pad circuit 300N-2 of the topmost semiconductor die 300N.

[0047] The output control circuits 300A-1 to 300N-1 can identify the die ID based on the die identification information. <n:0>The test mode signal TPARA, through multiple pre-assigned different pads, sequentially outputs one of the following: through multiple normal global lines NGIO. <n:0> <n:0>Transmitted read data and passed multiple global line TGIO tests <n:0> <n:0>Multiple test result signals were transmitted.

[0048] The output control circuit 300A-1 of the bottom semiconductor die 300A can be based on the die identification information DID. <n:0>And the test mode signal TPARA, select one of the following: via multiple normal global lines NGIO <n:0><0> Transmitted read data and passed multiple global line TGIO tests <n:0><0> Multiple test result signals are transmitted, and the selected signal can be coupled to the third signal line GIO-DQ of the first pad of the input / output pad circuit 300A-2. <m:0><0> One of them is used to output sequentially.

[0049] The output control circuit 300B-1 of the semiconductor die 300B can be based on the die identification information DID. <n:0>And the test mode signal TPARA, select one of the following: via multiple normal global lines NGIO <n:0><1> Transmitted read data and passed multiple global line TGIO tests <n:0><1> Multiple test result signals are transmitted, and the selected signal can be coupled to another third signal line GIO-DQ on the second pad of the input / output pad circuit 300B-2. <m:0><1> Output in sequence.

[0050] The output control circuit 300N-1 of the top semiconductor die 300N can be based on the die identification information DID. <n:0>And the test mode signal TPARA, select one of the following: via multiple normal global lines NGIO <n:0> <n>Transmitted read data and passed multiple global line TGIO tests <n:0> <n>Multiple test result signals are transmitted, and the selected signal can be coupled to another third signal line GIO-DQ, which is coupled to the nth pad of the input / output pad circuit 300N-2. <m:0> <n>Output in sequence.

[0051] The signal output to the nth pad of the input / output pad circuit 300N-2 of the topmost semiconductor die 300N can be output to a device outside the semiconductor device via multiple bonding leads 400A to 400N-1 and through the nth pad of the input / output pad circuit 300A-2 of the bottommost semiconductor die 300A. Similarly, the signal output to the second pad of the input / output pad circuit 300B-2 of the semiconductor die 300B can be output to a device outside the semiconductor device via multiple bonding leads 400A and through the second pad of the input / output pad circuit 300A-2 of the bottommost semiconductor die 300A.

[0052] Figure 5 It is shown Figure 4 A diagram showing a partial configuration of the test circuit. Figure 5 The following example is shown: A semiconductor device according to an embodiment of this disclosure is configured with four semiconductor dies and correspondingly configured with sixteen normal global lines (NGIO). <n:0>Sixteen test global lines TGIO <n:0>and four third signal lines GIO-DQ <m:0>.

[0053] See Figure 5 The semiconductor die 300N may include an output control circuit 300N-1 and an input / output pad circuit 300N-2. The input / output pad circuit 300N-2 may include multiple pads PD0 to PD15. The output control circuit 300N-1 may include multiple control units 301 to 316.

[0054] Multiple control units 301-316 can, based on die identification information DID<1:0> and test mode signal TPARA, multiplex and output through multiple pads PD0 to PD15, specifically pads PDO to PD3, via multiple normal global lines NGIO<3:0>. <3> Transmitted read data and passed through multiple test global lines TGIO<15:0> <3> One of the multiple test result signals transmitted. The rest are normal global lines NGIO<15:4> <3> Coupled with the remaining pads PD4 to PD15.

[0055] The first control unit 301 can select the normal global line NGIO<3:0> based on the die identification information DID<1:0> and the test mode signal TPARA. <3> Transmitted read data and pass the test global line TGIO <0> <3> One of the transmitted test result signals. The selected signal can then be output through one of multiple pads PD0 to PD15 (e.g., PD3), which is coupled to a third signal line GIO-DQ<3:0>. <3> One of them (e.g., GIO-DQ) <3> <3> ).

[0056] although Figure 5 Although not directly shown, the second control unit 302 can select the normal global line NGIO<3:0> based on the die identification information DID<1:0> and the test mode signal TPARA. <3> Transmitted read data and pass the test global line TGIO <1> <3> One of the transmitted test result signals, and can be transmitted via the third signal line GIO-DQ. <3> <3> Coupled pad PD3 output.

[0057] In the same manner, the sixteenth control unit 316 can select the normal global line NGIO<3:0> based on the die identification information DID<1:0> and the test mode signal TPARA. <3> Transmitted read data and pass the test global line TGIO <15> <3> One of the transmitted test result signals, and can be transmitted via the third signal line GIO-DQ. <3> <3> The coupled pad PD3 outputs it.

[0058] Figure 6 It is shown Figure 5 A diagram showing the configuration of the control unit 301.

[0059] See Figure 6 The control unit 301 may include a decoding circuit 320 and a multiplexing circuit 340.

[0060] The decoding circuit 320 can generate multiple selection signals TSEL<3:0> based on the die identification information DID<1:0> and the test mode signal TPARA.

[0061] The test mode signal TPARA can be activated when the semiconductor device enters test mode (e.g., parallel test mode). The test mode signal TPARA can be deactivated in the normal mode of the semiconductor device. Signal activation / deactivation can be distinguished by logic levels; in the following text, it is assumed that the signal is activated with a high level and deactivated with a low level.

[0062] Die ID (Digital ID) <n:0>Die Identification Information (DID) can be used to identify each of multiple semiconductor dies, and can have different values ​​for each die. <n:0>The number of bits in the data can vary depending on the number of semiconductor dies. Die Identification Information (DID) <n:0>It can be adjusted to have a different value for each stack location within the semiconductor device, or it can be adjusted to have a different value for each stack location outside the semiconductor device. Die Identification Information (DID) for each semiconductor die. <n:0>The semiconductor dies can have the same initial value (e.g., "00") before stacking, and can be incremented by "1" for each stacking position, so that the semiconductor dies have different die identification information (DID). <n:0>For example, assuming four semiconductor dies are stacked, the semiconductor dies can display die identification information (DID). <n:0>The positions from lowest to highest are stored as "00", "01", "10", and "11" respectively.

[0063] The decoding circuit 320 may include multiple logic gates 321 to 332. The first logic gate 321 can invert the die identification information DID. <0> And output the result. The second logic gate 322 can invert the die identification information DID. <1> The third logic gate 323 can output the result of an AND operation performed on the outputs of the first logic gate 321 and the second logic gate 322. The fourth logic gate 324 can output the result of an AND operation performed on the output of the third logic gate 323 and the test mode signal TPARA as the first selection signal TSEL0. The fifth logic gate 325 can invert the die identification information DID. <1> It also outputs the result. The sixth logic gate 326 can output the output of the fifth logic gate 325 and the die identification information (DID). <0> The result of the AND operation. The seventh logic gate 327 can output the result of the AND operation performed on the output of the sixth logic gate 326 and the test mode signal TPARA as the second selection signal TSEL1. The eighth logic gate 328 can invert the die identification information DID. <0> It also outputs the result. The ninth logic gate 329 can output the output of the eighth logic gate 328 and the die identification information (DID). <1> The result of the AND operation. The tenth logic gate 330 can output the result of the AND operation performed on the output of the ninth logic gate 329 and the test mode signal TPARA as the third selection signal TSEL2. The eleventh logic gate 331 can output the die identification information DID. <0> and raw film identification information DID <1> The result of performing the AND operation. The twelfth logic gate 332 can output the result of performing the AND operation on the output of the eleventh logic gate 331 and the test mode signal TPARA as the fourth selection signal TSEL3.

[0064] When the test mode signal TPARA is deactivated, the decoding circuit 320 can independently deactivate all the multiple selection signals TSEL<3:0> based on the die identification information DID<1:0>. When the test mode signal TPARA is activated, the decoding circuit 320 can activate one of the multiple selection signals TSEL<3:0> based on the die identification information DID<1:0>. If the value of the die identification information DID<1:0> is "00", the decoding circuit 320 can activate only the first selection signal TSEL0; if the value of the die identification information DID<1:0> is "01", the decoding circuit 320 can activate only the second selection signal TSEL1; if the value of the die identification information DID<1:0> is "10", the decoding circuit 320 can activate only the third selection signal TSEL2; and if the value of the die identification information DID<1:0> is "11", the decoding circuit 320 can activate only the fourth selection signal TSEL3.

[0065] The multiplexing circuit 340 can select and output through the normal global line NGIO<3:0> based on multiple selection signals TSEL<3:0>. <3> Transmitted read data and pass the test global line TGIO <0> <3> One of the transmitted test result signals.

[0066] The multiplexing circuit 340 may include multiple logic gates 341 to 352. The first logic gate 341 can pass the global test line TGIO. <0> <3> The result of the AND operation between the transmitted test result signal and the first selection signal TSEL0 is output to the third signal line GIO-DQ. <0> <3> The second logic gate 342 can invert the first selection signal TSEL0 and output the result. The third logic gate 343 can convert the output of the second logic gate 342 and the result through the normal global line NGIO. <0> <3> The result of the AND operation performed on the read data is output to the third signal line GIO-DQ. <0> <3> The fourth logic gate 344 can pass the global test line TGIO. <0> <3> The result of the AND operation performed on the transmitted test result signal and the second selection signal TSEL1 is output to the third signal line GIO-DQ. <1> <3> The fifth logic gate 345 inverts the second selection signal TSEL1 and outputs the result. The sixth logic gate 346 can convert the output of the fifth logic gate 345 and the result through the normal global line NGIO. <1> <3> The result of the AND operation performed on the read data is output to the third signal line GIO-DQ. <1> <3> The seventh logic gate 347 can pass the global line TGIO test. <0> <3> The result of the AND operation between the transmitted test result signal and the third selection signal TSEL2 is output to the third signal line GIO-DQ. <2> <3> The eighth logic gate 348 can invert the third selection signal TSEL2 and output the result. The ninth logic gate 349 can convert the output of the eighth logic gate 348 and the result through the normal global line NGIO. <2> <3> The result of the AND operation performed on the read data is output to the third signal line GIO-DQ. <2> <3> The tenth logic gate 350 can pass the global line TGIO test. <0> <3> The result of the AND operation between the transmitted test result signal and the fourth selection signal TSEL3 is output to the third signal line GIO-DQ. <3> <3> The eleventh logic gate 351 can invert the fourth selection signal TSEL3 and output the result. The twelfth logic gate 352 can convert the output of the eleventh logic gate 351 and the result through the normal global line NGIO. <3> <3> The result of the AND operation performed on the read data is output to the third signal line GIO-DQ. <3> <3> .

[0067] When multiple selection signals TSEL<3:0> are deactivated, the multiplexing circuit 340 can pass through the normal global line NGIO<3:0> <3> The transmitted read data is output to all third signal lines GIO-DQ<3:0> <3> When any one of the multiple selection signals TSEL<3:0> is activated, the multiplexing circuit 340 can pass the test global line TGIO. <0> <3> The transmitted test result signal is output to the third signal line GIO-DQ<3:0> <3> The signal line corresponding to the activation selection signal.

[0068] Figure 7 This is a diagram illustrating a test method according to an embodiment of the present disclosure. Figure 8 This is a diagram illustrating a method for outputting detection results according to an embodiment of the present disclosure.

[0069] In the following text, reference will be made to Figures 1 to 8 A parallel testing method according to embodiments of the present disclosure is described. It is assumed that the semiconductor device is in the form of four semiconductor dies stacked together, and each semiconductor die has 16 memory cells. It is also assumed that the die identification information DID<1:0> of the four semiconductor dies has values ​​"00", "01", "10", and "11" respectively, from the bottommost semiconductor die (i.e., the first semiconductor die DIE0) to the topmost semiconductor die (i.e., the fourth semiconductor die DIE3).

[0070] When entering test mode, the test mode signal TPARA can be activated.

[0071] In each semiconductor die, 16 memory banks BK0 to BK15 can sequentially output read data to multiple normal global lines NGIO<15:0> according to the test read command TRD, and the data compression circuit 210 can sequentially output a 1-bit unit test result signal generated by compressing the data output from the 16 memory banks BK0 to BK15 to multiple test global lines TGIO<15:0>.

[0072] For example, in each semiconductor die, if 16 memory banks BK0 to BK15 sequentially output read data according to their order, then a 1-bit test result signal for each memory bank can be sequentially written to the test global line in the same order as the memory bank order. More specifically, the test result signal generated based on the read data output from the first memory bank BK0 can be sent to the test global line TGIO. <0> The test result signal generated based on the data read from the second memory bank BK1 after the first test can be sent to the test global line TGIO. <1> In the same manner, the test result signals corresponding to the remaining memory banks BK2 to BK15 can be output sequentially through the test global line TGAO<15:2>.

[0073] The first semiconductor die DIE0 can have die identification information DID<1:0> of "00", therefore, when the test mode signal TPARA is activated, the first selection signal TSEL0 is activated. The second semiconductor die DIE1 can have die identification information DID<1:0> of "01", therefore, when the test mode signal TPARA is activated, the second selection signal TSEL1 is activated. The third semiconductor die DIE2 can have die identification information DID<1:0> of "10", therefore, when the test mode signal TPARA is activated, the third selection signal TSEL2 is activated. The fourth semiconductor die DIE4 can have die identification information DID<1:0> of "11", therefore, when the test mode signal TPARA is activated, the fourth selection signal TSEL3 is activated.

[0074] See Figure 7 When the first selection signal TSEL0 is activated, the first semiconductor die DIE0 can communicate with the third signal line GIO-DQ. <0> <0> The first pad PD0, which is coupled together, will be tested via multiple global test lines TGIO<15:0>. <0> Multiple test result signals are sequentially transmitted and output to devices outside the semiconductor device (e.g., external package pads DQ0).

[0075] When the second selection signal TSEL1 is activated, the second semiconductor die DIE1 can communicate with the third signal line GIO-DQ. <1> <1> The second pad PD1 coupled to the second pad PD1 of the first semiconductor die DIE0 will be tested through multiple global test lines TGIO<15:0>. <1> Multiple test result signals are sequentially transmitted and output to devices outside the semiconductor device (e.g., external package pad DQ1).

[0076] When the third selection signal TSEL2 is activated, the third semiconductor die DIE2 can be coupled to the third signal line GIO-DQ. <2> <2> The third pad PD2 of the second semiconductor die DIE1 and the third pad PD2 of the first semiconductor die DIE0 will pass multiple test global lines TGIO<15:0>. <2> Multiple test result signals are sequentially transmitted and output to external devices (e.g., external package pads DQ2).

[0077] When the fourth selection signal TSEL3 is activated, the fourth semiconductor die DIE3 can communicate with the third signal line GIO-DQ. <3> <3> The fourth pad PD3 of the coupled semiconductor die DIE2, the fourth pad PD3 of the second semiconductor die DIE1, and the fourth pad PD3 of the first semiconductor die DIE0 will be connected via multiple test global lines TGIO<15:0>. <3> Multiple test result signals are sequentially transmitted and output to devices outside the semiconductor device (e.g., external package pad DQ3).

[0078] like Figure 8 As shown, in one embodiment of the present invention, when the test read command TRD is input, the test result is output by performing parallel tests based on the clock signal CLK after a predetermined time. The first semiconductor die DIE0 to the fourth semiconductor die DIE3 can simultaneously output a 1-bit test result signal through each of the 16 memory banks BK0 to BK15 via a pad (each pad corresponds to 16 burst lengths).

[0079] As described above, the pads DQ0 to DQ3 used for outputting test results are not individually allocated, nor are they pads added specifically for testing. Even during normal read / write operations, the pads are shared. Therefore, the semiconductor device according to embodiments of this disclosure not only enables efficient testing without adding pads, but also reduces test time because test results can be output to all memory areas in parallel using only a single read command.

[0080] The concept of this disclosure has been disclosed in conjunction with examples and embodiments. Those skilled in the art will understand that various modifications, additions, combinations, and substitutions are possible without departing from the scope and concept of this disclosure. The embodiments disclosed in this specification should be considered from an illustrative rather than a restrictive perspective. Therefore, the scope of this disclosure is not limited to the description provided. All variations within the meaning and equivalent scope of the claims are included within its scope. < / n> < / m:0> < / n> < / n:0> < / n> < / n:0> < / n:0> < / n:0> < / n> < / m:0>

Claims

1. A test circuit, comprising: A data compression circuit, comprising: compressing read data transmitted via multiple first signal lines to generate multiple test result signals, and outputting the multiple test result signals via multiple second signal lines; and The output control circuit selects one of the multiple test result signals and the read data based on the die identification information and the test mode signal, and outputs the selected signal sequentially through the pre-assigned pads in the multiple pads.

2. The test circuit according to claim 1, wherein, The output control circuit includes multiple control units, which multiplex some bits of the read data and one of the multiple test result signals according to the die identification information and the test mode signal.

3. The test circuit according to claim 2, wherein, Each of the plurality of control units includes: The decoding circuit generates multiple selection signals based on the die identification information and the test mode signal; and A multiplexing circuit that selects and outputs one of the following based on the plurality of selection signals: each of some bits of the read data and one of the plurality of test result signals.

4. A semiconductor device, comprising: Multiple unit storage areas; Multiple normal global lines are coupled together with the multiple unit storage areas; A data compression circuit, comprising: compressing read data transmitted through the plurality of normal global lines to generate a plurality of test result signals, and outputting the plurality of test result signals through the plurality of test global lines; and The output control circuit selects one of the multiple test result signals and the read data based on the die identification information and the test mode signal, and outputs the selected signal sequentially through the pre-assigned pads in the multiple pads.

5. The semiconductor device according to claim 4, wherein, The data compression circuit outputs a signal generated by compressing read data from one of the plurality of unit storage areas, which serves as one of the plurality of test result signals.

6. The semiconductor device according to claim 4, wherein, The output control circuit includes multiple control units, which multiplex some bits of the read data and one of the multiple test result signals according to the die identification information and the test mode signal.

7. The semiconductor device according to claim 6, wherein, Each of the plurality of control units includes: The decoding circuit generates multiple selection signals based on the die identification information and the test mode signal; and A multiplexing circuit that selects and outputs one of the following based on the plurality of selection signals: each of some bits of the read data and one of the plurality of test result signals.

8. A semiconductor device comprising a plurality of semiconductor dies, each semiconductor die having a plurality of pads coupled to each other by bonding leads, each semiconductor die being configured such that, when a test read command is input, the plurality of semiconductor dies simultaneously output test results through some of the pads in a different order.

9. The semiconductor device according to claim 8, wherein, Each of the plurality of semiconductor dies includes an output control circuit that selects a signal transmitted through one of a plurality of test global lines and a plurality of normal global lines based on die identification information and test mode signals, and outputs the selected signal through one of the plurality of pads.

10. The semiconductor device of claim 8, wherein each of the plurality of semiconductor dies includes a plurality of control units, the plurality of control units multiplexing and outputting a first set of signals transmitted through some of a plurality of normal global lines and a second signal transmitted through one of a plurality of test global lines based on die identification information and test mode signals.

11. The semiconductor device according to claim 10, wherein, Each of the plurality of control units includes: The decoding circuit generates multiple selection signals based on the die identification information and the test mode signal; and A multiplexing circuit that selects and outputs one of the following based on the plurality of selection signals: each of the first set of signals and the second signal.

12. The semiconductor device according to claim 8, wherein, Each of the plurality of semiconductor dies includes: Multiple normal global lines are coupled to multiple unit memory areas; A data compression circuit, which outputs multiple test result signals generated by compressing read data transmitted via multiple normal global lines via multiple test global lines; and Output control circuit, and When a test read command is input, the output control circuit of the first semiconductor die, which is the lowest among the plurality of semiconductor dies, outputs the plurality of test result signals through the first pad among the plurality of pads, and the output control circuit of the second semiconductor die stacked on the first semiconductor die simultaneously outputs the plurality of test result signals through the second pad among the plurality of pads.

13. The semiconductor device according to claim 12, wherein, When a normal read command is input, the output control circuit of one of the plurality of semiconductor dies will output the read data transmitted through the plurality of normal global lines to the plurality of pads.

14. The semiconductor device according to claim 12, wherein, The data compression circuit outputs a signal generated by compressing read data output from one of the plurality of unit storage areas, which serves as one of the plurality of test result signals.

15. The semiconductor device according to claim 12, wherein, The output control circuit includes multiple control units, which multiplex some bits of the read data and one of the multiple test result signals according to the die identification information and the test mode signal.

16. The semiconductor device according to claim 15, wherein, Each of the plurality of control units includes: The decoding circuit generates multiple selection signals based on the die identification information and the test mode signal; and A multiplexing circuit that selects and outputs one of the following based on the plurality of selection signals: each of some bits of the read data and one of the plurality of test result signals.

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