Flash memory grain grading method, controller and medium based on multiple screening criteria

Abstract

The application discloses a flash memory chip grading method, controller and medium based on multiple screening standards, and relates to the technical field of flash memory chip grading. The method comprises the following steps: performing erasing and writing screening processing on data blocks of a to-be-tested flash memory chip, and determining initial to-be-tested blocks from the data blocks according to obtained erasing and writing results; performing multiple screening test processing on all the initial to-be-tested blocks based on multiple screening standards at different test temperatures, and obtaining multiple screening results of the initial to-be-tested blocks of the flash memory chip; wherein the multiple screening test processing comprises the following steps: performing first screening test based on a first screening standard, performing second screening test based on a second screening standard, performing third screening test based on a third screening standard, performing fourth screening test based on a fourth screening standard and performing fifth screening test based on a fifth screening standard; and determining a product grade of the flash memory chip according to the multiple screening results. The reliability and accuracy of flash memory chip grading can be improved.

Description

Technical Field

[0001] This application relates to the field of flash memory chip grading technology, and in particular to a flash memory chip grading method, controller and medium based on multiple screening criteria. Background Technology

[0002] Currently, the primary method for screening flash memory is to perform continuous erase, write, and read operations at high and low temperatures. This covers screening under different temperature conditions, including high-temperature write / high-temperature read, high-temperature write / low-temperature read, low-temperature write / low-temperature read, and low-temperature write / high-temperature read. The quality of data blocks is ultimately determined by the presence of high- and low-temperature erase, write, and read failures, thus completing the grading of flash memory products. However, while existing technology can perform preliminary product grading, the reliability and accuracy of current flash memory chip grading methods need improvement due to the limited number of tests, relatively simple testing standards, the randomness of experiments, and the instability of flash memory products. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a flash memory chip grading method, controller, and medium based on multiple screening criteria, which can perform multiple screening tests based on multiple screening criteria, and classify flash memory chips into product grades based on the obtained multiple screening results, thereby improving the reliability and accuracy of flash memory chip grading.

[0004] In a first aspect, embodiments of this application provide a flash memory chip grading method based on multiple screening criteria, wherein the flash memory chip includes multiple data blocks, and each data block includes multiple data pages; the method includes: The data blocks of the flash memory chip to be tested are subjected to erase and write screening processes, and the initial test blocks are determined from the data blocks based on the erase and write results. At different test temperatures, all initial test blocks are subjected to multiple screening tests based on multiple screening criteria to obtain the multiple screening results of the initial test blocks of flash memory chips. The multiple screening test process includes: a first screening test based on the first screening criterion, a second screening test based on the second screening criterion, a third screening test based on the third screening criterion, a fourth screening test based on the fourth screening criterion, and a fifth screening test based on the fifth screening criterion. The product grade of flash memory chips is determined based on the results of multiple screenings.

[0005] In a second aspect, embodiments of this application provide a controller, including: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the flash memory chip grading method based on multiple screening criteria as described in the first aspect.

[0006] Thirdly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the flash memory chip grading method based on multiple screening criteria as described in the first aspect.

[0007] The embodiments of this application include: In the process of grading flash memory chips, firstly, the data blocks of the flash memory chips to be tested undergo an erase and write screening process, and the initial test blocks are determined from the data blocks based on the erase and write results. Secondly, at different test temperatures, multiple screening tests are performed on all the initial test blocks based on multiple screening criteria to obtain the multiple screening results of the initial test blocks of the flash memory chips. The multiple screening tests include: a first screening test based on a first screening criterion, a second screening test based on a second screening criterion, a third screening test based on a third screening criterion, a fourth screening test based on a fourth screening criterion, and a fifth screening test based on a fifth screening criterion. In this way, the data blocks in the flash memory chips are more finely screened and classified based on multiple screening criteria. Finally, the product grade of the flash memory chips is determined based on the multiple screening results. The product grade of the flash memory chips is then determined based on the obtained multiple screening results, thereby improving the reliability and accuracy of flash memory chip grading. In other words, the embodiments of this application can perform multiple screening tests based on multiple screening criteria and classify the product grades of flash memory chips based on the obtained multiple screening results, thereby improving the reliability and accuracy of flash memory chip grading. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a system architecture for performing a flash memory chip grading method based on multiple screening criteria, provided in one embodiment of this application; Figure 2 This is a flowchart illustrating a flash memory chip grading method based on multiple screening criteria provided in one embodiment of this application; Figure 3 This is a schematic diagram of a specific process of a flash memory chip grading method based on multiple screening criteria provided in one embodiment of this application; Figure 4 This is a schematic diagram of the hardware structure of a controller provided in one embodiment of this application. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments.

[0010] It should be noted that although a logical order is shown in the flowcharts in this application, in some cases, the steps shown or described may be performed in a different order than that shown in the flowcharts. In the description of this application, "several" means one or more, and "more" means two or more. The terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or implicitly indicating the order in which the technical features are indicated.

[0011] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0012] This application provides a flash memory chip grading method, controller, and computer-readable storage medium based on multiple screening criteria, relating to the field of flash memory chip grading technology; it can perform multiple screening tests based on multiple screening criteria, and classify flash memory chips into product grades based on the obtained multiple screening results, thereby improving the reliability and accuracy of flash memory chip grading.

[0013] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0014] like Figure 1 As shown, the system architecture for executing a flash memory chip grading method based on multiple screening criteria includes: a controller and a flash memory chip under test electrically connected to the controller. The flash memory chip includes multiple data blocks, and each data block includes multiple data pages. It is understood that the controller is used to execute the flash memory chip grading method based on multiple screening criteria provided in this application embodiment. It is capable of performing multiple screening tests based on multiple screening criteria and classifying the flash memory chips into product grades based on the obtained multiple screening results, thereby improving the reliability and accuracy of flash memory chip grading.

[0015] Those skilled in the art will understand that the system structure shown in the figures does not constitute a limitation on the embodiments of this application, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0016] The system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0017] It will be understood by those skilled in the art that the system architecture and application scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. It is known by those skilled in the art that with the evolution of system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0018] Based on the above system structure, the following are various embodiments of the flash memory chip grading method based on multiple screening criteria of this application.

[0019] Firstly, such as Figure 2 As shown, this flash memory chip grading method based on multiple screening criteria can be applied to, for example... Figure 1 In the system framework shown, the flash memory chip includes multiple data blocks, and each data block includes multiple data pages; the flash memory chip classification method based on multiple screening criteria may include, but is not limited to, steps S100 to S300.

[0020] Step S100: Perform erase / write screening on the data blocks of the flash memory chip to be tested, and determine the initial test block from the data blocks based on the erase / write results.

[0021] According to some embodiments of this application, step S100 includes, but is not limited to, steps S110 to S130.

[0022] Step S110: In the preset storage mode, perform erase and write operations on the data blocks of the flash memory chip to obtain the erase and write results.

[0023] Specifically, in this step, the preset storage mode refers to SLC mode, which means that each storage unit stores only 1 bit of data. The erase / write result is either erase / write failure or erase / write failure.

[0024] Step S120: Identify data blocks whose erase / write results are failed as bad blocks.

[0025] In this step, the bad blocks identified in step S120 will not be subjected to further testing.

[0026] Step S130: The data block with a successful erase / write result is identified as the initial test block.

[0027] In this step, the initial test block has passed the initial erase and write operation, and subsequent tests will be conducted on the initial test block.

[0028] Steps S110 to S130 complete the erase and write screening process, identifying the initial test block and laying the foundation for subsequent multiple screening tests.

[0029] Step S200: At different test temperatures, perform multiple screening tests on all initial test blocks based on multiple screening criteria to obtain the multiple screening results of the initial test blocks of the flash memory chips; wherein, the multiple screening test process includes: a first screening test based on the first screening criterion, a second screening test based on the second screening criterion, a third screening test based on the third screening criterion, a fourth screening test based on the fourth screening criterion, and a fifth screening test based on the fifth screening criterion.

[0030] Specifically, the different test temperatures include: a preset first high temperature, a second high temperature lower than the first high temperature, and a preset low temperature lower than the second high temperature. The first high temperature is denoted as T0, the second high temperature as T1, and the preset low temperature as T3.

[0031] According to some embodiments of this application, step S200 is further described. Step S200: At different test temperatures, multiple screening tests are performed on all initial test blocks based on multiple screening criteria to obtain the multiple screening results of the initial test blocks of the flash memory chips, including but not limited to steps S210 to S260.

[0032] Step S210: Under the first high temperature, perform a first screening test on the pre-determined test pages in all the initial test blocks to obtain the first block classification result.

[0033] Specifically, before conducting the first screening test in step 210, a series of analytical experiments are needed to screen out the poorer data pages in the product (a product has one or more flash memory chips, one chip has multiple data blocks, and each block has multiple data pages). Taking a certain product as an example, this product has X blocks per chip, and each block has Y data pages. Experimental analysis shows that in SLC mode, data pages 0-N perform poorly, typically exhibiting a higher ECC than other pages, and this phenomenon is more pronounced under high-temperature environments. Therefore, the pre-test refers to conducting a series of analytical experiments before conducting the first screening test in step 210. This application does not limit the specific type of analytical experiments performed. The page to be tested refers to the poorly performing data pages 0-N in the flash memory chip under test, which have a higher ECC than other pages.

[0034] Step S220: Switch to the second high temperature and perform a second screening test on the first test block determined based on the first block classification result to obtain the second block classification result.

[0035] Step S230: Switch to the preset low temperature and perform a third screening test on the second test block determined based on the second block classification result to obtain the third block classification result.

[0036] Step S240: At a preset low temperature, a fourth screening test is performed on the third test block determined based on the third block classification result to obtain the fourth block classification result.

[0037] Step S250: Switch to the second high temperature and perform a fifth screening test on the fourth test block determined based on the fourth block classification result to obtain the fifth block classification result; wherein, the first screening test, the second screening test, the third screening test, the fourth screening test and the fifth screening test each adopt different screening criteria.

[0038] Step S260: Determine the fifth classification result as the final multi-screening result.

[0039] Through steps S210 to S260, tests are conducted in conjunction with high and low temperature environments. Four tests are required, with test temperatures including a first high temperature T0, a second high temperature T1, and a preset low temperature T2. Furthermore, data blocks in the flash memory chips are screened and classified in a more refined manner based on multiple screening criteria.

[0040] Further explanation of step S210: Specifically, the first screening test includes: a first cycle test of a preset number of times. The preset number of times M can be pre-configured according to actual testing needs, and this application does not impose specific restrictions on the value of the preset number of times.

[0041] According to some embodiments of this application, step S210: perform a first screening test on the pre-tested pages in all initial test blocks to obtain the first block classification result, including but not limited to steps S211 to S213.

[0042] Step S211: Perform a first loop test on the initial block to be tested to obtain the intermediate classification result; wherein, each first loop test includes: sequential first erase, write and read operations, error bit count processing, and block classification processing based on the maximum error bit count, and the reread operation is disabled in the first erase, write and read operation.

[0043] Specifically, in Example 1: A first cycle test is used for: performing a first erase, write, and read operation on the initial test block and disabling reread operations to obtain the first erase, write, and read result; identifying the initial test block with a failed first erase, write, and read result as a bad block; performing error bit count processing on the reading of the test page in the test block with a successful first erase, write, and read result to obtain the maximum error bit count; performing block classification processing on the maximum error bit count and a preset bit count threshold to obtain a comparison result; if the comparison result shows that the maximum error bit count is greater than the preset bit count threshold, the initial test block is identified as a bad block; if the comparison result shows that the maximum error bit count is not greater than the preset bit count threshold, the initial test block is identified as a first-class block, and the first-class block is a non-bad block; and obtaining the intermediate classification result after classifying each test block.

[0044] Step S212: Perform the next first loop test on the test object determined based on the intermediate classification results of this test to obtain the next intermediate classification results.

[0045] Specifically, the intermediate classification results include: the classification of each initial test block, indicating whether it is a bad block or a non-bad block (Class I). It's understandable that the number of bad blocks and Class I blocks in the intermediate classification results of step S212 may vary: all initial test blocks may be Class I blocks, all initial test blocks may be bad blocks, or some may be Class I blocks and some may be bad blocks. If all initial test blocks are bad blocks, further testing will not be performed. If Class I blocks are present in the intermediate classification results, further testing will continue on the Class I blocks.

[0046] Specifically, the object to be tested determined based on the intermediate classification result in step S212 refers to the first class block.

[0047] In this step, the first category block identified in the previous step is subjected to the next first loop test to obtain the next intermediate classification result. The specific process of the next first loop test is the same as that in Embodiment 1 above. Then, the first category block in the next intermediate classification result is identified as the test object for the next step after that, and the test object for the next step after that is subjected to the first loop test as in Embodiment 1, and so on, in an iterative loop test.

[0048] Step S213: When the number of times the first loop test is executed is equal to the preset number of times, the first classification result is obtained based on the intermediate classification result of each time, and the first screening test ends; wherein, the first classification result includes bad blocks and first-class blocks; the first-class blocks are non-bad blocks.

[0049] In this step, the first type of block determined in the previous first loop test is used as the test object for the next first loop test. This iterative loop test is performed until the number of executions of the first loop test equals the preset number. When the first loop test is successfully executed M times, there are M intermediate classification results (each intermediate classification result distinguishes between bad blocks and first type blocks). The M intermediate classification results are summarized to obtain the first block classification result obtained from the first screening test. The first block classification result includes the number of bad blocks and the number of first type blocks.

[0050] For example, let's illustrate the first screening test based on the first screening criterion. Example 1: Set the test temperature to the first high temperature T0. Under the first high temperature T0, perform the first erase, write, and read operation (the read operation needs to disable reread operation to ensure that data can be read correctly without using offset). Any erase, write, or read operation that returns an incorrect status needs to be removed as a bad block, and no further operations will be performed. After successful erase and write, the main focus is on controlling the read operation. Under the first high temperature T0, obtain the maximum number of error bits for pages 0-N. If the maximum number of error bits exceeds the preset bit threshold K, then the block is marked as a runtime bad block, and no further operations will be performed. Pages N+1 P and Y do not need to be analyzed for their ECC; it is only necessary to ensure that data can be read correctly without applying offset voltage. This process is repeated M times under the first high temperature T0 environment. Each cycle test does not test runtime bad blocks that appeared in the previous cycle test.

[0051] Understandably, the first screening criteria include: identifying test blocks that fail the first erase / write read test as bad blocks; after performing error bit count processing on the read of test pages in test blocks that succeed in the first erase / write read test test, identifying test blocks with the maximum error bit count greater than a preset bit count threshold as bad blocks; and filtering out bad blocks in each first loop test.

[0052] The first screening test is completed through steps S211 to S213, and the first classification result is obtained, which lays a reference foundation for the subsequent second screening test.

[0053] According to some embodiments of this application, the second screening test includes a second cyclic test with a preset number of times; further, step S220 is described, wherein the second screening test is performed on the first block to be tested determined based on the first block classification result to obtain the second block classification result, including but not limited to steps S221 to S224.

[0054] Step S221: Determine the first class block in the first classification result as the first test block.

[0055] In this step, the first class block in the first classification result is identified as the first test block, and no further testing is performed on the bad blocks in the first classification result.

[0056] Step S222: Perform a second loop test on the first test block to obtain the intermediate classification result; wherein, each second loop test is performed to: perform a second erase, write, and read operation on the first test block and disable the reread operation to obtain the second erase, write, and read result of each first test block; reclassify each first test block according to the second erase, write, and read result, and determine the first test block with the second erase, write, and read result as a newly added bad block, or determine the first test block with the second erase, write, and read result as a second type of block; Step S223: After repeating the second loop test a preset number of times, the second block classification result is obtained; wherein, the second block classification result includes: the second type of block and the newly added bad block; the second type of block is a non-bad block.

[0057] Specifically, after screening is completed under the first high temperature T0 environment, the test temperature is set to the second high temperature T1. The second high temperature T1 will always be lower than the first high temperature T0, and it must be completely consistent with the product specifications. For example, if a product's high and low temperature specifications shipped to customers are -25℃ to 85℃, then the second high temperature T1 is 85℃. The first high temperature T0 can be 95℃ or 105℃; the specific temperature to be determined through experimental analysis is needed to find the most suitable screening temperature. Therefore, the first high temperature T0 and the second high temperature T1 are related to the specifications of the flash memory to be tested. Without restricting the flash memory specifications, this application does not impose specific restrictions on the values ​​of the first high temperature T0 and the second high temperature T1.

[0058] Understandably, the second erase / write / read test is performed at the second high temperature T1. This is after the initial erase / write / read test at the first high temperature T0, which has already filtered out relatively weak data blocks. At this point, the remaining blocks (i.e., the first type of blocks) need to be tested. Following the same steps, the second erase / write / read test is performed at the second high temperature T1, marking failed erase / write / read blocks as bad blocks and removing them. At the second high temperature T1, the reread function also needs to be disabled, but the maximum number of error bits for pages 0-N is no longer considered. Instead, the focus is on whether data can be read correctly without using offset voltage to classify bad and non-bad blocks. In other words, the second screening criterion used in the second screening test is: if the second erase / write / read result is a failure, the corresponding first test block is identified as a newly added bad block; if the second erase / write / read result is a success, the corresponding first test block is identified as a non-bad second type of block.

[0059] The second screening test is completed through steps S221 to S223, and the second classification result is obtained, which lays a reference foundation for the subsequent third screening test.

[0060] According to some embodiments of this application, step S230 is further described, wherein a third screening test is performed on the second test block determined based on the second block classification result to obtain a third block classification result, including but not limited to steps S231 to S234.

[0061] Step S231: Determine the second class block in the second classification result as the second test block.

[0062] In this step, the second type of block in the second classification result is identified as the second test block, and no further testing is performed on the bad blocks in the second classification result.

[0063] Step S232: Perform a read-only operation on the second test block and enable the reread operation to obtain the first read result of the second test block.

[0064] Step S233: Reclassify the second test block according to the first reading result. The second test block whose first reading result is a reading failure is identified as a newly added bad block, or the second test block whose first reading result is a reading success is identified as a third type of block. Step S234: After reclassifying each second block to be tested, the classification result of the third block is obtained; wherein, the classification result of the third block includes: newly added bad blocks and third-class blocks, and the third-class blocks are non-bad blocks.

[0065] Specifically, after screening is completed under the second high-temperature environment T1, the toilet temperature is set to the preset low-temperature environment T2. Read-only operations are performed at temperature T2, completing the high-temperature write and low-temperature read. It is important to note that the reread function needs to be enabled at this stage, because flash memory products often perform worse in cross-temperature operations than in same-temperature operations. Disabling the reread function may result in a large number of bad blocks (depending on the specific product specifications). When reading data at temperature T2, the judgment is not based on the maximum number of error bits; only the correctness of the first read result needs to be considered. That is to say, the third screening test uses the following third screening criterion: if the first read result is a read failure, the corresponding second test block is identified as a newly added bad block; if the first read result is a read success, the corresponding second test block is identified as a third-class block.

[0066] Steps S231 to S234 complete the third screening test and obtain the third classification result, laying a reference foundation for the subsequent fourth screening test.

[0067] According to some embodiments of this application, step S240 is further described, the fourth screening test includes a third cycle test of a preset number of times; the preset number of times M can be pre-configured according to actual testing needs, and this application does not impose specific restrictions on the value of the preset number of times.

[0068] Among them, step S240: perform a fourth screening test on the third test block determined based on the third block classification result to obtain the fourth block classification result, including but not limited to steps S241 to S244.

[0069] Step S241: Determine the third class block in the third block classification result as the third test block.

[0070] In this step, the third type of block in the third classification result is identified as the third block to be tested, and no further testing is performed on the bad blocks in the third classification result.

[0071] Step S242: Perform a third loop test on the third test block to obtain the intermediate classification result; wherein, each third loop test includes: sequential third erase, write and read operations and data block classification processing.

[0072] In this step, Example 2: A third loop test is used to: perform a third erase, write, and read operation on the third test block to obtain the third erase, write, and read result and disable the reread operation; then, based on the third erase, write, and read result and the second screening criteria, the data block is classified to obtain the intermediate classification result: the third test block with a failed third erase, write, and read result is identified as a bad block; the third test block with a successful third erase, write, and read result is identified as a non-bad block in the fourth category.

[0073] Specifically, the intermediate classification result in step S242 includes: the classification status of each third test block, and whether the third test block is a bad block or a non-bad block (a fourth-class block). It is understandable that the number of bad blocks and fourth-class blocks in the intermediate classification result of step S242 may vary: all may be fourth-class blocks, all may be bad blocks, or some may be first-class blocks and some may be bad blocks. If all third test blocks are bad blocks, further testing will not be performed. If the intermediate classification result contains fourth-class blocks, further testing will continue on the fourth-class blocks.

[0074] Step S243: Perform the third loop test on the test object determined based on the intermediate classification results of this test to obtain the next intermediate classification results.

[0075] Specifically, the object to be tested in this step, determined based on the intermediate classification results, is the fourth type of block.

[0076] In this step, the fourth category block identified in the previous test is subjected to the third loop test again to obtain the next intermediate classification result. The specific process of the next third loop test is the same as that in Example 2 above. Then, the fourth category block in the next intermediate classification result is identified as the test object for the next test, and the third loop test is performed again as in Example 2, and so on, in an iterative loop test.

[0077] Step S244: When the number of times the third loop test is executed is equal to the preset number of times, the fourth classification result is obtained based on the intermediate classification result of each time, and the fourth screening test ends; wherein, the fourth block classification result includes: the fourth type block and the newly added bad block; the fourth type block is a non-bad block.

[0078] In this step, the fourth type of block determined in the previous third loop test is used as the test object for the next third loop test. This iterative loop test is performed until the number of executions of the third loop test equals the preset number. When the third loop test is successfully executed M times, there are M intermediate classification results (each intermediate classification result distinguishes between bad blocks and fourth type blocks). The M intermediate classification results are summarized to obtain the fourth block classification result obtained by the fourth screening test. The fourth block classification result includes the number of bad blocks and the number of fourth type blocks.

[0079] For example, to illustrate the fourth-level screening test based on the fourth screening criterion, Example 2: After completing a read-only operation at a preset low temperature T2, it is necessary to continue with erase / write / read operations under the same preset low temperature T2 environment. In this environment, the reread function needs to be disabled, and M third-loop tests are also required. There is no need to control the maximum number of error bits (ECC); it is only necessary to ensure that the erase / write / read state is error-free. Furthermore, if the operation fails during multiple loop tests, the number of failures can be recorded for further data analysis.

[0080] Steps S241 to S244 complete the fourth screening test and obtain the fourth classification result, laying a reference foundation for the subsequent fifth screening test.

[0081] According to some embodiments of this application, step S250: performing a fifth screening test on the fourth test block determined based on the fourth block classification result to obtain the fifth block classification result, including but not limited to steps S251 to S254.

[0082] Step S251: Determine the fourth class block in the fourth block classification result as the fourth test block.

[0083] In this step, the fourth block in the fourth classification result is identified as the fourth block to be tested, and no further processing is performed on the bad blocks in the fourth classification result.

[0084] Step S252: Perform a read-only operation on the fourth test block and enable the reread operation to obtain the second read result of the fourth test block.

[0085] Step S253: Reclassify the fourth test block according to the second reading result. The fourth test block with the second reading result of reading failure is identified as a newly added bad block, or the fourth test block with the second reading result of reading success is identified as a fifth type of block.

[0086] Step S254: After reclassifying each fourth block to be tested, the classification result of the fifth block is obtained; wherein, the classification result of the fifth block includes: newly added bad blocks and fifth-class blocks, and the fifth-class blocks are non-bad blocks.

[0087] After completing the erase / write / read operation at the preset low temperature T2 via steps S251 to S254, a read-only operation needs to be performed again at the second high temperature T1. Set the test temperature to the second high temperature T1 and perform a read-only operation in this environment to complete the low-temperature write and high-temperature read. At this point, the reread function needs to be enabled to ensure data reliability. ECC control is not required. After completing the read-only operation at the second high temperature T1, all screening steps are complete.

[0088] Step S300: Determine the product grade of the flash memory chip based on the results of multiple screenings.

[0089] Specifically, flash memory is graded based on the number of bad blocks in the multiple screening results to determine the product grade of the flash memory chips. The more bad blocks, the lower the quality of the flash memory chip, and the lower its product grade. This application does not impose specific limitations on the specific grading criteria.

[0090] In the process of grading flash memory chips through steps S100 to S300, firstly, the data blocks of the flash memory chips to be tested undergo an erase / write screening process, and the initial test blocks are determined from the data blocks based on the erase / write results. Secondly, at different test temperatures, multiple screening tests are performed on all the initial test blocks based on multiple screening criteria to obtain the multiple screening results of the initial test blocks of the flash memory chips. The multiple screening tests include: a first screening test based on a first screening criterion, a second screening test based on a second screening criterion, a third screening test based on a third screening criterion, a fourth screening test based on a fourth screening criterion, and a fifth screening test based on a fifth screening criterion. Thus, the data blocks in the flash memory chips are screened and classified more finely based on multiple screening criteria. Finally, the product grade of the flash memory chips is determined based on the multiple screening results. The product grades of the flash memory chips are classified based on the obtained multiple screening results, thereby improving the reliability and accuracy of flash memory chip grading. In other words, the embodiments of this application can perform multiple screening tests based on multiple screening criteria and classify flash memory chips into product grades based on the obtained multiple screening results, thereby improving the reliability and accuracy of flash memory chip grading.

[0091] Understandably, the current common practice is to complete a single round of high and low temperature testing, simply determining whether there are any write / erase failures at these temperatures to complete the chip selection. However, this approach cannot avoid the randomness of experiments and the instability of flash memory products. Therefore, this application addresses these shortcomings and the characteristics of some flash memory products by adding multiple rounds of selection testing under different temperature environments. Simultaneously, it tightens testing for areas with weaker specific product characteristics, thereby achieving different card control standards for different areas and different numbers of test rounds. Furthermore, during data reading, the maximum ECC obtained during data reading will be used as one of the grading standards to distinguish between bad and non-bad blocks. Taking a certain SLC flash memory chip as an example, combined with... Figure 3 Here is an example to illustrate the flash memory chip grading method based on multiple screening criteria in this application.

[0092] Step S1: Erase and write in SLC mode.

[0093] Step S2: Determine if the erase / write operation failed; if yes, mark the bad block; if no, proceed to step S3.

[0094] Step S3: Perform the first cycle test M times on the non-bad block at the first high temperature T0 and disable the reread function, and take the maximum number of error bits of the page to be tested.

[0095] Step S4: Determine whether the maximum number of error bits is greater than the preset number of bits threshold K; if yes, mark the newly added bad block; if no, proceed to step S5.

[0096] Step S5: Under the second high temperature T1, perform M third-cycle tests on non-bad blocks and disable the reread function. Each third-cycle test includes erase, write and read operations.

[0097] Step S6: Determine whether the erase / write / read operation failed; if yes, mark the newly added bad block; if no, proceed to step S7.

[0098] Step S7: Perform read-only operation on non-bad blocks at the preset low temperature T2 and enable the reread function.

[0099] Step S8: Determine if the read was successful; if not, mark the newly added bad block; if yes, proceed to step S9.

[0100] Step S9: Perform erase, write, and read operations M times at a preset low temperature T2 and disable the reread function.

[0101] Step S10: Determine whether the erase / write / read operation was successful; if not, mark the newly added bad block; if yes, proceed to step S11.

[0102] Step S11: Perform a read-only operation at the second high temperature T1 and enable the reread function.

[0103] Step S12: Determine if the read was successful; if not, mark the newly added bad block; if yes, proceed to step S13.

[0104] Step S13: Summarize the results of multiple filtering; then end.

[0105] In summary, this application first uses a high temperature exceeding the shipped product specifications for erase, write, and read tests, while simultaneously implementing ECC control for weaker pages. Furthermore, under this first high temperature condition, the reread function is disabled to ensure data security without the use of offset voltage. This round of screening has relatively strict criteria and involves multiple cycles of screening, allowing most of the weaker blocks to be identified in this round. Using a second high temperature and a preset low temperature for testing serves not only to select weaker blocks but also to verify the results of the first high temperature screening. Both the second high temperature and the preset low temperature are boundary temperatures of the product specifications; performing multiple cycles of testing at these temperatures ensures the product's reliability within the specification range.

[0106] This patent focuses on the screening and grading of flash memory products. For flash memory products before shipment, a series of effective tests are required to identify and mark weaker data blocks, preventing subsequent users from using the bad block areas of the flash memory product. This application can effectively screen out poor-performing flash memory products, ensuring that such products do not enter the market.

[0107] like Figure 4 As shown, this application also provides a controller, including: The processor 401 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 402 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 402 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 402 and is called and executed by the processor 401 using the flash memory chip grading method based on multiple screening criteria in the embodiments of this application. Input / output interface 403 is used to implement information input and output; The communication interface 404 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 405 transmits information between various components of the device (e.g., processor 401, memory 402, input / output interface 403, and communication interface 404); The processor 401, memory 402, input / output interface 403 and communication interface 404 are connected to each other within the device via bus 405.

[0108] This application embodiment also provides a storage medium, which is a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the above-described flash memory chip grading method based on multiple screening criteria.

[0109] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0110] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0111] The above provides a detailed description of the preferred embodiments of this application. However, this application is not limited to the above-described embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by this application.

Claims

1. A flash memory chip grading method based on multiple screening criteria, characterized in that, Flash memory chips comprise multiple data blocks, each data block comprising multiple data pages; the method includes: The data blocks of the flash memory chip to be tested are subjected to erase and write screening processes, and the initial test blocks are determined from the data blocks based on the erase and write results. At different test temperatures, all initial test blocks are subjected to multiple screening tests based on multiple screening criteria to obtain the multiple screening results of the initial test blocks of flash memory chips. The multiple screening test process includes: a first screening test based on the first screening criterion, a second screening test based on the second screening criterion, a third screening test based on the third screening criterion, a fourth screening test based on the fourth screening criterion, and a fifth screening test based on the fifth screening criterion. The product grade of flash memory chips is determined based on the results of multiple screenings.

2. The flash memory chip grading method based on multiple screening criteria according to claim 1, characterized in that, Different test temperatures include: a preset first high temperature, a second high temperature lower than the first high temperature, and a preset low temperature lower than the second high temperature; At different test temperatures, all initial test blocks were subjected to multiple screening tests based on multiple screening criteria to obtain the multiple screening results of the initial test blocks of the flash memory chips, including: Under the first high temperature, the pre-tested pages in all the initial test blocks are subjected to the first screening test to obtain the first block classification result; Switch to the second high temperature, and perform a second screening test on the first test block determined based on the first classification result to obtain the second classification result; Switch to the preset low temperature and perform a third screening test on the second test block determined based on the second block classification result to obtain the third block classification result; At a preset low temperature, a fourth screening test is performed on the third test block determined based on the third block classification result to obtain the fourth block classification result; Switching to the second high temperature, a fifth screening test is performed on the fourth test block determined based on the fourth block classification result to obtain the fifth block classification result; among them, the first screening test, the second screening test, the third screening test, the fourth screening test, and the fifth screening test each use different screening criteria; The fifth classification result is determined as the final multi-screening result.

3. The flash memory chip grading method based on multiple screening criteria according to claim 2, characterized in that, The first screening test includes: a first cycle test with a preset number of iterations; The first screening test is performed on the pages to be tested identified in the pre-test of all the initial test blocks to obtain the first block classification result, including: The initial test block is subjected to a first loop test to obtain the intermediate classification result. Each first loop test includes: sequential first erase, write and read operations, error bit count processing, and block classification processing based on the maximum error bit count. The reread operation is disabled in the first erase, write and read operation. The test objects identified based on the intermediate classification results are subjected to the next first-cycle test to obtain the next intermediate classification results; When the number of times the first loop test is executed equals the preset number of times, the first classification result is obtained based on the intermediate classification result of each iteration, and the first screening test ends; wherein, the first classification result includes bad blocks and first-class blocks; the first-class blocks are non-bad blocks.

4. The flash memory chip grading method based on multiple screening criteria according to claim 3, characterized in that, The second screening test includes a second round of testing with a preset number of cycles; The second screening test is performed on the first test block determined based on the first block classification result to obtain the second block classification result, including: The first class block in the first classification result is identified as the first block to be tested. A second loop test is performed on the first test block to obtain the intermediate classification result. Each second loop test is performed as follows: a second erase, write, and read operation is performed on the first test block while rereading is disabled to obtain the second erase, write, and read result for each first test block; each first test block is reclassified based on the second erase, write, and read result, and the first test block with a failed second erase, write, and read result is identified as a newly added bad block, or the first test block with a successful second erase, write, and read result is identified as a second-class block. After repeating the second cycle test a preset number of times, the second block classification result is obtained; the second block classification result includes: the second type of block and the newly added bad block; the second type of block is a non-bad block.

5. The flash memory chip grading method based on multiple screening criteria according to claim 4, characterized in that, The third screening test is performed on the second test block determined based on the second block classification result to obtain the third block classification result, including: The second class block in the second classification result is identified as the second test block; Perform a read-only operation on the second block under test and enable the reread operation to obtain the first read result of the second block under test. The second test block is reclassified based on the first read result. The second test block whose first read result is a read failure is identified as a newly added bad block, or the second test block whose first read result is a read success is identified as a third type of block. After reclassifying each second block to be tested, the classification result of the third block is obtained; the classification result of the third block includes: newly added bad blocks and third-class blocks, and the third-class blocks are non-bad blocks.

6. The flash memory chip grading method based on multiple screening criteria according to claim 5, characterized in that, The fourth screening test includes a third cycle test with a preset number of iterations; A fourth screening test is performed on the third test block determined based on the third block classification result to obtain the fourth block classification result, including: The third block in the third classification result is identified as the third block to be tested. A third loop test is performed on the third test block to obtain the intermediate classification result; each third loop test includes: sequential third erase, write and read operations and data block classification processing; The test objects identified based on the intermediate classification results are then subjected to a third round of testing to obtain the next intermediate classification results. When the number of times the third loop test is executed equals the preset number of times, the fourth classification result is obtained based on the intermediate classification result of each iteration, and the fourth screening test ends. The fourth classification result includes: the fourth type of block and the newly added bad blocks; the fourth type of block is the non-bad block.

7. The flash memory chip grading method based on multiple screening criteria according to claim 6, characterized in that, The fifth screening test is performed on the fourth test block determined based on the fourth block classification result to obtain the fifth block classification result, including: The fourth block in the fourth classification result is identified as the fourth block to be tested. Perform a read-only operation on the fourth block under test and enable the reread operation to obtain the second read result of the fourth block under test. Based on the second read result, the fourth test block is reclassified. The fourth test block with a second read result of read failure is identified as a newly added bad block, or the fourth test block with a second read result of read success is identified as a fifth type of block. After reclassifying each fourth block to be tested, the classification result of the fifth block is obtained; the classification result of the fifth block includes: newly added bad blocks and fifth-class blocks, and the fifth-class blocks are non-bad blocks.

8. The flash memory chip grading method based on multiple screening criteria according to claim 1, characterized in that, The data blocks of the flash memory chip under test are subjected to erase and write screening. Based on the erase and write results, the initial test blocks are determined from the data blocks, including: In the preset storage mode, the data blocks of the flash memory chip are erased and written to obtain the erase and write results; Data blocks that fail to be erased or rewritten are identified as bad blocks. The data block that was successfully erased / written is selected as the initial test block.

9. A controller, characterized in that, Includes at least one processor and memory for communicating with at least one processor; The memory stores instructions that can be executed by at least one processor, which enables the at least one processor to perform the flash memory chip grading method based on multiple screening criteria as claimed in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to perform the flash memory chip grading method based on multiple screening criteria as claimed in any one of claims 1 to 8.

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