Two-stage open-loop comparator and integrated chip
By introducing a voltage follower circuit and a dynamic bias current source into the two-stage open-loop comparator, the problem of output mis-flipping caused by power supply jitter is solved, achieving a high-speed response and low-power design, and optimizing the comparator's performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JOULWATT TECH INC LTD
- Filing Date
- 2025-09-29
- Publication Date
- 2026-06-12
Smart Images
Figure CN122204011A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic technology, specifically relating to a two-stage open-loop comparator and its integrated chip. Background Technology
[0002] Two-stage open-loop comparators are widely used in high-speed comparison applications due to their fast response speed. For example... Figure 1 and Figure 2 As shown, the two-stage open-loop comparator has a two-stage amplification structure: the first stage is used to amplify the difference in the input signal, the output of the first stage is used as the input signal of the second stage, the second stage further amplifies and outputs the final comparison result, which is usually a high level or a low level.
[0003] by Figure 1 For example, pull-up transistor M1 is connected to the power supply terminal VDD, which is usually provided by the chip's internal power supply. Because this internal power supply connects to many circuits, VDD is not an ideally stable signal and exhibits some high-low voltage jitter. The two-stage open-loop comparator is a high-speed comparator, so the internal components and capacitors are very small. When Vcap is low, the output voltage of the first stage is insufficient to completely turn off pull-up transistor M0. If VDD jitters (increases), pull-up transistor M0 may mis-turn on, causing the output of the two-stage switching comparator to incorrectly switch high, leading to subsequent timing logic errors.
[0004] Similarly, such as Figure 2 As shown, when Vcap is small, voltage fluctuations at GND can cause the pull-down transistor M0 to switch its conduction state incorrectly, resulting in the outputs of the two-stage switching comparators flipping incorrectly, which in turn leads to subsequent timing logic disorder.
[0005] To address these issues, existing technologies propose solutions such as "increasing the size of the transistors inside the two-stage open-loop comparators and adding capacitors to suppress fluctuations" and "adding an RC filter circuit at the output of the second stage to filter out erroneous switching signals." However, these existing solutions slow down the overall response speed of the two-stage open-loop comparators and increase the signal transmission time. Further improving the response speed would require increasing power consumption, sacrificing power efficiency and increasing chip area. Summary of the Invention
[0006] To address the technical problems that existing solutions lead to slower comparator response speeds or increased power consumption, this invention proposes a two-stage open-loop comparator and its integrated chip, wherein the two-stage open-loop comparator includes:
[0007] The first-stage amplifier circuit receives the reference voltage and the ramp voltage to output a first output voltage that represents the difference between the reference voltage and the ramp voltage.
[0008] The second-stage amplifier circuit includes a first power transistor, the source of which is connected to a first node, and the drain of which is connected to an output node. The first node is either a ground terminal or a power supply terminal.
[0009] A voltage follower circuit controls the gate voltage of the first power transistor to follow the voltage change of the first node when the ramp voltage is less than a preset threshold, wherein the preset threshold is less than the ramp voltage.
[0010] Furthermore, the first-stage amplifier circuit includes:
[0011] The differential transistor pair generates the first output voltage based on the reference voltage and the ramp voltage;
[0012] The tail current source provides a variable bias current to the differential transistor pair.
[0013] The average value of the bias current decreases throughout the entire operating cycle.
[0014] Furthermore, the voltage follower circuit includes at least one power transistor, the size of which is smaller than the size of the first power transistor.
[0015] Furthermore, when the voltage follower circuit is turned on, the bias current of the first-stage amplifier circuit is at its minimum.
[0016] Furthermore, when the ramp voltage increases to near the reference voltage, the bias current of the first-stage amplifier circuit is at its maximum.
[0017] Furthermore, during the bias current variation, the absolute value of the difference between the reference voltage and the ramp voltage is negatively correlated with the magnitude of the bias current.
[0018] Furthermore, the magnitude of the bias current is positively correlated with the slew rate of the gate of the first power transistor.
[0019] Furthermore, the ramp voltage controls the magnitude of the bias current, and the bias current gradually increases as the ramp voltage increases until it stabilizes.
[0020] Furthermore, the voltage follower circuit includes:
[0021] The second power transistor is connected between the gate of the first power transistor and the first node, and the second power transistor is turned on when the ramp voltage is less than the preset threshold.
[0022] The second power transistor is smaller than the first power transistor.
[0023] Furthermore, the voltage follower circuit also includes:
[0024] The driving circuit pulls up or down the gate voltage of the second power transistor according to the ramp voltage to control the on / off state of the second power transistor;
[0025] The driving circuit includes a power transistor and a current source. The size of the power transistor is smaller than that of the first power transistor, and the current source outputs a nanoampere current.
[0026] Furthermore, the driving circuit includes a pull-up current source and a pull-down power transistor connected in series. The pull-up current source is connected to the power supply terminal, and the pull-down power transistor is connected to the ground terminal. A driving voltage is provided to the gate of the second power transistor through the common node of the pull-up current source and the pull-down power transistor.
[0027] The switching on and off of the pull-down power transistor is controlled according to the ramp voltage.
[0028] Furthermore, the preset threshold is set according to the conduction threshold of the power transistor.
[0029] Furthermore, the tail current source includes:
[0030] The first current source is directly connected to the differential transistor pair;
[0031] The second current source is connected to the differential transistor through the third power transistor;
[0032] As the ramp voltage increases, the conduction degree of the third power transistor gradually increases until it is fully turned on.
[0033] An integrated chip that integrates the two-stage open-loop comparator described above.
[0034] On the one hand, the voltage follower circuit in this invention can control the gate voltage of the first power transistor to follow the voltage change of the first node when the ramp voltage is small, thereby keeping the first power transistor in the off state and avoiding the first power transistor from being mis-turned on.
[0035] On the other hand, this invention further proposes to set a tail current source to provide a dynamic bias current, thereby reducing the average bias current throughout the entire operating cycle and achieving a reduction in power consumption. Specifically, when the ramp voltage is small, a smaller bias current can be set due to the conduction of the voltage follower circuit. When the ramp voltage is large, a larger bias current is set to increase the slew rate of the gate of the first power transistor, ensuring rapid pull-up or pull-down of the gate voltage of the first power transistor. This improves the fast response capability of the second-stage amplifier circuit, enhances the anti-interference capability, and prevents the first power transistor from being mis-turned on due to fluctuations in the ground terminal voltage or the power supply terminal voltage. Attached Figure Description
[0036] Figure 1 and Figure 2 The block diagram of an existing two-stage open-loop comparator;
[0037] Figure 3 and Figure 4 This is a block diagram of the two-stage open-loop comparator proposed in this invention;
[0038] Figure 5 This is the specific circuit structure of the two-stage open-loop comparator in the first embodiment;
[0039] Figure 6 The second embodiment shows the specific circuit structure of the two-stage open-loop comparator. Detailed Implementation
[0040] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.
[0041] As mentioned in the background section, in a two-stage open-loop comparator, when the ramp voltage Vcap is small (the difference between the ramp voltage Vcap and the reference voltage Vref is large), voltage fluctuations at the ground or power supply terminals may cause the output of the two-stage open-loop comparator to erroneously flip. Existing solutions to address this output erroneous flipping problem reduce the comparator's response speed or increase its power consumption, leaving significant room for optimization. Therefore, to address the comparator output erroneous flipping problem while maintaining the comparator's response speed and power consumption, this invention proposes a two-stage open-loop comparator, such as... Figure 3 and Figure 4 As shown, it includes:
[0042] The first-stage amplifier circuit receives a reference voltage and a ramp voltage to generate a first output voltage, which represents the difference between the reference voltage and the ramp voltage.
[0043] The second-stage amplifier circuit includes a first power transistor M1. The source of the first power transistor is connected to the first node, the drain of the first power transistor is connected to the output node, and the gate of the first power transistor receives the first output voltage. When the first node is a ground terminal, the first power transistor is connected between the output node and the ground terminal. When the first power transistor is turned on, the voltage of the output node is low, and when the first power transistor is turned off, the voltage of the output node is high. When the first node is a power supply terminal, the first power transistor is connected between the output node and the power supply terminal. When the first power transistor is turned on, the voltage of the output node is high, and when the first power transistor is turned off, the voltage of the output node is low.
[0044] The voltage follower circuit controls the gate voltage of the first power transistor to follow the voltage change of the first node when the ramp voltage is less than a preset threshold (the preset threshold is less than the reference voltage), thereby avoiding the first power transistor from being mis-turned on when the voltage of the first node fluctuates.
[0045] In the first embodiment, as Figure 3 As shown, the first power transistor M1 is positioned between the power supply terminal VDD and the output node Vout, and M1 is a P-type MOSFET. The first output voltage is proportional to the reference voltage Vref minus the ramp voltage Vcap. When the ramp voltage Vcap is small, the first output voltage minus the power supply voltage > Vth_M1, at which point the first power transistor M1 is turned off. If the voltage at the power supply terminal VDD increases due to fluctuations, it may cause the first output voltage minus the power supply voltage to be less than Vth_M1, resulting in the first power transistor M1 being falsely turned on. However, this invention incorporates a voltage follower circuit. When the ramp voltage Vcap is less than a preset threshold Vth, the voltage follower circuit is turned on. When the voltage follower circuit is on, the gate voltage of the first power transistor M1 is approximately equal to the power supply voltage, so the first power transistor M1 will remain off and will not be falsely turned on. The preset threshold Vth is a small threshold voltage so that the voltage follower circuit is on when the ramp voltage Vcap is small.
[0046] In the second embodiment, as Figure 4 As shown, the first power transistor M1 is positioned between the output node Vout and the ground terminal, and M1 is an N-type MOSFET. The first output voltage is proportional to the slope voltage Vcap minus the reference voltage Vref. When the slope voltage Vcap is small, the first output voltage minus the ground terminal voltage is less than Vth_M1, at which point the first power transistor M1 is turned off. If the ground terminal voltage decreases due to fluctuations, it may cause the first output voltage minus the ground terminal voltage to exceed Vth_M1, resulting in the first power transistor M1 being falsely turned on. Similarly, the voltage follower circuit in this invention turns on when the slope voltage Vcap is less than the preset threshold Vth. When the voltage follower circuit is on, the gate voltage of the first power transistor M1 is approximately equal to the ground terminal voltage, so the first power transistor M1 will remain off and will not be falsely turned on.
[0047] In summary, the voltage follower circuit in this invention can control the gate voltage of the first power transistor to follow the voltage change of the first node, thereby keeping the first power transistor in a turned-off state and preventing the first power transistor from being mis-turned on.
[0048] Furthermore, considering that the two-stage open-loop comparator is a high-speed comparator with a small size, the present invention also proposes to use small-sized devices when specifically constructing the voltage follower circuit in order to avoid increasing the chip area and power consumption.
[0049] Specifically, in the first embodiment, such as Figure 5 As shown, the voltage follower circuit includes a second power transistor M2 and a drive circuit that controls the switching of the second power transistor M2. The second power transistor M2 is connected between the gate of the first power transistor M1 and the power supply terminal VDD. The drive circuit includes two cascaded pull-up current sources and pull-down power transistors connected in series. Both pull-up current sources are connected to the power supply terminal, and both pull-down power transistors are connected to the ground terminal GND. Specifically, in the first path, the gate of the pull-down power transistor M3 receives the ramp voltage Vcap. In the second path, the gate of the pull-down power transistor M4 is connected to the intermediate node between the pull-up current source I1 and the pull-down power transistor M3 in the first path. The intermediate node between the pull-up current source I2 and the pull-down power transistor M4 in the second path is connected to the gate of the second power transistor M2. The second power transistor M2 is a PMOS transistor, the pull-down power transistors M3 and M4 are NMOS transistors, and the pull-up current sources I1 and I2 are nanoampere-level current sources. When the ramp voltage Vcap is less than the turn-on threshold of the pull-down power transistor M3, M3 in the first path is turned off, and the gate of the pull-down power transistor M4 in the second path is pulled up and turned on, thus the gate of the second power transistor M2 is pulled down and turned on. The dimensions of the second power transistor M2, pull-down power transistors M3 and M4 are smaller than those of the first power transistor M1, and the introduced capacitance is negligible and will not affect the overall response time. The turn-on thresholds of pull-down power transistors M3 and M4 are also relatively small. The preset threshold can be set to a value close to the turn-on threshold based on the turn-on threshold of pull-down power transistor M3. Therefore, this driving circuit achieves the control of the second power transistor M2 to turn on when the ramp voltage Vcap is small (less than the preset threshold), so that the gate voltage of the first power transistor M1 follows the supply voltage (source voltage), thereby preventing the first power transistor M1 from being mis-turned on.
[0050] Specifically, in the second embodiment, such as Figure 6As shown, the voltage follower circuit includes a second power transistor M2 and a drive circuit that controls the switching of the second power transistor M2. The second power transistor M2 is connected between the gate of the first power transistor M1 and ground. The drive circuit includes a pull-up current source I1 and a pull-down power transistor M3 connected in series. The pull-up current source I1 is connected to the power supply terminal VDD, and the pull-down power transistor M3 is connected to ground. The gate of the pull-down power transistor M3 receives a ramp voltage Vcap. The intermediate node between the pull-up current source I1 and the pull-down power transistor M3 is connected to the gate of the second power transistor M2. The second power transistor M2 and the pull-down power transistor M3 are both NMOS transistors, and the pull-up current source I1 is a nanoampere-level current source. When the ramp voltage Vcap is less than the turn-on threshold of the pull-down power transistor M3, the pull-down power transistor M3 is turned off, and the gate of the second power transistor M2 is pulled up and turned on. The dimensions of the second power transistor M2 and the pull-down power transistor M3 are smaller than the dimensions of the first power transistor M1, and the introduced capacitance is negligible and will not affect the overall response time. The turn-on threshold of the pull-down power transistor M3 is also relatively small. The preset threshold can be set to a value close to the turn-on threshold based on the turn-on threshold of the pull-down power transistor M3. Therefore, this driving circuit enables the second power transistor M2 to be turned on when the ramp voltage Vcap is small (less than the preset threshold), so that the gate voltage of the first power transistor M1 follows the ground terminal voltage (source voltage), thereby preventing the first power transistor M1 from being mis-turned on.
[0051] Furthermore, such as Figure 3 and Figure 4 As shown, in a two-stage open-loop comparator, the first-stage amplifier circuit is often a differential circuit, which includes a differential transistor pair and a tail current source. The tail current source provides a bias current to the differential transistor pair so that the differential transistor pair can generate a first output voltage based on the difference between the reference voltage and the ramp voltage. In the prior art, the magnitude of the bias current provided by the tail current source is constant and relatively large. However, it is obvious that in this invention, when the absolute value of the difference between the ramp voltage and the reference voltage is large, the voltage follower circuit alone can control the first power transistor M1 to turn off. At this time, even if the first-stage amplifier circuit does not work, it will not affect the normal operation of the two-stage open-loop comparator.
[0052] Based on this, the present invention proposes to dynamically set the bias current of the first-stage amplifier circuit to reduce the average bias current throughout the entire operating cycle, thereby reducing power consumption (compared to the existing situation where the bias current remains constant). Specifically, the bias current is minimal when the voltage follower circuit is on, at which point the voltage follower circuit mainly controls the first power transistor M1 to turn off. The bias current is maximum when the ramp voltage increases to near the reference voltage, thereby accelerating the pull-up or pull-down speed of the first power transistor M1 and improving the response capability of the two-stage open-loop comparators. Preferably, during the bias current variation, the magnitude of the bias current is negatively correlated with the absolute value of the difference between the input signal and the reference voltage. That is, as the ramp voltage increases, the absolute value of the difference between the reference voltage and the ramp voltage gradually decreases, and the bias current gradually increases.
[0053] Therefore, the bias current of the first-stage amplifier circuit is relatively small in the early stage of the operating cycle and increases in the later stage, effectively reducing the average bias current throughout the entire operating cycle, thereby reducing the power consumption of the entire operating cycle. Simultaneously, due to the larger bias current of the first-stage amplifier circuit in the later stage, the slew rate of the gate of the first power transistor M1 is increased, allowing for rapid pull-up or pull-down of the gate voltage of the first power transistor M1. This improves the fast response capability of the second-stage amplifier circuit, thereby enhancing its anti-interference capability. Furthermore, when the ramp voltage approaches the reference voltage, the first power transistor M1 will not be mis-turned on due to voltage fluctuations at the ground or power supply terminals.
[0054] Specifically, such as Figure 5 and Figure 6 As shown, in order to reduce the power consumption of the two-stage open-loop comparator throughout the entire operating cycle and improve the response capability and anti-interference capability, this invention also proposes to set the bias current in the first-stage amplifier circuit to be variable. During the bias current change, the bias current follows the absolute value of the difference between the reference voltage and the ramp voltage. Specifically, as the ramp voltage gradually increases, the absolute value of the difference between the reference voltage and the ramp voltage gradually decreases, and the bias current gradually increases until it stabilizes.
[0055] In the first embodiment, as Figure 5 As shown, the first-stage amplifier circuit includes:
[0056] The differential transistor pair generates the first output voltage based on the reference voltage and the ramp voltage.
[0057] The tail current source provides a variable bias current to the differential transistor pair, reducing the average bias current over the entire operating cycle. In this embodiment, the absolute value of the difference between the reference voltage and the ramp voltage when the bias current changes is negatively correlated with the magnitude of the bias current.
[0058] The tail current source includes current source I3 and current source I4. A third power transistor M7, which is an NMOS transistor, is connected in series on the branch containing current source I3. When the ramp voltage Vcap is less than the turn-on threshold of the third power transistor M7, the bias current is I4. When the ramp voltage Vcap increases to the turn-on threshold of the third power transistor M7, the conduction degree of the third power transistor M7 gradually increases with the increase of the ramp voltage Vcap, and the current of current source I3 gradually increases until it stabilizes at I3. That is, as the ramp voltage Vcap increases, the bias current gradually increases from I4 and stabilizes at I3 + I4.
[0059] Therefore, the bias current of the first-stage amplifier circuit is relatively small in the early stage of the operating cycle and increases in the later stage, resulting in a decrease in the average bias current throughout the entire operating cycle, thereby reducing the average power consumption over the entire operating cycle. Simultaneously, when the ramp voltage Vcap is close to the reference voltage Vref, the bias current of the first-stage amplifier circuit is at its maximum, accelerating the pull-down of the gate voltage of the first power transistor M1. This rapid pull-down of the gate voltage of the first power transistor M1 enables a fast response and improves the ability to withstand interference from power supply voltage fluctuations.
[0060] In the second embodiment, as Figure 6 As shown, the first-stage amplifier circuit includes:
[0061] The differential transistor pair generates the first output voltage based on the reference voltage and the ramp voltage.
[0062] The tail current source provides a variable bias current to the differential transistor pair, reducing the average bias current over the entire operating cycle. In this embodiment, the absolute value of the difference between the reference voltage and the ramp voltage when the bias current changes is negatively correlated with the magnitude of the bias current.
[0063] The tail current source includes current source I2 and current source I3. A third power transistor M7 is connected in series on the branch containing current source I3. The gate of the third power transistor M7 is connected to the common node of the pull-up resistor R0 and the pull-down transistor M6. The third power transistor M7 is a PMOS, and the pull-down power transistor M6 is an NMOS. When the ramp voltage Vcap is less than the turn-on threshold of the pull-down power transistor M6, the pull-down power transistor M6 is turned off, and the third power transistor M7 is pulled up and turned off, at which point the bias current is I2. When the ramp voltage Vcap increases to the turn-on threshold of the pull-down power transistor M6, the pull-down power transistor M6 turns on, and the third power transistor M7 is pulled down and turned on. As the ramp voltage Vcap increases, the conduction degree of the third power transistor M7 gradually increases, and the current of current source I3 gradually increases until it stabilizes at I3. That is, as the ramp voltage Vcap increases, the bias current gradually increases from I2 and stabilizes at I3 + I2.
[0064] Therefore, the bias current of the first-stage amplifier circuit is relatively small in the early stage of the operating cycle and increases in the later stage. The average bias current decreases throughout the entire operating cycle, thus reducing the average power consumption. Simultaneously, when the ramp voltage Vcap is close to the reference voltage Vref, the bias current of the first-stage amplifier circuit is at its maximum, accelerating the pull-up of the gate voltage of the first power transistor M1. This rapid pull-up of the gate voltage of the first power transistor M1 enables fast response and improves the ability to withstand ground voltage fluctuations.
[0065] The current source in the aforementioned tail current source is a nanoampere-level current source. The size of the power transistor is smaller than that of the first power transistor. The introduced capacitance is negligible and will not affect the overall response time. It will also not occupy a large chip area or increase the chip's power consumption.
[0066] This invention also proposes an integrated chip that integrates the two-stage open-loop comparator described above. Compared to existing integrated chips, the integrated chip in this invention solves the problem of output result mis-flipping without increasing chip power consumption or area.
[0067] It should be noted that the specific implementations and corresponding illustrations provided are merely one way of describing the implementation method of the present invention, and are not intended to limit the specific structure of the implementation scheme of the present invention. Various changes or modifications can be made to these implementation schemes without departing from the principles and essence of the present invention, but all such changes and modifications fall within the protection scope of the present invention.
[0068] Although the embodiments are described and illustrated separately above, some common technologies are involved. Those skilled in the art can replace and integrate them between the embodiments. If there is any content not explicitly described in one embodiment, then another embodiment that is described can be referred to.
[0069] The embodiments described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.
Claims
1. A two-stage open-loop comparator, characterized in that, include: The first-stage amplifier circuit receives the reference voltage and the ramp voltage to output a first output voltage that represents the difference between the reference voltage and the ramp voltage. The second-stage amplifier circuit includes a first power transistor, the source of which is connected to a first node, the drain of which is connected to an output node, and the gate of which receives the first output voltage. The first node is either a ground terminal or a power supply terminal. A voltage follower circuit controls the gate voltage of the first power transistor to follow the voltage change of the first node when the ramp voltage is less than a preset threshold, wherein the preset threshold is less than the ramp voltage.
2. The two-stage open-loop comparator as described in claim 1, characterized in that, The first stage amplifier circuit includes: The differential transistor pair generates the first output voltage based on the reference voltage and the ramp voltage; The tail current source provides a variable bias current to the differential transistor pair. The average value of the bias current decreases throughout the entire operating cycle.
3. The two-stage open-loop comparator as described in claim 1, characterized in that, The voltage follower circuit includes at least one power transistor, the size of which is smaller than that of the first power transistor.
4. The two-stage open-loop comparator as described in claim 2, characterized in that, When the voltage follower circuit is turned on, the bias current of the first-stage amplifier circuit is at its minimum.
5. The two-stage open-loop comparator as described in claim 2, characterized in that, When the ramp voltage increases to near the reference voltage, the bias current of the first-stage amplifier circuit is at its maximum.
6. The two-stage open-loop comparator as described in claim 2, characterized in that, During the period of bias current variation, the absolute value of the difference between the reference voltage and the ramp voltage is negatively correlated with the magnitude of the bias current.
7. The two-stage open-loop comparator as described in claim 2 or 5, characterized in that, The magnitude of the bias current is positively correlated with the slew rate of the gate of the first power transistor.
8. The two-stage open-loop comparator as described in claim 2, characterized in that, The ramp voltage controls the magnitude of the bias current, which gradually increases with the increase of the ramp voltage until it stabilizes.
9. The two-stage open-loop comparator as described in claim 1, characterized in that, The voltage follower circuit includes: The second power transistor is connected between the gate of the first power transistor and the first node, and the second power transistor is turned on when the ramp voltage is less than the preset threshold. The second power transistor is smaller than the first power transistor.
10. The two-stage open-loop comparator as described in claim 9, characterized in that, The voltage follower circuit also includes: The driving circuit pulls up or down the gate voltage of the second power transistor according to the ramp voltage to control the on / off state of the second power transistor; The driving circuit includes a power transistor and a current source. The size of the power transistor is smaller than that of the first power transistor, and the current source outputs a nanoampere-level current.
11. The two-stage open-loop comparator as described in claim 10, characterized in that, The driving circuit includes a pull-up current source and a pull-down power transistor connected in series. The pull-up current source is connected to the power supply terminal, and the pull-down power transistor is connected to the ground terminal. A driving voltage is provided to the gate of the second power transistor through the common node of the pull-up current source and the pull-down power transistor. The switching on and off of the pull-down power transistor is controlled according to the ramp voltage.
12. The two-stage open-loop comparator as described in claim 10, characterized in that, The preset threshold is set according to the conduction threshold of the power transistor.
13. The two-stage open-loop comparator as described in claim 2, characterized in that, The tail current source includes: The first current source is directly connected to the differential transistor pair; The second current source is connected to the differential transistor through the third power transistor; As the ramp voltage increases, the conduction degree of the third power transistor gradually increases until it is fully turned on.
14. An integrated chip, characterized in that, Integrate the two-stage open-loop comparator as described in any one of claims 1-13.