Generator for a nonlinear spread spectrum profile that uses a linear combination

Abstract

Generators (1000, 2000, 3000, 4110, 5110) for a nonlinear spread spectrum clock signal, which has the following: a phase detector which is configured to to receive a reference signal and a feedback signal, to detect a phase difference between the reference signal and the feedback signal, and to output an up signal and a down signal according to the detected phase difference; a charge pump (1120, 2120, 3120) which is configured to to receive the up signal and the down signal, and to output a control current according to the up signal and the down signal; a loop filter (1130, 2130, 3130) which is configured to to receive the control current, and to output a control voltage according to the control current; a generator (1210, 2200, 3200) for a nonlinear profile, which is configured to to generate a plurality of voltage signals, each with separate magnitudes, which vary according to separate linear ramp functions, each of which has separate slopes and initiation time values, and to selectively output a linear ramp voltage signal, wherein the selectively output linear ramp voltage signal has a largest absolute value among the majority of voltage signals, such that the selectively output ramp voltage signal approximates a voltage signal which has a nonlinear profile curve; and a voltage-controlled oscillator (1140, 2140, 3140) configured to to receive the control voltage and the selectively output linear ramp voltage, and to output a signal according to the control voltage and the selectively output linear ramp voltage.

Description

BACKGROUND

[0001] The inventive concepts described herein relate to a spread-spectrum clock signal generator which produces clock signals whose frequency is changed non-linearly and which assume a non-linear curve profile using a plurality of linear combinations.

[0002] The technology referred to as "spread spectrum clock signal generation" is used to reduce electromagnetic interference (EMI) in electronic devices. Specifically, spread spectrum clock signal generation makes it possible to reduce peak power by varying the operating frequency over time. In this technology, a frequency profile that changes over time is crucial for determining the degree of peak power decrement.

[0003] In some cases, various nonlinear profiling methods have been reported to reduce electromagnetic interference. Complex circuits can sometimes be used to generate a signal with a nonlinear waveform. The performance of the spread-spectrum clock signal generator may be reduced due to the complexity of the circuits used to generate the signal. Additionally, an increase in circuit complexity can lead to an increase in chip area.

[0004] US patent 2011 / 0150168A1 discloses a clock generator incorporating a multi-modulus frequency divider and a delta-sigma modulator. The multi-modulus frequency divider is archived by switching its phase. It effectively increases the operating frequency of the clock generator and has a half-period resolution characteristic to reduce jitter in the output clock signal when its spectrum is spread. Furthermore, the delta-sigma modulator enhances the accuracy of the triangle wave modulation and reduces quantization error by adding certain components. This could potentially extend the clock generator to a programmable clock generator.

[0005] The article by Moon, Yong-Hwan, et al.: "A Spread Spectrum Clock Generator for SATA II with Rounded Hershey-Kiss Modulation Profile," published in: Journal of IKEEE 15.2, 2011, pages 129-133, discloses a circuit that generates the spread-spectrum clock by directly inputting the modulation voltage into the current source of the voltage-controlled oscillator (VCO) for SATA II. The resulting 33 kHz modulation profile has a Hershey-Kiss shape with a rounded tip.

[0006] The article by Oh, Seung-Wook, et al.: "A Spread Spectrum Clock Generator for DisplayPort 1.2 with a Hershey-Kiss Modulation Profile," published in: JSTS: Journal of Semiconductor Technology and Science 13.4, 2013, pages 282–290, discloses a spread spectrum clock generator (SSCG) for the DisplayPort 1.2 standard. A Hershey-Kiss modulation profile is generated by two sigma-delta modulators. The structure generates different modulation edges to form a nonlinear modulation profile.

[0007] US 7,813,411 B1 discloses a frequency synthesizer that constitutes a system and a method for modulation. In particular, the frequency synthesizer includes a control circuit for generating multiple input signals that are scalable to a frequency profile. Each of the input signals includes a slope and a direction of the slope. A higher-order accumulator block is coupled to the control circuit and receives the plurality of input signals. The higher-order accumulator block contains at least two accumulators. The higher-order accumulator block sums the multiple input signals to generate a standard curve that is non-linear. A frequency-spreading control pattern-generating modulator is coupled to the higher-order accumulator block and modulates the standard curve to generate the desired frequency profile.

[0008] Therefore, there is a need to develop a method for generating a signal that has a non-linear curve profile using a simple algorithm. SUMMARY

[0009] Some exemplary embodiments of the inventive concept provide a spread-spectrum clock signal generator which generates clock signals, wherein the spread-spectrum clock signal generator uses a non-linear curve profile signal which approximates a non-linear curve profile using a plurality of linear combinations.

[0010] According to some exemplary embodiments of the inventive concepts, a generator for a nonlinear spread-spectrum clock signal can comprise a phase-locked loop configured to receive a reference signal; the phase-locked loop, to compensate for an output signal of the phase-locked loop, comprises a divider configured to receive the output signal and to generate a feedback signal by dividing the output signal by a division ratio; and a division ratio controller configured to control the division ratio. The division ratio controller can comprise a generator for a nonlinear profile and a delta-sigma modulator.The nonlinear profile generator can be configured to produce a plurality of signals, each with separate magnitudes that vary according to separate linear ramp functions. These linear ramp functions have different slopes and initiation times. The output signal is a nonlinear signal whose magnitude varies according to the largest absolute value of the plurality of signals, such that the output signal has a waveform that approximates a nonlinear waveform profile. The delta-sigma modulator can be configured to receive the nonlinear signal and control the division ratio according to the output signal.

[0011] According to some exemplary embodiments of the inventive concepts, a generator for a nonlinear spread-spectrum clock signal can comprise a phase detector, a charge pump, a loop filter, a nonlinear profile generator, and a voltage-controlled oscillator. The phase detector can be configured to receive a reference signal and a feedback signal, to detect a phase difference between the reference signal and the feedback signal, and to output an up signal and a down signal according to the detected phase difference. The charge pump can be configured to receive the up signal and the down signal and to output a control current according to the up signal and the down signal. The loop filter can be configured to receive the control current and to output a control voltage according to the control current.The generator for a nonlinear profile can be configured to produce a plurality of voltage signals, each with separate magnitudes and varying according to separate linear ramp functions. Each linear ramp function has separate slopes and initiation time values. The generator can also be configured to selectively output a linear ramp voltage signal, the selectively output linear ramp voltage signal having the largest absolute value of the plurality of voltage signals, such that the selectively output linear ramp voltage signal approximates a voltage signal with a nonlinear profile curve. The voltage-controlled oscillator can be configured to receive the control voltage and the selectively output linear ramp voltage and to output a signal corresponding to the control voltage and the selectively output linear ramp voltage.

[0012] According to some exemplary embodiments of the inventive concepts, a device can include a nonlinear profile generator. The nonlinear profile generator can be configured to generate a plurality of signals, wherein the signals have separate magnitudes that vary according to separate linear ramp functions, the separate linear ramp functions having different slopes and different initiation time values; and to output a nonlinear signal that has a magnitude that varies according to a largest absolute value of the plurality of signals, such that the output nonlinear signal has a curve that approximates a nonlinear curve profile. The invention is defined in the attached independent claims. Further developments of the invention are specified in the dependent claims. BRIEF DESCRIPTION OF THE FIGURES

[0013] The above and other tasks and features will become apparent from the following description with reference to the following figures, wherein identical reference symbols refer to identical parts across the different figures unless otherwise specified, and wherein: Fig. 1A is a block diagram illustrating a generator for a spread spectrum clock signal according to some exemplary embodiments of the inventive concepts; Fig. 1B is a graph of a curve which has a Hershey-Kiss profile according to some exemplary embodiments of the inventive concepts; Fig. 2 is a graph illustrating a profile of a triangular wave and a spectrum thereof according to some exemplary embodiments of the inventive concepts; Fig. 3 is a graph illustrating a Hershey-Kiss profile and a spectrum thereof according to some exemplary embodiments of the inventive concepts; Fig. 4 is a block diagram illustrating a generator for a nonlinear profile, which is in Fig. 1 is illustrated; Fig. Figure 5 is a block diagram illustrating a generator for a nonlinear profile, which is in Fig. 4 is illustrated; Fig. 6 is a graph that illustrates the curve of a digital value generated by a non-linear profile generator. Fig. 4 or Fig. 5 is issued; Fig. 7 is a graph which shows the overall curve of a digital value generated by a non-linear profile generator. Fig. 4 or 5 is displayed, illustrates; Fig. 8 is a block diagram illustrating a generator for a spread spectrum clock signal according to some exemplary embodiments of the inventive concepts; Fig. Figure 9 is a block diagram illustrating a section of a generator for a nonlinear profile, which is in Fig. 8 is illustrated; Fig. 10 is a block diagram illustrating a generator for a nonlinear profile and a first OR gate, which is in Fig. 9 is illustrated; Fig. 11 is a block diagram illustrating a first OR gate, which is in Fig. 10 is illustrated; Fig. 12 is a flowchart illustrating the curve progressions of step pulses according to some exemplary embodiments; Fig. 13 is a flowchart illustrating a curve of a result in which an OR operation is performed with respect to an output signal of a generator for a nonlinear profile according to some exemplary embodiments of the inventive concepts; Fig. 14A and Fig. 14B Block diagrams are used to describe a procedure in which voltage pulses generated by a step pulse generator are transformed by passing through a phase control loop according to some exemplary embodiments of the inventive concepts; Fig. 15 is a flowchart illustrating an output curve of a control voltage according to some exemplary embodiments of the inventive concepts; Fig. 16 is a block diagram illustrating a generator for a spread spectrum clock signal according to some exemplary embodiments of the inventive concepts; Fig. 17 is a block diagram illustrating a section of a generator for a nonlinear clock signal, which is in Fig. 16 is illustrated; Fig. Figure 18 is a block diagram illustrating a generator for a nonlinear profile, which is in Fig. 16 is illustrated; Fig. Figure 19 is a block diagram illustrating a generator for a nonlinear profile, which is in Fig. 18 is illustrated; Fig. 20 is a block diagram illustrating the output voltage of the generator for a non-linear profile, which is in Fig. 18 or Fig. 19 is illustrated; Fig. 21 is a block diagram illustrating a solid-state drive (SSD) according to some exemplary embodiments of the inventive concepts; and Fig. 22 is a block diagram illustrating a mobile device 3000 to which the inventive concept is applied. DETAILED DESCRIPTION

[0014] Below, exemplary embodiments of inventive concepts will be described in more detail so that those skilled in the art can easily understand the inventive concepts.

[0015] Fig. Figure 1A is a block diagram illustrating a generator for a spread spectrum clock signal according to some exemplary embodiments of the inventive concepts. Fig. Figure 1B is a graph of a curve that has a Hershey-Kiss profile according to some exemplary embodiments of the inventive concepts. A generator 1000 for a spread-spectrum clock signal can include a phase-locked loop 1100 and a division ratio control circuit 1200.

[0016] Referring to Fig. The phase-locked loop 1100 can include a phase frequency detector 1110, a charge pump 1120, a loop filter 1130, a voltage-controlled oscillator 1140, and a divider 1150. The phase-locked loop 1100 can stabilize the phase of an output signal CLK_out to prevent it from changing. Furthermore, to reduce electromagnetic interference (EMI), the phase-locked loop 1100 can modulate the reference signal CLK_ref such that the frequency-time graph of the output signal CLK_out exhibits a non-linear waveform.

[0017] The phase frequency detector 1110 can receive the reference signal CLK_ref and a feedback signal CLK_div, compare the frequency of the reference signal CLK_ref with the frequency of the feedback signal CLK_div, and compare the phase of the reference signal CLK_ref with the phase of the feedback signal CLK_div. For example, if the phase of the reference signal CLK_ref leads the phase of the feedback signal CLK_div, the phase frequency detector 1110 can output an up signal UP of logic 1 and a down signal DN of logic 0. Conversely, if the phase of the reference signal CLK_ref lags the phase of the feedback signal CLK_div, the phase frequency detector 1110 can output the up signal UP of logic 0 and the down signal DN of logic 1. For example, the feedback signal CLK_div can be a signal obtained by dividing the output signal CLK_out by 1 / N.Here, "N" can be a division ratio of the divider 1150.

[0018] The charge pump 1120 can receive the up signal UP and the down signal DN and can generate a control current ICTRL based on the up signal UP and the down signal DN. The charge pump 1120 can have at least one current source, at least two switches that operate in response to the up signal UP and the down signal DN, and at least one capacitor. The charge pump 1120 is an example. However, the scope and intent of the inventive concepts cannot be limited here. For example, the charge pump 1120 can be implemented with different configurations, each of which converts a signal supplied to the charge pump 1120 into a current.

[0019] The loop filter 1130 can operate as a differentiator or an integrator, converting the control current ICTRL, output by the charge pump 1120, into a control voltage VCTRL. Furthermore, the loop filter 1130 can remove a high-frequency component from a signal (i.e., the control current ICTRL) output by the charge pump 1120. This means that the loop filter 1130 can operate as a low-pass filter. For example, the loop filter can include at least one capacitor and at least one resistor. The loop filter 1130 is just one example. However, the scope and intent of the inventive concepts cannot be limited to this. For example, the loop filter 1130 can be implemented with various configurations, each of which can operate as a differentiator, an integrator, or a low-pass filter.

[0020] The voltage-controlled oscillator 1140 can receive the control voltage VCTRL and output the signal CLK_out using this control voltage. At the same time, a frequency-to-time graph can be modified via the control voltage VCTRL to adopt a specific curve shape. For example, if the curve shape of the control voltage VCTRL-to-time graph exhibits a Hershey-Kiss profile, the frequency-to-time graph via the output signal CLK_out can also adopt a Hershey-Kiss profile.

[0021] The divider 1150 can receive the output signal CLK_out and divide it by the division ratio "N". This means that, to precisely control the reference signal CLK_ref, the divider 1150 can adjust the frequency of an input signal (i.e., the feedback signal CLK_div) from the phase frequency detector 1110 by dividing the output signal CLK_out by "N", which is an integer of 1 or greater. The divider 1150 can output a signal generated by dividing the output signal CLK_out by "N" as the feedback signal CLK_div.

[0022] The phase-locked loop 1100 can repeat operations of the components described above, thereby stabilizing the output signal CLK_out. According to some exemplary embodiments of the inventive concepts, however, various control methods can be used such that the curve of the frequency-to-time graph of the output signal CLK_out assumes the Hershey-Kiss profile. A curve that "assumes" the Hershey-Kiss profile can refer here to a curve that at least "approximates" the Hershey-Kiss profile. A method for changing the division ratio N of the divider 1150 in real time can be used as one of the various control methods.

[0023] The division ratio control device 1200 can be configured to change the division ratio N in real time. The division ratio control circuit 1200 can include a Hershey-Kiss profile generator 1210 and a delta-sigma modulator 1230.

[0024] The Hershey-Kiss profile generator 1210 can output a Hershey-Kiss signal 1215, where signal 1215 is a combination of a plurality of signals that vary according to different linear ramp functions, each with different slopes. As in Fig. As shown in Figure 1B, the curve of a digital value-to-time graph of the signal 1215, which is output by the Hershey-Kiss profile generator 1210, can approximate the Hershey-Kiss profile. As a result, the curve of the frequency-to-time graph of the output signal CLK_out (the curve of the output signal CLK_out) can approximate the Hershey-Kiss profile. This is shown with reference to Fig. 4 will be described.

[0025] The delta-sigma modulator 1220 can receive the signal 1215, which is generated by the Hershey-Kiss profile generator 1210, and can transmit a control signal DCTRL to the divider 1150. Generally, the division ratio "N" of the divider 1150 can be a natural number. However, in some cases, the division ratio N must be a decimal value that matches the curve of the output signal CLK_out to achieve the Hershey-Kiss profile. The delta-sigma modulator 1220 can be used to achieve this result.

[0026] According to some exemplary embodiments of the inventive concepts, a nonlinear Hershey-Kiss profile (for example, a profile approximating the Hershey-Kiss profile) can be generated using a combination of signals exhibiting different waveforms according to different linear ramp functions with different voltage slopes. As a result, it may be possible to simplify the configuration of a circuit and an algorithm and to improve operating speed.

[0027] In some exemplary embodiments, the Hershey-Kiss profile generator 1210 is a nonlinear profile generator that can output a nonlinear output signal 1215, wherein the signal 1215 is a combination of a plurality of signals that vary according to different linear ramp functions having different slopes. The curve of a digital value-to-time graph of the nonlinear signal 1215, which is output by the nonlinear profile generator 1210, can assume (approximate) a nonlinear curve profile. For example, the nonlinear signal 1215 can approximate a sinusoidal curve profile. As a result, the curve of the frequency-to-time graph of the output signal CLK_out (the curve of the output signal CLK_out) can assume (approximate) the nonlinear curve profile.

[0028] The delta-sigma modulator 1220 can receive the nonlinear signal 1215, which is generated by the generator 1210 for a nonlinear profile, and can output a control signal D. CTRL The value is transferred to the divider 1150. Generally, the division ratio "N" of the divider 1150 can be a natural number. However, in some cases, the division ratio N of a decimal value must match the curve of the output signal CLK_out to achieve the desired non-linear waveform. The delta-sigma modulator 1220 can be used to achieve the result described above.

[0029] According to some exemplary embodiments of the inventive concepts, a nonlinear waveform profile (for example, a profile approximating the nonlinear waveform profile) can be generated using a combination of signals having different waveforms according to different linear ramp functions, which have different voltage slopes. As a result, it may be possible to simplify the configuration of a circuit and an algorithm and to improve operating speed. The nonlinear waveform profile can be a Hershey-Kiss profile such that the generator 1210 for a nonlinear profile is a Hershey-Kiss profile generator 1210, as shown in Fig. 1A is shown.

[0030] Fig. Figure 2 is a graph illustrating a profile and spectrum of a triangular wave according to some exemplary embodiments of the inventive concepts. Fig. Figure 3 is a graph illustrating a Hershey-Kiss profile and a spectrum thereof according to some exemplary embodiments of the inventive concepts.

[0031] Referring to Fig. Figure 2 illustrates a triangular wave in which a frequency periodically increases or decreases by Δf over a period of time, with a center frequency f0. It is understood from a spectrum of the triangular wave at a frequency domain that a power is changed by ΔP1 while a frequency is changed between 'f0-Δf' and 'f0+Δf'. On the other hand, referring to Fig. Figure 3 illustrates a Hershey-Kiss profile in which a frequency periodically increases or decreases by Δf over a period of time, with the center frequency f0 as the midpoint. Similarly, a spectrum of the Hershey-Kiss profile at one frequency domain indicates that power changes by ΔP2 while a frequency changes between 'f0-Δf' and 'f0+Δ'.

[0032] While a frequency changes over time, the intensity of electromagnetic interference can be determined according to a maximum value of a changing power. That is, while a frequency changes over time, if the maximum value of the changing power becomes small, the effect of electromagnetic interference can be reduced. In a triangular wave, a changing power can have a maximum value at a point in time when the frequency is approximately 'f0-Δf' or 'f0+Δf'. On the other hand, in the Hershey-Kiss profile, the maximum value of the changing power can be smaller than the value of the triangular wave. Furthermore, even if there is a difference of ΔP2 in the Hershey-Kiss profile, a relatively constant power value can be maintained across the entire area between 'f0-Δf' and 'f0+Δf'.In the Hershey-Kiss profile, since the time when frequencies close to 'f0-Δf' and 'f0+Δf' are maintained is short, fluctuations in the maximum value of a changing power at a frequency domain can be relatively small, and therefore a generally stable power can be obtained. As a result, a clock signal that adopts the Hershey-Kiss profile can be used, making it possible to reduce the influence of electromagnetic interference. A configuration and a procedure are described below which correspond to an output curve of the voltage-controlled oscillator 1140 (reference is made to...). Fig. 1) allow the Hershey-Kiss profile to be described.

[0033] Fig. Figure 4 is a block diagram illustrating a generator 1210 for a nonlinear profile, which is in Fig. Figure 1 illustrates this. Referring to Fig. 4 can be a generator 1210 for a nonlinear profile, which can include a Hershey-Kiss profile generator 1210, a plurality of ramp function generators 121-1 to 121-n and a digital multiplexer 1218.

[0034] Each of the ramp function generators 121-1 to 121-n can generate a separate signal that varies according to a separate linear ramp function (also referred to herein as a separate signal having a separate curve according to a separate linear ramp function). Separate linear ramp functions can have different slopes relative to each other. Furthermore, the times at which the linear ramp functions are initially generated (also referred to herein as "initiation time values") can differ relative to each other. For example, a signal with a curve according to a linear ramp function having a large slope can be generated later than a signal with a curve according to a linear ramp function having a small slope.

[0035] The first to nth ramp function generators 121-1 to 121-n are described with reference to Fig. 4. For example, the first ramp function generator 121-1 can generate a signal that varies according to a first linear ramp function, which corresponds to ①. The signal generated by the first ramp function generator 121-1 can vary according to a first linear ramp function with a slope that has the smallest value among the slopes of the ramp functions of signals generated by ramp function generators 121-1 to 121-n. Furthermore, the second ramp function generator 121-2 can generate a signal that varies according to a second linear ramp function, which corresponds to ②. The slope of the second linear ramp function can be greater than that of the first linear ramp function. In addition, the signal that varies according to the second linear ramp function can be generated later than the signal that varies according to the first linear ramp function.Ultimately, the nth linear ramp function generator 121-n can generate a signal that varies according to an nth linear ramp function, which corresponds to ⓝ. The nth linear ramp function can have a slope that is the steepest among the slopes of the ramp functions of signals generated by the ramp function generators 121-1 through 121-n. Furthermore, the signal that varies according to the nth linear ramp function can be generated later than the signals that vary according to the first through (n-1)th linear ramp functions.

[0036] The 1218 digital multiplexer can receive a plurality of signals, each varying according to separate linear ramp functions and each generated by the ramp function generators 121-1 to 121-n. Furthermore, the 1218 digital multiplexer can be configured to output a signal at a given time that varies according to a ramp function whose absolute value is the largest among the absolute values ​​of the plurality of signals generated at that given time.

[0037] Fig. Figure 5 is a block diagram illustrating a generator 1210 for a nonlinear profile, which is in Fig. Figure 4 illustrates this. The generator 1210 for a nonlinear profile can be a Hershey-Kiss profile generator. As described above, the generator 1210 for a nonlinear profile can be an example of an output of a signal that varies according to a ramp function (as a result of a digital value) whose absolute value is the largest at any given time. The digital multiplexer 1218 of the Fig. Comparator 4 can have a plurality of comparators 1218_1 to 1218_n-1. The first comparator, 1218_1, can be configured to compare digital values ​​of signals received by the ramp function generators 121-1 and 121-2. Each of the comparators 1218_2 to 1218_n can be configured to compare digital values ​​of signals received by a corresponding ramp function generator and a corresponding preceding comparator. For example, comparator 1218_2 can be configured to compare digital values ​​of signals received by the second ramp function generator, 121-2, and the first comparator, 1218_1. As a result, a signal that varies according to a ramp function whose absolute value is the largest among a plurality of linear ramp functions can be selectively output.In some exemplary embodiments, the comparators 1218_1 to 1218_n-1 can be an embodiment of the digital multiplexer 1218 of the . Fig. 4. However, the scope and intent of the inventive concepts need not be limited thereto. For example, the digital multiplexer 1218 can have different configurations, each configured to output a signal that has the largest digital value (“absolute size”) of the digital values ​​output via signals from the ramp function generators.

[0038] Fig. Figure 6 is a graph illustrating the curve of a signal that varies according to a digital value output by a generator for a nonlinear profile according to some exemplary embodiments. A method for generating a curve that corresponds to an interval A of the Fig. 3 corresponds to, is in Fig. 6 will be described. For the sake of descriptive expediency, it is assumed that four ramp function generators are used.

[0039] A first ramp function generator 121-1 can generate a signal that varies according to a first linear ramp function, corresponding to ① at time T1. A second ramp function generator 121-2 can generate a signal that varies according to a second linear ramp function, corresponding to ② at time T2. A third ramp function generator 121-3 can generate a signal that varies according to a third linear ramp function, corresponding to ③ at time T3. Finally, a fourth ramp function generator 121-4 can generate a signal that varies according to a fourth linear ramp function, corresponding to ④ at time T4.

[0040] Digital values ​​of signals output by the first to fourth ramp function generators 121-1 to 121-4 can be fed to the comparators 1218_1 to 1218_4. Generator 1210 for a non-linear profile can output a signal with a digital value ("absolute value") that is the largest of the digital values ​​of the signals output by the first to fourth ramp function generators 121-1 to 121-4.

[0041] In a graph of Fig. At time interval A-1, signal (1), which varies according to the first linear ramp function, can be output by generator 1210 because its value (absolute magnitude) is the highest (largest) of the plurality of signals (1)-(4). At time interval A-2, signal (2), which varies according to the second linear ramp function, can be output by generator 1210 because its value (absolute magnitude) is the highest (largest) of the plurality of signals (1)-(4). At time interval A-3, signal (3), which varies according to the third linear ramp function, can be output by generator 1210 because its value (absolute magnitude) is the highest (largest) of the plurality of signals (1)-(4).Ultimately, for a time interval A-4, since a value ("absolute magnitude") of signal (4), which varies according to the fourth linear ramp function, is the highest ("largest") of the plurality of signals (1)-(4), signal (4) can be output by generator 1210. Because only four linear combinations are used, the overall curve of the signal output by generator 1210 can be roughly expressed ("approximated"). However, it is understood that a rough ("approximated") curve of an output value of the signal is associated with a nonlinear curve profile. This nonlinear curve profile can be a Hershey-Kiss profile.

[0042] Fig. Figure 7 is a graph illustrating the overall curve of a Hershey-Kiss signal generated by a nonlinear profile generator in Fig. 4 or Fig. 5 is output. A graph corresponding to the interval A, which is in Fig. Figure 7 illustrates this and can be directly compared to a graph which is in Fig. Figure 6 illustrates this. Furthermore, intervals B, C, and D can correspond to intervals B, C, and D, which are shown in Fig. 3 are illustrated. As in Fig. As illustrated in Figure 7, a signal generated by a Hershey-Kiss profile generator 1210 (“Hershey-Kiss signal”) can have a digital value (“magnitude”) that periodically increases or decreases based on a value “k”. Furthermore, a digital value generated by the Hershey-Kiss profile generator 1210 can be greater than “0”.

[0043] According to some exemplary embodiments of the inventive concepts, each ramp function generator 121-1 to 121-4 can generate a signal which varies four times according to a separate, respective ramp function such that the curve of a signal output by the Hershey-Kiss profile generator 1210 has a complete Hershey-Kiss profile. For example, the first ramp function generator 121-1 can generate a signal which, according to a first ramp function (corresponding to ① and ⑤ in Fig. 7) varies at times t1, t5, t9, and t13. If the first ramp function generator 121-1 generates the signal that varies according to the first ramp function, the fourth ramp function generator 1214 can generate a signal that varies according to a fourth ramp function (corresponding to ④ and ⑧ in Fig. 7) at times t4, t5, t12, and t13. In contrast, the signal generated by the first ramp function generator 121-1 can vary continuously over intervals B and C, and the slope of the first linear ramp function at interval B can be equal to the slope of the first linear ramp function at interval C. Therefore, the first ramp function generator 121-1 can generate a signal that varies at least three times according to a ramp value (i.e., the first linear ramp function).

[0044] After generating a signal with a non-linearly increasing digital value that assumes the Hershey-Kiss profile for interval A, a signal with a non-linearly decreasing digital value that assumes the Hershey-Kiss profile for interval B can be generated. A method in which a plurality of linear ramp functions for an interval B are generated can be similar to a method that, with reference to the Fig. 4, Fig. 5 to Fig. As described in section 6, the ramp function generators 121-1 to 121-4 can each generate a plurality of signals that vary according to separate linear ramp functions at t5. Furthermore, the slopes across the generated signals can differ, and the generation intervals across the generated signals can also differ. For example, the first signal ①, generated by the first ramp function generator 121-1, can vary according to a negative slope with the smallest absolute value. Additionally, the interval during which a signal with a digital value (i.e., the first signal ①) is output can be "t9-t5" and can be the longest. Finally, the signal generated by the fourth ramp function generator 121-4, which varies according to the fourth linear ramp function ④, can vary according to a negative slope with the largest absolute value.Furthermore, an interval during which a signal which outputs a digital value (i.e., signal ④) can be “t6-t5”, and can be the shortest.

[0045] In some exemplary embodiments, a signal with a non-linearly decreasing digital value, which assumes the Hershey-Kiss profile at interval C, can be generated. Referring to Fig. 7. The slope of the first linear ramp function of signal ①, output at interval B, can be equal to the slope of the fifth linear ramp function of signal ⑤, output at interval C. Similarly, the slope of the second linear ramp function of signal ②, output at interval B, can be equal to the slope of the sixth linear ramp function of signal ⑥, output at interval C. The slope of the third linear ramp function of signal ③, output at interval B, can be equal to the slope of the seventh linear ramp function of signal ⑦, output at interval C. The slope of the fourth linear ramp function of signal ④, output at interval B, can be equal to the slope of the eighth linear ramp function of signal ⑧, output at interval C.

[0046] The first ramp function generator 121-1 can generate the signal that varies according to the fifth linear ramp function ⑤, which has a negative slope at time t9. At interval C, the signal that varies according to the fifth linear ramp function ⑤ can be maintained until time t13. The signal that varies according to the fifth linear ramp function ⑤ can have a negative slope whose absolute value is the smallest among the slopes of the signals that vary according to the linear ramp functions generated at interval C, and can be generated earliest.

[0047] When the signal varying according to the fifth linear ramp function ⑤ is generated, at time t12 the fourth ramp function generator 121-4 can generate the signal varying according to the eighth linear ramp function ⑧, which has a negative slope and negative digital values. The signal varying according to the eighth linear ramp function ⑧ can be sustained until time t13. The signal varying according to the eighth linear ramp function ⑧ can have a negative slope whose absolute value is the largest among the slopes of the signals varying according to the linear ramp functions generated at interval C, and can be the last one generated.In some exemplary embodiments, a digital value of a signal which varies according to the eighth linear ramp function ⑧ at time t13 may be the smallest of the digital values ​​of signals generated by a Hershey-Kiss profile generator.

[0048] At interval D, a signal with a non-linearly increasing digital value, exhibiting a Hershey-Kiss profile, can be generated. (Referring to...) Fig. 7. The slope of the first linear ramp function of signal ⑤, output at interval D, can be equal to the slope of the first linear ramp function of signal ①, output at interval A. Similarly, the slope of the sixth linear ramp function of signal ⑥, output at interval D, can be equal to the slope of the second linear ramp function of signal ②, output at interval A. The slope of the seventh linear ramp function of signal ⑦, output at interval D, can be equal to the slope of the third linear ramp function of signal ③, output at interval A. The slope of the eighth linear ramp function of signal ⑧, output at interval D, can be equal to the slope of the fourth linear ramp function of signal (4), output at interval A.A signal output at interval D can have a positive slope, such that the value of the signal increases over time during the time interval D.

[0049] As in Fig. As illustrated in Figure 7, a point in time when a signal varying according to a ramp function is generated, a point in time when the generation of the signal varying according to the ramp function is complete, a slope, and so on can be adjusted to output a signal with a non-linearly increasing digital value. At time interval D, the signals varying according to the fifth to eighth linear ramp functions ⑤ to ⑧ can be generated to have a positive slope at the same time (i.e., time t13). However, an absolute value above the slope of the fifth linear ramp function of signal ⑤ can be the smallest, and an absolute value above the slope of the eighth linear ramp function of signal ⑧ can be the largest.A non-linearly increasing digital value of the signal, which has the Hershey-Kiss profile, can be output by controlling the ramp function generators 121-1 to 121-n to generate signals which have digital values ​​which are illustrated at the time interval D.

[0050] A signal that varies according to a linear ramp function, whose absolute value is greatest around a digital value generated at intervals A to D, can be output by the generator 1210 for a nonlinear profile using the configuration and procedure described above. This means that a digital-value-to-time graph of a signal output by the generator 1210 for a nonlinear profile is similar to the frequency-to-time graph of the Fig. It can be 3. The Delta-Sigma Modulator 1220 (refer to) Fig. 1) can generate the control signal DCTRL using the digital value of the signal output by the generator 1210 for a non-linear profile, and can provide a division ratio of the divider 1150 (reference is made to Fig. 1) Control based on the control signal DCTRL. As a result, the output signal CLK_out, which is output by the phase-locked loop 1100, can have a value that varies according to the non-linear curve profile shown in the frequency-to-time graph of the Fig. 3 is illustrated.

[0051] According to some exemplary embodiments of the invention, a signal with a value that varies according to a nonlinear waveform profile can be generated by combining a plurality of signals that vary according to a plurality of linear ramp functions, thereby implementing a generator for a spread-spectrum clock signal that makes it possible to reduce electromagnetic interference. Furthermore, the nonlinear waveform profile of the signal value can be implemented using a linear combination without the need for a complex circuit or operation, thus enabling a reduction in chip size and an improvement in operating speed.

[0052] Fig. Figure 8 is a block diagram illustrating a generator 2000 for a spread-spectrum clock signal according to some exemplary embodiments of the inventive concepts. A generator 2000 for a spread-spectrum clock signal can include a phase-locked loop 2100 and a generator 2200 for a non-linear profile. As shown in Fig. As shown in Figure 8, the generator 2200 for a nonlinear profile can be a Hershey-Kiss profile generator. The phase-locked loop 2100 can include a phase frequency detector 2110, a charge pump 2120, a loop filter 2130, a voltage-controlled oscillator 2140, a divider 2150, and an OR gate 2160. According to some exemplary embodiments of the inventive concepts, a method is described in which a frequency-to-time graph of the output signal CLK_out assumes a nonlinear curve profile by adjusting a signal 2210 supplied to the charge pump 2120.

[0053] Fig. Figure 9 is a block diagram showing a section of a Generator 2000 for a nonlinear profile, which is in Fig. Figure 8 illustrates this. According to some exemplary embodiments of the inventive concepts, after the phase-locked loop 2100 is locked (i.e., after the output signal CLK_out is stabilized), step pulses 2210, which the generator 2200 produces for a nonlinear profile, can be generated. However, the step pulses 2210 can also be generated before the phase-locked loop 2100 is locked.

[0054] The phase frequency detector 2110 can receive the reference signal CLK_ref and the feedback signal CLK_div, compare a frequency of the reference signal CLK_ref with a frequency of the feedback signal CLK_div, and compare a phase of the reference signal CLK_ref with a phase of the feedback signal CLK_div. If a phase of the reference signal CLK_ref leads a phase of the feedback signal CLK_div, the phase frequency detector 2110 can output an Up signal UP of logic 1 and a Down signal DN of logic 0. Conversely, if a phase of the reference signal CLK_ref lags a phase of the feedback signal CLK_div, the phase frequency detector 2110 can output the Up signal UP of logic 1 and the Down signal DN of logic 1.

[0055] When the phase-locked loop 2100 is locked, the phase-locked loop 2110 can output the up signal UP and the down signal DN, which are output simultaneously and each is composed of short pulses with very short pulse widths. If and / or when there is no or substantially no phase difference between the reference signal CLK_ref and the feedback signal CLK_div, the phase-locked loop 2100 can be locked, and consequently, the output signal CLK_out can be stabilized. At this time, a pulse with a very short width can be output at an interval of a rising edge.

[0056] The OR gate 2160 can have a first OR gate 2162 and a second OR gate 2164. The first OR gate 2162 can perform an OR operation on the input signal UP and the output signal 2210 from the generator 2200 for a nonlinear profile and can output a result UP_OR. A value of a signal that has a high level under the input signal UP and the output signal (for example, one of the step pulses) 2210 of the generator 2200 for a nonlinear profile can be output according to the result of the OR operation. If the phase-locked loop 210 is locked, a value of a signal that has a high level under the step pulses 2210 of the generator 2200 for a nonlinear profile can be output.

[0057] Furthermore, the second OR gate 2164 can perform an OR operation on the down signal DN and the output signal (for example, the step pulse) 2210 from the generator 2200 for a nonlinear signal and can output a result DN_OR. Similarly, the value of a signal that has a high level under the down signal DN and the output signal 2210 of the generator 2200 for a nonlinear profile can be output according to the result of the OR operation. The first OR gate 2162 can be essentially the same as the second OR gate 2164, except that the second OR gate 2164 receives the down signal DN instead of the up signal UP.

[0058] The charge pump 2120 can operate under the control of an output signal UP_OR and DN_OR from the OR gate 2160 and can generate the control current ICTRL. The charge pump 2120 can convert the output signal 2210 of the generator 2200 into a current with a non-linear profile.

[0059] Fig. Figure 10 is a block diagram illustrating a generator 2200 for a nonlinear profile and a first OR gate 2162, which are in Fig. 9 are illustrated. Fig. Figure 11 is a block diagram illustrating a first OR gate 2162, which is used in Fig. 10 is illustrated.

[0060] The generator 2200 for a nonlinear profile can have a plurality of step pulse generators 220-1 to 220-n. Each of the step pulse generators 220-1 to 220-n can generate each of the step pulses SP1 to SPn. The first OR gate 2162 can receive the step pulses SP1 to SPn and the up signal UP and can perform an OR operation with respect to the step pulses SP1 to SPn and the up signal UP.

[0061] A configuration of the first OR gate 2162 according to some exemplary embodiments is shown in Fig. Figure 11 illustrates this. The first OR gate 2162 can have a plurality of OR gates 2162_1 to 2162_(n-1) that receive the step pulses SP1 to SPn and one OR gate 2162_n that receives the UP signal. The UP_OR signal can be output according to the result of the OR operation by the first OR gate 2162. One structure of the first OR gate 2162 is an example. However, the scope and idea of ​​the inventive concepts cannot be limited to this. For example, the first OR gate 2162 can be implemented with different configurations, each of which selectively outputs a value of a signal that has a high level and consists of the step pulses SP1 to SPn and the UP signal UP.

[0062] Fig. Figure 12 is a flowchart illustrating the waveforms of step pulses SP1 to SPn. For simplification, the generator 2200 can have four step pulse generators for a nonlinear profile. It is assumed that the first OR gate 2162 has three OR gates and one OR gate that receives the up signal UP. Pulses a1 to a5, which are placed on the upper line, can correspond to the first step pulses SP1, and the second to fourth step pulses SP2 to SP4 can then be illustrated sequentially.

[0063] The pulse width of each of the first step pulses generated by the first step pulse generator 220-1 can have an increment of Δa. This means that the difference between the pulse widths of two adjacent pulses among the first step pulses can be Δa. Similarly, the pulse widths of two adjacent pulses among the second step pulses generated by the second step pulse generator 220-2 can have a difference of Δb. The pulse widths of two adjacent pulses among the third step pulses generated by the third step pulse generator 220-3 can have a difference of Δc. The pulse widths of two adjacent pulses among the fourth steps generated by the fourth step pulse generator 220-4 can have a difference of Δd. Here, Δa < Δb < Δc < Δd.

[0064] Compared to the first stage pulses, the second stage pulse generator 220-2 can output the second stage pulses, which are delayed by one pulse period. Compared to the second stage pulses, the third stage pulse generator 220-3 can output the third stage pulses, which are delayed by one pulse period. Compared to the third stage pulses, the fourth stage pulse generator 220-4 can output the fourth stage pulses, which are delayed by one pulse period.

[0065] The second pulse, however, generated by each step pulse generator, can have a width that is the widest among the widths of pulses generated at the same timing. For example, the second pulse a2, generated by the first step pulse generator 220-1, can have the widest pulse width among the pulse widths of pulses (i.e., a2 and b1) generated at the same timing. Similarly, the second pulse d2, generated by the fourth step pulse generator 220-4, can have the widest pulse width among the pulse widths of pulses (i.e., a5, b4, c3, and d2) generated at the same time. This is in Fig. 12 illustrated as shaped.

[0066] Fig. Figure 13 is a flowchart illustrating the curve of a first result P_OR, in which an OR operation is performed on an output signal 2210 of a generator 2000 for a nonlinear profile. If an OR operation is performed on the first to fourth stage pulses SP1 to SP4, a pulse with the widest pulse width can be output. The pulses a1, a2, b2, c2, and d2, whose pulse widths increase nonlinearly, can be output as a result. More specifically, the pulse width of pulse a2 can be wider than the pulse width of pulse a1 by Δa. The pulse width of pulse b2 can be wider than the pulse width of pulse a2 by Δb - Δa. The pulse width of pulse c2 can be wider than the pulse width of pulse b2 by Δc - Δb. Ultimately, the pulse width of pulse d2 can be wider than the pulse width of pulse c2 by Δd-Δc.

[0067] As such, voltage pulses whose pulse widths increase non-linearly can pass through the charge pump 2120, the loop filter 2130, and the voltage-controlled oscillator 2140, and can be used to generate a frequency-to-time graph that exhibits a non-linear curve profile. This non-linear curve profile can be a Hershey-Kiss profile.

[0068] The Fig. 14A and Fig. Figure 14B shows block diagrams for describing a procedure in which voltage pulses generated by a step pulse generator are transformed by passing through a phase control loop.

[0069] Fig. Figure 14A illustrates a transformation procedure via first step pulses generated by the first step pulse generator 2201, and Fig. Figure 14B illustrates a transformation procedure using second-step pulses generated by the second-step pulse generator 2202. To differentiate between a processing procedure using the first-step pulses and one using the second-step pulses, an operation can be omitted by means of an OR gate.

[0070] Referring to Fig. Figure 14, which shows the transformation of the first step pulses, shows that the first step pulses SP1, which are generated by the first step pulse generator 2201, can be transformed into the control current ICTRL by the charge pump 2120. At this time, a pulse width can be maintained after the transformation to be the same as that before the transformation.

[0071] As in the Fig. As illustrated in Figure 14A-B, the control current ICTRL can be transformed into a stepped waveform by passing it through the loop filter 2130. The loop filter 2130 can operate as an integrator as well as a low-pass filter, which removes a high-frequency component. Referring to the output waveform of the loop filter 2130, a voltage level with a positive slope can increase at intervals corresponding to intervals where the control current ICTRL level is logic "1", while the slope can be "0" at intervals corresponding to intervals where the control current ICTRL level is logic 0. As shown in the Fig. As illustrated in 14A-B, a curve profile (i.e., a control voltage VCTRL) can be schematically formed.

[0072] However, since a change in the pulse width of each of the second step pulses SP2 is greater than a change in the pulse width of each of the first step pulses SP1, as in Fig. As illustrated in 14A-B, a curve (i.e., a control voltage VCTRL) with a large voltage increase is formed. Even if the output results of the first step pulses SP1 and the second step pulses SP2 are in the Fig. As illustrated in Figures 14A-B, when an OR operation is performed with respect to many voltage pulses, the output result (i.e., the control voltage VCTRL) can schematically assume a nonlinear waveform. This nonlinear waveform can be a Hershey-Kiss profile.

[0073] Fig. Figure 15 is a flowchart illustrating the output curve of a control voltage VCTRL according to some exemplary embodiments of the inventive concepts. One embodiment of the inventive concepts is exemplified in Fig. 15, when step pulses generated by the step pulse generators 2201 to 2204 are processed by the OR gate 2160, the charge pump 2120, and the loop filter 2130, and represented by the processed output result. That is to say that Fig. 15 schematically illustrates a curve progression when pulses which are in Fig. Figure 13 illustrates how the components pass through the OR gate 2160, the charge pump 2120 and the loop filter 2130.

[0074] A solid line can represent the actual waveform of the control voltage VCTRL, which is an output of the loop filter 2130. A dotted line can represent a line connecting the edges of the control voltage VCTRL. Since only four step pulse generators are used, the output voltage waveform will have a nonlinear profile that is relatively coarse ("approximated"). However, as the number of step pulse generators increases, the output voltage waveform will have a relatively smooth, nonlinear profile. A waveform with the following shape can pass through the voltage-controlled oscillator 2140 and be output. Consequently, a frequency-to-time graph of the same shape as a graph in Fig. 15 is illustrated, will be obtained.

[0075] The graph, which is in Fig. As illustrated in 15, an interval A of Fig. 13. The control voltages VCTRL corresponding to each of intervals B, C, and D can be generated using the procedure described above, with appropriate modifications. For example, the control voltages VCTRL having a negative slope can be generated by reducing the pulse widths of pulses produced by each of the step pulse generators. Furthermore, the control voltage VCTRL having a negative value can be generated using an inverter such that pulses produced by each of the step pulse generators have a negative value.

[0076] According to some exemplary embodiments of the inventive concepts, the output signal CLK_out, which adopts a nonlinear Hershey-Kiss profile, can be generated by linearly combining a plurality of pulses, each generated by a plurality of step pulse generators. As described above, since the nonlinear Hershey-Kiss profile can be generated using a linear combination that does not directly generate the nonlinear Hershey-Kiss profile, the circuit configuration can be simplified, thereby reducing the chip area. Furthermore, because a complex operation is no longer necessary, the operating speed can be improved.

[0077] Fig. Figure 16 is a block diagram illustrating a generator 3000 for a spread-spectrum clock signal according to some exemplary embodiments of the inventive concepts. One embodiment of the inventive concepts is shown by way of example where a frequency-to-time graph of the output signal CLK_out assumes a nonlinear waveform profile by directly generating the control voltage VCTRL, which assumes the nonlinear waveform profile, and supplying the generated control voltage VCTRL to the voltage-controlled oscillator 2140. The nonlinear waveform profile can be a Hershey-Kiss profile.

[0078] A generator 3000 for a spread-spectrum clock signal can include a phase-locked loop 3100 and a generator 3200 for a nonlinear waveform. The generator 3200 for a nonlinear waveform can be a Hershey-Kiss profile generator 3200, as shown in Fig. Figure 16 shows that the phase-locked circuit 3100 can comprise a phase frequency detector 3110, a charge pump 3120, a loop filter 3130, a voltage-controlled oscillator 3140, a divider 3150, and a detector 3160. A description that is duplicated with a description given with reference to the embodiment described above may be omitted.

[0079] According to some exemplary embodiments of the inventive concepts, however, the phase-locked loop 3100 can further comprise the detector 3160, which detects whether the phase-locked loop 3100 is locked. The detector 3160 can detect whether the phase-locked loop 3100 is locked, and accordingly, the generator 3200 produces an output signal 3210 for a non-linear profile.

[0080] Fig. 17 is a block diagram illustrating a section of a generator 3000 for a non-linear clock signal, which is in Fig. Figure 16 illustrates that the detector 3160 can receive the reference signal CLK_ref and the feedback signal CLK_div. Although it is illustrated that the detector 3160 receives the reference signal CLK_ref and the feedback signal CLK_div via the phase frequency detector 3110, the detector 3160 can receive the reference signal CLK_ref and the feedback signal CLK_div directly without passing through the phase frequency detector 3110. Furthermore, the detector 3160 can receive the up signal UP and the down signal DN from the phase frequency detector 3110.

[0081] The detector 3160 can determine whether the phase-locked loop 3100 is locked using the four received signals (i.e., the reference signal CLK_ref, the feedback signal CLK_div, the up signal UP, and the down signal DN). For example, if there is no phase difference between the reference signal CLK_ref and the feedback signal CLK_div, and no phase difference between the up signal UP and the down signal DN, this indicates that the phase-locked loop 3100 is locked. At this time, the detector 3160 can control the generator 3200 for a nonlinear profile to produce an output voltage that exhibits a nonlinear waveform.

[0082] Fig. Figure 18 is a block diagram illustrating a generator 3200 for a nonlinear profile, which is in Fig. 16 is illustrated.

[0083] Referring to Fig. 18. For a nonlinear profile, the generator 3200 can have a plurality of ramp voltage generators 321-1 to 321-n and a voltage buffer 3220. The first ramp voltage generator 321-1 can generate a first linear ramp voltage ①, whose voltage slope is the smallest among the plurality of ramp voltages. When the first ramp voltage generator 321-1 generates the first linear ramp voltage ①, the second ramp voltage generator 321-2 can generate a second linear ramp voltage ②, whose voltage slope (rate of change of the magnitude of the linear ramp voltage over time) is greater than the voltage slope of the first linear ramp voltage ①. The generation time ("initiation time value") of the second linear ramp voltage ② lags behind the generation time of the first linear ramp voltage ①.Ultimately, the nth ramp voltage generator 321-n can generate an nth linear ramp voltage ⓝ whose voltage slope is the largest among a plurality of linear ramp voltages. However, the time of generation of the nth linear ramp voltage ⓝ can be the latest.

[0084] The voltage buffer 3220 can receive a plurality of linear ramp voltages and can selectively output a voltage which has a magnitude which is the largest of the magnitudes of the linear ramp voltages which are output by the generators 321-1 to 321-n.

[0085] Fig. Figure 19 is a block diagram illustrating a generator 3200 for a nonlinear profile, which is in Fig. Figure 18 illustrates this. The voltage buffer 3220 can comprise a plurality of voltage followers 322-1, 322-n, each connected to a plurality of ramp voltage generators 321-1 to 321-n. Each voltage follower can maintain a level of a voltage received from the corresponding ramp voltage generator. As a result, a voltage whose absolute value is the largest among a plurality of linear ramp voltages can be selectively output. An embodiment of the inventive concepts is shown by way of example, where the voltage followers 322-1 to 322-n are considered an embodiment of the voltage buffer 3220, which is in Fig. Figure 18 illustrates how the inventive concepts can be used. However, the scope and intent of the inventive concepts cannot be limited thereto. For example, the voltage buffer 3220 can be implemented with different configurations, each of which maintains a constant level of a voltage supplied by each of the ramp voltage generators and can selectively output the voltage.

[0086] Fig. Figure 20 is a block diagram showing the output voltage of a 3200 generator for a non-linear profile, which is in Fig. 18 or Fig. Figure 19 illustrates this. It is assumed that six ramp voltage generators are used. For two linear ramp voltages (for example, a linear ramp voltage ② and a linear ramp voltage ③) generated at an interval (for example, from a time of generation of linear ramp voltage (2) to a time of generation of linear ramp voltage ③), a rate of change of linear ramp voltage ②, which is generated earlier than linear ramp voltage ③, can be smaller than a rate of change of linear ramp voltage ③.

[0087] The graph, which is in Fig. As illustrated in 20, this can correspond to an interval A, which in Fig. Figure 3 illustrates this. A voltage corresponding to each of the remaining intervals B, C, and D, exhibiting a nonlinear waveform, can be generated by controlling the ramp voltage generators such that the linear ramp voltage produced by each ramp voltage generator has a negative rate of change, or by controlling the ramp voltage generators such that the linear ramp voltage has a negative voltage level. The nonlinear waveform can be a Hershey-Kiss profile. A voltage exhibiting the nonlinear waveform can pass through the voltage-controlled oscillator 3140, ultimately generating the output signal CLK_out, which also exhibits the nonlinear waveform.

[0088] According to some exemplary embodiments of the inventive concepts, an output signal exhibiting a nonlinear waveform can be obtained using a combination of linear ramp voltages. Since the nonlinear waveform can be generated using a linear combination, rather than directly generating the nonlinear waveform, the circuit configuration can be simplified, thereby reducing the chip area. Furthermore, the operating speed of a generator for a spread-spectrum clock signal can be improved.

[0089] Fig. Figure 21 is a block diagram showing a solid-state drive (SSD) 4000 according to some exemplary embodiments of the inventive concepts. Referring to Fig. 21. An SSD 4000 can have a controller 4100 which has a generator 4110 for a spread-spectrum clock signal according to some exemplary embodiments of the inventive concepts. In addition, the SSD 4000 can have a plurality of non-volatile memories 4200 and the buffer 4300.

[0090] The Controller 4100 can establish a physical connection between a host and the SSD 4000. This means that the Controller 4100 can connect to the SSD 4000 in accordance with the host's bus format. Specifically, the Controller 4100 can decode commands issued by the host. Based on the decoded commands, the Controller 4100 can access the non-volatile memory 4200. The host's bus format can be Universal Serial Bus (USB), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), Advanced Technology Attachment (ATA), Parallel ATA (PTA), Serial ATA (SATA), or Serial Attached SCSI (SAS).

[0091] The controller 4100 can include the spread-spectrum clock signal generator 4110 according to some exemplary embodiments of the inventive concepts. The spread-spectrum clock signal generator 4110 can generate clock signals ("clock signals") that have a non-linear waveform profile and whose frequency is changed non-linearly using a plurality of linear combinations. The clock signals generated by the spread-spectrum clock signal generator 4110 can be used to couple with the host or the non-volatile memory 4200. As a result, an EMI phenomenon can be reduced, thereby improving the reliability of the SSD 4000.

[0092] The non-volatile memory 4200 can be configured as a storage medium for the SSD 4000. For example, the non-volatile memory 4200 can be configured as a high-capacity NAND flash memory. The non-volatile memory 4200 can comprise multiple storage devices. In this case, each storage device can be connected to the controller 4100 via a channel. One embodiment of the inventive concepts is illustrated by way of example, where the non-volatile memory 4200 is implemented with NAND flash memory as the storage medium. However, the scope and intent of the inventive concepts are not limited to this. For example, the non-volatile memory 4200 can be implemented with other non-volatile storage devices.This means that the storage medium of the non-volatile memory 4200 can be implemented with a phase-change random access memory (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (RiRAM), a ferroelectric RAM (FRAM), a NOR flash memory, and the like, and a storage system which has different types of storage devices can be used as the storage medium of the non-volatile memory 4200.

[0093] Write data intended for the host, or data read from the non-volatile memory 4200, can be temporarily stored in buffer 4300. Buffer 4300 can be a synchronous dynamic random access memory (SDRAM) to provide sufficient buffering for the SSD 4000, which is used as a high-capacity auxiliary storage device. However, it is obvious to experts that buffer 4300 is not limited to this.

[0094] Fig. Figure 22 is a block diagram illustrating a mobile device 3000 to which the inventive concept is applied. Referring to Fig.22. A mobile device 5000 can be configured to support a Mobile Industrial Processor Interface (MIPI) standard or an Embedded DisplayPort (EDP) standard. The mobile device 5000 can include an application processor 5100, a display unit 5200, a vision unit 5300, a data storage unit 5400, a wireless transceiver unit 5500, and a user interface 5600.

[0095] The application processor 5100 can control the overall operation of the mobile device 5000. The application processor 5100 can include a spread-spectrum clock signal generator 5110 according to some exemplary embodiments of the inventive concepts. The spread-spectrum clock signal generator 5110 can generate clock signals that exhibit a nonlinear waveform profile and whose frequency is varied nonlinearly using a plurality of linear combinations. The clock signals generated by the spread-spectrum clock signal generator 5110 can be used in various ways on the mobile devices 5000. For example, the clock signals generated by the spread-spectrum clock signal generator 5110 can be used for operation on the application processor 5100.The clock signals generated by the 5110 spread-spectrum clock generator can be used to couple with the 5400 data storage device. The clock signals generated by the 5110 spread-spectrum clock generator can also be used to operate the 5210 display panel.

[0096] The 5200 display unit can include the 5210 display panel and a 5220 serial display interface (DSI) peripheral circuit. The 5210 display panel can display image data. A DSI host mounted on the 5100 application processor can establish serial communication with the 5210 display panel via a DSI. The 5220 DSI peripheral circuit can include a timing controller, a data driver, and other components required to operate the 5210 display panel.

[0097] The 5300 data processing unit can include a 5310 camera module and a 5320 camera serial interface (CSI) peripheral circuit. The 5300 image processing unit can include a lens, an image sensor, an image processor, and the like. Image data generated by the 5310 camera module can be processed by the image processor, and the processed image can be transmitted to the 5100 application processor via a CSI.

[0098] The 5400 data storage unit can include an embedded Universal Flash Storage (UFS) unit 5410 and a removable UFS card 524. The embedded UFS unit 5410 and the removable UFS card 5420 can communicate with the 5100 application processor via an M-PHY layer. Meanwhile, a host (i.e., the 5100 application processor) can have a bridge to communicate with the removable UFS card 5420 using a protocol other than a UFS protocol. The 5100 application processor and the 5420 removable UFS card can communicate with each other using various card protocols (for example, a Universal Serial Bus (USB) Flash Drive (UFD), a Multimedia Card (MMC), an embedded Multimedia Card (eMMC), a Secure Digital (SD), a Mini SD, a Micro SD, and the like).The embedded UFS memory 5410 and the removable UFS card 5420 can be implemented with a three-dimensional non-volatile storage device in which a cell strand of memory cells is formed to be perpendicular to a substrate.

[0099] A wireless transceiver unit 5500 can comprise an antenna 5510, a radio frequency (RF) unit 5520, and a modulator-demodulator (modem) 5530. One embodiment of the inventive concepts is shown by way of example as the modem 5530, which communicates with the application processors 5100 via an M-PHY layer. However, the scope and intent of the inventive concepts are not limited to this. For example, the modem 5530 can be contained within the application processor 5100.

[0100] The generator for a spread-spectrum clock signal according to some exemplary embodiments of the inventive concepts can generate clock signals whose frequency is changed non-linearly and which assume a non-linear curve profile using a plurality of linear combinations.

[0101] Although detailed embodiments of inventive concepts have been described, it should be understood that various other modifications, changes, variations, and substitutions can be devised by those skilled in the art. Furthermore, it should be understood that the inventive concepts encompass various techniques which can be easily modified and implemented based on the embodiments described above.

Claims

[1] Generators (1000, 2000, 3000, 4110, 5110) for a nonlinear spread spectrum clock signal, which has the following: a phase detector which is configured to to receive a reference signal and a feedback signal, to detect a phase difference between the reference signal and the feedback signal, and to output an up signal and a down signal according to the detected phase difference; a charge pump (1120, 2120, 3120) which is configured to to receive the up signal and the down signal, and to output a control current according to the up signal and the down signal; a loop filter (1130, 2130, 3130) which is configured to to receive the control current, and to output a control voltage according to the control current; a generator (1210, 2200, 3200) for a nonlinear profile, which is configured to to generate a plurality of voltage signals, each with separate magnitudes, which vary according to separate linear ramp functions, each of which has separate slopes and initiation time values, and to selectively output a linear ramp voltage signal, wherein the selectively output linear ramp voltage signal has a largest absolute value among the majority of voltage signals, such that the selectively output ramp voltage signal approximates a voltage signal which has a nonlinear profile curve; and a voltage-controlled oscillator (1140, 2140, 3140) configured to to receive the control voltage and the selectively output linear ramp voltage, and to output a signal according to the control voltage and the selectively output linear ramp voltage. [2] Generators (1000, 2000, 3000, 4110, 5110) for a nonlinear spread spectrum clock signal according to claim 1, wherein the generator (1210, 2200, 3200) for a nonlinear profile is a Hershey-Kiss profile generator (1210, 3200) configured to selectively output the linear ramp voltage signal, wherein the selectively output linear ramp voltage signal has a largest absolute size of the majority of the voltage signals such that the selectively output linear ramp voltage signal approximates a voltage signal which has a Hershey-Kiss profile curve; and The Hershey-Kiss profile generator (1210, 3200) is further configured to generate a first voltage signal according to a first linear ramp function, wherein the first linear ramp function has a first slope, and to generate a second voltage signal according to a second linear ramp function, wherein the second linear ramp function has a second slope, wherein the second voltage signal is generated following the generation of the first voltage signal, the second slope having a larger absolute value than an absolute value of the first slope. [3] Generators (1000, 2000, 3000, 4110, 5110) for a nonlinear spread spectrum clock signal according to claim 2, wherein the Hershey Kiss profile generator (1210, 3200) comprises: a first generator (321-1) for a linear ramp voltage, which is configured to generate the first voltage signal; a second generator (321-2) for a linear ramp voltage, which is configured to generate the second voltage signal; and a voltage buffer (3220) which is configured to output a selected voltage signal of the first voltage signal and the second voltage signal, wherein the selected voltage signal has a largest absolute value of the first voltage signal and the second voltage signal. [4] Generators (1000, 2000, 3000, 4110, 5110) for a nonlinear spread spectrum clock signal according to claim 3, wherein the voltage buffer (3220) comprises: a first voltage follower (322-1) configured to receive the first voltage signal; and a second voltage follower (322-2) which is configured to receive the second voltage signal. [5] Generators (1000, 2000, 3000, 4110, 5110) for a nonlinear spread spectrum clock signal according to claim 2, wherein the Hershey-Kiss profile generator (1210, 3200) is configured to to generate a third voltage signal according to a third linear ramp function, wherein a third voltage signal generation initiation is simultaneous with the first voltage signal generation setting, wherein the third linear ramp function has a third slope, wherein the third slope has an absolute value equal to the absolute value of the first slope, and wherein the third slope has an opposite sign relative to the first slope; and to generate a fourth voltage signal according to a fourth linear ramp function, wherein a fourth voltage signal generation initiation is simultaneous with the second voltage signal generation setting, wherein the fourth linear ramp function has a fourth slope, wherein the fourth slope has an absolute value equal to the absolute value of the second slope, and wherein the fourth slope has an opposite sign relative to the second slope. [6] Generators (1000, 2000, 3000, 4110, 5110) for a nonlinear spread spectrum clock signal according to claim 5, wherein the Hershey Kiss profile generator (1210, 3200) is configured to set a fourth voltage signal generation before setting a third voltage signal generation. [7] Generators (1000, 2000, 3000, 4110, 5110) for a nonlinear spread spectrum clock signal according to claim 2, further comprising: a detector which is configured to to receive the up signal, the down signal, the reference signal, and the output signal, and to determine whether a phase-locked loop (1100, 2100, 3100) is locked according to the up signal, the down signal, the reference signal and the output signal, wherein the phase-locked loop (1100, 2100, 3100) includes the phase frequency detector, the charge pump (1120, 2120, 3120), the loop filter (1130, 2130, 3130) and the voltage-controlled oscillator (1140, 2140, 3140). [8] Generators (1000, 2000, 3000, 4110, 5110) for a nonlinear spread spectrum clock signal according to claim 7, wherein the Hershey-Kiss profile generator (1210, 3200) is configured to generate the first voltage signal and the second voltage signal based on a determination that the phase control loop (1100, 2100, 3100) is locked. [9] Device comprising the following: a generator (1210, 2200, 3200) for a nonlinear profile, which is configured to to generate a plurality of signals, wherein the signals have separate magnitudes which vary according to separate linear ramp functions, wherein the separate linear ramp functions have different slopes and different initiation time values; and to output a non-linear signal which has a magnitude that varies according to a largest absolute magnitude of the majority of signals such that the output non-linear signal has a curve that approximates a non-linear curve profile. [10] Device according to claim 9, wherein the generator (1210, 2200, 3200) for a nonlinear profile is a Hershey-Kiss profile generator (1210, 3200) configured to output the nonlinear signal which has a magnitude which varies according to a largest absolute magnitude of the plurality of signals such that the output nonlinear signal is a Hershey-Kiss signal which has a curve which approximates a Hershey-Kiss profile. [11] Device according to claim 10, wherein the Hershey Kiss profile generator (1210, 3200) comprises: a plurality of ramp function generators (121-1 to 121-n) for a linear ramp function, configured to generate separate signals from the plurality of signals; and a digital multiplexer (1218) which is configured to output a selected signal from the plurality of signals as the Hershey-Kiss signal based on the selected signal which has the largest absolute size of the plurality of signals. [12] Device according to claim 11, wherein the digital multiplexer (1218) comprises: a plurality of comparators (1218_1 to 1218_n) which is configured to each receive separate signals from the plurality of signals. [13] Device according to claim 10, wherein the Hershey-Kiss profile generator (1210, 3200) is configured to set the generation of at least one signal of the plurality of signals simultaneously with the initiation of the generation of another signal of the plurality of signals. [14] Device according to claim 10, further comprising: a phase-locked loop (1100, 2100, 3100) which is configured to generate an output signal according to a received reference signal and the Hershey-Kiss signal, wherein the phase-locked loop (1100, 2100, 3100) has: a divider (1150, 2150, 3150) configured to generate a feedback signal based on dividing the output signal by a division ratio; and A division ratio controller (1200) is configured to control the division ratio according to the Hershey-Kiss signal. [15] Device according to claim 14, wherein the phase control loop (1100, 2100, 3100) further comprises a phase detector configured to receive the reference signal and the feedback signal, to detect a phase difference between the reference signal and the feedback signal, and to generate an up signal and a down signal according to the detected phase difference; a charge pump (1120, 2120, 3120) configured to receive the up signal and the down signal, and to generate a control current based on the up signal and the down signal; a loop filter (1130, 2130, 3130) configured to receive the control current, and to output a control voltage based on the control current; and a voltage-controlled oscillator (1140, 2140, 3140) configured to to receive the control voltage, and to generate the output signal based on the control voltage.

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