Low temperature drift low offset rc oscillator
By designing a low-temperature drift, low-offset RC oscillator, the temperature change is offset by using a reference source circuit and a common comparator circuit to eliminate comparator hysteresis error, thus solving the problem of RC oscillator frequency changing with temperature and achieving stability of the output clock frequency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHENGDU SINO MICROELECTRONICS TECH CO LTD
- Filing Date
- 2022-12-27
- Publication Date
- 2026-06-05
AI Technical Summary
The frequency of existing RC oscillators is greatly affected by power supply voltage and ambient temperature, resulting in frequency variations that cannot meet the clock frequency requirements of high-precision systems.
A low-temperature drift, low-offset RC oscillator is used, with reference current and voltage provided by a reference source circuit. Combined with a capacitor oscillator and comparator using a shared comparator circuit and discharge switch, the circuit structure is symmetrical and temperature changes are offset, thus eliminating comparator hysteresis error.
The oscillator output clock frequency is essentially unaffected by temperature, achieving low temperature drift and low offset, thus meeting the requirements of high-precision systems.
Smart Images
Figure CN115955195B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to an RC oscillator. Background Technology
[0002] Oscillators are an essential component of electronic systems, providing accurate clock signals to chips. RC oscillators are widely used due to their simple structure and ease of integration. However, the clock frequency of existing RC oscillators is affected by power supply voltage or ambient temperature, resulting in significant frequency variations. This makes ring oscillators unsuitable for the high-precision clock frequency requirements of systems.
[0003] In existing technologies, the frequency of an RC oscillator is usually determined by the capacitance, charging current, and switching voltage. The temperature drift of the integrated capacitor is generally small, while the charging current and switching voltage are generally generated by a reference voltage source. Although the reference voltage and reference current generated by the reference source may have good temperature coefficients, they are mostly near room temperature. With temperature changes, the temperature drift caused by the quadratic coefficient cannot be ignored. In particular, the temperature change curves of the reference voltage and current are usually inconsistent, causing the frequency to change with temperature. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a low-temperature drift, low-offset RC oscillator whose output clock frequency is basically unaffected by temperature.
[0005] The technical solution adopted by the present invention to solve the aforementioned technical problem is a low-temperature drift, low-offset RC oscillator, including a reference source circuit, wherein the reference source circuit includes a reference current signal output terminal and a reference voltage output terminal, characterized in that it further includes:
[0006] A common comparator circuit is used, the input of which is connected to the reference voltage output of the reference source circuit to provide a comparison reference level.
[0007] A first capacitor oscillator with a discharge switch has its current signal input terminal connected to the reference current signal output terminal of a reference source circuit, and its oscillation voltage output terminal connected to a first comparator.
[0008] The second capacitor oscillator with a discharge switch has its current signal input terminal connected to the reference current signal output terminal of the reference source circuit, and its oscillation voltage output terminal connected to the second comparator.
[0009] The first comparator has its first level input terminal connected to the output terminal of the first capacitor oscillator, and its second level input terminal connected to the output terminal of the common comparator circuit.
[0010] The second comparator has its first-level input terminal connected to the output terminal of the second capacitor oscillator, and its second-level input terminal connected to the output terminal of the common comparator circuit.
[0011] An RS flip-flop has its first input connected to the output of a first comparator, its second input connected to the output of a second comparator, its first output connected to the discharge switch control terminal of a first capacitor oscillator, and its second output connected to the discharge switch control terminal of a second capacitor oscillator.
[0012] The reference source circuit includes a first operational amplifier, a first PMOS transistor, a first PNP transistor, a first NMOS transistor, a first resistor, and a first bias current source;
[0013] The first resistor, the first NMOS transistor, and the first PMOS transistor are connected in series between ground and power supply. The gate and drain of the first PMOS transistor are shorted. The first PNP transistor and the bias current source are connected in series between ground and power supply. The base and collector of the first PNP transistor are shorted. The output terminal of the first operational amplifier is connected to the gate of the first NMOS transistor, the non-inverting input terminal is connected to the emitter of the first PNP transistor, and the inverting input terminal is connected to the source of the first NMOS transistor. The drain of the first PMOS transistor is connected to the reference current signal output terminal, and the non-inverting input terminal of the first operational amplifier is connected to the reference voltage output terminal.
[0014] The first capacitor oscillator consists of a second NMOS transistor, a second PMOS transistor, and a first capacitor. The gate of the second PMOS transistor is connected to the reference current signal output terminal, the source is connected to a high level, and the drain is grounded through the first capacitor as the oscillation voltage output terminal. The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, the source is grounded, and the gate is used as the discharge switch control terminal.
[0015] The second capacitor oscillator consists of a third NMOS transistor, a third PMOS transistor, and a second capacitor. The gate of the third PMOS transistor is connected to the reference current signal output terminal, the source is connected to a high level, and the drain serves as the oscillation voltage output terminal and is grounded through the second capacitor. The drain of the third NMOS transistor is connected to the drain of the third PMOS transistor, the source is grounded, and the gate serves as the discharge switch control terminal.
[0016] The common comparator circuit includes a fourth NMOS transistor, a fourth PMOS transistor, and a second bias current source. The source of the fourth PMOS transistor is connected to a high level, and its gate and drain are connected together. The drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor. The gate serves as the input terminal, and the drain serves as the output terminal and is grounded through the second bias current source.
[0017] The first comparator consists of a fifth NMOS transistor and a fifth PMOS transistor. The gate of the fifth PMOS transistor is connected to the drain of the fourth PMOS transistor, the source is connected to a high level, and the drain serves as the output terminal. The drain of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor, the gate is connected to the output terminal of the first capacitor oscillator, and the source is connected to the output terminal of the common comparator circuit.
[0018] The second comparator consists of a sixth NMOS transistor and a sixth PMOS transistor. The gate of the sixth PMOS transistor is connected to the drain of the fourth PMOS transistor, the source is connected to a high level, and the drain serves as the output terminal. The drains of the sixth NMOS transistor and the sixth PMOS transistor are connected, the gate is connected to the output terminal of the second capacitor oscillator, and the source is connected to the output terminal of the common comparator circuit.
[0019] The first, second, and third PMOS transistors are of the same size. The first and second capacitors have the same capacitance value.
[0020] This invention cancels out the temperature changes of the reference current and reference voltage, so that the output clock frequency of the oscillator circuit remains basically unchanged with temperature. The oscillator circuit structure is symmetrical, eliminating the error in clock frequency caused by comparator hysteresis. Attached Figure Description
[0021] Figure 1 This is a schematic diagram of the present invention.
[0022] Figure 2 This is a schematic diagram of a specific embodiment of the present invention;
[0023] Figure 3 This is a waveform diagram of the positive terminals of the first and second capacitors of the present invention.
[0024] Explanation of the symbols in the attached diagram:
[0025] Ibias1 - First bias current source, Ibias2 - Second bias current source, C1 - First capacitor, C2 - Second capacitor, OP1 - First operational amplifier, MN1 - First NMOS transistor, MN2 - Second NMOS transistor, MN3 - Third NMOS transistor, MN4 - Fourth NMOS transistor, MN5 - Fifth NMOS transistor, MN6 - Sixth NMOS transistor, MP1 - First PMOS transistor, MP2 - Second PMOS transistor, MP3 - Third PMOS transistor, MP4 - Fourth PMOS transistor, MP5 - Fifth PMOS transistor, MP6 - Sixth PMOS transistor, Q1 - First PNP transistor, R1 - First resistor, V REF -Reference voltage, I REF - Reference current, V C1 - Voltage at the positive terminal of C1, V C2 -C2 positive terminal voltage, CLK- output clock signal, T CLK -CLK clock cycle. Detailed Implementation
[0026] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. For ease of comparison with the drawings, the device will sometimes be represented by only the reference numerals in the drawings, for example, "MP2" will be used to represent "second PMOS transistor MP2".
[0027] See Figure 1 The low-temperature drift, low-offset RC oscillator of the present invention includes a reference source circuit, wherein the reference source circuit includes a reference current signal output terminal and a reference voltage output terminal, characterized in that it further includes:
[0028] A common comparator circuit is used, the input of which is connected to the reference voltage output of the reference source circuit to provide a comparison reference level.
[0029] A first capacitor oscillator with a discharge switch has its current signal input terminal connected to the reference current signal output terminal of a reference source circuit, and its oscillation voltage output terminal connected to a first comparator.
[0030] The second capacitor oscillator with a discharge switch has its current signal input terminal connected to the reference current signal output terminal of the reference source circuit, and its oscillation voltage output terminal connected to the second comparator.
[0031] The first comparator has its first level input terminal connected to the output terminal of the first capacitor oscillator, and its second level input terminal connected to the output terminal of the common comparator circuit.
[0032] The second comparator has its first-level input terminal connected to the output terminal of the second capacitor oscillator, and its second-level input terminal connected to the output terminal of the common comparator circuit.
[0033] An RS flip-flop has its first input connected to the output of a first comparator, its second input connected to the output of a second comparator, its first output connected to the discharge switch control terminal of a first capacitor oscillator, and its second output connected to the discharge switch control terminal of a second capacitor oscillator.
[0034] The reference source circuit includes a first operational amplifier, a first PMOS transistor, a first PNP transistor, a first NMOS transistor, a first resistor, and a first bias current source;
[0035] The first resistor, the first NMOS transistor, and the first PMOS transistor are connected in series between ground and power supply. The gate and drain of the first PMOS transistor are shorted. The first PNP transistor and the bias current source are connected in series between ground and power supply. The base and collector of the first PNP transistor are shorted. The output terminal of the first operational amplifier is connected to the gate of the first NMOS transistor, the non-inverting input terminal is connected to the emitter of the first PNP transistor, and the inverting input terminal is connected to the source of the first NMOS transistor. The drain of the first PMOS transistor is connected to the reference current signal output terminal, and the non-inverting input terminal of the first operational amplifier is connected to the reference voltage output terminal.
[0036] The first capacitor oscillator consists of a second NMOS transistor, a second PMOS transistor, and a first capacitor. The gate of the second PMOS transistor is connected to the reference current signal output terminal, the source is connected to a high level, and the drain is grounded through the first capacitor as the oscillation voltage output terminal. The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, the source is grounded, and the gate is used as the discharge switch control terminal.
[0037] The second capacitor oscillator consists of a third NMOS transistor, a third PMOS transistor, and a second capacitor. The gate of the third PMOS transistor is connected to the reference current signal output terminal, the source is connected to a high level, and the drain serves as the oscillation voltage output terminal and is grounded through the second capacitor. The drain of the third NMOS transistor is connected to the drain of the third PMOS transistor, the source is grounded, and the gate serves as the discharge switch control terminal.
[0038] The common comparator circuit includes a fourth NMOS transistor, a fourth PMOS transistor, and a second bias current source. The source of the fourth PMOS transistor is connected to a high level, and its gate and drain are connected together. The drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor. The gate serves as the input terminal, and the drain serves as the output terminal and is grounded through the second bias current source.
[0039] The first comparator consists of a fifth NMOS transistor and a fifth PMOS transistor. The gate of the fifth PMOS transistor is connected to the drain of the fourth PMOS transistor, the source is connected to a high level, and the drain serves as the output terminal. The drain of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor, the gate is connected to the output terminal of the first capacitor oscillator, and the source is connected to the output terminal of the common comparator circuit.
[0040] The second comparator consists of a sixth NMOS transistor and a sixth PMOS transistor. The gate of the sixth PMOS transistor is connected to the drain of the fourth PMOS transistor, the source is connected to a high level, and the drain serves as the output terminal. The drains of the sixth NMOS transistor and the sixth PMOS transistor are connected, the gate is connected to the output terminal of the second capacitor oscillator, and the source is connected to the output terminal of the common comparator circuit.
[0041] The first, second, and third PMOS transistors are of the same size. The first and second capacitors have the same capacitance value. Example
[0042] To improve the problem of frequency drift with temperature, the oscillator provided by this invention includes a reference source circuit and an oscillator circuit, such as... Figure 2 As shown.
[0043] The reference source circuit outputs a reference current signal I. REF and reference voltage V REF The oscillator circuit consists of two identical capacitor charging and discharging oscillation circuits.
[0044] The reference source circuit includes a first operational amplifier OP1, a first PMOS transistor MP1, a first PNP transistor Q1, a first NMOS transistor MN1, a first resistor R1, and a first bias current source Ibias1;
[0045] The first resistor R1, the first NMOS transistor MN1, and the first PMOS transistor MP1 are connected in series between ground and power supply. The first PNP transistor Q1 and the first bias current source Ibias1 are connected in series between ground and power supply. The gate and drain of MP1 are shorted, and the base and collector of Q1 are shorted. The output of the first operational amplifier OP1 is connected to the gate of MN1, and the positive and negative inputs are connected to the emitter of Q1 and the source of MN1, respectively. The current flowing through MP1 is the reference current I. REF The emitter voltage of Q1 is the reference voltage V. REF .
[0046] Therefore, the reference voltage
[0047] (Equation 1)
[0048] Among them, V BE1 It is the base-emitter voltage of Q1.
[0049] OP1, MN1, and R1 form a negative feedback loop. Based on the principle of virtual short voltage at the positive and negative input terminals of the operational amplifier, the voltages at the two input terminals of OP1 are the same. Therefore, the current flowing through R1...
[0050] (Equation 2)
[0051] The current flowing through MP1 and R1 is the same, therefore the reference current I is... REF
[0052] (Equation 3)
[0053] The oscillator circuit comprises two identical capacitor charging / discharging oscillation circuits. The first circuit consists of a second NMOS transistor MN2, a second PMOS transistor MP2, and a first capacitor C1. The second circuit consists of a third NMOS transistor MN3, a third PMOS transistor MP3, and a second capacitor C2. The dimensions of MP1, MP2, and MP3 are in a 1:1:1 ratio, and they are current mirrors; therefore, the current flowing through MP2 and MP3 is equal to I. REF .
[0054] MP2 and MN2 charge and discharge C1 respectively, with the charging current being I. REF During discharge, MN2 is in the linear region, and the voltage at the positive terminal of C1 drops rapidly to ground. MP3 and MN3 charge and discharge C2 respectively, with a charging current of I. REFDuring discharge, MN3 is in the linear region, and the voltage at the positive terminal of C2 drops rapidly to ground.
[0055] The first comparator and the second comparator share a common comparator circuit.
[0056] The first comparator consists of the fifth NMOS transistor MN5 and the fifth PMOS transistor MP5, the second comparator consists of the sixth NMOS transistor MN6 and the sixth PMOS transistor MP6, and the common comparator circuit includes the fourth NMOS transistor MN4, the fourth PMOS transistor MP4, and the second bias current source Ibias2; the first comparator and the common comparator circuit form a differential single-stage amplifier COMP1, with the positive and negative input terminals connected to V respectively. REF The positive terminal of C1, the second comparator, and the common comparator circuit form a differential single-stage amplifier COMP2, with the positive and negative input terminals connected to V respectively. REF and the positive end of C2.
[0057] The present invention also includes an RS flip-flop composed of a first NAND gate NAND1 and a second NAND gate NAND2, used to control the alternating charging and discharging of the two capacitor charging and discharging oscillation circuits. The charging and discharging process is as follows: when the first capacitor C1 is charged with I... REF When the current charges, the second capacitor C2 discharges rapidly to ground through MN3; when the voltage V at the positive terminal of C1... C1 achieve VREF Afterwards, the drain output of MN5 goes low, the output level of the RS flip-flop toggles and feeds back to turn on MN2, allowing C1 to discharge quickly to ground, while simultaneously turning off MN3. REF The current charges C2; when the voltage V at the positive terminal of C2... C2 Reaching V REF Afterwards, the drain output of MN6 goes low, the output level of the RS flip-flop toggles and feeds back to turn on MN3, allowing C2 to discharge quickly to ground, while simultaneously turning off MN2. REF The current charges capacitor C1; this process repeats continuously, generating the output clock CLK. The sum of the charging times of capacitors C1 and C2 is the clock period of CLK. C1 and V C2 The voltage waveform is as follows Figure 3 As shown.
[0058] C1 is charged from ground voltage to V. REF Time T C1 for
[0059] (Equation 4)
[0060] C2 is charged from ground voltage to V. REF Time T C2 for
[0061] (Equation 5)
[0062] Therefore, the clock period T of CLK CLK for
[0063] (Equation 6)
[0064] Preferably, capacitors C1 and C2 are identical, both having a capacitance value of C. Substituting equations 1 and 3 into equation 6, we obtain...
[0065] (Equation 7)
[0066] As can be seen from Equation 7, V REF and I REF The effects are canceled out; the oscillator's output clock is no longer related to the reference voltage and reference current, but only to the capacitor and resistor. Resistor R1 can be canceled out by a resistor with the opposite temperature coefficient, and capacitor C can be a metal-oxide-metal (MOM) capacitor with an extremely small temperature coefficient. Therefore, the oscillator's output clock frequency can remain essentially unchanged with temperature, achieving the function of low-temperature drift and low-offset.
[0067] The structure of the first and second comparators sharing the same comparator circuit allows for good matching of the differential input transistors MN4, MN5, and MN6, reducing comparator offset errors. In addition, the combination of comparators COMP1 and COMP2 with logic circuits NAND1 and NAND2 is designed as a completely symmetrical structure, eliminating the error in oscillation frequency caused by comparator path hysteresis.
[0068] The foregoing description is a preferred embodiment of the present invention. In the embodiment, the PNP transistor Q1 that generates the reference voltage and reference current source can also be replaced with an NPN transistor or an NMOS transistor, and the same effect of the present invention can be achieved.
Claims
1. A low-temperature drift, low-offset RC oscillator, comprising a reference source circuit, said reference source circuit including a reference current signal output terminal and a reference voltage output terminal, characterized in that, Also includes: A common comparator circuit is used, the input of which is connected to the reference voltage output of the reference source circuit to provide a comparison reference level. A first capacitor oscillator with a discharge switch has its current signal input terminal connected to the reference current signal output terminal of a reference source circuit, and its oscillation voltage output terminal connected to a first comparator. The second capacitor oscillator with a discharge switch has its current signal input terminal connected to the reference current signal output terminal of the reference source circuit, and its oscillation voltage output terminal connected to the second comparator. The first comparator has its first level input terminal connected to the output terminal of the first capacitor oscillator, and its second level input terminal connected to the output terminal of the common comparator circuit. The second comparator has its first-level input terminal connected to the output terminal of the second capacitor oscillator, and its second-level input terminal connected to the output terminal of the common comparator circuit. An RS flip-flop has its first input terminal connected to the output terminal of a first comparator, its second input terminal connected to the output terminal of a second comparator, its first output terminal connected to the discharge switch control terminal of a first capacitor oscillator, and its second output terminal connected to the discharge switch control terminal of a second capacitor oscillator. The reference source circuit includes a first operational amplifier, a first PMOS transistor, a first PNP transistor, a first NMOS transistor, a first resistor, and a first bias current source; The first resistor, the first NMOS transistor, and the first PMOS transistor are connected in series between ground and power supply. The gate and drain of the first PMOS transistor are shorted. The first PNP transistor and the bias current source are connected in series between ground and power supply. The base and collector of the first PNP transistor are shorted. The output terminal of the first operational amplifier is connected to the gate of the first NMOS transistor, the non-inverting input terminal is connected to the emitter of the first PNP transistor, and the inverting input terminal is connected to the source of the first NMOS transistor. The drain of the first PMOS transistor is connected to the reference current signal output terminal, and the non-inverting input terminal of the first operational amplifier is connected to the reference voltage output terminal. The first capacitor oscillator consists of a second NMOS transistor, a second PMOS transistor, and a first capacitor. The gate of the second PMOS transistor is connected to the reference current signal output terminal, the source is connected to a high level, and the drain is grounded through the first capacitor as the oscillation voltage output terminal. The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, the source is grounded, and the gate is used as the discharge switch control terminal. The second capacitor oscillator consists of a third NMOS transistor, a third PMOS transistor, and a second capacitor. The gate of the third PMOS transistor is connected to the reference current signal output terminal, the source is connected to a high level, and the drain is grounded through the second capacitor as the oscillation voltage output terminal. The drain of the third NMOS transistor is connected to the drain of the third PMOS transistor, the source is grounded, and the gate is used as the discharge switch control terminal. The common comparator circuit includes a fourth NMOS transistor, a fourth PMOS transistor, and a second bias current source. The source of the fourth PMOS transistor is connected to a high level, and its gate and drain are connected together. The drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor. The gate serves as the input terminal, and the drain serves as the output terminal and is grounded through the second bias current source. The first comparator consists of a fifth NMOS transistor and a fifth PMOS transistor. The gate of the fifth PMOS transistor is connected to the drain of the fourth PMOS transistor, the source is connected to a high level, and the drain serves as the output terminal. The drain of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor, the gate is connected to the output terminal of the first capacitor oscillator, and the source is connected to the output terminal of the common comparator circuit. The second comparator consists of a sixth NMOS transistor and a sixth PMOS transistor. The gate of the sixth PMOS transistor is connected to the drain of the fourth PMOS transistor, the source is connected to a high level, and the drain serves as the output terminal. The drains of the sixth NMOS transistor and the sixth PMOS transistor are connected, the gate is connected to the output terminal of the second capacitor oscillator, and the source is connected to the output terminal of the common comparator circuit.
2. The low-temperature drift, low-offset RC oscillator as described in claim 1, characterized in that, The first PMOS transistor, the second PMOS transistor, and the third PMOS transistor have the same size.
3. The low-temperature drift, low-offset RC oscillator as described in claim 1, characterized in that, The first capacitor and the second capacitor have the same capacitance value.