Circuit structure for receiving an FSK modulated signal

Abstract

The utility model discloses a kind of circuit structure of receiving FSK modulated signal, it is related to network communication technical field, the circuit structure includes FSK modulated signal filter circuit, square wave conversion circuit;The square wave conversion circuit includes comparator, voltage reference chip;The comparator is provided with voltage input end and signal input end;The reference voltage chip is connected to the voltage input end, the FSK modulated signal filter circuit is connected to the signal input end, the output end of the comparator is connected to square wave signal output end;Reference voltage chip and the voltage input end between being provided with voltage dividing resistor, to convert sine wave signal.

Description

Technical Field

[0001] This utility model relates to the field of network communication technology, and in particular to a circuit structure for receiving FSK modulated signals. Background Technology

[0002] FSK (Frequency Shift Keying) is a modulation technique that transmits digital information by changing the carrier frequency. Its core principle is to use carrier signals of different frequencies to represent binary data (0 or 1), specifically involving two processes: modulation and demodulation. This technology can be applied in the oil well logging industry for communication and data exchange between downhole instruments.

[0003] After sending the FSK modulated signal, the CPU (Central Processing Unit) at the data receiving end needs to decode the data by determining the sine wave frequency of the received FSK modulated signal. However, the CPU cannot directly process the sine wave signal, so it needs to be converted. Utility Model Content

[0004] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, one objective of this invention is to provide a circuit structure for receiving FSK modulated signals to convert sinusoidal signals.

[0005] According to an embodiment of the present invention, a circuit structure for receiving FSK modulated signals is provided. The circuit structure includes an FSK modulated signal filtering circuit and a square wave conversion circuit. The square wave conversion circuit includes a comparator and a voltage reference chip.

[0006] The comparator is provided with a voltage input terminal and a signal input terminal;

[0007] The reference voltage chip is connected to the voltage input terminal, the FSK modulation signal filtering circuit is connected to the signal input terminal, and the output terminal of the comparator is connected to the square wave signal output terminal.

[0008] A voltage divider resistor is provided between the reference voltage chip and the voltage input terminal.

[0009] Optionally, the voltage divider resistor includes: a fixed voltage divider resistor and a variable voltage divider resistor; the variable voltage divider resistor is connected in parallel with the third voltage divider resistor, and a MOS switch is provided on the parallel path of the third voltage divider resistor.

[0010] Optionally, an RC filter circuit is provided between the FSK modulation signal filtering circuit and the signal input terminal.

[0011] Optionally, the circuit structure further includes a diode, the negative terminal of which is connected to the connection line between the FSK modulation signal filtering circuit and the comparator.

[0012] Optionally, the circuit structure includes a hysteresis resistor;

[0013] The voltage input terminal is connected to the first terminal of the hysteresis resistor, and the output terminal of the comparator is connected to the second terminal of the hysteresis resistor, to form a comparator hysteresis circuit including the hysteresis resistor, the fixed voltage divider resistor and the variable voltage divider resistor.

[0014] Optionally, the FSK modulation signal filtering circuit includes a local oscillator signal generation circuit, a mixer circuit, and a low-pass filter circuit.

[0015] The local oscillator signal generation circuit includes a crystal oscillator and a frequency divider chip, wherein the crystal oscillator is connected to the input terminal of the frequency divider chip;

[0016] The mixing circuit includes a mixing chip, wherein the first input interface of the mixing chip is connected to the output terminal of the frequency divider chip;

[0017] The second input interface of the mixer chip is connected to the signal receiving end of the FSK modulated signal;

[0018] The first output interface of the mixer chip is connected to the input terminal of the low-pass filter circuit;

[0019] The low-pass filter circuit includes a multi-stage operational amplifier circuit, and the output terminal of the low-pass filter circuit is connected to the signal input terminal.

[0020] Optionally, the first and second input terminals of the frequency divider chip are connected to the first and second terminals of the crystal oscillator, and both the first and second input terminals are grounded through a filter capacitor; the crystal oscillator is connected in parallel with a protection resistor.

[0021] Optionally, the output terminal of the frequency divider chip is provided with a frequency reduction element.

[0022] In the solution provided by this utility model embodiment, the received FSK modulated signal is processed by the FSK modulated signal filtering circuit to obtain the filtered sine wave signal. Then, the voltage of the sine wave signal is compared with the voltage output of the voltage reference chip by the comparator, thereby outputting the square wave signal corresponding to the sine wave to the CPU for processing, thus realizing the conversion of the sine wave signal.

[0023] Furthermore, by setting voltage divider resistors in the circuit, the voltage value received at the voltage input terminal can be adjusted more flexibly, thereby allowing for flexible adjustment of the comparator's comparison reference.

[0024] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a circuit structure for receiving FSK modulated signals provided in an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of a square wave conversion circuit provided in an embodiment of the present invention;

[0027] Figure 3 This is a schematic diagram of the structure of a local oscillator signal generation circuit provided in an embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram of a mixer circuit provided in an embodiment of the present invention;

[0029] Figure 5 This is a schematic diagram of a low-pass filter circuit provided in an embodiment of the present invention. Detailed Implementation

[0030] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model.

[0031] The circuit structure for receiving FSK modulated signals according to an embodiment of the present invention is described below with reference to the accompanying drawings.

[0032] In one embodiment of this utility model, see Figure 1 The circuit structure includes an FSK modulation signal filtering circuit and a square wave conversion circuit; the square wave conversion circuit includes a comparator and a voltage reference chip.

[0033] The comparator has a voltage input terminal and a signal input terminal;

[0034] The reference voltage chip is connected to the voltage input terminal, the FSK modulation signal filter circuit is connected to the signal input terminal, and the comparator output terminal is connected to the square wave signal output terminal.

[0035] A voltage divider resistor is provided between the reference voltage chip and the voltage input terminal.

[0036] The structure diagram of the square wave conversion circuit is as follows: Figure 2As shown. Since the CPU cannot directly process sine wave signals, it needs to be converted into a corresponding square wave for processing.

[0037] Specifically, the comparator U14A receives a 2.5V voltage VREF from the voltage reference chip D14 at its positive input terminal 3 (marked with a "+" sign in the diagram, representing the voltage input) and compares it with a sine wave input at the comparator's signal input terminal 2. If the VREF is higher than 2.5V, the comparator's output terminal 1 outputs a low level to the square wave signal output terminal FSK_IOC; otherwise, it outputs a high level. This results in a square wave signal corresponding to the sine wave being sent to the CPU for processing.

[0038] Capacitors C71 and C65 are placed between D14 and the reference test point VREF1, which detects a 2.5V voltage, to stabilize the voltage output of the reference voltage chip. Resistor R75 is also used to control voltage stability, ensuring that the voltage at point VREF1 remains at 2.5V.

[0039] The inverting input terminal 2 of comparator U14A is the signal input terminal, marked as - in the figure.

[0040] Figure 2 In subsequent embodiments, +5VD represents a power supply voltage of +5 volts. Figure 2 In the diagram, R64 and R65 are resistors, and C62 is a capacitor.

[0041] Specifically, voltage divider resistors include: fixed voltage divider resistors and variable voltage divider resistors;

[0042] The variable voltage divider resistor is connected in parallel with the third voltage divider resistor, and a MOSFET switch is installed on the parallel path of the third voltage divider resistor.

[0043] like Figure 2 As shown, R73 is a fixed voltage divider resistor. R68 is a variable voltage divider resistor, whose variableness depends on whether the MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) switch Q5 (the G, S, and D pins of the MOS switch are shown in the figure) controls the connection of the third voltage divider resistor R67 in the circuit, thus allowing for more flexible adjustment of the voltage value in the circuit. The Vth_EN input enable signal controls R67 to be grounded through Q5, thereby connecting it in parallel with R68.

[0044] Specifically, Q5 can be an enhancement-type MOSFET, which is off by default when there is no gate voltage. The enable signal is equivalent to providing a gate voltage greater than the preset threshold voltage, thereby turning Q5 on; when the gate voltage returns to zero, Q5 turns off again, and resistor R67 is no longer connected to the circuit.

[0045] like Figure 2The voltage measured at comparator pin 3 depends on the voltage division ratio of R73 and R68. Therefore, the voltage ratio changes when R67 is connected or not connected to the circuit, which means that the reference voltage can be adjusted, making it more versatile.

[0046] In the solution provided by this utility model embodiment, the received FSK modulated signal is processed by the FSK modulated signal filtering circuit to obtain the filtered sine wave signal. Then, the voltage of the sine wave signal is compared with the voltage output of the voltage reference chip by the comparator, thereby outputting the square wave signal corresponding to the sine wave to the CPU for processing, thus realizing the conversion of the sine wave signal.

[0047] Furthermore, by setting voltage divider resistors in the circuit, the voltage value received at the voltage input terminal can be adjusted more flexibly, thereby allowing for flexible adjustment of the comparator's comparison reference.

[0048] In one embodiment, an RC (Resistor-Capacitor) filter circuit is provided between the FSK modulated signal filter circuit and the signal input terminal. For example... Figure 2 As shown, the RC filter circuit consists of resistor R74 and capacitor C64. It filters the low-frequency component signal at the output of the low-pass filter, attenuating the high-frequency signal and further reducing the influence of high-frequency noise on the low-frequency component.

[0049] In one embodiment, the circuit structure further includes a diode, the negative terminal of which is connected to the connection line between the FSK modulation signal filter circuit and the comparator.

[0050] Specifically, such as Figure 2 RFO represents the output terminal of the FSK modulation signal filter circuit, which outputs a sine wave signal. A diode D13 is added to the branch of the circuit between RFO and comparator U14A. Diode D13 can protect the circuit from reverse voltage and prevent overvoltage. The unidirectional conduction characteristic of the diode means that when there is a positive voltage in the circuit, diode D13 does not conduct; when there is a negative voltage in the circuit, diode D13 conducts to ground, clearing the negative voltage.

[0051] like Figure 2 The circuit structure includes a hysteresis resistor;

[0052] The voltage input terminal is connected to the first terminal of the hysteresis resistor, and the output terminal of the comparator is connected to the second terminal of the hysteresis resistor, which is used to form a comparator hysteresis circuit including a hysteresis resistor, a fixed voltage divider resistor, and a variable voltage divider resistor.

[0053] like Figure 2As shown, the voltage divider resistors R73 and R68, capacitor C63, and hysteresis resistor R66 constitute a comparator hysteresis circuit, which can improve the circuit's anti-interference capability. R66 is connected in parallel with both the comparator's voltage input and output terminals.

[0054] The comparator hysteresis circuit determines two different threshold voltages based on the reference voltage, including an upper threshold voltage greater than 2.5V and a lower threshold voltage less than 2.5V, so that the output state only changes when the input signal RFO exceeds the upper threshold voltage or falls below the lower threshold voltage.

[0055] In this process, capacitor C63 is added as a filter capacitor to guide the glitch signal to... Figure 2 The grounding wire above the connection point Q5 further enhances the anti-interference capability.

[0056] Furthermore, since comparator U14A is an open-drain output, a pull-up resistor R69 needs to be added to the output terminal.

[0057] In one embodiment, the FSK modulation signal filtering circuit includes a local oscillator signal generation circuit, a mixer circuit, and a low-pass filter circuit.

[0058] The local oscillator signal generation circuit includes a crystal oscillator and a frequency divider chip, with the crystal oscillator connected to the input terminal of the frequency divider chip.

[0059] The mixing circuit includes a mixing chip, wherein the first input interface of the mixing chip is connected to the output terminal of the frequency divider chip;

[0060] The second input interface of the mixer chip is connected to the signal receiving end of the FSK modulated signal;

[0061] The first output interface of the mixer chip is connected to the input terminal of the low-pass filter circuit;

[0062] The low-pass filter circuit contains multiple operational amplifier stages, and the output of the low-pass filter circuit is connected to the signal input.

[0063] For the specific structure of the local oscillator signal generation circuit, please refer to [link / reference]. Figure 3 .

[0064] The crystal oscillator is Y1. For example, Y1 generates a signal with a frequency of 8.192MHz. Port 1 of Y1 is connected to the first input terminal Q0 of the frequency divider chip through line 10, and port 2 is connected to the second input terminal / Q1 of the frequency divider chip through line 11, inputting the generated signal to the frequency divider chip.

[0065] The frequency divider chip U10 outputs the aforementioned signal, which is then output to the output terminal via P10. After receiving the signal from Y1, the frequency divider chip optimizes the received signal. Since the crystal oscillator is affected by temperature drift, the frequency of the signal it generates may be inaccurate. The frequency divider chip can calibrate the signal, making the frequency of the signal closer to the set value. In this embodiment, the frequency of the signal is made closer to 8.192MHz.

[0066] In one embodiment, the output of the frequency divider chip is provided with a frequency reduction element.

[0067] 1 / 1024 is the frequency reduction factor of the frequency reduction element connected to pin 15, which is equivalent to reducing 8.192MHz by 1024 times to obtain the local oscillator signal f = 8.192M / 1024 = 8KHz.

[0068] Setting the local oscillator frequency to 8.192MHz is merely an example; other frequencies can also be set arbitrarily. This invention does not limit the scope of the embodiments.

[0069] Figure 3 In this configuration, VCC is the power supply, which is powered through pin 16 of the CC port of U10.

[0070] Capacitor C41 is a filter capacitor used for circuit protection. R56 is the voltage sensing resistor for the power supply VCC. RES is connected to reset pin 12, and resistor R53 is set on the ground line.

[0071] See Figure 3 The first input terminal Q0 and the second input terminal / Q1 of the frequency divider chip are connected to the first terminal 1 and the second terminal 2 of the crystal oscillator, and both the first input terminal and the second input terminal are grounded through a filter capacitor; the crystal oscillator is connected in parallel with the protection resistor.

[0072] The protection resistor R55, by setting a resistor with a large resistance value in conjunction with the filter capacitors C40 and C42, can stabilize the oscillation amplitude of the crystal oscillator, thereby generating a more stable frequency signal.

[0073] Figure 4 This is a schematic diagram of a mixer circuit, where the mixer chip is U3. The first input interfaces IN1, IN2, IN3, and IN4 correspond to pins 1, 16, 9, and 8 respectively, receiving the local oscillator signal in four separate channels. Figure 4 Continued use Figure 3 In the embodiment described, after a 1024-fold downclocking, the local oscillator signal frequency is 8kHz.

[0074] The second input interfaces S1, S2, S3, and S4 correspond to pins 3, 14, 11, and 6, respectively, and receive FSK modulated signals in four channels. For example, S1 and S2 receive the low-frequency signal (8.6kHz) from the FSK modulated signal, while S3 and S4 receive the high-frequency signal (9kHz) from the FSK modulated signal. The FSK modulated signal uses carrier signals of different frequencies to represent binary data 0 or 1; for example, the low-frequency signal represents 0, and the high-frequency signal represents 1.

[0075] The mixer chip performs down-conversion processing. The specific implementation of down-conversion processing is as follows: the received FSK modulated signal contains sine wave signals at frequencies of 9kHz and 8.6kHz, which are mixed with a sine wave at a local oscillator frequency of 8kHz. That is, the 8.6kHz and 9kHz sine waves are ±8kHz respectively, resulting in sine waves of 600Hz, 1kHz, 17kHz, and 16.6kHz.

[0076] according to Figure 4 In one embodiment, based on the signal grouping calculation of the second input interface and the second input interface, the following settings can be configured: S1+IN1, to obtain a 16.6kHz sine wave; S2-IN2, to obtain a 600Hz sine wave; S3+IN3, to obtain a 17kHz sine wave; S4-IN4, to obtain a 1kHz sine wave.

[0077] The first output interface D1, D2, D3, and D4 of the mixer chip output the four sine wave signals mentioned above, respectively, through pins 2, 15, 10, and 7; pin 5 is the GND line.

[0078] exist Figure 4 In this context, TP stands for Test Point, which refers to a physical point in a circuit used to verify the circuit's state or inject test signals. Figure 4 In the figures, TP12, TP9, TP13, etc., all represent this meaning. In other embodiments of the figures, the TP markings also have the same meaning, which will not be described in detail here.

[0079] Figure 4 In the diagram, R22, R48, R3, R44, and R45 are resistors; C6 and C38 are capacitors. C38 is connected to the negative terminal V- of the U3 chip through pin 4, and C6 is connected to the positive terminal V+ of the U3 chip through pin 13.

[0080] Figure 5 A specific embodiment of a low-pass filter circuit is shown, which includes a two-stage operational amplifier circuit. In this circuit, capacitor C23, resistor R27, and amplifier A constitute the first-stage operational amplifier circuit, while capacitor C25, resistor R28, and amplifier B constitute the second-stage operational amplifier circuit.

[0081] In the first-stage operational amplifier circuit, pins 2 and 3 of amplifier A are the input terminals, and pin 1 is the output terminal. Figure 5 In the diagram, VCC represents the power supply, R9 is a resistor, C18 is a capacitor, and F represents simulated ground. The same letter F in this diagram and other accompanying embodiments represents this meaning.

[0082] In the two-stage operational amplifier circuit, the settings of C25, R28, and pins 5, 6, and 7 of amplifier B are the same as those of capacitor C23, resistor R27, and amplifier A, forming a multi-stage identical circuit structure.

[0083] Figure 5 It also includes resistors R15, R16, and R49, capacitors C27, C28, and C39, and VEE is the negative power supply.

[0084] Each operational amplifier stage has the same structure. Therefore, in other embodiments, this structure can be reused to form multi-stage operational amplifier circuits with three or more stages.

[0085] A low-pass filter circuit is used to obtain low-frequency components. (Continued) Figure 4 In one embodiment, 600 Hz and 1 kHz are low-frequency components. 1 kHz can be set to correspond to binary 1 and 600 Hz to correspond to binary 0. These components are retained through low-pass filtering. The 17 kHz and 16.6 kHz sine waves are filtered out as high-frequency components. Thus, the low-frequency signal receiver inputs low-frequency components, which both preserves the binary information and reduces the signal frequency.

[0086] As can be seen from the above, in the solution provided by the embodiments of this application, the local oscillator signal is generated by the local oscillator signal generation circuit. After the mixer chip receives the local oscillator signal, it obtains the high-frequency component signal and the low-frequency component signal by mixing. Then, it is filtered by the low-pass filter circuit to retain the low-frequency component, thereby reducing the frequency of the received signal. Correspondingly, the frequency of interrupting the CPU to process the received signal for decoding is reduced, thereby improving the CPU execution efficiency while ensuring the carrier frequency determination.

[0087] Furthermore, through the above scheme, if there are abnormal signals in the FSK modulation signal, such as some low-frequency noise, they will become high-frequency noise after mixing and be filtered out. For example, if there is 0.5kHz noise in the downhole environment, and an 8kHz local oscillator signal is used for mixing, the 0.5kHz noise will generate a 7.5kHz component after mixing. Compared with the low-frequency components of 600Hz and 1kHz, these are all high-frequency components, and therefore can be filtered out by low-pass filtering. For example, frequencies higher than 2kHz can be set to be filtered out, thus removing noise. This optimizes the signal for the high temperature, high pressure, and strong electromagnetic interference environment in downhole environments, improves signal stability, and can, to a certain extent, handle problems such as long communication distances, strong electromagnetic interference, and the ease with which data errors, data loss, and communication interruptions can occur during communication.

[0088] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0089] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0090] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0091] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0092] In this utility model, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0093] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A circuit structure for receiving FSK modulated signals, characterized in that, The circuit structure includes an FSK modulation signal filtering circuit and a square wave conversion circuit; the square wave conversion circuit includes a comparator and a voltage reference chip. The comparator is provided with a voltage input terminal and a signal input terminal; The reference voltage chip is connected to the voltage input terminal, the FSK modulation signal filtering circuit is connected to the signal input terminal, and the output terminal of the comparator is connected to the square wave signal output terminal. A voltage divider resistor is provided between the reference voltage chip and the voltage input terminal.

2. The circuit structure according to claim 1, characterized in that, The voltage divider resistor includes a fixed voltage divider resistor and a variable voltage divider resistor; the variable voltage divider resistor is connected in parallel with a third voltage divider resistor, and a MOS switch is provided on the parallel path of the third voltage divider resistor.

3. The circuit structure according to claim 1, characterized in that, An RC filter circuit is provided between the FSK modulation signal filtering circuit and the signal input terminal.

4. The circuit structure according to claim 1, characterized in that, The circuit structure also includes a diode, the negative terminal of which is connected to the connection line between the FSK modulation signal filtering circuit and the comparator.

5. The circuit structure according to claim 2, characterized in that, The circuit structure includes a hysteresis resistor; The voltage input terminal is connected to the first terminal of the hysteresis resistor, and the output terminal of the comparator is connected to the second terminal of the hysteresis resistor, to form a comparator hysteresis circuit including the hysteresis resistor, the fixed voltage divider resistor and the variable voltage divider resistor.

6. The circuit structure according to claim 1, characterized in that, The FSK modulation signal filtering circuit includes a local oscillator signal generation circuit, a mixer circuit, and a low-pass filter circuit. The local oscillator signal generation circuit includes a crystal oscillator and a frequency divider chip, wherein the crystal oscillator is connected to the input terminal of the frequency divider chip; The mixing circuit includes a mixing chip, wherein the first input interface of the mixing chip is connected to the output terminal of the frequency divider chip; The second input interface of the mixer chip is connected to the signal receiving end of the FSK modulated signal; The first output interface of the mixer chip is connected to the input terminal of the low-pass filter circuit; The low-pass filter circuit includes a multi-stage operational amplifier circuit, and the output terminal of the low-pass filter circuit is connected to the signal input terminal.

7. The circuit structure according to claim 6, characterized in that, The first and second input terminals of the frequency divider chip are connected to the first and second terminals of the crystal oscillator, and both the first and second input terminals are grounded through a filter capacitor; the crystal oscillator is connected in parallel with a protection resistor.

8. The circuit structure according to claim 6, characterized in that, The output terminal of the frequency divider chip is equipped with a frequency reduction element.

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