Optoelectronic image processing board

Abstract

The utility model relates to a kind of photoelectric image processing board, including first SoC chip, CPU chip, HDMI interface and PAL unit;The output port of CPU chip is electrically connected to the first input port of first SoC chip;The input port of HDMI interface is electrically connected to the output port of first SoC chip;PAL unit includes sequentially electrically connected PAL codec chip and PAL interface, and the input / output bidirectional port of PAL codec chip is electrically connected to the first input / output bidirectional port of first SoC chip.The utility model can realize the conversion of multiple video interfaces by first SoC chip, HDMI interface and PAL interface, to meet the generalization display demand and video transmission demand.

Description

Technical Field

[0001] This utility model relates to the field of image interface conversion technology, specifically to an optoelectronic image processing board. Background Technology

[0002] The transmission of photoelectric images between different devices relies on video format conversion using various video interface technologies. Video signals are transmitted from one device to another through video hardware interfaces. Video interfaces do not have the capability to transmit control signals; these signals are transmitted via Ethernet through the internal network switching chip of the circuit board, enabling interconnection and collaboration between devices.

[0003] Currently, the functions of optoelectronic image transmission interfaces are relatively dispersed. Typically, a single SOC chip only performs the conversion of one type of video interface, resulting in a waste of logic resources. Utility Model Content

[0004] Based on the above description, this utility model provides an optoelectronic image processing board, which aims to solve the problem of the relatively scattered functions of existing optoelectronic image transmission interfaces.

[0005] The technical solution of this utility model to solve the above-mentioned technical problems is as follows:

[0006] An optoelectronic image processing board includes:

[0007] First SoC chip;

[0008] A CPU chip, wherein the output port of the CPU chip is electrically connected to the first input port of the first SoC chip;

[0009] An HDMI interface, wherein the input port of the HDMI interface is electrically connected to the output port of the first SoC chip;

[0010] The PAL unit includes a PAL codec chip and a PAL interface that are electrically connected in sequence. The input / output bidirectional port of the PAL codec chip is electrically connected to the first input / output bidirectional port of the first SoC chip.

[0011] Based on the above technical solution, the present invention can be further improved as follows.

[0012] Furthermore, it includes a second SoC chip and an optical module, wherein the first input port of the second SoC chip is electrically connected to the output port of the CPU chip, and the input / output bidirectional port of the optical module is electrically connected to the first input / output bidirectional port of the second SoC chip.

[0013] Furthermore, it includes a network unit, which comprises a network streaming chip and a network interface electrically connected in sequence, wherein the input port of the network streaming chip is electrically connected to the output port of the second SoC chip.

[0014] Furthermore, the second input / output bidirectional port of the second SoC chip is electrically connected to the second input / output bidirectional port of the first SoC chip.

[0015] Furthermore, it includes a VPx interface, the output port of which is electrically connected to the second input port of the first SoC chip and the second input port of the second SoC chip.

[0016] Furthermore, the network streaming chip is a HiSilicon chip.

[0017] Furthermore, the network interface is an RJ45 interface.

[0018] Compared with the prior art, the technical solution of this application has the following beneficial technical effects:

[0019] (1) This utility model can realize the conversion of multiple video interfaces through the first SoC chip, HDMI interface and PAL interface, thereby meeting the needs of universal display and video transmission.

[0020] (2) This utility model can further enrich the video interface through the second SoC chip and optical module to improve the video transmission requirements.

[0021] (3) In this utility model, the second SoC chip sends the image to the network streaming chip through the network unit, so that the network streaming chip generates the bit stream and outputs it through the network interface, thereby enhancing the real-time streaming energy. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a sectional view of an optoelectronic image processing board provided in an embodiment of the present invention.

[0024] Explanation of reference numerals in the attached figures:

[0025] 1. First SoC chip;

[0026] 2. CPU chip;

[0027] 3. HDMI interface;

[0028] 4. PAL unit; 41. PAL codec chip; 42. PAL interface;

[0029] 5. Second SoC chip;

[0030] 6. Optical module;

[0031] 7. Network unit; 71. Network streaming chip; 72. Network interface;

[0032] 8. VPx interface. Detailed Implementation

[0033] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0035] It is understood that spatial relation terms such as "below," "under," "below," "below," "above," "above," etc., can be used here to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as "below" or "below" of the other element or feature will be oriented "above" the other element or feature. Therefore, the exemplary terms "below" and "below" can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0036] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0037] Reference Figure 1 As shown, this utility model provides a technical solution: an optoelectronic image processing board, including a first SoC chip 1, a CPU chip 2, an HDMI interface 3, and a PAL unit 4; the output port of the CPU chip 2 is electrically connected to the first input port of the first SoC chip 1; the input port of the HDMI interface 3 is electrically connected to the output port of the first SoC chip 1; the PAL unit 4 includes a PAL codec chip 41 and a PAL interface 42 connected in sequence, and the input / output bidirectional port of the PAL codec chip 41 is electrically connected to the first input / output bidirectional port of the first SoC chip 1.

[0038] For example, the first SoC chip 1 can be a Xilinx Zynq-7000, etc. The PAL codec chip 41 can be a TVP5150AM1, etc.

[0039] In this embodiment, when the CPU chip 2 generates the operating system interface, it can send the HDMI signal to the first SoC chip 1. The first SoC chip 1 performs image processing and outputs the signal through the HDMI interface 3. When the first SoC chip 1 outputs a PAL signal to the PAL interface 42 or the PAL interface 42 inputs a PAL signal to the first SoC chip 1, the PAL codec chip 41 performs the conversion between analog and digital signals.

[0040] Reference Figure 1 As shown, in some embodiments, the optoelectronic image processing board includes a second SoC chip 5 and an optical module 6. The first input port of the second SoC chip 5 is electrically connected to the output port of the CPU chip 2, and the input / output bidirectional port of the optical module 6 is electrically connected to the first input / output bidirectional port of the second SoC chip 5.

[0041] For example, the second SoC chip 5 could be a Xilinx Zynq-7000 or similar.

[0042] In this embodiment, when the CPU chip 2 generates the operating system interface, it can send the HDMI signal to the second SoC chip 5. The second SoC chip 5 sends the FC protocol signal to the optical module 6, driving the optical module 6 to perform electro-optical signal conversion.

[0043] Reference Figure 1 As shown, in some embodiments, the optoelectronic image processing board includes a network unit 7, which includes a network streaming chip 71 and a network interface 72 connected in sequence. The input port of the network streaming chip 71 is electrically connected to the output port of the second SoC chip 5.

[0044] For example, the network streaming chip 71 can be a Hisilicon chip, etc.; the Ethernet PHY chip can be a Marvell 88E1111, etc.; and the switching chip can be a 5396 chip, etc. The network interface 72 can be an RJ45 interface.

[0045] In this embodiment, the second SoC chip 5 sends the image to the network streaming chip 71, which generates a bitstream and outputs it through the network interface 72, displaying the network streaming image on a computer via the electrical network.

[0046] Reference Figure 1 As shown, in some embodiments, the second input / output bidirectional port of the second SoC chip 5 is electrically connected to the second input / output bidirectional port of the first SoC chip 1.

[0047] In this embodiment, when the CPU chip 2 generates the operating system interface, it can send the HDMI signal to the second SoC chip 5. The second SoC chip 5 performs image processing and outputs the signal through the first SoC chip 1 and the HDMI interface 3. Both the first SoC chip 1 and the second SoC chip 5 can send their respective images to the network streaming chip 71, causing the network streaming chip 71 to generate a bitstream and output it through the network interface 72. The network streaming image is then displayed on a computer via the electrical network.

[0048] Reference Figure 1 As shown, in some embodiments, the optoelectronic image processing board includes a VPx interface 8, the output port of which is electrically connected to the second input port of the first SoC chip 1 and the second input port of the second SoC chip 5.

[0049] In this embodiment, the VPx interface 8 transmits and receives external Ethernet control commands to control the first SoC chip 1 and the second SoC chip 5 to perform optional processing such as splicing, scaling, overlaying, shaping, and format conversion according to the Ethernet control commands.

[0050] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. A photoelectric image processing board, characterized in that, include: First SoC chip (1); CPU chip (2), the output port of the CPU chip (2) is electrically connected to the first input port of the first SoC chip (1); HDMI interface (3), the input port of the HDMI interface (3) is electrically connected to the output port of the first SoC chip (1); The PAL unit (4) includes a PAL codec chip (41) and a PAL interface (42) connected in sequence. The input / output bidirectional port of the PAL codec chip (41) is electrically connected to the first input / output bidirectional port of the first SoC chip (1).

2. The photoelectric image processing board according to claim 1, characterized in that, It includes a second SoC chip (5) and an optical module (6). The first input port of the second SoC chip (5) is electrically connected to the output port of the CPU chip (2), and the input / output bidirectional port of the optical module (6) is electrically connected to the first input / output bidirectional port of the second SoC chip (5).

3. The photoelectric image processing board according to claim 2, characterized in that, The device includes a network unit (7), which includes a network streaming chip (71) and a network interface (72) connected in sequence. The input port of the network streaming chip (71) is electrically connected to the output port of the second SoC chip (5).

4. The photoelectric image processing board according to claim 3, characterized in that, The second input / output bidirectional port of the second SoC chip (5) is electrically connected to the second input / output bidirectional port of the first SoC chip (1).

5. The photoelectric image processing board according to claim 3, characterized in that, It includes a VPx interface (8), the output port of which is electrically connected to the second input port of the first SoC chip (1) and the second input port of the second SoC chip (5).

6. The photoelectric image processing board according to claim 3, characterized in that, The network streaming chip (71) is a HiSilicon chip.

7. The photoelectric image processing board according to claim 3, characterized in that, The network interface (72) is an RJ45 interface.

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