A method for verifying EFlash BIST functionality
By integrating an EFlash BIST sequence generation module inside the chip, the inefficiency of traditional EFlash testing methods is solved, enabling rapid and comprehensive verification, ensuring the correctness and reliability of the EFlash BIST function, and improving the overall verification efficiency of the MCU chip.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGSU HUACHUANG MICROSYSTEM CO LTD
- Filing Date
- 2026-01-26
- Publication Date
- 2026-06-16
AI Technical Summary
Traditional EFlash testing methods rely on external devices, resulting in long testing times, high costs, and poor flexibility. The SOC verification process is cumbersome and has poor reusability, making it difficult to efficiently verify the EFlash BIST function.
An EFlash BIST sequence generation module is integrated inside the chip to generate test modes, functions, and data. Data transmission, reception, and result checking are achieved through internal circuitry to ensure the verification of EFlash BIST functionality.
This improved chip verification efficiency, shortened simulation verification time, enhanced the observability and repeatability of verification results, and ensured the correctness and reliability of the EFlash BIST controller and FLASH chip functions.
Smart Images
Figure CN122220172A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the chip technical field, and in particular to a verification method for EFlash BIST function. BACKGROUND
[0002] EFlash BIST (Embedded Flash Built-In Self-Test) is a self-test technology specially designed for embedded flash memory, which is used to verify the function, performance and reliability of EFlash. EFlash needs to ensure the reliability of data storage and reading in long-term use, and the test needs to verify its durability and stability. However, the traditional EFlash test method usually relies on external test equipment to test the chip through test Fixture, but this method has the problems of long test time, high test cost and poor flexibility. In order to solve the limitations of the traditional test method, BIST technology is introduced into EFlash test.
[0003] The traditional verification method currently generally adopts to build a SOC (System On Chip) level verification environment, to give excitation conforming to EFlash BIST interface on the chip pin, to realize read operation, write operation and erase operation of EFlash particles through EFlash BIST controller, and to generate test cases by using System Verilog hardware description language to realize sending of test sequence and receiving of data, but this verification process is tedious and has poor reusability. Therefore, how to integrate a special circuit in the chip to generate test mode, test function and data, to complete data sending and receiving and test result checking, to realize verification of EFlash BIST function, and to improve SOC verification efficiency is particularly important. SUMMARY
[0004] In view of the above problems, the purpose of the present application is to provide a verification method for EFlash BIST function, which can ensure the correctness and reliability of EFlash BIST controller function and part of FLASH particle function, effectively reduce the chip simulation verification machine time and the overall verification workload, can carry out a round of EFlash BIST controller function problem troubleshooting work in the early stage of chip verification, and improve the overall verification efficiency of MCU chip.
[0005] The following technical solutions are realized: A verification method for EFlash BIST functionality includes the following steps: S1, instantiating an EFlash BIST sequence generation module at the top level of the register transfer level (RTL) in the chip; after simulation starts, waiting for the chip to enter the working state via electrolytic reset, and during EFlash BIST function verification, setting the test mode control pin of the chip's general-purpose input / output interface high, thus entering test mode; S2, after entering test mode, generating a stimulus sequence through the EFlash BIST sequence generation module and inputting the stimulus sequence to the BIST interface through the general-purpose input / output interface, which then enters the BIST controller. The BIST controller identifies the stimulus sequence and converts it into an access operation to the FLASH module. The FLASH module executes the current operation and returns the operation result data to the EFlash BIST sequence generation module upon completion, performing the next round of stimulus sequence input, stimulus sequence identification, and operation execution until all stimulus sequences are sent and the operation result data is returned correctly. This invention integrates a dedicated circuit within the chip to generate test modes, test functions, and data, complete data transmission and reception, and perform test result checks, thereby enabling the verification of EFlash BIST functionality and improving the overall verification efficiency of the MCU chip.
[0006] Preferably, in step S1, when the test mode control pin of the chip's general-purpose input / output interface is low, the chip enters the normal operating mode. Selecting the chip's operating mode via the test mode control pin ensures that the chip accurately enters the test mode.
[0007] Preferably, in normal operating mode, the chip processing core communicates with other modules for signal control and data exchange via the APB bus and AHB bus, wherein the other modules include at least a general-purpose input / output interface module and a FLASH module. The APB bus and AHB bus configuration enables efficient communication with other modules while the chip is in normal operating mode.
[0008] Preferably, in step S1, the EFlash BIST sequence generation module is used to select either the JTAG interface or the SPI interface to send the excitation sequence and receive the operation result data, depending on the interface used in the chip's test mode. By instantiating an EFlash BIST sequence generation module, the EFlash BIST function can be verified.
[0009] Preferably, the EFlash BIST sequence generation module includes a JTAG sequence generation module and an SPI sequence generation module, which are used to generate control signals and data signals conforming to the JTAG and SPI protocols, respectively. These signals are then interconnected using an interface selector to select the corresponding interface on the chip, forming a data path. The JTAG and SPI sequence generation modules improve chip verification efficiency.
[0010] Preferably, both the JTAG sequence generation module and the SPI sequence generation module internally include four parts: a clock division submodule, a data transmission and reception submodule, a test function and data generation submodule, and a test mode selection and data checking submodule. By integrating these four functional modules into the JTAG and SPI sequence generation modules respectively, the verification of the EFlash BIST function can be achieved, effectively improving chip verification efficiency.
[0011] Preferably, the clock division submodule is used to divide the chip clock into a working clock that meets the requirements of the SDC design document; the data transmission and reception submodule is used to send and receive test data according to the interface protocol; the test function and data generation submodule is used to generate corresponding stimulus sequences; and the test mode selection and data checking submodule is used to select different modes and check the test data. Through these submodules and their functions, a complete verification method can be formed, exhibiting strong reusability and effectively improving verification efficiency.
[0012] Preferably, the stimulus sequence generated by the test function and data generation submodule includes at least a sequence of read operations, write operations, and erase operations. By generating the stimulus sequence, the correctness of access operations initiated by the controller to the FLASH module can be ensured.
[0013] The beneficial effects of this invention compared to the prior art are: The technical solution of this invention proposes a method that integrates a dedicated circuit within the chip to generate test modes, test functions, and data, complete data transmission and reception, and check test results, thereby enabling the verification of the EFlashBIST function. This verification method can be applied to both pre-simulation and post-simulation verification of the chip, featuring fast simulation verification speed, comprehensive BIST function verification coverage, easy observation of verification results, and high verification repeatability. This invention allows for the verification of the EFlash BIST controller function and some FLASH chip functions during the pre-simulation stage, ensuring the correctness and reliability of the EFlash BIST controller function and some FLASH chip functions. This effectively reduces the time required for post-simulation verification and the overall verification workload, enabling a round of troubleshooting for EFlash BIST controller function issues in the early stages of chip verification, thus improving the overall verification efficiency of the MCU chip. Attached Figure Description
[0014] Figure 1 A flowchart of a verification method for EFlash BIST functionality; Figure 2 This is a schematic diagram of the structure of a verification environment for the EFlash BIST function. Figure 3 This is a schematic diagram of the structure of the JTAG sequence generation module / SPI sequence generation module. Detailed Implementation
[0015] The following will refer to the appendices in the embodiments of the present invention. Figures 1-3 The technical solutions in the embodiments of the present invention will be described in detail below.
[0016] like Figure 1 The diagram shows a flowchart of a verification method for the EFlash BIST function. First, after simulation begins, the chip waits for an electrolytic reset to enter the working state. Then, the test mode control pin of the chip's general-purpose input / output interface is set high, and the chip enters test mode. Next, an stimulus sequence is generated by the EFlash BIST sequence generation module and input to the BIST interface through the general-purpose input / output interface. The BIST controller converts the stimulus sequence into an access operation to the FLASH module, executes the current operation, and returns the operation result data to the EFlash BIST sequence generation module for the next round of operation. Before starting simulation, an EFlash BIST sequence generation module needs to be instantiated at the top level of the register transfer level (RTL). This invention ensures the correctness and reliability of the BIST controller function and some FLASH chip functions, improving the overall verification efficiency of the chip.
[0017] The method specifically includes the following steps: S1. Instantiate an EFlash BIST sequence generation module at the top level of the register transfer level (RTL) in the chip. After the simulation starts, wait for the chip to undergo an electrolytic reset and enter the working state. When performing EFlash BIST function verification, set the test mode control pin of the chip's general input / output interface high, and the chip enters the test mode.
[0018] Specifically, in step S1, when the test mode control pin of the chip's general-purpose input / output interface is low, the chip enters the normal operating mode. In the normal operating mode, the chip's processing core communicates with other modules via the APB bus and AHB bus for signal control and data exchange. These other modules include at least a general-purpose input / output interface module and a FLASH module. APB stands for Advanced Peripheral Bus, used to connect and manage peripheral devices in the system; AHB stands for Advanced High-Performance Bus, used for high-performance data transmission. Thus, this invention selects the chip's operating mode via the test mode control pin, ensuring the chip accurately enters the test mode. Furthermore, the settings of the APB and AHB buses enable efficient communication with other modules while the chip is in normal operating mode.
[0019] like Figure 2 The diagram shows a schematic of a verification environment for the EFlash BIST function. An EFlash BIST sequence generation module is instantiated at the top level of the register transfer level (RTL). This EFlash BIST sequence generation module starts working when the chip test mode pin of the general input / output interface is set high to verify the EFlash BIST function.
[0020] In this embodiment, the EFlash BIST sequence generation module is used to select either the JTAG interface or the SPI interface to send the stimulus sequence and receive the operation result data, depending on the interface used in the chip's test mode. The EFlash BIST sequence generation module includes a JTAG sequence generation module and an SPI sequence generation module, which are used to generate control signals and data signals conforming to the JTAG and SPI protocols, respectively. They are then interconnected using an interface selector to select the corresponding interface on the chip, forming a data path. JTAG stands for Joint Test Action Group, a standard interface for integrated circuit testing and debugging; SPI stands for Serial Peripheral Interface, a serial communication bus protocol. Therefore, by instantiating an EFlash BIST sequence generation module, the EFlash BIST function can be verified, improving chip verification efficiency.
[0021] like Figure 3The diagram shows the structure of the JTAG sequence generation module / SPI sequence generation module. Both the JTAG and SPI sequence generation modules internally include four parts: a clock division submodule, a data transmission and reception submodule, a test function and data generation submodule, and a test mode selection and data checking submodule. This invention integrates these four functional modules into the JTAG and SPI sequence generation modules respectively, forming a complete verification method to verify the EFlash BIST function. It also exhibits strong reusability and effectively improves chip verification efficiency.
[0022] In this embodiment, the clock division submodule is used to divide the chip clock into a working clock that meets the requirements of the SDC design file. SDC stands for Synopsys Design Constraints, which describes the goals and limitations of digital circuit design in terms of timing, area, and power consumption. The data transmission and reception submodule is used to send and receive test data according to the interface protocol specification to complete communication with the FLASH module. The test function and data generation submodule is used to generate corresponding stimulus sequences, and the generated stimulus sequences include at least read operation, write operation, and erase operation sequences, which can ensure the correctness of the access operation initiated by the controller to the FLASH module. The test mode selection and data inspection submodule is used to select different modes and check the test data, including writing data first and then reading it, checking whether the read and written data are consistent, and checking whether the data has been completely erased.
[0023] S2. After the chip enters the test mode, it generates a stimulus sequence through the EFlash BIST sequence generation module and inputs the stimulus sequence to the BIST interface through the general input / output interface. The BIST controller then identifies the stimulus sequence and converts it into an access operation to the FLASH module. The FLASH module executes the current operation and returns the operation result data to the EFlash BIST sequence generation module after completion. This process continues for the next round of stimulus sequence input, stimulus sequence identification, and operation execution until all stimulus sequences have been sent and the operation result data has been returned correctly.
[0024] In summary, this invention proposes a method that integrates a dedicated circuit within the chip to generate test modes, test functions, and data, complete data transmission and reception, and check test results, thereby enabling the verification of the EFlash BIST function. This verification method can be applied to both pre-simulation and post-simulation verification of the chip, featuring fast simulation verification speed, comprehensive BIST function verification coverage, easy observation of verification results, and high verification repeatability. Furthermore, this invention allows for the verification of the EFlash BIST controller function and some FLASH chip functions during the pre-simulation stage, ensuring the correctness and reliability of the EFlash BIST controller function and some FLASH chip functions. This effectively reduces the time required for post-simulation verification and the overall verification workload, enabling a round of troubleshooting for EFlash BIST controller function issues in the early stages of chip verification, thus improving the overall verification efficiency of the MCU chip and demonstrating significant advancements.
[0025] The above embodiments are merely illustrative of the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solutions based on the technical concept proposed in this invention shall fall within the scope of protection of this invention.
Claims
1. A verification method for EFlash BIST functionality, characterized in that, The method includes the following steps: S1. Instantiate an EFlash BIST sequence generation module at the top level of the register transfer level RTL in the chip; after the simulation starts, wait for the chip to be electrolytically reset and enter the working state, and when performing EFlash BIST function verification, set the test mode control pin of the chip's general input / output interface high, and the chip enters the test mode. S2. After the chip enters the test mode, it generates a stimulus sequence through the EFlash BIST sequence generation module and inputs the stimulus sequence to the BIST interface through the general input / output interface. The BIST controller then identifies the stimulus sequence and converts it into an access operation to the FLASH module. The FLASH module executes the current operation and returns the operation result data to the EFlash BIST sequence generation module after completion. This process continues for the next round of stimulus sequence input, stimulus sequence identification, and operation execution until all stimulus sequences have been sent and the operation result data has been returned correctly.
2. The verification method for EFlash BIST function according to claim 1, characterized in that, In step S1, when the test mode control pin of the chip's general input / output interface is set low, the chip enters normal operating mode.
3. The verification method for EFlash BIST function according to claim 2, characterized in that, In normal operating mode, the chip processing core communicates with other modules via the APB bus and AHB bus for signal control and data exchange. These other modules include at least a general-purpose input / output interface module and a FLASH module.
4. The verification method for EFlash BIST function according to claim 1, characterized in that, In step S1, the EFlash BIST sequence generation module is used to select either the JTAG interface or the SPI interface to send the excitation sequence and receive the operation result data, depending on the interface used in the chip's test mode.
5. The verification method for EFlash BIST function according to claim 1, characterized in that, The EFlashBIST sequence generation module includes a JTAG sequence generation module and an SPI sequence generation module, which are used to generate control signals and data signals that conform to the JTAG protocol and the SPI protocol, respectively. They are interconnected by selecting the corresponding interface of the chip through the interface selector to form a data path.
6. The verification method for EFlash BIST function according to claim 5, characterized in that, Both the JTAG sequence generation module and the SPI sequence generation module internally consist of four parts: a clock division submodule, a data transmission and reception submodule, a test function and data generation submodule, and a test mode selection and data checking submodule.
7. The verification method for EFlash BIST function according to claim 6, characterized in that, The clock divider submodule is used to divide the chip clock into a working clock that meets the requirements of the SDC design file; the data transmission and reception submodule is used to send and receive test data according to the interface protocol. The test function and data generation submodule is used to generate the corresponding stimulus sequence; the test mode selection and data inspection submodule is used to select different modes and inspect the test data.
8. The verification method for EFlash BIST function according to claim 7, characterized in that, The stimulus sequence generated by the test function and data generation submodule includes at least a sequence of read operations, write operations, and erase operations.