Message signal interrupt processing method and system on chip
By using inter-domain communication mechanisms to handle message signal interrupts in a hardware-isolated multi-core SoC system, the problems of untimely access to storage devices and waste of CPU resources are solved, and fast and accurate interrupt distribution and processing are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SEMIDRIVE TECHNOLOGY LTD
- Filing Date
- 2026-05-19
- Publication Date
- 2026-06-16
AI Technical Summary
In hardware-isolated multi-core SoC systems, PCIe interrupts cannot be directly distributed across hardware domains, leading to problems such as untimely access to storage devices or wasted CPU computing resources.
The first hardware domain sends an access request to the storage device, generating a message signal interrupt information. The second hardware domain receives and parses the interrupt information, generates an inter-domain communication interrupt, and sends the interrupt to the target hardware domain through the Mailbox mechanism, thus avoiding the waste of CPU computing resources.
It enables fast and accurate distribution of storage device interrupts across hardware domains, avoiding waste of CPU computing resources and excessive hardware processing burden.
Smart Images
Figure CN122220271A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a method and system-on-a-chip for handling message signal interrupts in a multi-core SoC without Hypervisor hard isolation. Background Technology
[0002] Currently, storage devices in in-vehicle infotainment systems, such as SSDs (Solid State Drives), support SR-IOV (Single Root I / O Virtualization). SR-IOV allows a single PCIe (Peripheral Component Interconnect Express) physical device (PF) to be presented as multiple virtual devices (VFs), improving I / O performance and efficiency in a virtualized environment. When using a hypervisor, each virtual machine (VM) accesses a designated VF on the SSD. Once a VF completes a read / write operation, it triggers an MSI (Message Signaled Interrupt) interrupt. The hypervisor then responds to the interrupt and redistributes the interrupt to the corresponding VM.
[0003] However, in hardware-isolated multi-core SoC systems, there is no Hypervisor layer. There is physical isolation, address space isolation, and interrupt routing isolation between different hardware domains. PCIe interrupts cannot be directly distributed across hardware domains. Although the NVMe driver of the hardware domain can determine whether the SSD's VF has completed read and write operations through polling, if the polling interval is too small, it will waste CPU computing resources. If the interval is too large, it may cause data to not be processed in time.
[0004] Therefore, how to ensure that the hardware domain can access the storage device in a timely and accurate manner in a hard-isolated system, while avoiding the waste of CPU computing resources, is a problem that needs to be solved by existing technologies. Summary of the Invention
[0005] The purpose of this application is to provide a method for handling message signal interruptions and an on-chip system, so as to solve the problem that the prior art may cause waste of CPU computing resources or cause data to not be processed in a timely manner by polling.
[0006] The technical solution disclosed in this application is applicable to on-chip systems with no hypervisor, multiple hardware domains with hard isolation, and external SSDs that support SR-IOV.
[0007] In a first aspect, embodiments of this application provide a method for handling message signal interruptions, applied to a system-on-a-chip (SoC). The SoC includes multiple hardware domains, each hardware domain being a collection of hardware resources, and the hardware domains are hard isolated from each other. The method includes: The first hardware domain sends an access request to the corresponding virtual device in the storage device, so that the storage device generates a message signal interrupt information based on the access request; wherein, the storage device includes multiple virtual devices, and the hardware domain corresponds one-to-one with the virtual device; The second hardware domain receives information about message signal interruption sent from the storage device, and determines the first hardware domain to be sent based on the message signal interruption information. Based on the determined first hardware domain to be sent, a corresponding inter-domain communication interrupt is generated and sent to the first hardware domain.
[0008] In some embodiments, receiving information about a message signal interruption from a storage device through a second hardware domain, and determining a first hardware domain to be sent based on the message signal interruption information, includes: The system receives message signal interrupt information from the storage device through the second hardware domain and triggers a hardware interrupt based on the message signal interrupt information. In response to a hardware interrupt, the message signal interrupt information is parsed to obtain the parsing result; Based on the parsing results, determine the first hardware domain to be sent.
[0009] In some embodiments, based on a determined first hardware domain to be pre-sent, generating a corresponding inter-domain communication interrupt and sending the inter-domain communication interrupt to the first hardware domain includes: Based on the determined first hardware domain to be sent, a corresponding inter-domain communication interrupt is generated; Inter-domain communication interrupts are sent to the first hardware domain via inter-domain communication.
[0010] In some embodiments, after sending an inter-domain communication interruption to a first hardware domain, the method includes: In response to an inter-domain communication interruption, the first hardware domain checks the status of the execution result of the access command corresponding to the access request in the completion queue.
[0011] In some embodiments, sending an access request to the corresponding virtual device in the storage device through a first hardware domain includes: The access command is written into the first queue through the first hardware domain, and the access command is written into the address space corresponding to the first hardware domain; In response to an access command being written to the address space, a corresponding transaction layer data packet is generated; Send transaction layer data packets to the corresponding virtual device in the storage device.
[0012] In some embodiments, writing the access command into the address space corresponding to the first hardware domain includes: Write the access command to the fixed offset address of the space corresponding to the first hardware domain; A fixed offset address in the address space maps access commands to the corresponding address space.
[0013] In some embodiments, the transaction layer data packet includes the target memory address, and the access command includes address data of the first hardware domain; And, sending transaction layer data packets to the corresponding virtual device in the storage device, including: The transaction layer data packet is sent to the corresponding virtual device in the storage device, so that the storage device can obtain the address data of the first hardware domain from the first queue, send the obtained address data of the first hardware domain to the target memory at the target memory address, and write the execution result of the access command to the completion queue.
[0014] In some embodiments, before sending an access request to the corresponding virtual device in the storage device through the first hardware domain, the method further includes: During system-on-chip initialization, the corresponding virtual device message data is configured according to the interrupt vector of the message signal interrupt pre-assigned to each hardware domain.
[0015] Secondly, embodiments of this application provide a system-on-a-chip, including multiple hardware domains, each hardware domain being a collection of hardware resources, and the hardware domains being hard isolated from each other; The first hardware domain is configured to send an access request to the corresponding virtual device in the storage device, so that the storage device generates a message signal interrupt information based on the access request; wherein the storage device includes multiple virtual devices, and the hardware domain corresponds one-to-one with the virtual device; The second hardware domain is configured to receive information about message signal interruption sent from the storage device, and based on the message signal interruption information, determine the first hardware domain to be sent; based on the determined first hardware domain to be sent, generate a corresponding inter-domain communication interrupt, and send the inter-domain communication interrupt to the first hardware domain.
[0016] Thirdly, embodiments of this application provide a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the message signal interruption processing method as claimed in any one of claims 1 to 8.
[0017] The message signal interruption handling method provided in this application embodiment first sends an access request to the corresponding virtual device in the storage device through a first hardware domain, so that the storage device generates message signal interruption information based on the access request; wherein, the storage device includes multiple virtual devices, and the hardware domain corresponds one-to-one with the virtual device; then, the message signal interruption information sent from the storage device is received through a second hardware domain, and the first hardware domain to be sent is determined based on the message signal interruption information; finally, based on the determined first hardware domain to be sent, a corresponding inter-domain communication interrupt is generated, and the inter-domain communication interrupt is sent to the first hardware domain. Using the technical solution provided in this application embodiment, in a multi-hardware domain scenario, the MSI interrupt request can be redistributed through an internal inter-domain communication mechanism, accurately and quickly sending the storage device MSI interrupt message to each hardware domain, ensuring that the hardware domain completes access to the storage device in a timely and accurate manner, avoiding waste of CPU computing resources. At the same time, the storage device MSI interrupt message can be accurately and quickly sent to each hardware domain, avoiding excessive hardware processing burden on the hardware domain. Attached Figure Description
[0018] Figure 1 This is a flowchart illustrating a message signal interruption handling method provided in an embodiment of this application. Figure 2 This is a flowchart illustrating step S200 in an embodiment of this application; Figure 3 This is a flowchart illustrating step S300 in an embodiment of this application; Figure 4 This is a flowchart illustrating step S100 in an embodiment of this application; Figure 5 This is a flowchart illustrating another message signal interruption handling method provided in an embodiment of this application. Detailed Implementation
[0019] Various embodiments and features of this application are described herein with reference to the accompanying drawings.
[0020] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this application will be apparent to those skilled in the art.
[0021] Before providing a detailed description of the embodiments of this application, the full names and Chinese names of the proprietary technology names / abbreviations involved in the embodiments of this application will be explained first, as shown in Table 1.
[0022] Table 1. Full and Chinese Names of Proprietary Technology Names / Abbreviations
[0023] The following detailed description, with reference to the accompanying drawings, illustrates a message signal interruption handling method provided in this application embodiment. This method is applied to a system-on-a-chip (SoC), which includes multiple hardware domains. Each hardware domain is a collection of hardware resources, and the hardware domains are physically isolated from each other. Hard isolation refers to the physical isolation between hardware components or sets of hardware, ensuring the independence of each hardware component or set of hardware. The SoC in this embodiment includes multiple hardware isolation domains, such as an application domain, a security domain, a multimedia domain, and a management domain. Physical address isolation, interrupt routing isolation, and peripheral access isolation are implemented between the hardware domains.
[0024] Optionally, the system-on-a-chip (SoC) can be applied to an in-vehicle infotainment system (IVS), which may include storage devices such as eMMC (embedded flash memory) and SSD (solid-state drive). The SoC communicates with the storage device. IVS typically uses eMMC to store the operating system, applications, and user data. SSDs offer advantages over eMMC, such as higher read / write speeds, especially in random read / write performance, and the fact that they have no mechanical parts, making them more resistant to shock and vibration. Therefore, the ability to quickly and accurately distribute MSI interrupts across multiple hardware domains in an IVS system is crucial. In this application, the SSD storage device supports SR-IOV, connects to the SoC via a PCIe interface, and virtualizes multiple virtual function fields (VFs). Each hardware domain is only allowed to access its corresponding VF, forming a hardware-isolated I / O virtualization architecture.
[0025] Figure 1 This is a flowchart illustrating a message signal interruption handling method provided in an embodiment of this application. The method first sends an access request to the corresponding virtual device in the storage device through a first hardware domain, causing the storage device to generate message signal interruption information based on the access request. The storage device includes multiple virtual devices, and each hardware domain corresponds one-to-one with a virtual device. Then, the message signal interruption information sent from the storage device is received through a second hardware domain, and a first hardware domain to be pre-sent is determined based on the message signal interruption information. Finally, based on the determined first hardware domain to be pre-sent, a corresponding inter-domain communication interrupt is generated and sent to the first hardware domain. This message signal interruption handling method, in a multi-hardware-domain scenario, redistributes MSI interrupt requests through an internal inter-domain communication mechanism. Through these technical means, this solution ensures timely and accurate access to the storage device by the hardware domains in scenarios where multiple hardware domains access multiple VF devices using SSD SR-IOV technology, avoiding waste of CPU computing resources. Simultaneously, it can accurately and quickly send storage device MSI interrupt messages to each hardware domain, avoiding excessive hardware processing burden on the hardware domains.
[0026] For details, see Figure 1 As shown, the methods for handling message signal interruptions include: S100, an access request is sent to the corresponding virtual device in the storage device through the first hardware domain, so that the storage device generates a message signal interrupt information based on the access request; wherein, the storage device includes multiple virtual devices, and the hardware domain corresponds one-to-one with the virtual device; The hardware domain can include protection domains, application domains, multi-functional domains, security domains, etc. Storage devices can include eMMC, SSDs, etc. For ease of description, the following explanation uses the application domain as the hardware domain and the SSD as the storage device.
[0027] See Figure 5 As shown, multiple hardware domains can include multiple application domains. For example, multiple application domains can include application domain-1, application domain-2, application domain-3, and application domain-4. An SSD device can include multiple virtual devices. For example, multiple virtual devices can include VF1, VF2, VF3, and VF4, where application domain-1 corresponds to VF1, application domain-2 corresponds to VF2, application domain-3 corresponds to VF3, and application domain-4 corresponds to VF4.
[0028] For example, the first hardware domain is application domain-1. Application domain-1 sends an access request to the corresponding VF1 in the SSD device. The VF1 in the SSD device generates an MSI interrupt message based on the access request.
[0029] For example, the first hardware domain is application domain-4. Application domain-4 sends an access request to the corresponding VF4 in the SSD device. The VF4 in the SSD device generates an MSI interrupt message based on the access request.
[0030] S200: Receives message signal interruption information from the storage device through the second hardware domain, and determines the first hardware domain to be sent based on the message signal interruption information. The second hardware domain can be different from the first hardware domain. For example, the first hardware domain is application domain-1, and the second hardware domain is application domain-4. Application domain-1 sends an access request to the corresponding VF1 in the SSD device. The VF1 in the SSD device generates an MSI interrupt message based on the access request and sends it to application domain-4. Application domain-4 receives the MSI interrupt message from the SSD device and determines, based on the MSI interrupt message, that the application domain to be sent is application domain-1.
[0031] The second hardware domain can also be the same as the first hardware domain. For example, both the first and second hardware domains can be application domain-4. Application domain-4 sends an access request to the corresponding VF4 in the SSD device. The VF4 in the SSD device generates an MSI interrupt message based on the access request and sends it to application domain-4. Application domain-4 receives the MSI interrupt message from the SSD device and determines the application domain to be sent as application domain-4 based on the MSI interrupt message.
[0032] In this application, the system can be configured such that the second hardware domain can receive and process PCIe MSI interrupts, while the other hardware domains do not have the authority to receive PCIe MSI interrupts issued by the SSD device, in order to ensure isolation and security.
[0033] S300 generates a corresponding inter-domain communication interrupt based on the determined first hardware domain to be sent, and sends the inter-domain communication interrupt to the first hardware domain.
[0034] Inter-domain communication (also known as inter-core communication) refers to communication between different hardware domains within a system-on-a-chip. This can include asynchronous message passing via Mailbox mechanisms or cross-hardware domain data sharing via shared memory mechanisms.
[0035] Continuing with the previous example, when application domain-4 determines that the application domain to be sent is application domain-1, it generates a corresponding Mailbox interrupt and sends the Mailbox interrupt to application domain-1. When application domain-4 determines that the application domain to be sent is application domain-4, it generates a corresponding Mailbox interrupt and sends the Mailbox interrupt to application domain-4.
[0036] The message signal interrupt handling method provided in this application embodiment can ensure that the hardware domain completes access to the storage device in a timely and accurate manner, avoiding waste of CPU computing resources. Simultaneously, it can accurately and quickly send storage device MSI interrupt messages to each hardware domain, preventing excessive hardware processing burden on the hardware domains.
[0037] Optionally, see Figure 5As shown, the SSD device establishes a communication connection with the SOC through the PCIe (High-Speed Serial Computer Expansion Bus) interface. Typically, a PCIe SSD is a single physical function, but through virtualization SR-IOV technology, it can be represented as multiple virtual "avatars," similar to having multiple PCIe SSD virtual devices (VFs). PCIe VF refers to a virtual function based on the High-Speed Serial Computer Expansion Bus standard (PCIe). Currently, SSD devices support Single Root I / O Virtualization (SR-IOV), which can present a single PCIe physical device (PF) as multiple virtual devices (VFs) to improve I / O performance and efficiency in a virtualized environment.
[0038] In some embodiments, see Figure 2 As shown, the system receives message signal interruption information from the storage device through the second hardware domain, and determines the first hardware domain to be sent based on the message signal interruption information, including: S201, receives message signal interrupt information sent from the storage device through the second hardware domain, and triggers a hardware interrupt based on the message signal interrupt information; S202, in response to a hardware interrupt, parses the information of the message signal interrupt and obtains the parsing result; S203, based on the parsing results, determine the first hardware domain to be sent.
[0039] See Figure 5 As shown, the PCIe Driver of Application Domain-4 on the SOC side receives the transaction layer data packet of the MSI interrupt message sent by the SSD device, and triggers a PCIe hardware interrupt based on the transaction layer data packet of the MSI interrupt message. In response to the PCIe hardware interrupt, Application Domain-4 parses the transaction layer data packet of the MSI interrupt message through the MSI interrupt handling function, obtains the parsing result, and determines the application domain to be sent based on the parsing result.
[0040] In some embodiments, see Figure 3 As shown, based on a determined first hardware domain to be sent, a corresponding inter-domain communication interrupt is generated, and the inter-domain communication interrupt is sent to the first hardware domain, including: S301, based on the determined first hardware domain to be sent, generates a corresponding inter-domain communication interrupt; S302 sends an inter-domain communication interrupt to the first hardware domain via inter-domain communication.
[0041] Referring to Figure 2, for example, when application domain-4 determines that the application domain to be sent is application domain-1, application domain-4 generates a corresponding Mailbox interrupt and sends the Mailbox interrupt to application domain-1 via Mailbox communication. When application domain-4 determines that the application domain to be sent is application domain-4, application domain-4 generates a corresponding Mailbox interrupt and sends the Mailbox interrupt to application domain-4 via Mailbox communication.
[0042] In this embodiment, MSI interrupt message distribution responds to PCIe hardware interrupts in application domain-4, parses the transaction layer data packet of the MSI interrupt message using the MSI interrupt handling function, and then notifies the target application domain via Mailbox communication. This avoids excessive hardware processing burden on the hardware domain, ensuring timely and accurate access to the storage device while preventing waste of CPU computing resources. By using Mailbox communication instead of the traditional rpmsg method to notify the target application domain, communication load is reduced and notification speed is accelerated. In some embodiments, after sending the inter-domain communication interrupt to the first hardware domain, the method includes: In response to an inter-domain communication interruption, the first hardware domain checks the status of the execution result of the access command corresponding to the access request in the completion queue.
[0043] For example, see Figure 5 As shown, when application domain-1 receives a Mailbox interrupt, it responds to the interrupt by checking the execution status of the access command corresponding to the access request in the completion queue through the Mailbox interrupt handler function. Then, it notifies the NVMe Drive, thus completing one access operation. NVMe (Non-Volatile Memory Express) is a high-speed interface protocol designed for flash storage. The NVMe Drive is the driver for NVMe devices, responsible for communication and management between the hardware domain and the NVMe device.
[0044] In some embodiments, see Figure 4 As shown, sending an access request to the corresponding virtual device in the storage device through the first hardware domain includes: S101, the access command is written into the first queue through the first hardware domain, and the access command is written into the address space corresponding to the first hardware domain; S102, in response to the address space being written to an access command, generate the corresponding transaction layer data packet; S103, send the transaction layer data packet to the corresponding virtual device in the storage device.
[0045] Specifically, taking application domain-1 as an example, the process of application domain-1 initiating an access operation is explained. First, application domain-1 writes the access command into the first queue (the specific format follows the NVMe (Non-Volatile Memory Express) protocol) and writes the access command into the address space corresponding to application domain-1. Then, in response to the access command being written into the address space, application domain-1 generates the corresponding transaction layer data packet and sends the transaction layer data packet to the corresponding VF1 in the SSD device.
[0046] In some embodiments, writing the access command into the address space corresponding to the first hardware domain includes: Write the access command to the fixed offset address of the space corresponding to the first hardware domain; A fixed offset address in the address space maps access commands to the corresponding address space.
[0047] Specifically, each VF (Vehicle Function) in an SSD device is configured with an independent BAR (Browser Address Register). The SOC (System-on-a-Chip) configures a corresponding address space based on this BAR register. Read and write operations on this address space by the SOC generate different types of TLP (Transmission Pointer Protocol) packets, which are then sent to the corresponding VF of the SSD device. In other words, the SOC configures a fixed offset address and address space based on the BAR register of each VF, with a one-to-one correspondence between the BAR register of each VF and the fixed offset address of the SOC, and vice versa.
[0048] For example, an SSD device includes four Virtual Functions (VFs), each VF is configured with an independent BAR register, and the SOC is configured with four fixed offset addresses and four address spaces. The four BAR registers, the four fixed offset addresses, and the four address spaces correspond one-to-one.
[0049] Specifically, application domain-1 writes the access command into the first queue (the specific format follows the NVMe (Non-Volatile Memory Express) protocol) and also writes the access command to the fixed offset address corresponding to application domain-1, informing the VF1 of the SSD device to process the request. The fixed offset address maps the access command to the corresponding address space. Then, in response to the access command being written to the address space, application domain-1 generates the corresponding transaction layer data packet and sends it to the VF1 of the SSD device.
[0050] In some embodiments, the transaction layer data packet includes the target memory address, and the access command includes address data of the first hardware domain; And, sending transaction layer data packets to the corresponding virtual device in the storage device, including: The transaction layer data packet is sent to the corresponding virtual device in the storage device, so that the storage device can obtain the address data of the first hardware domain from the first queue, send the obtained address data of the first hardware domain to the target memory at the target memory address, and write the execution result of the access command to the completion queue.
[0051] Continuing with the previous example, the transaction layer data packet contains the target memory address, and the access command includes the address data of application domain-1. When application domain-1 sends the generated transaction layer data packet to VF1 of the SSD device, VFI retrieves the address data of application domain-1 from the first queue and sends the retrieved address data of application domain-1 to the target memory address via DMA (Direct Memory Access). Simultaneously, the execution result of the access command is written to the completion queue. The completion queue is a specific storage space within the SOC.
[0052] In some embodiments, before sending an access request to the corresponding virtual device in the storage device through the first hardware domain, the method further includes: During system-on-chip initialization, the corresponding virtual device message data is configured according to the interrupt vector of the message signal interrupt pre-assigned to each hardware domain.
[0053] Specifically, firstly, after the on-chip system starts up, application domain-4 completes PCIe device enumeration and SR-IOV function initialization, correctly establishes the PCIe topology, and completes the establishment of the PCIe communication link.
[0054] Then, application domain-4 completes PCIe interrupt registration and MSI function initialization, pre-allocating MSI interrupt vectors for each application domain. The MSI interrupt vector range allocated to each hardware domain is independent, fixed, and non-overlapping. It configures the interrupt message data for each VF, ensuring that the MSI interrupts generated by the VF carry the vector information of the corresponding hardware domain. Therefore, each MSI interrupt generated by each VF naturally carries the target hardware domain identifier, and the management domain (such as...) Figure 5 In the application domain-4), the target domain can be directly located via vectors, ensuring that the SSD device MSI interrupt message can be correctly parsed.
[0055] Then, each application domain completes NVMe driver initialization and registers Mailbox interrupt handler functions to handle Mailbox interrupts sent by application domain-4.
[0056] In this embodiment, the MSI interrupt pre-allocation is for scenarios with multiple VFs and multiple hardware domains. A specified number of MSI interrupt vectors are pre-allocated to each hardware domain so that the target hardware domain can be accurately and quickly located during PCIe interrupt processing.
[0057] In a specific application scenario, see Figure 5 As shown, the SOC includes 4 application domains, and the SSD device includes 4 VFs. Each of the 4 application domains corresponds one-to-one with a VF. The SSD device establishes a communication connection with the SOC through the PCIe interface. The specific process of an access operation initiated by application domain-1 of the SOC to VF1 of the SSD device is as follows: Step 1: System initialization and MSI vector pre-allocation.
[0058] After the on-chip system starts up, it is managed by the management domain (such as...) Figure 5 Application domain -4) completed.
[0059] Specifically, firstly, application domain-4 completes PCIe device enumeration and SR-IOV function initialization, correctly establishes the PCIe topology, and completes the establishment of the PCIe communication link.
[0060] Then, application domain-4 completes PCIe interrupt registration and MSI function initialization, allocating independent, fixed, and non-overlapping MSI interrupt vector ranges to each application domain; binding MSI vectors to VFs one by one; configuring the interrupt message data of each VF to ensure that the MSI generated by the VF carries the vector information of the corresponding hardware domain. Thus, the MSI interrupt generated by each VF naturally carries the target hardware domain identifier, and the management domain can directly locate the target domain through the vector, ensuring that the MSI interrupt messages of the SSD device can be correctly parsed.
[0061] Then, each application domain completes NVMe driver initialization and registers Mailbox interrupt handler functions to handle Mailbox interrupts sent by application domain-4.
[0062] Step 2: The first hardware domain (e.g., application domain-1) initiates access.
[0063] The NVMe driver in the first hardware domain initiates read and write commands.
[0064] Specifically, the NVMe of application domain-1 initiates a read I / O operation. Application domain-1 writes the read command to the first queue and also writes the read command to the fixed offset address of the BAR space of the VF1 corresponding to application domain-1, in order to notify the VF1 of the SSD device to process this request. The fixed offset address maps the read command to the corresponding address space. Then, in response to the read command being written to the address space, application domain-1 generates a corresponding transaction layer data packet and sends the transaction layer data packet to the VF1 corresponding to the SSD device. The transaction layer data packet contains the target memory address, and the read command includes the address data of application domain-1.
[0065] Then, after the SSD device's VF1 receives the transaction layer data packet, VFI retrieves the address data of application domain-1 from the first queue and sends the retrieved address data of application domain-1 to the target memory address via DMA. At the same time, it writes the execution result of the read command to the completion queue. The completion queue is a specific storage space of the SOC.
[0066] Finally, see Figure 5 As shown, after the execution result of the read command is written to the completion queue, VF1 in the SSD device generates and sends an MSI interrupt message to the application domain-1 of the SOC to notify the SOC side that the data transmission is complete.
[0067] Step 3: Manage the domain (e.g., Figure 5 Application Domain-4) Unified reception of MSI interrupts.
[0068] All MSI interrupts generated by VF are routed to the management domain and trigger PCIe hardware interrupts.
[0069] In the interrupt service routine, the management domain reads the MSI message and interrupt vector number, uniquely determines the target hardware domain according to the preset vector-hardware domain mapping relationship, and completes the ACK and clear of the MSI interrupt.
[0070] Specifically, in the SSD device, VF1 responds by writing the execution result of the read command to the completion queue, generates a transaction layer data packet of the MSI interrupt message, and sends it to the PCIe Driver of application domain-4. Based on the transaction layer data packet of the MSI interrupt message, the PCIe Driver triggers a PCIe hardware interrupt. In response to the PCIe hardware interrupt, application domain-4 parses the transaction layer data packet of the MSI interrupt message through the MSI interrupt handling function, obtains the parsing result, and determines the application domain to be sent based on the parsing result.
[0071] Step 4: MSI interrupt is converted to Mailbox hardware interrupt.
[0072] Based on the parsing results, the management domain generates a hardware Mailbox interrupt for the target hardware domain, which is then sent directly to the first hardware domain (such as application domain-1) through the on-chip system hardware routing mechanism, without the need for software forwarding, CPU copying, or shared memory traversal.
[0073] This application uses hardware Mailbox interrupts instead of software messages such as rpmsg, which features low latency, hardware triggering, hardware routing, and no CPU usage.
[0074] Step 5: The first hardware domain (e.g., application domain-1) responds to the interrupt and completes the processing queue.
[0075] Upon receiving the Mailbox interrupt, Application Domain-1 enters the interrupt service routine, directly reads the corresponding completion queue, obtains the command execution result, and notifies the NVMe driver to complete the I / O operation. The entire process requires no polling; the CPU is only awakened when actual processing is needed.
[0076] Specifically, when application domain-4 determines that the application domain to be sent is application domain-1, a corresponding Mailbox interrupt is generated, and the Mailbox interrupt is sent to application domain-1 through Mailbox communication.
[0077] When application domain-1 receives a Mailbox interrupt, it responds to the Mailbox interrupt and checks the status of the execution result of the access command corresponding to the access request in the completion queue through the Mailbox interrupt handler function. Then it notifies NVMeDrive, thus completing a read operation.
[0078] The key points and beneficial effects achieved by the embodiments of this application may include: First, MSI interrupt message distribution: In this embodiment of the application, the PCIe hardware interrupt is responded to in application domain-4, the MSI interrupt vector is parsed through the MSI interrupt handling function, and the target application domain is notified through Mailbox.
[0079] Second, MSI interrupt pre-allocation: In this application embodiment, for scenarios with multiple VFs and multiple application domains, a specified number of MSI vectors are pre-allocated to each application domain, which can accurately and quickly find the target application domain during PCIe interrupt processing.
[0080] Third, Mailbox interruption accelerates notification: When using Mailbox to notify the target application domain, instead of using the traditional rpmsg method, this application embodiment reduces communication load and speeds up notification by using Mailbox interruption.
[0081] Compared with the prior art, the embodiments of this application propose an MSI interrupt message processing method for multiple hardware domains of an SOC to access multiple VFs of an SSD device in a hard isolation scenario. This method can not only ensure that the hardware domains complete the access to the storage device in a timely and accurate manner, but also avoid the waste of CPU computing resources, thus having high practical value.
[0082] Based on the same inventive concept, embodiments of this application also provide a system-on-a-chip (SOC), combined with Figure 5 As shown, the SOC includes multiple hardware domains, each of which is a collection of hardware resources, and the hardware domains are physically isolated from each other. The first hardware domain is configured to send an access request to the corresponding virtual device in the storage device, so that the storage device generates a message signal interrupt information based on the access request; wherein the storage device includes multiple virtual devices, and the hardware domain corresponds one-to-one with the virtual device; The second hardware domain is configured to receive information about message signal interruption sent from the storage device, and based on the message signal interruption information, determine the first hardware domain to be sent; based on the determined first hardware domain to be sent, generate a corresponding inter-domain communication interrupt, and send the inter-domain communication interrupt to the first hardware domain.
[0083] The system-on-a-chip (SoC) provided in this application includes multiple hardware domains, each a collection of hardware resources, and the hardware domains are physically isolated from each other. A first hardware domain is configured to send an access request to a corresponding virtual device in the storage device, causing the storage device to generate a message signal interrupt based on the access request. The storage device includes multiple virtual devices, and each hardware domain corresponds one-to-one with a virtual device. A second hardware domain is configured to receive the message signal interrupt information sent from the storage device and, based on the message signal interrupt information, determine the first hardware domain to be sent to. Based on the determined first hardware domain, a corresponding inter-domain communication interrupt is generated and sent to the first hardware domain. This application embodiment can, in a multi-hardware-domain scenario, redistribute MSI interrupt requests through an internal inter-domain communication mechanism, accurately and quickly sending storage device MSI interrupt messages to each hardware domain, ensuring that the hardware domains complete access to the storage device promptly and accurately, avoiding waste of CPU computing resources. Simultaneously, it can accurately and quickly send storage device MSI interrupt messages to each hardware domain, avoiding excessive hardware processing burden on each hardware domain.
[0084] In some embodiments, the system-on-a-chip (SoC) is communicatively connected to the storage device. Optionally, the storage device establishes a communication connection with the SoC via a PCIe interface.
[0085] In some embodiments, the hardware domain may include a protection domain, an application domain, a multi-function domain, a security domain, etc. Storage devices may include eMMC, SSDs, etc.
[0086] This application provides a vehicle including the system-on-a-chip as described in the above embodiments. The implementation and effects of the vehicle provided in this application can be referenced from the foregoing embodiments, and will not be repeated here.
[0087] In this application, "vehicle" can refer to "automobile," "vehicle," or "complete vehicle," or other similar terms, including general motor vehicles such as sedans, SUVs, MPVs, buses, trucks, and other freight or passenger vehicles; water transport vehicles including various boats and vessels; and aircraft, including hybrid vehicles, electric vehicles, gasoline vehicles, plug-in hybrid vehicles, fuel cell vehicles, and other alternative fuel vehicles. Hybrid vehicles refer to vehicles with two or more power sources, and electric vehicles include pure electric vehicles and range-extended electric vehicles; this application does not specifically limit their use.
[0088] This application also provides an electronic device, including a processor and a memory, wherein the memory stores an executable program, and the memory executes the executable program to perform the steps of the method described above. The implementation and effects of the electronic device provided in this application can be referred to the foregoing embodiments, and will not be repeated here.
[0089] This application also provides a storage medium carrying one or more computer programs, which, when executed by a processor, implement the steps of the method described above.
[0090] This application also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the method described above.
[0091] It should be understood that in the embodiments of this application, the processor may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
[0092] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).
[0093] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) is integrated into the processor.
[0094] It should be noted that the memories described herein are intended to include, but are not limited to, these and any other suitable types of memories.
[0095] It should also be understood that the first, second, third, fourth and various numerical designations used herein are merely for descriptive convenience and are not intended to limit the scope of this application.
[0096] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.
[0097] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.
[0098] In the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0099] Those skilled in the art will recognize that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.
[0100] In the embodiments provided in this application, it should be understood that the disclosed methods and electronic devices can be implemented in other ways. For example, the division of units is merely a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.
[0101] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0102] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0103] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.
[0104] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A method for handling message signal interruption, characterized in that, Applied to a system-on-a-chip (SoC), the SoC includes multiple hardware domains, each hardware domain being a collection of hardware resources, and the hardware domains are hard isolated from each other. The method includes: An access request is sent to the corresponding virtual device in the storage device through the first hardware domain, so that the storage device generates a message signal interruption information based on the access request; wherein, the storage device includes multiple virtual devices, and the hardware domain corresponds one-to-one with the virtual device; The second hardware domain receives information about the interruption of the message signal sent from the storage device, and determines the first hardware domain to be sent based on the information about the interruption of the message signal. Based on the determined first hardware domain to be sent, a corresponding inter-domain communication interrupt is generated and the inter-domain communication interrupt is sent to the first hardware domain.
2. The method according to claim 1, characterized in that, Receive information about the message signal interruption sent from the storage device through the second hardware domain, and determine the first hardware domain to be sent based on the message signal interruption information, including: The second hardware domain receives the message signal interrupt information sent from the storage device and triggers a hardware interrupt based on the message signal interrupt information. In response to the hardware interrupt, the information of the message signal interrupt is parsed to obtain the parsing result; Based on the parsing results, the first hardware domain to be sent is determined.
3. The method according to claim 1, characterized in that, Based on a determined first hardware domain to be pre-sent, a corresponding inter-domain communication interrupt is generated, and the inter-domain communication interrupt is sent to the first hardware domain, including: Based on the determined first hardware domain to be sent, a corresponding inter-domain communication interrupt is generated; The inter-domain communication interrupt is sent to the first hardware domain via inter-domain communication.
4. The method according to claim 1, characterized in that, After sending the inter-domain communication interrupt to the first hardware domain, the method includes: In response to an interruption in inter-domain communication, the first hardware domain checks the status of the execution result of the access command corresponding to the access request in the completion queue.
5. The method according to claim 1, characterized in that, Sending an access request to the corresponding virtual device in the storage device through the first hardware domain includes: The access command is written into the first queue through the first hardware domain, and the access command is written into the address space corresponding to the first hardware domain; In response to the access command being written into the address space, a corresponding transaction layer data packet is generated; The transaction layer data packet is sent to the corresponding virtual device in the storage device.
6. The method according to claim 5, characterized in that, Writing the access command into the address space corresponding to the first hardware domain includes: Write the access command to the fixed offset address of the space corresponding to the first hardware domain; The fixed offset address in the space maps the access command to the corresponding address space.
7. The method according to claim 5, characterized in that, The transaction layer data packet includes the target memory address, and the access command includes the address data of the first hardware domain; And, sending the transaction layer data packet to the corresponding virtual device in the storage device includes: The transaction layer data packet is sent to the corresponding virtual device in the storage device, so that the storage device obtains the address data of the first hardware domain from the first queue, sends the obtained address data of the first hardware domain to the target memory of the target memory address, and writes the execution result of the access command into the completion queue.
8. The method according to claim 1, characterized in that, Before sending an access request to the corresponding virtual device in the storage device through the first hardware domain, the method further includes: During the initialization of the on-chip system, the corresponding virtual device message data is configured according to the interrupt vector of the message signal interrupt pre-assigned to each hardware domain.
9. A system-on-a-chip, characterized in that, It includes multiple hardware domains, each of which is a collection of hardware resources, and the hardware domains are physically isolated from each other. The first hardware domain is configured to send an access request to the corresponding virtual device in the storage device, so that the storage device generates a message signal interruption information based on the access request; wherein the storage device includes multiple virtual devices, and the hardware domain corresponds one-to-one with the virtual devices; The second hardware domain is configured to receive information about the message signal interruption sent from the storage device, and based on the information about the message signal interruption, determine the first hardware domain to be sent; based on the determined first hardware domain to be sent, generate a corresponding inter-domain communication interruption, and send the inter-domain communication interruption to the first hardware domain.
10. A computer program product comprising a computer program / instructions that, when executed by a processor, implement the steps of the message signal interruption processing method as described in any one of claims 1 to 8.