Gain amplifier circuit with self-zeroing and level shifting function and electronic device

Abstract

The application provides a gain amplifier circuit with self-zeroing and level shifting functions and electronic equipment, and relates to the technical field of integrated circuits. Two groups of binary weighted input capacitor arrays are connected with input ends of a fully differential operational amplifier; a programmable feedback capacitor array is connected across the output end and the input end of the fully differential operational amplifier; and a reset switch is further connected across the output end and the input end of the fully differential operational amplifier. The application realizes rail-to-rail input common-mode compatible range from ground to power supply without introducing additional area and power consumption overhead; solves the signal clipping distortion problem caused by common-mode mismatch, maximizes the effective dynamic range of the sensor signal chain; without additional auxiliary circuit, significantly improves the DC accuracy and signal-to-noise ratio of the PGA; under the full working condition of process deviation, power supply fluctuation and wide temperature range change, the amplifier always works in the linear interval, and has strong environmental adaptability and high robustness.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a gain amplifier circuit and electronic device with self-zeroing and level shifting functions. Background Technology

[0002] Using AC-coupled capacitors can effectively isolate DC common-mode components and eliminate the direct influence of input common-mode voltage on the operating point of the PGA. It is a common solution to the problem that the input common-mode range of traditional DC-coupled PGAs is limited by the linear operating range of the amplifier and is difficult to be compatible with the wide common-mode output range of different ROICs.

[0003] However, in traditional capacitive AC-coupled PGAs, the amplifier's input common-mode level is fixed at a preset VCM reference voltage. When the common-mode component of the input signal shifts significantly due to changes in the ROIC (Read-Out Integrated Circuit) power domain, the fixed input common-mode setting still cannot guarantee the linear swing of the output and will still produce signal clipping distortion.

[0004] Therefore, a level shifting mechanism that can adaptively adjust according to the actual common-mode level of the input signal is needed to achieve compatibility with a wide range of common-mode inputs while retaining the advantages of capacitive AC coupling. Summary of the Invention

[0005] In view of the above problems, this application proposes a gain amplifier circuit and electronic device with self-zeroing and level shifting functions to overcome the shortcomings of the prior art.

[0006] In a first aspect, embodiments of this application provide a gain amplifier circuit with self-zeroing and level shifting functions, including: Two sets of binary weighted input capacitor arrays are connected to the input terminals of the fully differential operational amplifier, wherein the upper plate of each capacitor is connected to the input terminal of the fully differential operational amplifier, and the lower plate can be switched to receive the input signal, common-mode reference voltage, high reference voltage or low reference voltage through a multiplexer switch; A programmable feedback capacitor array is connected between the output and input terminals of the fully differential operational amplifier; A reset switch is also connected between the output and input terminals of the fully differential operational amplifier, and the reset switch is connected in parallel with the programmable feedback capacitor array. When the reset switch is closed, the gain amplifier circuit is in self-zeroing and reset phase operation mode; when the reset switch is open, the gain amplifier circuit is in signal amplification phase operation mode, and in single-ended input mode, the binary weighted input capacitor array connected to the negative terminal is multiplexed into a capacitive digital-to-analog converter to generate a programmable level shift voltage.

[0007] Optionally, when the reset switch is closed, the lower plate of each capacitor is connected to the common-mode reference voltage via the multiplexer switch, the fully differential operational amplifier is configured in unity-gain feedback mode, and the offset voltage of the fully differential operational amplifier is stored in the programmable feedback capacitor array. When the reset switch is opened or closed, depending on whether the input signal is a differential input signal or a single-ended input signal, the multiplexer is used to connect the lower plate of each capacitor in the two sets of binary weighted input capacitor arrays to the input signal, the high reference voltage, or the low reference voltage. The fully differential operational amplifier is configured to gain amplification mode to perform programmable gain amplification on the input signal.

[0008] Optionally, when the reset switch is open or closed, if the input signal is the differential input signal, the lower plate of each capacitor in the binary weighted input capacitor array connected to the positive terminal is connected to the positive differential input signal via the multiplexer, and the lower plate of each capacitor in the binary weighted input capacitor array connected to the negative terminal is connected to the negative differential input signal. The fully differential operational amplifier is configured to a gain amplification state to perform programmable gain amplification on the differential input signal. The input terminals of the fully differential operational amplifier include positive and negative terminals. When the reset switch is open or closed, if the input signal is the single-ended input signal, the lower plate of each capacitor in the binary weighted input capacitor array connected to the positive terminal is connected to the single-ended input signal through the multiplexing switch. The binary weighted input capacitor array connected to the negative terminal is multiplexed into a capacitive digital-to-analog converter. By controlling the lower plate of each capacitor to switch to the high reference voltage or the low reference voltage, the programmable level shift voltage is generated. When the programmable level-shift voltage is configured to match the DC common-mode component of the single-ended input signal, the fully differential amplifier converts the single-ended input signal into a corresponding differential output. The magnitude of the programmable level shift voltage is determined by a digital control code.

[0009] Optionally, when the fully differential operational amplifier is configured in the unity-gain feedback state, the actual offset of the input virtual ground node of the fully differential operational amplifier is:

[0010] In the above formula, V OS The offset voltage is Av, and the open-loop gain of the fully differential operational amplifier is Av.

[0011] Optionally, if the input signal is the differential input signal, then the differential output voltage of the fully differential operational amplifier can be expressed as:

[0012] In the above formula, V IP V IN For the differential input signal, V OP V ON The output differential signal of the fully differential operational amplifier is... This represents the total capacitance of the two sets of binary weighted input capacitor arrays. The capacitance value of the programmable feedback capacitor array. This refers to the closed-loop voltage gain of the fully differential operational amplifier. When the gain amplifier circuit is in the self-zeroing and reset phase operating state, the offset voltage is stored in the programmable feedback capacitor array, and the offset error in the output differential signal of the fully differential operational amplifier is canceled out.

[0013] Optionally, if the input signal is the differential input signal, then the differential output voltage of the fully differential operational amplifier can be expressed as:

[0014] In the above formula, V IP V is the single-ended input signal. OP V ON The output differential signal of the fully differential operational amplifier is... This represents the total capacitance of the two sets of binary weighted input capacitor arrays. The capacitance value of the programmable feedback capacitor array. This is the closed-loop voltage gain of the fully differential operational amplifier, V. CDAC The programmable level shift voltage.

[0015] Optionally, the programmable level shift voltage V CDAC Satisfy the following formula:

[0016] In the above formula, V RH For the high reference voltage, V RL For the aforementioned low reference voltage, D is an n-bit digital control code, b iThis is the i-th binary control bit.

[0017] Optionally, the n-bit digital control code is dynamically adjusted by the off-chip monitoring module based on the histogram distribution of the output code of the back-end analog-to-digital converter. The off-chip monitoring module detects whether there is a cutoff or common-mode offset in the output code of the back-end analog-to-digital converter by analyzing the histogram distribution, and the adaptive control logic updates the n-bit digital control code based on the detection result. The n-bit digital control code enables the programmable level-shifting voltage V CDAC The minimum adjustment step size is (V RH V RL ) / 2 n .

[0018] Optionally, the capacitance value of the programmable feedback capacitor array ranges from 2. N 2 C to 2 N C, where N represents the number of feedback capacitors in the programmable feedback capacitor array, and C represents the capacitance value of a single feedback capacitor; By controlling the number of feedback capacitors connected to the programmable feedback capacitor array and switching their overall capacitance values, the closed-loop voltage gain of the fully differential operational amplifier can be programmably adjusted.

[0019] Secondly, embodiments of this application provide an electronic device, which includes a gain amplifier circuit with self-zeroing and level shifting functions as described in any of the first aspects.

[0020] The gain amplifier circuit with self-zeroing and level shifting functions proposed in this application has two sets of binary weighted input capacitor arrays, which are respectively connected to the input terminal of the fully differential operational amplifier. The upper plate of each capacitor is connected to the input terminal of the fully differential operational amplifier, and the lower plate can be switched to the input signal, common-mode reference voltage, high reference voltage or low reference voltage through a multiplexer switch.

[0021] A programmable feedback capacitor array is connected between the output and input terminals of the fully differential operational amplifier. A reset switch is also connected between the output and input terminals of the fully differential operational amplifier, and the reset switch is connected in parallel with the programmable feedback capacitor array. When the reset switch is closed, the gain amplifier circuit is in self-zeroing and reset phase operation mode; when the reset switch is open or closed, the gain amplifier circuit is in signal amplification phase operation mode. In single-ended input mode, the binary weighted input capacitor array connected to the negative terminal is multiplexed as a capacitive digital-to-analog converter to generate a programmable level-shift voltage.

[0022] This application proposes a programmable gain amplifier circuit that combines self-zeroing technology with adaptive capacitive level shifting. By multiplexing the input sampling capacitor array on the PGA side into an n-bit capacitive digital-to-analog converter (CDAC), it achieves rail-to-rail input common-mode compatibility from ground to power supply without introducing additional area or power consumption overhead. This innovative design, which multiplexes the input sampling capacitor array into an n-bit CDAC, has no additional circuitry, area, or power consumption overhead, perfectly adapts to a wide range of common-mode outputs from different manufacturers and process nodes of ROICs, completely solves the signal clipping distortion problem caused by common-mode mismatch, and maximizes the effective dynamic range of the sensor signal chain.

[0023] The built-in periodic self-zeroing mechanism enables a highly integrated self-zeroing noise reduction design, eliminating the need for additional auxiliary circuits. Utilizing the amplifier's own unity-gain feedback state, it stores and eliminates offset voltage and low-frequency noise before each sampling period, significantly improving the PGA's DC accuracy and signal-to-noise ratio, meeting the stringent requirements of high-precision sensor front-end signal conditioning. A programmable feedback capacitor array provides wide-range adjustable gain, dynamically configuring the optimal gain level based on the front-end ROIC output signal swing, maximizing the dynamic range utilization of the back-end ADC. It also natively supports both fully differential and single-ended input modes, directly adapting to the output interfaces of different front-end sensors without additional interface conversion circuits, enhancing its flexibility across various scenarios. The high resolution of the n-bit CDAC ensures accurate common-mode compensation under PVT fluctuations. Combined with the closed-loop adaptive control of the back-end ADC, the amplifier maintains operation within the linear range under various operating conditions, including process deviations, power supply fluctuations, and wide temperature variations, exhibiting strong environmental adaptability and high robustness across all operating conditions. Therefore, the gain amplifier circuit proposed in this application has broad application prospects and high practicality. Attached Figure Description

[0024] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a circuit structure diagram of a gain amplifier circuit with self-zeroing and level shifting functions according to an embodiment of this application; Figure 2 This is a simplified circuit diagram illustrating the circuit states of a gain amplifier circuit with self-zeroing and level shifting functions under various operating phases, according to an embodiment of this application. Figure 2 (a) shows the circuit state for self-zeroing and reset phase. Figure 2 (b) represents the signal amplification phase when using a fully differential input. Figure 2 (c) represents the signal amplification phase when the input is single-ended; Figure 3 This is a preferred timing diagram of a gain amplifier circuit with self-zeroing and level shifting functions exemplified in the embodiments of this application; Figure 4 This application describes the working principle of a gain amplifier circuit with self-zeroing and level shifting functions, exemplified in the embodiments of this application, in achieving adaptive level shifting in a single-ended input scenario. Detailed Implementation

[0025] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0026] The inventors discovered that in the front-end readout integrated circuit system of sensors such as Infrared Focal Plane Arrays (IRFPAs), the PGA is a key circuit module connecting the sensor's analog output to the back-end Analog-to-Digital Converter (ADC). Its core function is to perform programmable gain amplification on the weak analog signal output by the sensor, so as to fully utilize the dynamic range of the back-end ADC and thus achieve high-precision signal acquisition.

[0027] However, in practical applications, the DC common-mode voltage (VCM) of ROIC output signals from different manufacturers or different process nodes often varies significantly, potentially covering a wide range from ground potential to power supply voltage. The input common-mode range of traditional DC-coupled PGAs is limited by the amplifier's linear operating range, making it difficult to be compatible with the wide common-mode output range of different ROICs. When the ROIC output common-mode voltage deviates from the PGA's optimal operating point, the differential output swing will be severely compressed, leading to signal clipping distortion and a significant reduction in the dynamic range of the entire signal chain.

[0028] Using capacitive AC coupling can effectively isolate DC common-mode components and eliminate the direct impact of input common-mode voltage on the PGA operating point, making it a common solution to the aforementioned problems. However, further research by the inventors revealed that in traditional AC-coupled PGAs, the amplifier's input common-mode level is fixed at a preset VCM reference voltage. When the common-mode component of the input signal shifts significantly due to changes in the ROIC power domain, the fixed input common-mode setting still cannot guarantee a linear output swing and will still produce signal clipping distortion. Therefore, a level-shifting mechanism that can adaptively adjust according to the actual common-mode level of the input signal is needed to achieve compatibility with a wide range of common-mode inputs while retaining the advantages of capacitive AC coupling.

[0029] Furthermore, the inventors discovered that practical operational amplifiers exhibit offset voltage (VOS). This offset is amplified by the gain and superimposed on the effective signal, causing systematic errors in the ADC output and thus limiting the dynamic range of the entire signal chain. Eliminating the offset voltage, thereby suppressing offset errors and low-frequency noise, is also a pressing problem that needs to be solved.

[0030] To address the aforementioned problems, the inventors, through extensive research, have creatively proposed a gain amplifier circuit and electronic device with self-zeroing and level shifting functions, as described in this application. The technical solution of this application is explained and described in detail below.

[0031] This application discloses a gain amplifier circuit with self-zeroing and level shifting functions, referring to... Figure 1 The circuit diagram shown includes: two sets of binary weighted input capacitor arrays, a fully differential operational amplifier, and a programmable feedback capacitor array.

[0032] Two sets of binary weighted input capacitor arrays are connected to the input terminals of the fully differential operational amplifier (OP). Specifically, one set of binary weighted input capacitor arrays is connected to the positive terminal of the OP, and the other set is connected to the negative terminal. The upper plate of each capacitor in the binary weighted input capacitor array is connected to the input terminal of the OP, while the lower plate can be switched to the input signal V via a multiplexer switch. IP V IN Common-mode reference voltage V CM High reference voltage V RH or low reference voltage V RL . Figure 1 The schematic diagram shows two sets of binary weighted input capacitor arrays. Each set contains N capacitors, represented by their capacitance values: C, 2C, 4C, 8C, 16C, 32C, ... 2. N-1 C.

[0033] Programmable feedback capacitor array C F A reset switch φ is connected between the output and input terminals of the fully differential operational amplifier OP; a reset switch φ is also connected between the output and input terminals of the fully differential operational amplifier OP. R Reset switch φ R With programmable feedback capacitor array C F Parallel connection; wherein, in the reset switch φ R When closed, the gain amplifier circuit is in self-zeroing and reset phase operation; at the reset switch φ R When the circuit is open, the gain amplifier circuit is in the signal amplification phase operating state, and in single-ended input mode (i.e., non-differential input signal), the binary weighted input capacitor array connected to the negative terminal (i.e., Figure 1 The binary weighted input capacitor array in the lower center is multiplexed into a capacitive digital-to-analog converter (CDAC) to generate programmable level-shifted voltages.

[0034] At the reset switch φ R When closed, the lower plate of each capacitor is connected to the common-mode reference voltage V via a multiplexer switch. CM The fully differential operational amplifier OP is then configured in unity-gain feedback mode, and the offset voltage of the fully differential operational amplifier OP is stored in the programmable feedback capacitor array C. F In the middle; while during reset switching, depending on whether the input signal is a differential input signal or a single-ended input signal, a multiplexer is used to connect the lower plate of each capacitor in the two sets of binary weighted input capacitor arrays to the input signal V. IP V IN High reference voltage V RH or low reference voltage V RL The fully differential operational amplifier OP is configured in gain amplification mode, thereby enabling it to amplify the input signal V. IP V IN Perform programmable gain amplification.

[0035] Specifically, in the reset switch φ R When opening and closing, if the input signal is a differential input signal V IP V IN Then, by using a multiplexer, the lower plate of each capacitor in the binary weighted input capacitor array connected to the positive terminal is connected to the positive differential input signal V. IP Connect the lower plate of each capacitor in the binary weighted input capacitor array connected to the negative terminal to the negative differential input signal V. IN The fully differential operational amplifier OP is configured in gain amplification mode to amplify the differential input signal V. IP V INFor programmable gain amplification, the input terminals of the fully differential operational amplifier (OP) include positive and negative terminals.

[0036] At the reset switch φ R When opening and closing, if the input signal is a single-ended input signal V IP Then, by using a multiplexer, the lower plate of each capacitor in the binary weighted input capacitor array connected to the positive terminal is connected to the single-ended input signal V. IP The binary weighted input capacitor array connected to the negative terminal is multiplexed into a capacitive digital-to-analog converter, and the lower plate of each capacitor is switched to a high reference voltage V by controlling the connection. RH or low reference voltage V RL This generates a programmable level-shift voltage; wherein, the programmable level-shift voltage is configured to interact with the single-ended input signal V. IP When the DC common-mode components are matched, the fully differential amplifier OP will convert the single-ended input signal V IP It is converted into the corresponding differential output; the magnitude of the programmable level shift voltage is determined by the digital control code.

[0037] Reference Figure 2 The diagram shown illustrates the circuit state of the programmable gain amplifier at each operating phase. Figure 2 (a) shows the circuit state for self-zeroing and reset phase. Figure 2 (b) represents the signal amplification phase when using a fully differential input. Figure 2 (c) represents the signal amplification phase when the input is single-ended.

[0038] like Figure 2 (a) shows the self-zeroing and reset phases, and the reset switch. Close the circuit, configuring the fully differential amplifier OP to unity-gain feedback mode. The lower plates of both input capacitor arrays are connected to the common-mode reference voltage V. CM At this time, the two sampling capacitors C IN (That is, the potential of the upper plate node in the two sets of binary weighted input capacitor arrays) is established at V CM Nearby, the offset voltage of the fully differential amplifier op... Stored in the feedback capacitor C F Above. Because the fully differential amplifier OP is in a deep negative feedback state, the actual offset of the input virtual ground node is only... Where Av is the open-loop gain of the fully differential amplifier OP, a value that is small enough to be approximately negligible. This process effectively eliminates amplifier offset and low-frequency noise.

[0039] The capacitance value of the programmable feedback capacitor array ranges from 2. N 2 C to 2 NC, where N represents the number of feedback capacitors in the programmable feedback capacitor array, and C represents the capacitance value of a single feedback capacitor; by controlling the number of feedback capacitors connected to the programmable feedback capacitor array, the overall capacitance value is switched, thereby enabling programmable adjustment of the closed-loop voltage gain of the fully differential operational amplifier OP.

[0040] like Figure 2 (b) The signal amplification phase of the fully differential input, and the reset switch. Disconnect, differential input signal V IP With V IN The lower plates of the capacitors in the two sets of binary weighted input capacitor arrays are connected respectively. According to the principle of charge conservation, the differential output voltage of the fully differential operational amplifier OP can be expressed as:

[0041] In the above formula, V IP V IN For differential input signals, V OP V ON The output differential signal of the fully differential operational amplifier (OP) is... This represents the total capacitance of the two sets of binary weighted input capacitor arrays. The capacitance value is for the programmable feedback capacitor array. This is the closed-loop voltage gain of the fully differential operational amplifier OP. When the gain amplifier circuit is in the self-zero and reset phase operating state, the offset voltage has been stored in the programmable feedback capacitor array. Therefore, the offset error in the output differential signal of the fully differential operational amplifier OP is effectively canceled, and the accuracy of the output signal is guaranteed.

[0042] like Figure 2 (c) shows the single-ended input signal amplification phase and the reset switch. Disconnect, single-ended input signal V IP The lower plate of the binary weighted input capacitor array connected to the positive terminal of the fully differential operational amplifier (OP) is connected to the MOSFET. Unlike the fully differential input mode, the binary weighted input capacitor array connected to the negative terminal of the fully differential operational amplifier (OP) is multiplexed into an n-bit capacitor-type DAC (i.e., an n-bit binary weighted CDAC). This is achieved by controlling the connection of the lower plate of each capacitor in the capacitor array to V. RH or V RL Generate programmable level-shift voltage Programmable level shift voltage V CDAC Satisfy the following formula:

[0043] In the above formula, V RH For high reference voltage, VRL For low reference voltage, D is an n-bit digital control code, b i This is the i-th binary control bit.

[0044] The n-bit digital control code is dynamically adjusted by an external monitoring module based on the histogram distribution of the output code of the back-end analog-to-digital converter. Specifically, the external monitoring module analyzes the histogram distribution to detect whether there is clipping or common-mode offset in the output code of the back-end analog-to-digital converter, and the adaptive control logic updates the n-bit digital control code based on the detection results. The n-bit digital control code enables the programmable level-shifting voltage V. CDAC The minimum adjustment step size is (V RH V RL ) / 2 n .

[0045] That is: when the level shift voltage generated by the CDAC Configured to work with a single-ended input signal V IP When the DC common-mode components are matched, the fully differential amplifier OP is equivalent to converting the single-ended input signal V... IP It is converted to a differential output, while effectively eliminating the input signal V. IP The common-mode DC component affects the output swing. This characteristic allows the differential output to be maintained within the optimal linear operating range by adjusting the n-bit CDAC control code, regardless of whether the common-mode voltage bias of the ROIC output signal is near ground potential, power supply midpoint, or power supply voltage, thus achieving full rail-to-rail input common-mode compatibility. The n-bit resolution makes the minimum adjustment step size of the CDAC (V...) RH V RL ) / 2 n This is sufficient to maintain accurate common-mode compensation under varying process, voltage, and temperature (PVT) conditions. Similarly, when the gain amplifier circuit is in self-zeroing and reset phase operation, the offset voltage is already stored in the programmable feedback capacitor array C. F Therefore, the offset error in the output differential signal of the fully differential operational amplifier (OP) is effectively canceled, ensuring the accuracy of the output signal. Furthermore, since the CDAC reuses the original binary weighted input capacitor array, there is no need to introduce an additional level shifting circuit module, thus avoiding any area and power consumption overhead.

[0046] Reference Figure 3 The diagram shown represents a preferred operating timing diagram, with the reset switch... During the high-level period (i.e., when the reset switch is closed), the gain amplifier circuit is in self-zero and reset phase, and the offset of the fully differential operational amplifier is stored in the feedback capacitor C. F Above, the output V OP and V ON All stabilized at the common-mode potential. At the reset switch... During the low-level period (i.e., when the reset switch is off), the gain amplifier circuit enters the signal amplification phase, and the differential output V... OP and V ON Differential oscillation is performed on the input signal to achieve programmable gain amplification of the input signal.

[0047] Reference Figure 4 The diagram illustrates the complete system operating principle of a gain amplifier circuit with self-zeroing and level shifting functions, demonstrating adaptive level shifting in a single-ended input scenario. Figure 4 The example shown is an 8-bit capacitor-type DAC. The output signal V of the front-end ROIC driver circuit is... IN via capacitor C IN The input is sent to the PGA, while the 8-bit capacitive DAC integrated in the negative input path operates according to the control code. A level-shifted voltage is generated and injected into the negative virtual ground node of the PGA.

[0048] Figure 4 The three sets of diagrams on the right illustrate three typical input common-mode scenarios: when the input signal V IN When the common-mode level is near the power supply voltage VDD ( =11111111), the CDAC generates the highest level shift voltage, shifting the effective input differential of the PGA to the linear amplification range, V OP and V ON ( Figure 4 China V OUT =V OP -V ON All can swing differentially normally; when the input common-mode level is at the power supply midpoint ( =10000000), the CDAC generates a moderate level shift, and the output remains normal; when the input common-mode level is near the ground potential ( =00000000), the CDAC generates the lowest level shift voltage, and the differential output of the PGA can also swing normally within the linear range. In all three cases, the output exhibits a normal differential waveform without clipping distortion, verifying the ability of the gain amplifier circuit with self-zeroing and level shifting functions proposed in this application to achieve full rail-to-rail input common-mode compatibility.

[0049] It is important to emphasize that although self-zeroing technology has been applied in other circuit structures, and the structure of connecting the positive and negative terminals of an operational amplifier with binary weighted capacitor arrays is documented in existing PGA designs, those skilled in the art have consistently failed to creatively combine the two when faced with the aforementioned application scenarios, let alone propose a technical solution to reuse the negative input capacitor array as a capacitive digital-to-analog converter. The reason for this lies in the following deeply ingrained technical biases and cognitive barriers within this field: First, there is an inherent bias in functional positioning: In the traditional PGA design paradigm, the input capacitor array is strictly defined as a "sampling element," whose sole function is to linearly sample the input signal, with a clear functional boundary between it and functions such as signal conversion and level generation. Those skilled in the art have long followed the design convention that "sampling capacitors are only used for sampling," and do not associate them with the core function of a DAC—that is, generating an analog output through the weighted superposition of reference voltages. This inherent bias in functional positioning makes it difficult to naturally propose the technical idea of ​​"multiplexing the sampling capacitor array into a CDAC."

[0050] Secondly, the design constraint of differential symmetry: In traditional designs, the positive and negative capacitor arrays of a fully differential operational amplifier are considered strictly symmetrical functional units, and they should perform exactly the same signal processing roles to ensure the common-mode rejection performance of the differential circuit. Those skilled in the art generally believe that applying differentiated control to the negative capacitor array (such as connecting V...) RH or V RL Instead of the input signal, this will disrupt the circuit's symmetry, introduce common-mode error, and consequently impair the differential amplifier's fundamental performance. This understanding forms a technical barrier hindering the aforementioned multiplexing schemes.

[0051] Third, there are concerns about charge management during mode switching: the implementation of self-zeroing technology relies on accurately storing the amplifier offset voltage on the feedback capacitor during the reset phase. If the CDAC function is introduced at the same time, the charge distribution relationship of the negative capacitor array under different operating phases will become complicated. Those skilled in the art are usually concerned about the interference between the offset compensation amount stored in the self-zeroing stage and the CDAC charge amount injected in the level shifting stage, which would lead to the two functions being coupled together and the accuracy decreasing. Therefore, they tend to use independent modules to implement the above two functions separately, rather than reusing them in the same structure.

[0052] Fourth, the conventional simplification of single-ended mode masks its actual cost: In the traditional capacitor-based PGA single-ended input configuration, the lower plate of the negative capacitor array is uniformly connected to a fixed common-mode level V. CMThis is the most common approach, with a simple circuit structure and low implementation cost, which discourages those skilled in the art from further examining whether there are better ways to utilize the negative-end capacitor array. However, this conventional approach has a significant practical cost in multi-channel signal acquisition systems: when the input common-mode levels of different channels differ, a separate common-mode bias circuit or level shifting module needs to be configured for each channel. The more channels there are, the more significant the area and power consumption overhead becomes, and the more difficult the system integration becomes. This "inertial dependence on simple solutions" further obscures the technical possibility of using multiplexed negative-end capacitor arrays to achieve adaptive level shifting.

[0053] Fifth, the conventional independent modular design mindset: In signal chain design, the PGA and level shifter circuits have traditionally been designed and implemented as independent modules, with clear circuit boundaries between them. Faced with the requirement of wide common-mode input compatibility, the usual approach for those skilled in the art is to add a dedicated level shifter circuit module before or after the PGA, rather than seeking functional reuse from the existing capacitor structure within the PGA. This modular design convention constitutes a hidden obstacle to creative thinking.

[0054] In view of this, after in-depth analysis of the working state of the negative-end capacitor array in single-ended input mode, the inventors of this application creatively discovered that: in single-ended input mode, the negative-end binary weighted input capacitor array does not undertake the sampling task of differential signal during signal amplification phase, and it is in a functional "idle" state; and the binary weighted topology of this array is structurally naturally compatible with the basic implementation principle of CDAC—by controlling the selective connection of the lower plate of each capacitor to a high reference voltage V RH or low reference voltage V RL This allows for precise and controllable charge injection at the negative virtual ground node, equivalent to injecting a programmable level shift into the fully differential operational amplifier without increasing circuit area or power consumption. This innovative approach breaks with traditional biases regarding functional positioning and symmetry, achieving organic unity between sampling and conversion functions on the same physical structure. Simultaneously, it completely eliminates the accumulated overhead of configuring bias circuits channel-by-channel in multi-channel systems, fundamentally solving the core problems of wide common-mode input compatibility and signal amplitude distortion at zero additional cost.

[0055] In summary, the gain amplifier circuit with self-zeroing and level shifting functions proposed in this application has two sets of binary weighted input capacitor arrays, which are respectively connected to the input terminals of the fully differential operational amplifier. The upper plate of each capacitor is connected to the input terminal of the fully differential operational amplifier, and the lower plate can be switched to receive the input signal, common-mode reference voltage, high reference voltage, or low reference voltage through a multiplexer switch.

[0056] A programmable feedback capacitor array is connected between the output and input terminals of the fully differential operational amplifier. A reset switch is also connected between the output and input terminals of the fully differential operational amplifier, and the reset switch is connected in parallel with the programmable feedback capacitor array. When the reset switch is closed, the gain amplifier circuit is in self-zeroing and reset phase operation mode; when the reset switch is open or closed, the gain amplifier circuit is in signal amplification phase operation mode. In single-ended input mode, the binary weighted input capacitor array connected to the negative terminal is multiplexed as a capacitive digital-to-analog converter to generate a programmable level-shift voltage.

[0057] This application proposes a programmable gain amplifier circuit that combines self-zeroing technology with adaptive capacitive level shifting. By multiplexing the input sampling capacitor array on the PGA side into an n-bit capacitive digital-to-analog converter (CDAC), it achieves rail-to-rail input common-mode compatibility from ground to power supply without introducing additional area or power consumption overhead. This innovative design, which multiplexes the input sampling capacitor array into an n-bit CDAC, has no additional circuitry, area, or power consumption overhead, perfectly adapts to a wide range of common-mode outputs from different manufacturers and process nodes of ROICs, completely solves the signal clipping distortion problem caused by common-mode mismatch, and maximizes the effective dynamic range of the sensor signal chain.

[0058] The built-in periodic self-zeroing mechanism enables a highly integrated self-zeroing noise reduction design, eliminating the need for additional auxiliary circuits. Utilizing the amplifier's own unity-gain feedback state, it stores and eliminates offset voltage and low-frequency noise before each sampling cycle, significantly improving the PGA's DC accuracy and signal-to-noise ratio, meeting the stringent requirements of high-precision sensor front-end signal conditioning. The programmable feedback capacitor array provides wide-range adjustable gain, dynamically configuring the optimal gain level based on the front-end ROIC output signal swing, maximizing the dynamic range utilization of the back-end ADC. It also natively supports both fully differential and single-ended input modes, directly adapting to the output interfaces of different front-end sensors without additional interface conversion circuits, enhancing its flexibility across all scenarios. The high resolution of the n-bit CDAC ensures accurate common-mode compensation under PVT fluctuations. Combined with the closed-loop adaptive control of the back-end ADC, it maintains the amplifier operating within the linear range under various operating conditions, including process deviations, power supply fluctuations, and wide temperature variations, exhibiting strong environmental adaptability and high robustness across all operating conditions. By configuring the fully differential operational amplifier to unity-gain feedback mode before the start of each sampling period through self-zeroing, the offset voltage is stored in a programmable feedback capacitor array and eliminated in subsequent amplification stages, effectively suppressing offset error and low-frequency noise. Therefore, the gain amplifier circuit proposed in this application has broad application prospects and high practicality.

[0059] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0060] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0061] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims. All of these forms are within the protection scope of this application.

Claims

1. A gain amplifier circuit with self-zeroing and level shifting functions, characterized in that, include: Two sets of binary weighted input capacitor arrays are connected to the input terminals of the fully differential operational amplifier, wherein the upper plate of each capacitor is connected to the input terminal of the fully differential operational amplifier, and the lower plate can be switched to receive the input signal, common-mode reference voltage, high reference voltage or low reference voltage through a multiplexer switch; A programmable feedback capacitor array is connected between the output and input terminals of the fully differential operational amplifier; A reset switch is also connected between the output and input terminals of the fully differential operational amplifier, and the reset switch is connected in parallel with the programmable feedback capacitor array. When the reset switch is closed, the gain amplifier circuit is in self-zeroing and reset phase operation mode; when the reset switch is open, the gain amplifier circuit is in signal amplification phase operation mode, and in single-ended input mode, the binary weighted input capacitor array connected to the negative terminal is multiplexed into a capacitive digital-to-analog converter to generate a programmable level shift voltage.

2. The gain amplifier circuit according to claim 1, characterized in that, When the reset switch is closed, the lower plate of each capacitor is connected to the common-mode reference voltage through the multiplexer switch, the fully differential operational amplifier is configured in unity-gain feedback mode, and the offset voltage of the fully differential operational amplifier is stored in the programmable feedback capacitor array. When the reset switch is opened or closed, depending on whether the input signal is a differential input signal or a single-ended input signal, the multiplexer is used to connect the lower plate of each capacitor in the two sets of binary weighted input capacitor arrays to the input signal, the high reference voltage, or the low reference voltage. The fully differential operational amplifier is configured to gain amplification mode to perform programmable gain amplification on the input signal.

3. The gain amplifier circuit according to claim 2, characterized in that, When the reset switch is open or closed, if the input signal is the differential input signal, the multiplexer switches connect the lower plate of each capacitor in the binary weighted input capacitor array connected to the positive terminal to the positive differential input signal and connect the lower plate of each capacitor in the binary weighted input capacitor array connected to the negative terminal to the negative differential input signal. The fully differential operational amplifier is configured to gain amplification mode to perform programmable gain amplification on the differential input signal. The input terminals of the fully differential operational amplifier include positive and negative terminals. When the reset switch is open or closed, if the input signal is the single-ended input signal, the lower plate of each capacitor in the binary weighted input capacitor array connected to the positive terminal is connected to the single-ended input signal through the multiplexing switch. The binary weighted input capacitor array connected to the negative terminal is multiplexed into a capacitive digital-to-analog converter. By controlling the lower plate of each capacitor to switch to the high reference voltage or the low reference voltage, the programmable level shift voltage is generated. When the programmable level-shift voltage is configured to match the DC common-mode component of the single-ended input signal, the fully differential amplifier converts the single-ended input signal into a corresponding differential output. The magnitude of the programmable level shift voltage is determined by a digital control code.

4. The gain amplifier circuit according to claim 2, characterized in that, When the fully differential operational amplifier is configured in the unity-gain feedback state, the actual offset of the input virtual ground node of the fully differential operational amplifier is: In the above formula, V OS The offset voltage is Av, and the open-loop gain of the fully differential operational amplifier is Av.

5. The gain amplifier circuit according to claim 3, characterized in that, If the input signal is the differential input signal, then the differential output voltage of the fully differential operational amplifier can be expressed as: In the above formula, V IP V IN For the differential input signal, V OP V ON The output differential signal of the fully differential operational amplifier is... This represents the total capacitance of the two sets of binary weighted input capacitor arrays. The capacitance value of the programmable feedback capacitor array. This refers to the closed-loop voltage gain of the fully differential operational amplifier. When the gain amplifier circuit is in the self-zeroing and reset phase operating state, the offset voltage is stored in the programmable feedback capacitor array, and the offset error in the output differential signal of the fully differential operational amplifier is canceled out.

6. The gain amplifier circuit according to claim 3, characterized in that, If the input signal is the differential input signal, then the differential output voltage of the fully differential operational amplifier can be expressed as: In the above formula, V IP V is the single-ended input signal. OP V ON The output differential signal of the fully differential operational amplifier is... This represents the total capacitance of the two sets of binary weighted input capacitor arrays. The capacitance value of the programmable feedback capacitor array. This is the closed-loop voltage gain of the fully differential operational amplifier, V. CDAC The programmable level shift voltage.

7. The gain amplifier circuit according to claim 3, characterized in that, The programmable level shift voltage V CDAC Satisfy the following formula: In the above formula, V RH For the high reference voltage, V RL For the aforementioned low reference voltage, D is an n-bit digital control code, b i This is the i-th binary control bit.

8. The gain amplifier circuit according to claim 7, characterized in that, The n-bit digital control code is dynamically adjusted by the off-chip monitoring module based on the histogram distribution of the output code of the back-end analog-to-digital converter. The off-chip monitoring module analyzes the histogram distribution to detect whether there is a cutoff or common-mode offset in the output code of the back-end analog-to-digital converter. The adaptive control logic updates the n-bit digital control code based on the detection results. The n-bit digital control code enables the programmable level-shifting voltage V CDAC The minimum adjustment step size is (V RH V RL ) / 2 n .

9. The gain amplifier circuit according to claim 1, characterized in that, The capacitance value of the programmable feedback capacitor array ranges from 2. N 2 C to 2 N C, where N represents the number of feedback capacitors in the programmable feedback capacitor array, and C represents the capacitance value of a single feedback capacitor; By controlling the number of feedback capacitors connected to the programmable feedback capacitor array and switching their overall capacitance values, the closed-loop voltage gain of the fully differential operational amplifier can be programmably adjusted.

10. An electronic device, characterized in that, The electronic device includes a gain amplifier circuit with self-zeroing and level shifting functions as described in any one of claims 1-9.

Images