Reconfigurable lna with high ip2 mode

Abstract

A reconfigurable amplifier with an analog subtractor is disclosed, the analog subtractor having a radio frequency (RF) output terminal (46), a non-inverting terminal (48), and a non-inverting terminal (50). A first amplifier transistor has a first current input coupled to the non-inverting terminal and a first current output coupled to a fixed voltage node (G1) forming the main path, and a first control terminal coupled to the RF input terminal (38). A second amplifier transistor has a second current input coupled to the non-inverting terminal and a second current output coupled to a fixed voltage node forming an auxiliary path, and a second control terminal coupled to the first current terminal, wherein when the auxiliary path is enabled, second-order intermodulation distortion components are canceled out by subtracting the signal in the auxiliary path from the signal in the main path.

Description

[0001] Related applications

[0002] This application claims the benefit of provisional patent application serial number 63 / 600,852, filed on November 20, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a reconfigurable low-noise amplifier that provides improved linearity. Background Technology

[0004] A mobile handheld device contains many radio components that may operate simultaneously and need to coexist. These radio components can transmit simultaneously as the handheld device attempts to receive a desired signal within the signal path. Multiple transmitter signals may experience intermodulation and generate in-band blocking signals, which will reduce the sensitivity of the receiver receiving the desired signal. In this situation, the receiver is considered the "jammed party."

[0005] The "suppressed" receiver typically uses a high-suppression filter before the low-noise amplifier (LNA) to prevent the transmitter from blocking the signal. Undesirably, the high-suppression filter needs to provide suppression of the blocking signal by essentially more than 60 dB to prevent it from reducing the sensitivity of the "suppressed" receiver through intermodulation. Such a high-suppression filter is difficult to implement and has relatively high insertion loss. Therefore, an LNA with significantly improved out-of-band linearity is still needed to allow for lower suppression requirements, which in turn allows for a relaxation of filter attenuation requirements. Summary of the Invention

[0006] A reconfigurable amplifier with an analog subtractor is disclosed, the analog subtractor having a radio frequency (RF) output terminal, a non-inverting terminal, and a non-inverting terminal. A first amplifier transistor has a first current input coupled to the non-inverting terminal and a first current output coupled to a fixed voltage node forming a main path, and a first control terminal coupled to the RF input terminal. A second amplifier transistor has a second current input coupled to the non-inverting terminal and a second current output coupled to a fixed voltage node forming an auxiliary path, and a second control terminal coupled to the first current terminal, wherein when the auxiliary path is enabled, second-order intermodulation distortion components are canceled out by subtracting the signal in the auxiliary path from the signal in the main path.

[0007] On the other hand, any of the foregoing aspects and / or the various individual aspects and features as described herein may be combined, individually or together, to obtain additional advantages. Unless otherwise indicated herein, any of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements.

[0008] Those skilled in the art will understand the scope of this disclosure and recognize its other aspects after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with embodiments, serve to explain the principles of this disclosure.

[0010] Figure 1 This is a diagram illustrating an embodiment of a reconfigurable low-noise amplifier (LNA) constructed according to this disclosure.

[0011] Figure 2A It is a graph of the input-referred second-order intercept (IIP2) as a function of the input power.

[0012] Figure 2B This is a graph of IIP2, extrapolated from P1=P1, as a function of input power.

[0013] Figure 3 This is a diagram illustrating an implementation of a reconfigurable LNA, depicting the use of an autotransformer as a... Figure 1 An exemplary structure of a simulated subtractor for the implementation scheme.

[0014] Figure 4 This is a graph of IIP2 versus the blocking signal at a given frequency of the disturbed party.

[0015] Figure 5 This is a diagram illustrating an implementation of a reconfigurable LNA that includes a phase shifter located in an auxiliary path.

[0016] Figure 6 This is a diagram illustrating an implementation of a reconfigurable LNA that includes an input matched tuner configured to provide phase shift.

[0017] Figure 7 It is a graph of IIP2 versus the blocking signal at a given frequency of the disturbed party without phase compensation or amplitude compensation.

[0018] Figure 8 This is a diagram illustrating an embodiment of a reconfigurable LNA constructed according to the present disclosure based on complementary metal-oxide-semiconductor (CMOS).

[0019] Figure 9 This is a diagram illustrating a CMOS-based implementation of a reconfigurable LNA including an additional cascode transistor according to this disclosure.

[0020] Figure 10A yes Figure 8The graphs show the performance of IIP2 and F1 in the CMOS-based implementation scheme.

[0021] Figure 10B yes Figure 8 The graph shows the noise factor (NF) versus frequency performance of the CMOS-based implementation.

[0022] Figure 10C yes Figure 8 The scattering parameter S21 versus frequency performance curve of the CMOS-based implementation scheme.

[0023] Figure 11 It is a CMOS implementation of a reconfigurable LNA that includes additional amplifier branches that are configured to be selectively enabled and disabled within an auxiliary path.

[0024] Figure 12 This is a diagram illustrating an implementation of a CMOS version of a reconfigurable LNA that includes an input matched tuner configured to provide phase shift.

[0025] Figure 13 This is a graph of IIP2 versus the blocking signal for a CMOS version of a reconfigurable LNA at a given disturbed frequency without phase or amplitude compensation.

[0026] Figure 14 This is a diagram illustrating how the disclosed reconfigurable amplifier can interact with user components such as wireless communication devices. Detailed Implementation

[0027] The embodiments described below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode of practice. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will appreciate the application of these concepts, even if not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0028] It will be understood that while the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending to another element," it may be directly on or directly extended to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly on another element" or "directly extending to another element," no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "above another element" or "extending above another element," it may be directly above or directly extended above the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly above another element" or "extending directly above another element," no intermediate elements are present. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0030] For example, relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region illustrated in the figures. It should be understood that these terms, and those discussed above, are intended to include different orientations of the device other than those depicted in the figures.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” are intended to also include the plural forms. It will also be understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that, unless expressly defined herein, the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and in the relevant art, and shall not be interpreted in an idealized or overly formal sense.

[0033] The embodiments of this disclosure are described herein with reference to schematic illustrations. Thus, the actual dimensions of layers and elements may differ, and their shapes are expected to differ from those illustrated due to, for example, manufacturing techniques and / or tolerances. For example, areas illustrated or described as squares or rectangles may have circular or curved features, and areas shown as straight lines may have some irregularity. Therefore, the areas illustrated in the figures are schematic, and their shapes are not intended to illustrate the precise shapes of the areas of the apparatus, nor are they intended to limit the scope of this disclosure. Furthermore, for illustrative purposes, the size of structures or areas may be enlarged relative to other structures or areas, and thus provide structures or areas to illustrate the general structure of the subject matter, and may be drawn to scale or not. Common elements between the figures may be indicated herein by common element designations and will not be described further thereafter.

[0034] This disclosure provides linearization circuitry for a reconfigurable low-noise amplifier (LNA) that, when enabled, improves the out-of-band (OOB) second-order input cutoff (IIP2) by approximately 20 dB, with a very modest increase in the LNA noise factor (NF). For example, in at least some embodiments, NF does not exceed 0.3 dB when the high-linearity IIP2 mode is enabled. An advantage provided by the disclosed reconfigurable LNA is that linearization produces IMD2 cancellation inherent in a wide range of second-order intermodulation distortion (IMD2) blocking combinations at a given disturbed frequency.

[0035] In some implementations, the linearization circuitry can be selectively disabled in the first LNA mode when no problematic blocking pair exists. The problematic high-power blocking primarily originates from user equipment such as handheld devices and is known in advance. Therefore, the baseband processor can be programmed to determine whether a second LNA mode with the linearization circuitry enabled will provide better sensitivity: the first LNA mode is an extremely low noise mode (NF approximately 0.9 dB, OOB IIP2 approximately 0 dBm). The second LNA mode is a low noise / high IP2 mode (NF approximately 1.2 dB, OOB IIP2 > +20 dBm).

[0036] Another advantage of at least some implementations is the ability to selectively adjust IMD2 cancellation based on the frequency of the obstructing party, utilizing subband information. The subband is known prior to the signal burst, and therefore, IMD2 cancellation can be maximized for the known receiver frequency of the obstructing party that could potentially become a blocking signal intermodulation point. This tuning can adjust the phase and / or amplitude tuning of the cancellation path, as well as the tuning of the input matching.

[0037] Furthermore, the reconfigurable LNA provides enhanced receiver coexistence performance, where intermodulation between other transmitted signals in the user equipment causes receiver insensitivity through second-order intermodulation. Compared to the high-suppression circuitry replaced by the disclosed linearization circuitry, the disclosed linearization circuitry has a relatively small size and lower financial cost. Moreover, the circuitry constituting the reconfigurable LNA can be applied to existing LNA topologies used in cellular RF front-ends.

[0038] Figure 1 This is a diagram illustrating an embodiment of a reconfigurable low-noise amplifier (LNA) 10 constructed according to this disclosure.

[0039] The reconfigurable LNA 10 has a first transistor Q1, which has a first collector 12, a first base 14, and a first emitter 16. A second transistor Q2 has a second collector 18, a second base 20, and a second emitter 22. A third transistor Q3 has a third collector 24, a third base 26, and a third emitter 28. A fourth transistor Q4 has a fourth collector 30, a fourth base 32, and a fourth emitter 34. Figure 1 In an exemplary embodiment, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs). However, it should be understood that other transistor technologies can be used to implement the reconfigurable LNA 10. Examples of a reconfigurable LNA 10 using a field-effect transistor (FET) fabricated using a complementary metal-oxide-semiconductor (CMOS) process are subsequently described in this disclosure.

[0040] The first emitter 16 of the first transistor Q1 is negatively fed back by an emitter inductor LE1 coupled between a fixed voltage node G1 and the first emitter 16. In this exemplary embodiment, the fixed voltage node is ground. The first base 14 is coupled to a first base bias terminal 36 via a first bias resistor RB1. In operation, a first bias voltage VB1 is applied to the first base bias terminal 36. The first base 14 is also coupled to an RF input terminal 38 via a first coupling capacitor CC1, which is coupled to an impedance matching circuit, such as a matching inductor L. MATCH1 RF input terminal 38 is marked as RF. IN The first collector 12 is coupled to the second emitter 22 to place the first transistor Q1 and the second transistor Q2 in a cascode configuration. The second base 20 is coupled to the cascode bias input 40. The first transistor Q1 is configured as a common-emitter amplifier, and the second transistor Q2 is configured as a common-base amplifier. In operation, a bias voltage VCAS1 is applied to the cascode bias input 40.

[0041] The reconfigurable LNA 10 provides high IP2 by employing enhanced linearization generated through an auxiliary path, which is... Figure 1 The linearization circuit 42 shown within the dashed box is constructed. The linearization circuit 42 includes an analog subtractor 44, which has a characteristic marked RF. OUT The RF output terminal 46, the in-phase terminal 48 marked with a plus sign, and the out-of-phase terminal 50 marked with a minus sign.

[0042] The second collector 18 of the second transistor Q2 is coupled to the non-inverting terminal 48 of the analog subtractor 44. The third emitter 28 of the third transistor Q3 is coupled to the fixed voltage node G1 without intermediate negative feedback. The third collector 24 is coupled to the fourth emitter 34 to place the third transistor Q3 and the fourth transistor Q4 in a cascode configuration. The third base 26 of the third transistor Q3 is coupled to the second base bias terminal 52 via the second bias resistor RB2. In operation, a second bias voltage VB2 is applied to the second base bias terminal 52. A second coupling capacitor CC2 is coupled between the third base 26 of the third transistor Q3, the first collector 12 of the first transistor Q1, and the second emitter 22 of the second transistor Q2. The fourth base 32 of the fourth transistor Q4 is coupled to the cascode bias input terminal 40. The fourth collector 30 is coupled to the out-of-phase terminal 50.

[0043] The current flowing through the third transistor Q3 and the fourth transistor Q4 in the auxiliary path is subtracted from the main signal path to provide IMD2 cancellation. The auxiliary path receives signals from the second emitter 22 of the second transistor Q2, which include the desired signal, the blocking signal, and the IMD2 distortion component. These signals are amplified into a current signal by means of the amplifier gain (Gm) of the third transistor Q3, accompanied by some additional distortion generated in the auxiliary path.

[0044] The amplifier gain Gm and phase shift provided in the auxiliary path cause the IMD2 signal output from the fourth transistor Q4 to have the same amplitude and substantially the same phase as the IMD2 component in the main signal path, which includes the second transistor Q2. Therefore, the IMD2 component is canceled out by the signal in the auxiliary path and subtracted from the signal in the main signal path, resulting in... Figure 2A and Figure 2BThe improved IIP2 is illustrated in the graph shown. The desired signal components in the auxiliary path and the main path are approximately 180 degrees out of phase. Therefore, after subtraction, when the auxiliary path is enabled, a gain boost of approximately 2 dB to 3 dB is provided to the fundamental component in the signal path. This gain boost, combined with the auxiliary path, tapers the signal after the initial amplification by the first transistor Q1, explaining why NF increases relatively modestly by approximately 0.3 dB when the auxiliary path is enabled.

[0045] Figure 3 This is a diagram illustrating an implementation of the reconfigurable LNA 10, depicting an exemplary structure employing an autotransformer LT1 as an analog subtractor 44. The autotransformer LT1 has coupling to the received supply voltage V. CC The power supply terminal 54 has a center tap 52. The center tap 52 is located between the two windings of the autotransformer LT1. The two windings have a coupling coefficient denoted by k, which is a dimensionless value for the magnetic coupling between the two windings. A tuning capacitor CT1 is coupled in parallel with the autotransformer LT1 and has a capacitance sized to efficiently transmit the desired frequency through the autotransformer LT1. While the autotransformer LT1 performs relatively well as an analog subtractor 44, it is only one of many possible analog subtractor elements and / or circuits that can be used without departing from the scope of this disclosure. In this exemplary embodiment of the reconfigurable LNA 10, a third coupling capacitor CC3 is coupled between the RF output terminal 46 and the second collector 18 of the second transistor Q2.

[0046] A relatively significant advantage of the reconfigurable LNA 10 is that the provided IMD2 cancellation works over a wide range of IMD blocking frequencies, and for IMD2 products that can be generated from the product of two blocking frequencies IMD2[+1, +1] or their difference IMD2[-1, +1]. This characteristic is illustrated in the simulation plot, where for a given disturbed frequency F_IM2, IIP2 is plotted as a function of F1 and F2 (i.e., for IMD2[+1, +1], F2 = F_IMD2 - F1, and for IMD2[−1, +1], F2 = F_IMD2 + F1). Figure 4 This is a graph of IIP2 versus the blocking signal at a given frequency of the affected party. It should be noted that the difference between the auxiliary path being enabled and disabled remains at 20.5 dBm within a bandwidth of at least 1.2 GHz.

[0047] The relative phases of the IMD2 products in the main and auxiliary paths are essentially in phase, and therefore, IMD2 is canceled out by subtraction. As the frequency of the disturbed party changes, there will be slight changes in the relative signal amplitude and phase, which will degrade IIP2. Figure 5This is a schematic diagram of an exemplary version of a reconfigurable LNA 10 configured to reduce the degradation of IIP2 when the frequency of the disturbed party changes. In this embodiment, the reconfigurable LNA 10 is configured to adjust the amplitude of the IMD2 component in the auxiliary path as a function of a sub-band, which is the known frequency of the disturbed party, by adjusting a second bias voltage VB2. The relative phase shift between the main path and the auxiliary path as a function of the sub-band is small (<±20 degrees) and can be adjusted according to the sub-band by means of one of at least two embodiments. Figure 5 One embodiment schematically depicted includes a tunable phase shifter 56 coupled within an auxiliary path. Processor 60 has a processor output 62 through which the processor adjusts the tunable phase shifter 56. Processor 60 is configured to tune the tunable phase shifter 56 according to the frequency of the disturbed party known to processor 60.

[0048] Figure 6 Another embodiment described herein includes having a matching inductor L MATCH1 Parallel-coupled impedance matching capacitor C MATCH1 A tunable input impedance matching circuit 58 is provided. In this case, the processor 60 has been configured to adjust the capacitance of the impedance matching capacitor according to the known frequency of the disturbed party. The two implementations operate in slightly different ways. The phase shift in the auxiliary path allows for fine adjustment of the IMD2 component of the auxiliary path, while tuning the input matching adjusts the phase of the IMD2 component formed by the first transistor Q1 in the main path. Both implementations have their own advantages. Figure 5 The implementation plan has a relatively small impact on NF, while Figure 6 The tunable input matching circuit 58 of the implementation scheme can be configured as a parallel LC notch filter to provide additional high-frequency filtering.

[0049] Figure 7 This is a graph showing IIP2 versus the blocking signal at a given affected frequency without phase or amplitude compensation. The dashed line shows the gain of the reconfigurable LNA 10 where the auxiliary path is active and cancels out the unwanted signal, while the solid curve near the bottom of the graph shows the IIP2 performance where the auxiliary path is inactive. It should be noted that this exemplary embodiment of the reconfigurable LNA 10 with the auxiliary path active provides at least +20 dBm of IIP2 enhancement over a 300 MHz bandwidth compared to operation with the auxiliary path inactive. It should also be noted that the IIP2 performance is enhanced by 10.6 dBm at 3.3 GHz and by 11 dBm at 4.2 GHz. The maximum IIP2 performance enhancement of 31 dBm occurs at 3.7 GHz.

[0050] Figure 8 This is a diagram illustrating a CMOS-based embodiment of a reconfigurable LNA 10 constructed according to the present disclosure. In this exemplary CMOS version of the reconfigurable LNA 10, a first field-effect transistor (FET) N1 has a first drain 64, a first gate 66, and a first source 68. A second FET N2 has a second drain 70, a second gate 72, and a second source 74. A third FET N3 has a third drain 76, a third gate 78, and a third source 80. A fourth FET N4 has a fourth drain 82, a fourth gate 84, and a fourth source 86.

[0051] The first drain 64 of the first FET N1 is negatively fed back by a source inductor LS1 coupled between a fixed voltage node G1 and a first source 68. In this exemplary embodiment, the fixed voltage node is ground. The first gate 66 is coupled to a first gate bias terminal 88 via a first gate resistor RG1. In operation, a first gate voltage VG1 is applied to a second gate 72. The first gate 66 is also coupled to an RF input terminal 38 via a first coupling capacitor CC1, which is coupled to an impedance matching circuit, such as a matching inductor L. MATCH1 A first drain 64 is coupled to a second source 74 to place the first FET N1 and the second FET N2 in a cascode configuration. A second gate 72 is coupled to a cascode bias input 40. The first FET N1 is configured as a common-source amplifier, and the second FET N2 is configured as a common-gate amplifier. In operation, a bias voltage VCAS1 is applied to the cascode bias input 40.

[0052] The CMOS version of the reconfigurable LNA 10 provides high IP2 by employing enhanced linearization generated via an auxiliary path, which is... Figure 8 The CMOS linearization circuit 90 shown within the dashed box is configured as follows. The CMOS linearization circuit 90 includes an analog subtractor 44, which has a designation RF. OUT The RF output terminal 46, the in-phase terminal 48 marked with a plus sign, and the out-of-phase terminal 50 marked with a minus sign.

[0053] The second drain 70 of the second FET N2 is coupled to the non-inverting terminal 48 of the analog subtractor 44. The third source 80 of the third FET N3 is coupled to the fixed voltage node G1 without intermediate negative feedback. The third drain 76 of the third FET N3 is coupled to the fourth source 86 of the fourth FET N4 to place the third FET N3 and the fourth FET N4 in a cascode configuration. The third gate 78 of the third FET N3 is coupled to the second gate bias terminal 92 via the second gate resistor RG2. In operation, the second gate voltage VG2 is applied to the second gate bias terminal 92. The second coupling capacitor CC2 is coupled between the third gate 78 of the third FET N3 and the first drain 64 of the first FET N1 and the second source 74 of the second FET N2. The fourth gate 84 of the fourth FET N4 is coupled to the cascode bias input terminal 40. The fourth drain 82 is coupled to the out-of-inverting terminal 50.

[0054] The current flowing through the third FET N3 and the fourth FET N4 in the auxiliary path is subtracted from the main signal path to provide IMD2 cancellation. The auxiliary path receives signals from the second source 74 of the second FET N2, which include the desired signal, the blocking signal, and the IMD2 distortion component. These signals are amplified into a current signal by means of the amplifier gain (Gm) of the third FET N3, accompanied by some additional distortion generated in the auxiliary path.

[0055] The amplifier gain Gm and phase shift provided in the auxiliary path cause the IMD2 signal output from the fourth FET N4 to have the same amplitude and substantially the same phase as the IMD2 component in the main signal path, which includes the second FET N2. Therefore, the IMD2 component is canceled out by the signal in the auxiliary path and subtracted from the signal in the main signal path, resulting in an improved IIP2.

[0056] Figure 9This is a diagram illustrating a CMOS-based embodiment of a reconfigurable LNA 10 including additional cascode transistors according to the present disclosure. In this exemplary embodiment, the additional cascode transistors are a fifth FET N5 and a sixth FET N6. The fifth FET N5 has a fifth drain 94, a fifth gate 96, and a fifth source 98. The sixth FET N6 has a sixth drain 100, a sixth gate 102, and a sixth source 104. The fifth drain 94 of the fifth FET N5 is coupled to a non-inverting terminal 48, and the fifth source 98 of the fifth FET N5 is coupled to a second drain 70 of a second FET N2, thereby creating a dual cascode structure in the main path. The drain 100 of the sixth FET N6 is coupled to a non-inverting terminal 50, and the source 104 of the sixth FET N6 is coupled to a fourth FET N4 drain 82 to configure a dual cascode structure in an auxiliary path. A second cascode bias input 106 is coupled to the fifth gate 96 of the fifth FET N5 and the sixth gate 102 of the sixth FET N6. During operation, the second bias voltage VCAS2 is applied to the second cascode bias input terminal 106.

[0057] Figure 10A yes Figure 8 The graphs show the performance of IIP2 and F1 in the CMOS-based implementation scheme. Figure 10B yes Figure 8 The graph shows the noise factor (NF) versus frequency performance of the CMOS-based implementation. Figure 10C yes Figure 8 The scattering parameter S21 versus frequency performance curve of the CMOS-based implementation scheme. Figure 10A , Figure 10B and Figure 10C The dashed curve in the figure represents the performance of the reconfigurable amplifier 10 when the auxiliary path is active / enabled in high IP2 mode. Figure 10A , Figure 10B and Figure 10C The solid curve in the figure represents the performance of the reconfigurable amplifier 10 when the auxiliary path is inactive / disabled in low-noise mode.

[0058] Figure 11This is a CMOS implementation of a reconfigurable LNA 10, which includes a first amplifier branch 108, a second amplifier branch 110, and an Nth amplifier branch 112 configured to be selectively enabled and disabled within an auxiliary path, where N is a natural count. The first amplifier branch 108 is composed of NFETs N3, N4, and N6. In this exemplary embodiment, the first switch FET A1 has a first switch source 114 coupled to a third drain 80 of the third FET N3 and a switch drain 118 coupled to a fixed voltage node G1. The first switch gate 116 is configured to receive a first enable / disable signal ENABLE-1 generated by the processor 60, and in response, to allow current to flow through the first branch 108 when the ENABLE-1 signal is an enable condition, and to block current from flowing through the first branch 108 when the ENABLE-1 signal is a disable condition.

[0059] The second amplifier branch 110 is composed of NFETs N3-2, N4-2, and N6-2, which are coupled together, like NFETs N3, N4, and N6, to form a second optional portion of the auxiliary path. A second switch FET A2 is coupled between NFETs N3-2, N4-2, and N6-2 and the fixed voltage node G1. The second switch gate 120 is configured to receive a second enable / disable signal ENABLE-2 generated by the processor 60, and in response, to allow current to flow through the second branch 110 when the ENABLE-2 signal is an enable condition, and to prevent current from flowing through the second branch 110 when the ENABLE-2 signal is a disable condition.

[0060] The Nth amplifier branch 112 is composed of NFETs N3-N, N4-N, and N6-N, which are coupled together, like FETs N3, N4, and N6, to form the Nth optional portion of the auxiliary path. The Nth switch FET AN is coupled between the NFETs N3-N, N4-N, and N6-N and the fixed voltage node G1. The Nth switch gate 122 is configured to receive the Nth enable / disable signal ENABLE-N generated by the processor 60, and in response, to allow current to flow through the Nth branch 112 when the ENABLE-N signal is an enable condition, and to block current from flowing through the Nth branch 112 when the ENABLE-N signal is a disable condition. Furthermore, in Figure 11 In some versions of the implementation, the first amplifier branch 108, the second amplifier branch 110, and the Nth amplifier branch 112 do not need to provide uniform amplification. For example, the first amplifier branch 108, the second amplifier branch 110, and the Nth amplifier branch 112 may have different numbers of cascode FETs, or the transconductance of the FETs between the amplifier branches may be different.

[0061] Processor 60 is configured to output enable / disable signals ENABLE-1, ENABLE-2, and ENABLE-N via processor output 62. Figure 11 In an exemplary embodiment, the processor output may be a serial bus or a parallel bus. It should be understood that, depending on the specific application, intermediate circuitry such as gate drivers and address decoders (not shown) may be used for level shifting and / or selective addressing of switches FETs A1 to AN and tunable phase shifter 56.

[0062] Figure 12 This is a diagram of an implementation of a CMOS version of a reconfigurable LNA 10 including an input matching tuner 58 configured to provide a phase shift to allow the IMD2 component to be canceled out by subtracting the signal in the auxiliary path from the signal in the main signal path, thereby producing an improved IIP2. Figure 13 This is a graph showing the IIP2 versus the blocking signal for the CMOS version of the reconfigurable LNA 10 at a given disturbed frequency without phase or amplitude compensation.

[0063] refer to Figure 14 The above concepts can be implemented in various types of wireless communication devices or user elements 124, such as mobile terminals, smartwatches, tablets, computers, navigation devices, access points, etc., that support wireless communication (such as cellular, wireless local area network (WLAN), Bluetooth, and near field communication). User element 124 will generally include a control system 126, a baseband processor 128, a transmitting circuit 130, a receiving circuit 132 including a reconfigurable LNA 10, an antenna switching circuit 134, multiple antennas 136, and a user interface circuit 138. The receiving circuit 132 receives radio frequency signals from one or more base stations via antennas 136 and through the antenna switching circuit 134. A low-noise amplifier and filter (not shown) cooperate to amplify and eliminate broadband interference from the received signal for processing. Then, down-conversion and digitization circuitry (not shown) down-converts the filtered received signal to an intermediate or baseband frequency signal, and then digitizes the signal into one or more digital streams.

[0064] The baseband processor 128 processes the digitized received signal to extract the transmitted information or data bits from the received signal. This processing typically includes demodulation, decoding, and error correction operations. The baseband processor 128 is typically implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

[0065] For transmission, baseband processor 128 receives digitized data, representing voice, data, or control information, encoded by control system 126 for transmission. The encoded data is output to transmission circuitry 130, where it is modulated by a modulator (not shown) to a carrier signal at one or more desired transmission frequencies. A power amplifier (not shown) amplifies the modulated carrier signal to a level suitable for transmission and passes it to antenna 136 via antenna switching circuitry 134. Antenna 136, along with the repeating transmission circuitry 130 and receiving circuitry 132, can provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0066] It is conceivable that any of the foregoing aspects, and / or the various individual aspects and features described herein, can be combined to obtain additional advantages. Unless otherwise indicated herein, any embodiment of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments.

[0067] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims. Claims (as amended under Article 19 of the Treaty) 1. A reconfigurable amplifier, comprising: An analog subtractor having a radio frequency (RF) output terminal (46), an in-phase terminal (48), and an out-of-phase terminal (50); The first amplifier transistor has a first current input terminal coupled to the in-phase terminal and a first current output terminal coupled to a fixed voltage node (G1) forming the main path, and a first control terminal coupled to the RF input terminal (38). A second amplifier transistor having a second current input terminal coupled to the out-of-phase terminal and a second current output terminal coupled to the fixed voltage node forming the auxiliary path, and a second control terminal coupled to the first current input terminal, wherein when the auxiliary path is enabled, the second-order intermodulation components are substantially canceled out by subtracting the signal in the auxiliary path from the signal in the main path; and A tunable phase shifter coupled within the auxiliary path and configured to fine-tune the cancellation of the second-order intermodulation components based on a subband known prior to the signal burst. 2. The reconfigurable amplifier of claim 1 further includes a switching transistor coupled between the second amplifier transistor and the fixed voltage node, wherein the switching transistor has a control terminal configured to receive an enable / disable signal. 3. The reconfigurable amplifier of claim 2, further comprising a processor having a processor output communicating with a control input of the switching transistor, wherein the processor is configured to: turn on the switching transistor to enable the auxiliary path in a high second-order intercept mode, in which the second-order intermodulation component in the auxiliary path is subtracted from the signal in the main path in the high second-order intercept mode; and turn off the switching transistor to disable the switching transistor in a lower noise mode to improve the noise factor. 4. The reconfigurable amplifier of claim 1, wherein the fixed voltage node is ground. 5. The reconfigurable amplifier of claim 1, wherein the first amplifier transistor and the second amplifier transistor are field-effect transistors (FETs) configured in a cascode configuration. 6. The reconfigurable amplifier of claim 1 further includes a negative feedback element coupled between the fixed voltage node and the first current input terminal of the first amplifier transistor. 7. The reconfigurable amplifier of claim 1, wherein the analog subtractor includes an autotransformer having a center tap coupled to a power supply terminal receiving a power supply voltage and two windings having a coupling coefficient, and the analog subtractor further includes a tuning capacitor coupled in parallel with the autotransformer. 8. The reconfigurable amplifier of claim 1 further includes a tunable input impedance matching circuit coupled in parallel with an impedance matching circuit located between the RF input terminal and the first control terminal, wherein the tunable input impedance matching circuit has an impedance matching capacitor whose capacitance can be adjusted according to a known frequency of the disturbed party. 9. The reconfigurable amplifier (10) of claim 1, further comprising: a third amplifier transistor (N3) having a third current input terminal (70) coupled to the in-phase terminal (48), a third current output terminal (74) coupled to the first current input terminal (64) of the first amplifier transistor (N1), and a third control terminal (72) coupled to the first cascode bias input terminal (40); and a fourth amplifier transistor (N4) having a fourth current input terminal (82) coupled to the out-of-phase terminal (50), a fourth current output terminal (86) coupled to the second current input terminal (76) of the second amplifier transistor (N2), and a fourth control terminal (84) coupled to the first cascode bias input terminal (40), wherein the auxiliary path receives a signal including a desired signal, a blocking signal, and a second-order intermodulation distortion component. 10. The reconfigurable amplifier of claim 9, further comprising: a fifth amplifier transistor (N5) having a fifth current input terminal (94) coupled to the non-inverting terminal (48), a fifth current output terminal (98) coupled to the third current input terminal (70) of the third amplifier transistor (N3), and a fifth control terminal (96) coupled to the second cascode bias input terminal (106); and a sixth amplifier transistor (N6) having a sixth current input terminal (100) coupled to the non-inverting terminal (50), a sixth current output terminal (104) coupled to the fourth current input terminal (82) of the fourth amplifier transistor (N4), and a sixth control terminal (102) coupled to the second cascode bias input terminal (106). 11. The reconfigurable amplifier of claim 1, further comprising a first selectively enable and disable amplifier branch connected in parallel with the auxiliary path, and a second selectively enable and disable amplifier branch connected in series with the auxiliary path, wherein each amplifier branch has a switching transistor having a control terminal configured to receive an enable / disable signal generated by a processor. 12. The reconfigurable amplifier of claim 11, further comprising N-1 additional selectively enable and disable amplifier branches connected in parallel with the second amplifier branch, wherein each amplifier branch has a switching transistor having a control terminal configured to receive an enable / disable signal generated by the processor. 13. The reconfigurable amplifier of claim 1 further includes an input matching tuner circuit that provides a phase shift to allow the second-order intermodulation components to cancel each other out by subtracting the signal in the auxiliary path from the signal in the main path, thereby producing an improved input second-order intercept (IIP2). 14. A method of operating a reconfigurable amplifier having an analog subtractor having an in-phase terminal (48) and an out-of-phase terminal (50), wherein a first amplifier branch (108) is coupled in a main path between the in-phase terminal and at least a second amplifier branch (110), the second amplifier branch being selectively enabled in an auxiliary path coupled between the out-of-phase terminal and ground, the method comprising: A radio frequency (RF) signal is applied to the RF input of the first amplifier branch; The amplified version of the RF signal is coupled to the at least second amplifier branch; Enable the at least second amplifier branch, wherein when the auxiliary path is enabled, the second-order intermodulation components are substantially canceled out by subtracting the signal in the auxiliary path from the signal in the main path; and The phase shift within the auxiliary path is adjusted based on the subband known prior to the signal burst to fine-tune the cancellation of the second-order intermodulation components. 15. The method of claim 14, further comprising receiving an enable / disable signal from a processor, and controlling at least the second amplifier branch based on the enable / disable signal. 16. The method of claim 14, wherein the first amplifier branch includes a first field-effect transistor (FET) having a first drain, a first gate, and a first source, and the method further includes applying a first gate voltage to the first gate of the first FET. 17. The method of claim 14, wherein coupling an amplified version of the RF signal to the at least second amplifier branch comprises passing the amplified RF signal through an impedance matching circuit coupled between the first amplifier branch and the at least second amplifier branch. 18. The method of claim 16, further comprising applying negative feedback to the current input of the first amplifier transistor by coupling a source inductor between a fixed voltage node and the first source of the first FET. 19. The method of claim 14, wherein enabling at least the second amplifier branch includes applying a bias voltage to a cascode bias input of the gate of a third field-effect transistor (FET) coupled to the auxiliary path. 20. The method of claim 14, further comprising applying a first enable / disable signal to a control terminal of a switching transistor coupled between the second amplifier branch and the ground, wherein enabling at least the second amplifier branch includes turning on the switching transistor in response to the first enable / disable signal. 21. The method of claim 14, further comprising receiving a second enable / disable signal from a processor, and applying the second enable / disable signal to the control terminal of the switching transistor to control at least the second amplifier branch. 22. The method of claim 14, wherein enabling at least the second amplifier branch includes selectively enabling a plurality of amplifier branches connected in parallel and in series within the auxiliary path, each of the plurality of amplifier branches having a switching transistor controlled by an enable / disable signal from the processor. 23. A wireless communication device, comprising: A baseband processor (128) configured to encode a digital version of a radio frequency (RF) signal to generate encoded data; A transmitting circuit (130) configured to receive the encoded data from the baseband processor and to modulate a carrier signal using the encoded data; and A reconfigurable amplifier, the reconfigurable amplifier comprising: An analog subtractor having an RF output terminal (46), a non-inverting terminal (48), and a non-inverting terminal (50); The first amplifier transistor has a first current input terminal coupled to the in-phase terminal and a first current output terminal coupled to a fixed voltage node (G1) forming the main path, and a first control terminal coupled to the RF input terminal (38). A second amplifier transistor having a second current input terminal coupled to the out-of-phase terminal and a second current output terminal coupled to the fixed voltage node forming the auxiliary path, and a second control terminal coupled to the first current terminal, wherein when the auxiliary path is enabled, the second-order intermodulation components are substantially canceled out by subtracting the signal in the auxiliary path from the signal in the main path; and A tunable phase shifter coupled within the auxiliary path and configured to fine-tune the cancellation of second-order intermodulation components based on a subband known prior to the signal burst. 24. The wireless communication device of claim 23, further comprising a switching transistor coupled between the second amplifier transistor and the fixed voltage node, wherein the switching transistor has a control terminal configured to receive an enable / disable signal from a processor. 25. The wireless communication apparatus of claim 24, wherein the processor is configured to turn on the switching transistor to enable the auxiliary path and improve the input second-order intercept (IIP2) in a high second-order intercept mode, and to turn off the switching transistor to disable the auxiliary path and reduce the noise factor. 26. The wireless communication device of claim 23, further comprising a tunable input impedance matching circuit coupled in parallel with an impedance matching circuit located between the RF input terminal and the first control terminal, wherein the tunable input impedance matching circuit has an impedance matching capacitor whose capacitance is adjustable according to a known frequency of the disturbed party. 27. The wireless communication device of claim 23, wherein the first amplifier transistor and the second amplifier transistor are field-effect transistors (FETs) configured in a common-source, common-gate configuration. 28. The wireless communication device of claim 23, further comprising: a third amplifier transistor (N3) having a third current input terminal (70) coupled to the in-phase terminal (48), a third current output terminal (74) coupled to the first current input terminal (64) of the first amplifier transistor (N1), and a third control terminal (72) coupled to the first cascode bias input terminal (40); and a fourth amplifier transistor (N4) having a fourth current input terminal (82) coupled to the out-of-phase terminal (50), a fourth current output terminal (86) coupled to the second current input terminal (76) of the second amplifier transistor (N2), and a fourth control terminal (84) coupled to the first cascode bias input terminal (40). 29. The wireless communication device of claim 28, further comprising: a fifth amplifier transistor (N5) having a fifth current input terminal (94) coupled to the in-phase terminal (48), a fifth current output terminal (98) coupled to the third current input terminal (70) of the third amplifier transistor (N3), and a fifth control terminal (96) coupled to the second cascode bias input terminal (106); and a sixth amplifier transistor (N6) having a sixth current input terminal (100) coupled to the out-of-phase terminal (50), a sixth current output terminal (104) coupled to the fourth current input terminal (82) of the fourth amplifier transistor (N4), and a sixth control terminal (102) coupled to the second cascode bias input terminal (106). 30. The wireless communication device of claim 23, further comprising a first selectively enable and disable amplifier branch connected in parallel with the auxiliary path, and at least one additional selectively enable and disable amplifier branch connected in series with the auxiliary path, wherein each amplifier branch has a switching transistor having a control terminal configured to receive an enable / disable signal generated by a processor. 31. The wireless communication device of claim 23, further comprising an input matching tuner circuit that provides a phase shift to allow second-order intermodulation components to cancel each other out due to the subtraction of the signal in the auxiliary path from the signal in the primary path, thereby producing an improved input second-order intercept (IIP2).

Claims

1. A reconfigurable amplifier, comprising: An analog subtractor having a radio frequency (RF) output terminal (46), an in-phase terminal (48), and an out-of-phase terminal (50); The first amplifier transistor has a first current input coupled to the in-phase terminal and a first current output coupled to a fixed voltage node (G1) forming the main path, and a first control terminal coupled to the RF input terminal (38). and The second amplifier transistor has a second current input coupled to the out-of-phase terminal and a second current output coupled to the fixed voltage node forming the auxiliary path, and a second control terminal coupled to the first current terminal, wherein when the auxiliary path is enabled, the second-order intermodulation components are canceled out by subtracting the signal in the auxiliary path from the signal in the main path.

2. The reconfigurable amplifier of claim 1 further includes a switching transistor coupled between the second amplifier transistor and the fixed voltage node, wherein the switching transistor has a control terminal configured to receive an enable / disable signal.

3. The reconfigurable amplifier of claim 2, further comprising a processor having a processor output communicating with a control input of the switching transistor, wherein the processor is configured to: turn on the switching transistor to enable the auxiliary path in a high second-order intercept mode, in which second-order intermodulation components in the auxiliary path are subtracted from the signal in the main path; and turn off the switching transistor to disable the switching transistor in a lower noise mode to improve the noise factor.

4. The reconfigurable amplifier of claim 1, wherein the fixed voltage node is ground.

5. The reconfigurable amplifier of claim 1, wherein the first amplifier transistor and the second amplifier transistor are field-effect transistors (FETs) configured in a cascode configuration.

6. The reconfigurable amplifier of claim 1 further includes a negative feedback element coupled between the fixed voltage node and the first current input terminal of the first amplifier transistor.

7. The reconfigurable amplifier of claim 1, wherein the analog subtractor includes an autotransformer having a center tap coupled to a power supply terminal receiving a power supply voltage and two windings having a coupling coefficient, and the analog subtractor further includes a tuning capacitor coupled in parallel with the autotransformer.

8. The reconfigurable amplifier of claim 1, wherein the auxiliary path has an adjustable phase shift to fine-tune the cancellation of second-order intermodulation components based on a subband known prior to the signal burst.

9. The reconfigurable amplifier of claim 1 further includes a tunable input impedance matching circuit coupled in parallel with an impedance matching circuit located between the RF input terminal and the first control terminal, wherein the tunable input impedance matching circuit has an impedance matching capacitor whose capacitance can be adjusted according to a known frequency of the disturbed party.

10. The reconfigurable amplifier of claim 1, further comprising: A third amplifier transistor having a third current input terminal coupled to the in-phase terminal and a third control terminal coupled to the first current output terminal; and a fourth amplifier transistor having a fourth current input coupled to the out-of-phase terminal and a fourth control terminal coupled to the second current output terminal, wherein the auxiliary path receives a signal from the third current input terminal, the signal including a desired signal, a blocking signal and a second-order intermodulation distortion component.

11. The reconfigurable amplifier of claim 10, further comprising: A fifth amplifier transistor having a fifth current input terminal coupled to the in-phase terminal and a fifth control terminal coupled to the third current output terminal; and a sixth amplifier transistor, the sixth amplifier transistor having a sixth current input terminal coupled to the out-of-phase terminal and a sixth control terminal coupled to the fourth current output terminal, wherein the auxiliary path forms a dual common-source cascode structure within the main path and the auxiliary path.

12. The reconfigurable amplifier of claim 1, further comprising a first selectively enable and disable amplifier branch connected in parallel with the auxiliary path, and a second selectively enable and disable amplifier branch connected in series with the auxiliary path, wherein each amplifier branch has a switching transistor having a control terminal configured to receive an enable / disable signal generated by a processor.

13. The reconfigurable amplifier of claim 12, further comprising N-1 additional selectively enable and disable amplifier branches connected in parallel with the second amplifier branch, wherein each amplifier branch has a switching transistor having a control terminal configured to receive an enable / disable signal generated by a processor.

14. The reconfigurable amplifier of claim 1 further includes an input matching tuner circuit that provides a phase shift to allow the second-order intermodulation components to cancel each other out by subtracting the signal in the auxiliary path from the signal in the main path, thereby producing an improved input third-order intercept (IIP2).

15. A method of operating a reconfigurable amplifier having an analog subtractor having an in-phase terminal (48) and an out-of-phase terminal (50), wherein a first amplifier branch (108) is coupled in a main path between the in-phase terminal and at least a second amplifier branch (110), the second amplifier branch being selectively enabled in an auxiliary path coupled between the out-of-phase terminal and ground, the method comprising: A radio frequency (RF) signal is applied to the RF input of the first amplifier branch; The amplified version of the RF signal is coupled to the at least second amplifier branch; as well as The at least second amplifier branch is enabled, wherein when the auxiliary path is enabled, the second-order intermodulation components are canceled out by subtracting the signal in the auxiliary path from the signal in the main path.

16. The method of claim 15, further comprising receiving an enable / disable signal from a processor, and controlling the at least second amplifier branch based on the enable / disable signal.

17. The method of claim 15, wherein the first amplifier branch includes a first field-effect transistor (FET) having a first drain, a first gate, and a first source, and the method further includes applying a first gate voltage to the first gate of the first FET.

18. The method of claim 15, wherein coupling an amplified version of the RF signal to the at least second amplifier branch comprises passing the amplified RF signal through an impedance matching circuit coupled between the first amplifier branch and the at least second amplifier branch.

19. The method of claim 15, further comprising applying negative feedback to the current input of the first amplifier transistor by coupling a source inductor between a fixed voltage node and the first source of the first FET.

20. The method of claim 15, wherein enabling the at least second amplifier branch includes applying a bias voltage to a cascode bias input of the gate of a third field-effect transistor (FET) coupled to the auxiliary path.

21. The method of claim 15, further comprising applying a first enable / disable signal to a control terminal of a switching transistor coupled between the second amplifier branch and the ground, wherein enabling the at least second amplifier branch includes turning on the switching transistor in response to the first enable / disable signal.

22. The method of claim 15, further comprising receiving a second enable / disable signal from a processor, and applying the second enable / disable signal to the control terminal of the switching transistor to control the at least second amplifier branch.

23. The method of claim 15, further comprising adjusting the phase shift within the auxiliary path based on a subband known prior to the signal burst to fine-tune the cancellation of the second-order intermodulation components.

24. The method of claim 15, wherein enabling the at least second amplifier branch comprises selectively enabling a plurality of amplifier branches connected in parallel and in series within the auxiliary path, each of the plurality of amplifier branches having a switching transistor controlled by an enable / disable signal from the processor.

25. A wireless communication device, comprising: A baseband processor (128) configured to encode a digital version of a radio frequency (RF) signal to generate encoded data; A transmitting circuit (130) is configured to receive the encoded data from the baseband processor and to modulate a carrier signal using the encoded data; and A reconfigurable amplifier, the reconfigurable amplifier comprising: An analog subtractor having an RF output terminal (46), a non-inverting terminal (48), and a non-inverting terminal (50); The first amplifier transistor has a first current input coupled to the in-phase terminal and a first current output coupled to a fixed voltage node (G1) forming the main path, and a first control terminal coupled to the RF input terminal (38). and The second amplifier transistor has a second current input coupled to the out-of-phase terminal and a second current output coupled to the fixed voltage node forming the auxiliary path, and a second control terminal coupled to the first current terminal, wherein when the auxiliary path is enabled, the second-order intermodulation components are canceled out by subtracting the signal in the auxiliary path from the signal in the main path.

26. The wireless communication device of claim 25, further comprising a switching transistor coupled between the second amplifier transistor and the fixed voltage node, wherein the switching transistor has a control terminal configured to receive an enable / disable signal from a processor.

27. The wireless communication device of claim 26, wherein the processor is configured to turn on the switching transistor to enable the auxiliary path and improve the input third-order intercept (IIP2) in a high second-order intercept mode, and to turn off the switching transistor to disable the auxiliary path and reduce the noise factor.

28. The wireless communication device of claim 25, further comprising a tunable input impedance matching circuit coupled in parallel with an impedance matching circuit located between the RF input terminal and the first control terminal, wherein the tunable input impedance matching circuit has an impedance matching capacitor whose capacitance is adjustable according to a known frequency of the disturbed party.

29. The wireless communication device of claim 25, further comprising a tunable phase shifter coupled within the auxiliary path and configured to fine-tune the cancellation of second-order intermodulation components based on a subband known prior to the signal burst.

30. The wireless communication device of claim 25, wherein the first amplifier transistor and the second amplifier transistor are field-effect transistors (FETs) configured in a common-source, common-gate configuration.

31. The wireless communication device of claim 25, further comprising: A third amplifier transistor having a third current input terminal coupled to the in-phase terminal and a third control terminal coupled to the first current output terminal; and a fourth amplifier transistor, the fourth amplifier transistor having a fourth current input terminal coupled to the out-of-phase terminal and a fourth control terminal coupled to the second current output terminal.

32. The wireless communication device of claim 31, further comprising: A fifth amplifier transistor having a fifth current input terminal coupled to the in-phase terminal and a fifth control terminal coupled to the third current output terminal; and a sixth amplifier transistor, the sixth amplifier transistor having a sixth current input terminal coupled to the out-of-phase terminal and a sixth control terminal coupled to the fourth current output terminal, wherein the auxiliary path forms a dual common-source cascode structure within the main path and the auxiliary path.

33. The wireless communication device of claim 25, further comprising a first selectively enable and disable amplifier branch connected in parallel with the auxiliary path, and at least one additional selectively enable and disable amplifier branch connected in series with the auxiliary path, wherein each amplifier branch has a switching transistor having a control terminal configured to receive an enable / disable signal generated by a processor.

34. The wireless communication device of claim 25, further comprising an input matching tuner circuit that provides a phase shift to allow second-order intermodulation components to cancel each other out due to the subtraction of the signal in the auxiliary path from the signal in the primary path, thereby producing an improved input third-order intercept (IIP2).

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