Multi-connected air conditioning system

Abstract

A multi-split air conditioning system is provided, including an outdoor unit system, an indoor unit system and an impedance matching circuit (111). The outdoor unit system includes a plurality of outdoor units. The indoor unit system includes a plurality of indoor units. Any one of the indoor units and the outdoor units is a sending communication node, and the other is a receiving communication node. The impedance matching circuit (111) is configured to match the impedance of the communication signal between the sending side system (101) and the receiving side system (102) during transmission. The impedance matching circuit (111) includes a first terminal impedance, a second terminal impedance and a distributed capacitance. The distributed capacitance is configured to eliminate the effect of the distributed inductance on the impedance matching on the home bus (110). The first terminal impedance is located at the sending side of any one of the sending communication nodes at both ends of the sending side system (101), or the second terminal impedance is located at the receiving side of any one of the receiving communication nodes at both ends of the receiving side system (102).

Description

Multi-split air conditioning system

[0001] This application claims priority to Chinese patent application No. 202410189183.X filed on February 20, 2024; and priority to Chinese patent application No. 202410190201.6 filed on February 20, 2024, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the technical field of air conditioning, and in particular to a multi-split air conditioning system. Background Art

[0003] With the continuous advancement of technology and the improvement of people's living standards, air conditioners have become an indispensable electrical appliance in daily life.

[0004] A multi-split air conditioning system is used to provide heating and cooling to a building or room. It consists of multiple outdoor units and multiple indoor units. Each indoor unit can independently control the temperature to meet the needs of different rooms. Typically, the multiple indoor and outdoor units communicate using a home bus.

[0005] Summary of the Invention

[0006] A multi-split air conditioning system is provided, comprising an outdoor unit system, an indoor unit system, and an impedance matching circuit. The outdoor unit system includes multiple outdoor units. The indoor unit system includes multiple indoor units. The multiple indoor units are configured to communicate with the multiple outdoor units via a home bus. One of the indoor unit and the outdoor unit is a transmitting communication node, and the other of the indoor unit and the outdoor unit is a receiving communication node. One of the indoor unit system and the outdoor unit system is a transmitting system, and the other of the indoor unit system and the outdoor unit system is a receiving system. The impedance matching circuit connects the transmitting system and the receiving system and is configured to match the impedance of communication signals during transmission between the transmitting and receiving systems. The impedance matching circuit includes a first terminal impedance, a second terminal impedance, and distributed capacitance. The first terminal impedance is provided in the transmitting system. The second terminal impedance is provided in the receiving system. The resistance of the first terminal impedance and the second terminal impedance are equal to the characteristic impedance of the home bus. The distributed capacitance is provided on the home bus and is configured to eliminate the effects of the distributed inductance on the home bus on impedance matching. The locations of the first and second terminal impedances satisfy at least one of a first preset condition or a second preset condition. The first preset condition includes the first terminal impedance being located on the transmitting side of any one of the transmitting communication nodes at either end of the transmitting system. The second preset condition includes the second terminal impedance being located on the receiving side of any one of the receiving communication nodes at either end of the receiving system. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG1 is a block diagram of a multi-split air conditioning system according to some embodiments;

[0008] FIG2 is a schematic diagram of the communication principle of a multi-split air conditioning system according to some embodiments;

[0009] FIG3 is a circuit diagram of an impedance matching circuit of a multi-split air conditioning system according to some embodiments;

[0010] FIG4 is a circuit diagram of a characteristic impedance circuit of a home bus of a multi-split air conditioning system according to some embodiments;

[0011] FIG5 is a circuit diagram of a reflection coefficient acquisition circuit of a multi-split air conditioning system according to some embodiments;

[0012] FIG6 is a schematic diagram showing a principle of an impedance matching circuit of a multi-split air conditioning system according to some embodiments;

[0013] FIG7 is a waveform diagram of a home bus, a communication chip sending end, and a main controller receiving end of a multi-split air conditioning system according to some embodiments;

[0014] FIG8 is a circuit diagram of a home bus of a multi-split air conditioning system according to some embodiments;

[0015] FIG9 is a schematic diagram showing another impedance matching circuit of a multi-split air conditioning system according to some embodiments;

[0016] FIG10 is a schematic diagram showing another impedance matching circuit of a multi-split air conditioning system according to some embodiments;

[0017] FIG11 is a schematic diagram showing another impedance matching circuit of a multi-split air conditioning system according to some embodiments;

[0018] FIG12 is a waveform diagram of communication in an ideal state of a multi-split air conditioning system according to some embodiments;

[0019] FIG13 is a waveform diagram of communication performed by a multi-split air conditioning system in an actual state according to some embodiments;

[0020] FIG14 is a circuit diagram of a demodulation circuit of a multi-split air conditioning system according to some embodiments;

[0021] FIG15 is a diagram showing input waveforms and output waveforms of a demodulation circuit of a multi-split air conditioning system according to some embodiments;

[0022] FIG16 is a waveform diagram of an actual test of a multi-split air conditioning system according to some embodiments;

[0023] FIG. 17 is a waveform diagram (showing collection points) of an actual test of a multi-split air conditioning system according to some embodiments. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings to clearly and completely describe some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0025] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0026] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0027] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can mean fixed connection, detachable connection, or integration; it can be directly connected or indirectly connected through an intermediate medium.

[0028] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0029] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0030] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0031] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0032] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0033] With the continuous advancement of technology and the improvement of people's living standards, air conditioners have become an indispensable appliance in daily life. A multi-split air conditioning system is used to provide cooling and heating for a building or room. It consists of multiple outdoor units and multiple indoor units. Each indoor unit can independently control the temperature to meet the needs of different rooms.

[0034] Typically, multiple indoor and outdoor units communicate using a home bus communication system. This system typically operates at a 9.6 kHz frequency, but due to design limitations of the communication hardware, it often cannot support higher frequencies. With the integration of Bluetooth, multi-hop (MESH), near-field communication (NFC), and wireless fidelity (WIFI) features with multi-split air conditioners, a low home bus frequency can reduce information transmission efficiency, making it difficult for multi-split air conditioner systems to interact with other communication devices.

[0035] In order to solve the above technical problems, some embodiments of the present disclosure provide a multi-split air-conditioning system, which achieves impedance matching between the transmitting side and the receiving side by setting a distributed capacitor between the transmitting side of the transmitting side system and the receiving side of the receiving side system, and by setting the terminal impedance in the transmitting side system and the terminal impedance in the receiving side system to be different from the end nodes of the transmitting side system and the receiving side system at the same time, thereby improving the communication frequency and communication quality.

[0036] In some embodiments, the air conditioner performs a refrigeration cycle or a heating cycle by using a compressor, a condenser, an expansion valve, and an evaporator. The refrigeration cycle or the heating cycle includes a series of processes involving compression, condensation, expansion, and evaporation to cool or heat an indoor space.

[0037] When an air conditioner operates in the cooling or heating cycle, low-temperature, low-pressure refrigerant enters the compressor, where it is compressed into high-temperature, high-pressure refrigerant gas and discharged. The discharged refrigerant gas flows into the condenser, where it is condensed into liquid refrigerant. During the condensation process, the heat in the refrigerant is released to the surrounding environment.

[0038] The expansion valve expands the high-temperature, high-pressure liquid refrigerant condensed in the condenser to a lower-pressure liquid. The evaporator evaporates the refrigerant expanded in the expansion valve and returns the low-temperature, low-pressure refrigerant gas to the compressor. The evaporator achieves cooling by utilizing the latent heat of evaporation to exchange heat with the material being cooled. Throughout this cycle, the air conditioner regulates the temperature of the indoor space.

[0039] An air conditioner includes an indoor unit and an outdoor unit. The outdoor unit includes a compressor and an outdoor heat exchanger, and the indoor unit includes an indoor heat exchanger. For example, an expansion valve is provided in the indoor unit or the outdoor unit.

[0040] The indoor heat exchanger and the outdoor heat exchanger function as a condenser or an evaporator. When the indoor heat exchanger functions as a condenser, the air conditioner functions as a heater in heating mode, and when the indoor heat exchanger functions as an evaporator, the air conditioner functions as a cooler in cooling mode.

[0041] The working principle of the multi-split air-conditioning system 100 provided in some embodiments of the present disclosure refers to the basic working principle of the air conditioner described above.

[0042] In some embodiments, referring to FIG1 , a multi-split air conditioning system 100 includes a plurality of indoor units (In Door Units, IDUs) and a plurality of outdoor units (Out Door Units, ODUs) communicatively connected to a home bus 110 (Homebus). The indoor unit IDUs and the outdoor unit ODUs communicate using bus differential signals on the home bus 110.

[0043] For example, the multi-split air conditioning system 100 includes 40 outdoor ODUs and 160 indoor IDUs, which constitute 200 nodes. The communication frequency between the indoor IDUs and the outdoor ODUs is 9.6 kHz.

[0044] One of the indoor IDU and the outdoor ODU serves as a transmission communication node, and the other serves as a reception communication node. The transmission communication node can communicate with the reception communication node.

[0045] Hereinafter, for the convenience of description, the entire system formed by a plurality of indoor unit IDUs is referred to as an indoor unit system, and the entire system formed by a plurality of outdoor unit ODUs is referred to as an outdoor unit system.

[0046] When using the multi-split air conditioning system 100, the communication signal can be sent from the indoor unit IDU in the indoor unit system to the outdoor unit ODU in the outdoor unit system, or from the outdoor unit ODU in the outdoor unit system to the indoor unit IDU in the indoor unit system. Therefore, referring to Figure 6, one of the indoor unit system or the outdoor unit system serves as the sending side system 101, and the other of the indoor unit system or the outdoor unit system serves as the receiving side system 102.

[0047] In some embodiments, when the outdoor unit system is the signal-transmitting system 101 and the indoor unit system is the signal-receiving system 102 , the communication signal is transmitted from the outdoor unit ODU to the indoor unit IDU.

[0048] The outdoor unit ODU located at the first end (such as the free end) in the outdoor unit system is the head outdoor unit of the outdoor unit system, and the outdoor unit ODU located at the second end is the tail outdoor unit of the outdoor unit system.

[0049] For example, referring to FIG1 , the head outdoor unit is the outdoor unit ODU1 , and the tail outdoor unit is the outdoor unit ODU40 .

[0050] The indoor unit IDU located at the first end of the indoor unit system is the head indoor unit of the indoor unit system, and the indoor unit IDU located at the second end (such as the free end) is the tail indoor unit of the indoor unit system.

[0051] For example, referring to FIG1 , the head indoor unit is the indoor unit IDU1 , and the tail indoor unit is the indoor unit IDU160 .

[0052] In some embodiments, when the indoor unit system is the transmitting-side system 101 and the outdoor unit system is the receiving-side system 102 , the communication signal is transmitted from the indoor unit to the outdoor unit.

[0053] The indoor unit located at the first end of the indoor unit system is a rear indoor unit of the indoor unit system, and the indoor unit located at the second end is a head indoor unit of the indoor unit system.

[0054] For example, referring to FIG1 , the head indoor unit is the indoor unit IDU160 , and the tail indoor unit is the indoor unit IDU1 .

[0055] The outdoor unit located at the first end of the outdoor unit system is a rear outdoor unit of the outdoor unit system, and the outdoor unit located at the second end is a head outdoor unit of the outdoor unit system.

[0056] For example, referring to FIG1 , the head outdoor unit is the outdoor unit ODU40 , and the tail outdoor unit is the outdoor unit ODU1 .

[0057] Hereinafter, communication between the indoor unit and the outdoor unit will be described by taking an indoor unit in the indoor unit system and an outdoor unit in the outdoor unit system as an example.

[0058] In some embodiments, the indoor unit IDU includes an indoor main controller and an indoor communication chip. The indoor main controller is configured to receive a signal through the indoor communication chip, process the received signal, and send the processed signal to the outdoor unit through the indoor communication chip.

[0059] As shown in Figure 2, the outdoor unit includes an outdoor main controller 310 and an outdoor communication chip 210. The outdoor main controller 310 is configured to receive signals through the outdoor communication chip 210, process the received signals, and send the processed signals to the indoor unit IDU via the outdoor communication chip 210. This enables communication between the indoor unit IDU and the outdoor unit.

[0060] For example, the outdoor communication chip 210 or the indoor communication chip is configured to receive a signal that has undergone Alternate Mark Inversion (AMI) processing (hereinafter referred to as an AMI signal). The AMI signal is a digital transmission signal. The AMI signal can be transmitted in a home bus system and consists of three values: a high level, an intermediate level, and a low level. The AMI signal passes through a positive signal line and a negative signal line (i.e., a bipolar signal line).

[0061] For example, in a communication method using an AMI signal, logic "1" is assigned to an intermediate level (eg, +2.5V), and logic "0" is alternately assigned to a high level (eg, +5V) and a low level (eg, 0V).

[0062] The communication chip 200 (including at least one of the indoor communication chip and the outdoor communication chip 210) includes a home bus interface. The home bus interface is configured to connect to the home bus 110. For example, the indoor communication chip connects to the home bus 110 via the home bus interface, and the outdoor communication chip 210 connects to the home bus 110 via the home bus interface.

[0063] In some embodiments, the home bus 110 includes bipolar signal lines, such as a first bus A and a second bus B, which transmit bus differential signals (ie, AMI signals) on the home bus 110 .

[0064] In some embodiments, the indoor unit IDU and the outdoor unit ODU further include peripheral circuits corresponding to the communication chip 200 to ensure the transmission of the AMI signal.

[0065] The following will take the outdoor unit as an example to introduce the peripheral circuit.

[0066] In some embodiments, as shown in FIG2 , the peripheral circuit includes a signal coupling circuit 20 . The signal coupling circuit 20 is configured to send and receive communication instructions to the outdoor communication chip 210 .

[0067] The signal coupling circuit 20 includes a receiving-side AC coupling circuit 21 . The receiving-side AC coupling circuit 21 is connected to the home bus 110 and is configured to receive communication signals from the indoor unit on the home bus 110 and transmit the received communication signals to the outdoor communication chip 210 .

[0068] For example, the receiving-side AC coupling circuit 21 receives the communication signal by selecting corresponding resistors and capacitors, thereby ensuring that the signal received from the home bus 110 is a signal after filtering out noise such as DC signals.

[0069] The signal coupling circuit 20 also includes a transmitting AC coupling circuit 22. The transmitting AC coupling circuit 22 is connected to the home bus 110 and is arranged in parallel with the receiving AC coupling circuit 21. The transmitting AC coupling circuit 22 is configured to receive signals from the outdoor communication chip 210 and output the received communication signals to the indoor unit via the home bus 110.

[0070] For example, the AC coupling circuit 22 on the transmitting side transmits the communication signal by selecting corresponding resistors and capacitors, thereby ensuring that the signal transmitted to the home bus 110 is a signal after filtering out noise such as DC signals.

[0071] In some embodiments, as shown in FIG2 , the peripheral circuit further includes a bus driver circuit 30 . The bus driver circuit 30 is connected between the first bus A and the second bus B. For example, the bus driver circuit 30 is connected between the outdoor communication chip 210 and the transmitting-side AC coupling circuit 22 . The bus driver circuit 30 is configured to drive and amplify the signal outputted by the outdoor communication chip 210 at the signal output terminal.

[0072] In some embodiments, the peripheral circuit further includes a demodulation circuit 40. The demodulation circuit 40 is connected between the outdoor main controller 310 and the outdoor communication chip 210 and is configured to convert the signal output by the outdoor communication chip 210 into a binary output signal corresponding to the AMI signal and transmit the binary output signal to the receiving terminal RXD of the outdoor main controller 310.

[0073] In some embodiments, the peripheral circuit further includes a modulation circuit 50 , which is connected between the outdoor host controller 310 and the outdoor communication chip 210 and is arranged in parallel with the demodulation circuit 40 . The modulation circuit 50 is configured to modulate the signal from the outdoor host controller 310 into a corresponding AMI signal and transmit the AMI signal to the outdoor communication chip 210 .

[0074] The communication between the outdoor main controller 310 and the outdoor communication chip 210 will be further described below.

[0075] As shown in FIG2 , after the outdoor communication chip 210 receives the AMI signal (e.g., the signal at IV) from the home bus 110 through the home bus interface, it outputs a command with a duty cycle of 50% corresponding to the logic “0” in the AMI signal through the output end, and synchronously transmits the command for the logic “1” in the AMI signal (e.g., the signal at V).

[0076] During a one-bit transmission cycle, the 50% duty cycle signal corresponding to a logic "0" in the AMI signal output by the outdoor communication chip 210 is converted into a 100% duty cycle command through the demodulation circuit 40. The signal corresponding to a logic "1" in the AMI signal (e.g., the signal at position VI) output by the outdoor communication chip 210 is synchronously transmitted through the demodulation circuit and received by the receiving terminal RXD of the outdoor master controller 310.

[0077] After being processed by the outdoor main controller 310 , the outdoor main controller 310 outputs a signal with a duty cycle of 100% (ie, a signal at I) through the signal transmitting terminal TXD and sends it to the modulation circuit 50 .

[0078] During a one-bit transmission cycle, the low-level instruction corresponding to a logic "0" in the transmission signal, with a 100% duty cycle, is converted by the modulation circuit into an instruction with a 50% duty cycle. The high-level instruction corresponding to a logic "1" in the transmission signal (e.g., the signal at position III) is synchronously transmitted by the modulation circuit and input to the input terminal of the outdoor communication chip 210.

[0079] As described above, the present disclosure relates to communication between the indoor unit side and the outdoor unit side. In order to improve the communication quality between the outdoor unit system and the indoor unit system and to increase the communication distance between the outdoor unit and the indoor unit, the impedance matching between the transmitting side system 101 and the receiving side system 102 will be introduced below.

[0080] In some embodiments, as shown in Figures 3 and 6, the multi-split air conditioning system 100 further includes an impedance matching circuit 111. The impedance matching circuit 111 connects the signal transmitting system 101 and the signal receiving system 102 and is configured to match the impedance of the communication signal during transmission between the signal transmitting system 101 and the signal receiving system 102.

[0081] It is understood that impedance matching is an operating state in which the terminal impedance and the internal impedance of the excitation source are mutually adapted to achieve maximum power output. By designing and adjusting the structure of the impedance matching circuit 111 of the multi-split air conditioning system 100, the communication frequency (e.g., to 48 kHz) and communication quality within the multi-split air conditioning system 100 can be increased.

[0082] Furthermore, the impedance matching circuit 111 can also increase the communication distance. When the communication distance is increased, the number of communication nodes on the home bus 110 can be increased, thereby achieving stable communication at a high communication frequency with multiple communication nodes over a long distance.

[0083] In some embodiments, impedance matching conditions are different for circuits with different characteristics. For example, the adjustment factors of impedance matching include terminal impedance and characteristic impedance.

[0084] For example, in a purely resistive circuit, when the terminal resistance is equal to the internal resistance of the excitation source, the circuit operates at maximum output power. This operating state is called matching, otherwise it is called mismatching.

[0085] When the internal impedance of the excitation source and the terminal impedance contain reactance components, in order to obtain the maximum power at the terminal, the terminal impedance and the internal impedance of the excitation source need to satisfy a conjugate relationship. For example, the resistance component of the terminal impedance and the internal resistance of the excitation source are equal, and the reactance components have the same value but opposite signs.

[0086] For example, referring to FIG3 , when the terminal impedance is conjugately matched with the internal impedance of the excitation source, the terminal impedance and the internal impedance of the excitation source satisfy expression (1):

[0087] RS+jXS=RL-jXL (1)

[0088] In expression (1), RS is the resistance component of the excitation source internal impedance, XS represents the reactance component of the excitation source internal impedance, RL is the resistance component of the terminal impedance, XL represents the reactance component of the terminal impedance, and RS = RL. E shown in Figure 3 is a voltage source.

[0089] The home bus 110 has a characteristic impedance, which is an inherent property of radio frequency transmission lines (such as the home bus 110). The physical meaning of characteristic impedance is the ratio of the incident wave voltage to the incident wave current, or the ratio of the reflected wave voltage to the reflected wave current, on the radio frequency transmission line. For example, the characteristic impedance Z0 of the home bus 110 is 75Ω.

[0090] When the ratio of voltage to current at each point of the radio frequency transmission line is constant, the characteristic impedance remains unchanged. Therefore, when the home bus 110 uses a fixed type of cable, the characteristic impedance of the home bus 110 remains unchanged.

[0091] In some embodiments, the characteristic impedance model of the home bus 110 is shown in FIG4 , and the characteristic impedance Z0 satisfies expression (2):

[0092] Z0=sqrt[(R+jωL) / (G+jωC)] (2)

[0093] In expression (2), R is the resistance per unit length of the home bus 110, in Ω / m; L is the inductance per unit length of the home bus 110, in H / m; G is the parallel conductance per unit length of the home bus 110, in S / m; C is the distributed capacitance per unit length of the home bus 110, in F / m; and Z0 is in Ω.

[0094] It can be understood that, in general, the values ​​of R and G are small and can be ignored. In this case, expression (2) can be simplified to expression (3):

[0095] Z0=sqrt(L / C) (3)

[0096] As can be seen from expression (3), the factors affecting the characteristic impedance Z0 include the inductance per unit length of the home bus 110 and the distributed capacitance per unit length of the home bus 110, while the parameters affecting the values ​​of the inductance and capacitance include the dielectric constant, dielectric thickness, line width, and copper foil thickness of the home bus 110.

[0097] In some embodiments, the reflection coefficient ΓL of the home bus 110 can be calculated using the terminal impedance Z1, the characteristic impedance Z0, and expression (4). The circuit for obtaining the reflection coefficient ΓL is shown in FIG5 . Expression (4) is as follows:

[0098] ΓL=Vrefl / Vinc=(Z1-Z0) / (Z1+Z0) (4)

[0099] In formula (4), Vrefl is the transmission impedance and Vinc is the reflection impedance.

[0100] It is understood that the reflection coefficient ΓL is the ratio of the reflected wave voltage to the incident wave voltage and can reflect the characteristics of the load (such as admittance, gain, and transconductance). The strength of the load reflection signal depends on the degree of mismatch between the excitation source impedance and the terminal impedance.

[0101] Therefore, when the absolute value of the reflection coefficient ΓL is less than a preset threshold (eg, less than 1 / 3), the reflection phenomenon of the signal during communication can be reduced, thereby facilitating improvement of communication quality and communication distance.

[0102] For multi-split air conditioners, data transmission and reception between the indoor unit IDU and the outdoor unit ODU is bidirectional. For example, the outdoor unit ODU can send data to the indoor unit via the home bus 110, and vice versa. Therefore, the terms "stimulus source" and "terminal" are interchangeable. For example, in certain situations, a "stimulus source" can function as both a source and a terminal. Similarly, a "terminal" can function as both a terminal and a source.

[0103] Therefore, after considering the terminal impedance Z1 and the characteristic impedance Z0, a model of the impedance matching circuit 111 can be established as shown in Figure 6. For example, the characteristic impedance Z0 of the home bus 110 is 75Ω.

[0104] 6 , when the outdoor unit in the outdoor unit system is regarded as a signal source, the outdoor unit system is the signal transmission side system 101. The reflection coefficient ΓL of the impedance matching circuit 111 is (ZL-Z0) / (ZL+Z0).

[0105] When the indoor unit in the indoor unit system is regarded as a signal source, the indoor unit system is the transmission-side system 101 , and the reflection coefficient ΓL of the impedance matching circuit 111 is (ZS−Z0) / (ZS+Z0).

[0106] For example, ZL represents the terminal impedance on the system side of the indoor unit (ie, the second terminal impedance ZL), and ZS represents the terminal impedance on the system side of the outdoor unit (ie, the first terminal impedance ZS).

[0107] From the two reflection coefficients of the impedance matching circuit 111 obtained above, it can be seen that when ZL=ZS=Z0, the reflection coefficient ΓL can reach the minimum value, thereby improving the impedance matching effect, reducing the reflection phenomenon of the signal during communication, and improving the communication quality and communication distance.

[0108] In some embodiments, the multi-split air conditioning system 100 further includes a distributed capacitor C and a distributed inductor L. The distributed capacitor C and the distributed inductor L are provided on the home bus 110 , and the distributed capacitor C is configured to eliminate the influence of the distributed inductor L on the home bus 110 on impedance matching.

[0109] It is understandable that when the number of indoor and outdoor units in the multi-split air conditioning system 100 exceeds 100, the waveform on the home bus 110 (i.e., IV shown in Figure 7) will oscillate, preventing the main controller 300 (see Figure 2) from correctly decoding and reducing communication quality. As shown in Figure 8, the circuit model of the home bus 110 includes multiple distributed parameters, including a resistance component R, a distributed inductance component L, and a distributed capacitance component C. The resistance component R has no effect on impedance matching; the distributed capacitance component C causes signal delay but does not affect signal impedance matching. Therefore, the distributed inductance L on the home bus 110 is the main cause of the waveform oscillation.

[0110] For example, the resistance R of the home bus 110 is 0.03Ω / 1m, the distributed inductance L is 0.32uH / 1m, and the distributed capacitance C is 80pF / 1m.

[0111] Based on the conjugate principle, impedance matching circuit 111 can eliminate the effects of inductance through capacitance. For example, by changing the placement of distributed capacitance, the inductive reactance of the inductor and the capacitive reactance of the capacitor are equal, thus eliminating the effects of inductance. The inductive reactance of the inductor is 2πfL, where f is the communication frequency and L is the inductance. The capacitive reactance of the capacitor is 1 / (2πfc), where c is the capacitance.

[0112] For example, the communication frequency f is greater than or equal to 20 kHz and less than or equal to 100 kHz. It is understood that when the communication frequency f is less than 20 kHz, the communication quality and communication distance of the home bus 110 are reduced; and when the communication frequency f is greater than 100 kHz, energy consumption is excessively high.

[0113] For example, the communication frequency f is 48KHz, which is beneficial to improving the quality of communication and reducing energy consumption.

[0114] Thus, when the length of the home bus 110 is 1000 meters, based on the parameters of the home bus 110 described above (resistance is 0.03Ω / 1m, distributed inductance is 0.32uH / 1m, and distributed capacitance is 80pF / 1m), the distributed inductance on the home bus 110 can be calculated as L = 1000×0.32 = 320 (uH). Since the inductive reactance of the inductor is equal to the capacitive reactance of the capacitor, 2πfL = 1 / (2πfc) can be used to calculate the capacitance on the home bus 110 as c = 34.4nF.

[0115] As described above, one of the outdoor unit system and the indoor unit system is the transmitting system 101, and the other is the receiving system 102. The impedance matching circuit 111 includes a first terminating impedance ZS and a second terminating impedance ZL. One of the first terminating impedance ZS and the second terminating impedance ZL is provided on the transmitting side of the transmitting system 101, while the other is provided on the receiving side of the receiving system 102.

[0116] 6 , when the outdoor unit system is the transmission-side system 101 and the indoor unit system is the reception-side system 102 , ZS is the first terminal impedance and ZL is the second terminal impedance.

[0117] When the outdoor unit system is the receiving-side system 102 and the indoor unit system is the transmitting-side system 101 , ZL is the first terminal impedance and ZS is the second terminal impedance.

[0118] In some embodiments, the transmitting side and the receiving side are relative to each other, and therefore, the first terminal impedance and the second terminal impedance are also relative to each other.

[0119] The following describes the locations of the terminal impedance Z1 and the distributed capacitance C.

[0120] In some embodiments, the setting positions of the first terminal impedance ZS and the second terminal impedance ZL meet at least one of the first preset condition or the second preset condition to improve the waveform effect of the signal transmitted in the home bus 110, thereby improving the communication quality.

[0121] For example, the first preset condition includes: the first terminal impedance ZS is located at the transmitting side of any one of the transmitting communication nodes at both ends of the transmitting side system 101 .

[0122] For example, the second preset condition includes: the second terminal impedance ZL is located at the receiving side of any one of the receiving communication nodes at both ends of the receiving system 102 .

[0123] In some embodiments, referring to FIG1 , if the signal-transmitting system 101 is an outdoor unit system, and the outdoor unit system includes forty connected outdoor units, the forty outdoor units are numbered ODU1, ODU2, ..., ODU40, respectively, based on the direction of communication signal transmission. For example, the head outdoor unit is ODU1, and the tail outdoor unit is ODU40.

[0124] In this case, the receiving system 102 is an indoor unit system, and the indoor unit system includes 160 connected indoor units. According to the direction of communication signal transmission, the 160 indoor units are numbered as IDU1, IDU2, ..., IDU160. For example, the head indoor unit is IDU1, and the tail indoor unit is IDU160.

[0125] In this case, the first preset condition includes that the first terminal impedance ZS is located on the transmission side of either the outdoor unit ODU1 or the outdoor unit ODU40. The second preset condition includes that the second terminal impedance ZL is located on the reception side of either the indoor unit IDU1 or the indoor unit IDU160.

[0126] In some embodiments, referring to FIG1 , when the transmitting system 101 is an indoor unit system, the head indoor unit is IDU 160 and the tail indoor unit is IDU 1. In this case, the receiving system 102 is an outdoor unit system, the head outdoor unit is ODU 40 and the tail outdoor unit is ODU 1.

[0127] In this case, the first preset condition includes that the first terminal impedance ZS is located on the transmission side of either the outdoor unit ODU1 or the outdoor unit ODU40. The second preset condition includes that the second terminal impedance ZL is located on the reception side of either the indoor unit IDU1 or the indoor unit IDU160.

[0128] In the following, various arrangement positions of the first terminal impedance ZS and the second terminal impedance ZL will be introduced, taking the transmitting-side system 101 as an outdoor unit system and the receiving-side system 102 as an indoor unit system as an example.

[0129] In some embodiments, the first terminal impedance ZS is set at the signaling side of the outdoor unit located at the end among the multiple outdoor units. For example, the first terminal impedance ZS is set at the signaling side of the outdoor unit ODU1 or the signaling side of the outdoor unit ODU40.

[0130] In this case, the second terminal impedance ZL may be provided on the receiving side of any indoor unit. For example, the second terminal impedance ZL may be provided on the receiving side of any outdoor unit from the outdoor unit IDU1 to the outdoor unit IDU160.

[0131] In some embodiments, the second terminal impedance ZL is set at the receiving side of the indoor unit located at the end among the multiple indoor units. For example, the second terminal impedance ZL is set at the receiving side of the indoor unit IDU1 or the receiving side of the indoor unit IDU160.

[0132] In this case, the first terminal impedance ZS may be provided on the signal transmission side of any outdoor unit. For example, the first terminal impedance ZS may be provided on the signal transmission side of any indoor unit from the indoor units ODU1 to ODU40.

[0133] Similarly, when the transmitting side system 101 is an indoor system and the receiving side system 102 is an outdoor system, the arrangement positions of the first terminal impedance ZS and the second terminal impedance ZL are similar to the above arrangement positions and are not repeated here.

[0134] In some embodiments, when the outdoor unit system is the signal-transmitting system 101 , the first terminal impedance ZS includes a first signal-transmitting terminal impedance and a second signal-transmitting terminal impedance.

[0135] The first transmission terminal impedance is provided on the transmission side of one of the head outdoor unit and the tail outdoor unit. For example, the first transmission terminal impedance is provided on the transmission side of one of the head outdoor unit ODU1 and the tail outdoor unit ODU40.

[0136] The second transmission terminal impedance is provided on the transmission side of the other of the head outdoor unit and the tail outdoor unit. For example, the second transmission terminal impedance is provided on the transmission side of the other of the head outdoor unit ODU1 and the tail outdoor unit ODU40.

[0137] The resistance value of the first transmitting terminal impedance is equal to the resistance value of the second transmitting terminal impedance, and the resistance value of the two when connected in parallel is equal to the resistance value of the first terminal impedance ZS.

[0138] The second terminating impedance ZL is provided on the receiving side of the rear indoor unit. For example, the second terminating impedance ZL is provided on the transmitting side of the rear indoor unit IDU160.

[0139] This is beneficial for improving the waveform effect of the signal transmitted in the home bus 110, thereby improving the communication quality.

[0140] In some embodiments, when the outdoor unit system is the receiving-side system 102 , the second terminal impedance ZL includes a first receiving terminal impedance and a second receiving terminal impedance.

[0141] The first receiving terminal impedance is provided on the receiving side of one of the head outdoor unit and the tail outdoor unit. For example, the first receiving terminal impedance is provided on the receiving side of one of the head outdoor unit ODU40 and the tail outdoor unit ODU1.

[0142] The second receiving terminal impedance is provided on the receiving side of the other of the head outdoor unit and the tail outdoor unit. For example, the first receiving terminal impedance is provided on the receiving side of the other of the head outdoor unit ODU40 and the tail outdoor unit ODU1.

[0143] The resistance value of the first receiving terminal impedance is equal to the resistance value of the second receiving terminal impedance, and the resistance value of the two when connected in parallel is equal to the resistance value of the second terminal impedance ZL.

[0144] The first terminating impedance ZS is provided on the signal transmission side of the head indoor unit. For example, the first terminating impedance ZS is provided on the signal transmission side of the head indoor unit IDU160.

[0145] This is beneficial for improving the waveform effect of the signal transmitted in the home bus 110, thereby improving the communication quality.

[0146] In some embodiments, as shown in FIG9 , the impedance matching circuit 111 includes a distributed capacitor C, a first terminal impedance ZS, and a second terminal impedance ZL. The distributed capacitor C is arranged in parallel with the first terminal impedance ZS. Alternatively, as shown in FIG10 , the distributed capacitor C is arranged in parallel with the second terminal impedance ZL.

[0147] For example, the capacitance value of the distributed capacitance C is 34.4 nF as calculated above.

[0148] In some embodiments, as shown in FIG11 , the distributed capacitance C includes a first distributed capacitance CS and a second distributed capacitance CL, which are arranged in parallel. The first distributed capacitance CS is connected in parallel to the first terminal impedance ZS, and the second distributed capacitance CL is connected in parallel to the second terminal impedance ZL.

[0149] For example, the capacitance value of the first distributed capacitor CS and the second distributed capacitor CL connected in parallel is equal to the capacitance value of the distributed capacitor C.

[0150] In some embodiments, the capacitance values ​​of the first distributed capacitor CS and the second distributed capacitor CL are set to be equal, which is beneficial to improving the waveform effect of the signal transmitted in the home bus 110 and further improving the communication quality.

[0151] In some embodiments, the first distributed capacitor CS includes a first sub-distributed capacitor CS1 and a second sub-distributed capacitor CS2. The first sub-distributed capacitor CS1 is connected in parallel to the first transmitting terminal impedance, and the second sub-distributed capacitor CS2 is connected in parallel to the second transmitting terminal impedance.

[0152] The capacitance value of the first sub-distributed capacitor CS1 and the second sub-distributed capacitor CS2 are connected in parallel, and the capacitance value after the parallel connection is equal to the capacitance value of the first distributed capacitor CS.

[0153] In some embodiments, the capacitance value of the first sub-distributed capacitor CS1 is equal to the capacitance value of the second sub-distributed capacitor CS2.

[0154] FIG. 12 is a waveform diagram showing communication in an ideal state of a multi-split air conditioning system according to some embodiments.

[0155] In some embodiments, as shown in Figures 2 and 12 , during a one-bit transmission period T, the outdoor communication chip 210 outputs a 50% duty cycle signal corresponding to a logic "0" in the AMI signal, which is converted into a 100% duty cycle instruction after passing through the demodulation circuit 40. The outdoor communication chip 210 outputs a signal corresponding to a logic "1" in the AMI signal (e.g., the signal at position VI) which is synchronously transmitted through the demodulation circuit and received by the receiving terminal RXD of the outdoor master controller 310.

[0156] Under an ideal waveform, the moment the signal output by the outdoor communication chip changes from a low level to a high level, the high level begins to be delayed by Δt'=1 / 2T.

[0157] After being processed by the outdoor main controller 310, the outdoor main controller 310 outputs a signal with a duty cycle of 100% (i.e., the signal at I) and a clock signal output by the clock signal output terminal Clock (i.e., the signal at II) through the signal transmitting terminal TXD, and sends them to the demodulation circuit 40.

[0158] During a one-bit transmission cycle, the low-level instruction corresponding to a logic "0" in the transmission signal, with a 100% duty cycle, is converted by the modulation circuit into an instruction with a 50% duty cycle. The high-level instruction corresponding to a logic "1" in the transmission signal (e.g., the signal at position III) is synchronously transmitted by the modulation circuit.

[0159] The signal at III is input to the input end of the outdoor communication chip 210, and then encoded into an AMI signal on the home bus 110 by the outdoor communication chip 210, thus completing a cycle of data transmission and reception.

[0160] As described above, referring to the ideal waveform shown in FIG12 , the demodulation circuit 40 is further configured to delay the high level by 1 / 2T (i.e., delay time Δt) when the output of the outdoor communication chip 210 changes from a low level to a high level, to ensure that the main controller 300 decodes correctly.

[0161] FIG. 13 is a waveform diagram illustrating communication in a multi-split air conditioning system in an actual state according to some embodiments.

[0162] As shown in Figure 13, in actual communication, the AMI waveform on the bus is affected by distributed capacitance, which can cause a communication waveform delay. In this case, if the delay time Δt' = 1 / 2T, it will exceed the sampling time of one cycle, resulting in a chaotic sampling cycle and incorrect sampled data, which in turn prevents the main controller 300 from accurately decoding.

[0163] Therefore, when the home bus communication system operates at a high communication frequency (eg, 48 kHz), in order for the main controller 300 to decode correctly, the delay time Δt needs to be adjusted through the demodulation circuit 40 .

[0164] In some embodiments, as shown in FIG14 , the demodulation circuit 40 includes a charge-discharge circuit 41 and a first switch control circuit 42. The charge-discharge circuit 41 is connected to the first switch control circuit 42. The output terminal of the charge-discharge circuit 41 is connected to the output terminal OUT of the communication chip 200 and is configured to control the on / off of the first switch control circuit 42 according to the level outputted at the output terminal OUT.

[0165] The demodulation circuit 40 also includes a second switch control circuit 43. The first switch control circuit 42 is connected to the second switch control circuit 43 to form a two-stage amplifier drive. The output of the first switch control circuit 42 is configured to control the on / off state of the second switch control circuit 43. The output Vout of the second switch control circuit 43 is connected to the signal receiving terminal RXD of the main controller 300.

[0166] In some embodiments, as shown in FIG14 , the charge and discharge circuit 41 includes a first diode D1 and a second diode D2 . The anode of the first diode D1 is connected to the anode of the second diode D2 . The cathode of the second diode D2 is connected to the control terminal of the first switch control circuit 42 .

[0167] The charge-discharge circuit 41 further includes a third resistor R3 , and a first end of the third resistor R3 is connected to the anode of the first diode D1 and the anode of the second diode D2 , respectively.

[0168] The charge-discharge circuit 41 further includes a first capacitor C1 . A first end of the first capacitor C1 is connected to the anode of the first diode D1 and the anode of the second diode D2 , respectively, and a second end of the first capacitor C1 is grounded.

[0169] The charge-discharge circuit 41 further includes a second resistor R2. A first end of the second resistor R2 is connected to a second end of a third resistor R3. The cathode of the first diode D1 is connected between the first end of the second resistor R2 and the second end of the third resistor R3. The first end of the second resistor R2 is also connected to a first power source VCC01 (e.g., a +5V DC power source). The other end of the second resistor R2 is connected to the cathode of the first diode D1 and the output terminal OUT of the communication chip 200.

[0170] The charge and discharge circuit 41 further includes a fourth resistor R4 , a first end of which is connected to the control end of the first switch control circuit 42 (ie, the base of the first transistor Q1 ), and a second end of which is grounded.

[0171] In some embodiments, the first switch control circuit 42 and the second switch control circuit 43 are switch circuits that are turned on at a high level. For example, the first switch control circuit 42 and the second switch control circuit 43 are NPN transistors.

[0172] In some embodiments, as shown in FIG14 , the first switch control circuit 42 includes a first transistor Q1 , and the second switch control circuit 43 includes a second transistor Q2 . The demodulation circuit 40 further includes a first pull-up resistor RU1 .

[0173] The base of the first transistor Q1 is connected between the first end of the fourth resistor R4 and the cathode of the second diode D2. The emitter of the first transistor Q1 is grounded. The collector of the first transistor Q1 is connected to the first end of the first pull-up resistor RU1 and to the base of the second transistor Q2.

[0174] The demodulation circuit 40 further includes a second power supply VCC02 (eg, a +5V DC power supply). The second power supply VCC02 is connected to the second end of the first pull-up resistor RU1 , and the second power supply VCC02 is the pull-up power supply of the first pull-up resistor RU1 .

[0175] The demodulation circuit 40 further includes a second pull-up resistor RU2 .

[0176] An emitter of the second transistor Q2 is grounded, and a collector of the second transistor Q2 is connected to a first end of the second pull-up resistor RU2 and to a signal receiving terminal RXD of the main controller 300 .

[0177] The demodulation circuit 40 further includes a third power supply VCC03 (eg, a +5V DC power supply). The third power supply VCC03 is connected to the second end of the second pull-up resistor RU2 and serves as the pull-up power supply of the second pull-up resistor RU2.

[0178] The demodulation circuit 40 further includes a fifth resistor R5 , a first end of which is connected between the second pull-up resistor RU2 and the collector of the second transistor Q2 , and a second end of which is connected to the output terminal Vout of the second switch control circuit 43 .

[0179] The demodulation circuit 40 further includes a sixth resistor R6 , a first end of which is connected between the collector of the first transistor Q1 and the first pull-up resistor RU1 , and a second end of which is connected to the base of the second transistor Q2 .

[0180] The demodulation circuit 40 further includes a seventh resistor R7. A first end of the seventh resistor R7 is connected to the first transistor Q1, the first pull-up resistor RU1, and the second transistor Q2, respectively. A second end of the seventh resistor R7 is grounded. The seventh resistor R7 is configured to filter out interference from external signals on the signal transmitted within the demodulation circuit.

[0181] The demodulation circuit 40 further includes a second capacitor C2. A first end of the second capacitor C2 is connected between the second end of the fifth resistor R5 and the output terminal Vout of the second switch control circuit 43, and a second end of the second capacitor C2 is grounded. The second capacitor C2 is configured to filter the signal output by the demodulation circuit 40.

[0182] Taking the transmission period of one bit as T, the demodulation circuit 40 is configured to convert the signal output by the communication chip 200 into a binary output signal corresponding to the AMI signal. The receiving terminal RXD of the main controller 300 receives the binary output signal.

[0183] The operation process of the demodulation circuit 40 includes steps S1 to S3.

[0184] In step S1 , when the signal outputted from the output terminal OUT of the communication chip 200 is at a high level (eg, corresponding to binary data of 1), the first diode D1 is not conducting, and the second diode D2 is conducting.

[0185] The first power source VCC01 starts charging the first capacitor C1 through the second resistor R2 and the third resistor R3 until the voltage VC1 on the first capacitor C1 reaches VF(D2)+VBE(Q1). In this case, charging is completed and the first transistor Q1 is turned on.

[0186] For example, VF(D2) is the forward voltage of the second diode D2, and VBE(Q1) is the voltage between the base and emitter of the first transistor Q1.

[0187] Since the first transistor Q1 is turned on, the base voltage of the second transistor Q2 is pulled down, the second transistor Q2 is turned off, and the third power supply VCC03 outputs a high level to the receiving terminal RXD of the main controller 300 through the fifth resistor R5, realizing the high level transmission of the communication chip 200.

[0188] In step S2, when the signal outputted from the output terminal OUT of the communication chip 200 changes from a high level to a low level, the first capacitor C1 is discharged to the output terminal OUT of the communication chip 200 through the first diode D1 until VC1 = VF(D2). In this case, the first transistor Q1 is turned off.

[0189] Since the first transistor Q1 is turned off, the base voltage of the second transistor Q2 is increased, the second transistor Q2 is turned on, and the receiving terminal RXD of the main controller 300 outputs a low level, thereby achieving low-level equal transmission of the communication chip 200.

[0190] In step S3, when the signal at the output terminal OUT of the communication chip 200 changes from low level to high level, the first diode D1 is turned off and the second diode D2 is turned on. The first power source VCC01 charges the first capacitor C1 through the second resistor R2 and the third resistor R3.

[0191] It is understandable that if the voltage VC1 on the first capacitor C1 is charged from VF(D2) to VF(D2)+VBE(Q1), the first transistor Q1 will be turned on, and the communication chip 200 will perform high-level transmission as in step S1.

[0192] Therefore, the high level output by the communication chip 200 can be delayed by utilizing the time period (i.e., the delay time Δt) when the voltage VC1 is charged from VF(D2) to VF(D2)+VBE(Q1), thereby avoiding interference from interference signals and enabling the receiving terminal RXD of the main controller 300 to correctly decode the communication signal.

[0193] The following describes how to calculate the delay time Δt.

[0194] According to the RC circuit charging formula, VBE(Q1)=VCC01×(1-e(-Δt / τ)), where τ=(R2+R3)×C1, we can obtain: Δt=-(R2+R3)×C1×ln{1-VBE(Q1) / VCC01)}.

[0195] In some embodiments, VCC01 is 5V, and the values ​​of R2, R3, C1, and VBE(Q1) are inherent properties of the components themselves. By adjusting the component selection, when the output of the communication chip 200 changes from a low level to a high level, the high level is delayed by Δt. For example, the low level time is extended by Δt.

[0196] In this way, after obtaining the value of the delay time Δt, the values ​​of each component in the charge and discharge circuit in the demodulation circuit 40 can be determined, so that the communication chip 200 can correctly output the demodulated waveform, and the receiving end RXD of the main controller 300 can collect accurate communication data.

[0197] In some embodiments, the demodulation circuit is configured to delay the high level output by the communication chip 200 for a first time (ie, delay time Δt) starting from the moment the output terminal of the communication chip 200 changes from a low level to a high level.

[0198] In some embodiments, the first time is determined based on the period T.

[0199] In some embodiments, the first time may be obtained by using a golden ratio segmentation point. For example, the first time is the product of half a period 1 / 2T and the golden ratio point.

[0200] For example, when the communication frequency is set to 48 kHz, the period T is 20.8 μs. The first time is 1 / 2×20.8×0.618=6.42 μs.

[0201] The parameters of the demodulation loop can be calculated using the first time obtained and the formula described above. For example, R2 = 1 kΩ, R3 = 10 kΩ, and C1 = 0.0033 μF.

[0202] In some embodiments, a simulation source is designed using simulation software so that the simulation source generates a waveform identical to the signal output by the communication chip 200 corresponding to binary data 0. During testing, the simulation source is connected to the OUT terminal in FIG14 and outputs a waveform as represented by the first waveform line X1 in FIG15 . The waveform represented by the second waveform line X2 in FIG15 is the waveform output at the Vout terminal in FIG14 .

[0203] After testing, it was found that the delay time Δt was 6.6 μs (see FIG. 15 ), which is not much different from the 6.42 μs calculated above.

[0204] In actual use, after testing, the communication waveform shown in Figure 16 can be obtained.

[0205] In Figure 16, the third waveform line X3 represents the AMI waveform, and X3: 2.00V indicates that for the third waveform line X3, each scale mark on the vertical axis in the figure is 2.00V. The fourth waveform line X4 represents the waveform output by the communication chip, and X4: 2.50V indicates that for the fourth waveform line X4, each scale mark on the vertical axis in the figure is 2.50V. The fifth waveform line X5 represents the waveform received at the host controller's receiving terminal RXD, and X5: 2.00V indicates that for the fifth waveform line X5, each scale mark on the vertical axis in the figure is 2.00V. Z: 2.0μs indicates that each scale mark on the horizontal axis in the figure is 2.0μs. Furthermore, line A represents the instant when the waveform output by the communication chip changes from a low level to a high level, while line B represents the instant when the waveform received at the host controller's receiving terminal RXD changes from a low level to a high level. Therefore, the difference between the time represented by line B and the time represented by line A is the delay time Δt.

[0206] It should be noted that the meanings of the marks in Figures 7 and 17 are the same as the meanings of the corresponding marks in Figure 16, and this disclosure will not repeat them.

[0207] It can be tested that, after the signal output by the communication chip 200 changes from a low level to a high level, the delay time to the high level is Δt=6.5 μs.

[0208] It is understandable that the above test results verify that by adjusting the delay time Δt and setting the parameters of the demodulation loop, interference from interference signals can be avoided and the decoding accuracy of the main controller 300 can be improved.

[0209] When the delay time Δt is accurate, the software will more accurately sample and read the waveform output by the demodulation circuit, thereby improving communication efficiency.

[0210] In some embodiments, the first time may also be determined based on the period T and a maximum delay time on the home bus 110 . The maximum delay time on the home bus 110 may be determined based on a test of the multi-split air conditioning system 100 .

[0211] In some embodiments, half a cycle corresponds to the delay time under an ideal waveform (see Δt' shown in FIG. 12 ), and the maximum delay time corresponds to the delay time under a waveform when the distributed capacitance on the home bus 110 is maximum. In this case, the first time is the average of the half cycle and the maximum delay time, thereby improving the quality and efficiency of communication between communication nodes on the home bus 110.

[0212] For example, when the communication frequency is 48KHz, the period is 20.8μs.

[0213] When the bus length is 1000 meters and the number of communication nodes is 200, the maximum delay time obtained from the test is 3.2 μs. Therefore, the first time can be calculated to be (1 / 2×20.8 μs+3.2 μs) / 2=6.8 μs.

[0214] In some embodiments, since the delay time starts from the moment the communication chip 200 outputs a low level to a high level, the first time Δt can be set to be greater than 1 / 4T. Furthermore, since the level change output by the communication chip 200 is a change from a low level to a high level corresponding to 1-bit binary data, the first time Δt can be set to be less than 1 / 2T.

[0215] In order to prevent the sampling period from exceeding the period, the first time Δt does not take a value of 1 / 2T.

[0216] In some embodiments, according to the value range of the first time Δt as described above, the first time Δt may also be selected to have other values ​​within the range.

[0217] As shown in Figure 17, after the correct delay time Δt is set, the software can obtain accurate readings when sampling the waveform, improving decoding accuracy. For example, referring to the sampling at circle P, after the delay time Δt, the low level (representing the value of "0") in the waveform line is correctly sampled, and the erroneous value between the low level and the high level is not sampled.

[0218] It should be noted that any one of the technical solutions disclosed in the present disclosure can, to a certain extent, solve one or more of the above-mentioned technical problems and achieve certain disclosure purposes; multiple technical disclosures can also be combined into an overall solution to solve one or more of the above-mentioned technical problems and achieve certain disclosure purposes; some of the technical disclosures can also be selected to be combined into an overall solution, while adopting related technologies and inferior solutions, but the inferior trend can be compensated by the means disclosed in this technology, and the above-mentioned one or more technical problems can be solved to a certain extent as a whole and certain disclosure purposes can be achieved; each technical disclosure combined into a complete technical solution constitutes an organic and inseparable overall solution, which solves technical problems as a whole and achieves certain disclosure purposes.

[0219] Any technical disclosure in this disclosure, as well as the recombination of multiple technical disclosures, can form a complete technical solution and can solve one or more of the above-mentioned technical problems and achieve the purpose of disclosure. They all belong to the content of this disclosure and are the content that is directly and unambiguously determined based on the content of this disclosure.

[0220] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A multi-split air conditioning system, comprising: An outdoor unit system, comprising a plurality of outdoor units; An indoor unit system, comprising a plurality of indoor units; The plurality of indoor units are configured to be communicatively connected to the plurality of outdoor units via a home bus; wherein either the indoor unit or the outdoor unit is a transmitting communication node, and the other of the indoor unit or the outdoor unit is a receiving communication node; one of the indoor unit system and the outdoor unit system is a transmitting-side system, and the other of the indoor unit system and the outdoor unit system is a receiving-side system; and an impedance matching circuit, connected to the transmitting system and the receiving system, and configured to match the impedance of the communication signal between the transmitting system and the receiving system during transmission; the impedance matching circuit comprising: A first terminal impedance is provided in the transmitting side system; A second terminal impedance is provided in the receiving side system; the resistance value of the first terminal impedance and the resistance value of the second terminal impedance are equal to the resistance value of the characteristic impedance of the home bus; and a distributed capacitor, provided on the home bus and configured to eliminate the influence of the distributed inductance on the home bus on impedance matching; The first terminal impedance and the second terminal impedance are arranged at positions that meet at least one of a first preset condition or a second preset condition; The first preset condition includes: the first terminal impedance is located at the transmitting side of any one of the transmitting communication nodes at both ends of the transmitting side system; The second preset condition includes: the second terminal impedance is located on a receiving side of any one of the receiving communication nodes at both ends of the receiving side system.

2. The multi-split air conditioning system according to claim 1, wherein: The first terminal impedance is provided at a transmitting side of any one of the transmitting communication nodes at both ends of the transmitting side system; The second terminating impedance is provided on the receiving side of any one of the plurality of receiving communication nodes in the receiving-side system.

3. The multi-split air conditioning system according to claim 1 or 2, wherein: The outdoor unit system serves as the signal-transmitting system; The first terminal impedance includes: A first transmitting terminal impedance is provided at a transmitting side of a transmitting communication node located at one end in the transmitting side system; and a second transmitting terminal impedance, arranged in parallel with the first transmitting terminal impedance and arranged at a transmitting side of a transmitting communication node located at the other end in the transmitting side system; The second terminal impedance is provided at a receiving side of a receiving communication node located at a second end portion in the receiving side system.

4. The multi-split air conditioning system according to claim 3, wherein: The resistance value of the first transmitting terminal impedance is equal to the resistance value of the second transmitting terminal impedance, and the resistance value of the first transmitting terminal impedance and the second transmitting terminal impedance connected in parallel is equal to the resistance value of the first terminal impedance.

5. The multi-split air conditioning system according to claim 1, wherein: The first terminal impedance is provided at the transmitting side of any one of the plurality of transmitting communication nodes in the transmitting side system; The second terminating impedance is provided on the receiving side of any one of the receiving communication nodes at both ends of the receiving side system.

6. The multi-split air conditioning system according to claim 1 or 5, wherein: The outdoor unit system serves as a receiving side system; The second terminal impedance includes: A first receiving terminal impedance is provided at a receiving side of a receiving communication node located at one end of the receiving side system; and a second receiving terminal impedance, provided in parallel with the first receiving terminal impedance and provided on a receiving side of a receiving communication node located at the other end of the receiving side system; The first terminal impedance is provided at a transmitting side of a transmitting communication node located at a first end in the transmitting side system.

7. The multi-split air conditioning system according to claim 6, wherein: The resistance of the first receiving terminal impedance is equal to the resistance of the second receiving terminal impedance, and the resistance of the first receiving terminal impedance and the second receiving terminal impedance in parallel is equal to the resistance of the second terminal impedance.

8. The multi-split air conditioning system according to any one of claims 1 to 7, wherein: The distributed capacitance is connected in parallel with the first terminal impedance.

9. The multi-split air conditioning system according to any one of claims 1 to 7, wherein: The distributed capacitance is connected in parallel with the second terminal impedance.

10. The multi-split air conditioning system according to any one of claims 1 to 9, wherein: The distributed capacitance includes: a first distributed capacitor, arranged in parallel with the first terminal impedance; and a second distributed capacitor, arranged in parallel with the second terminal impedance; The capacitance value of the first distributed capacitance and the second distributed capacitance connected in parallel is equal to the capacitance value of the distributed capacitance.

11. The multi-split air conditioning system according to claim 10, wherein: Any one of the outdoor unit and the indoor unit includes: Main controller; a communication chip, connected to the main controller; and The demodulation circuit is provided between the communication chip and the main controller and is configured as follows: Converting the signal output by the communication chip into a binary output signal corresponding to the AMI signal transmitted on the home bus; When the output terminal of the communication chip is at a high level or changes from a high level to a low level, transmitting the signal output by the communication chip; and At the moment when the output terminal of the communication chip changes from a low level to a high level, the high level output by the communication chip is delayed to reach a first time.

12. The multi-split air conditioning system according to claim 11, wherein: The first time is determined based on at least a period required for transmitting 1-bit binary data.

13. The multi-split air conditioning system according to claim 12, wherein: The first time is the product of half the period and the golden section point.

14. The multi-split air conditioning system according to claim 12, wherein: The first time is determined based on the period and the maximum delay time generated by the home bus; the maximum delay time is determined by testing a multi-split air-conditioning system.

15. The multi-split air conditioning system according to claim 14, wherein: The first time is an average value of half the period and the maximum delay time.

16. The multi-split air conditioning system according to any one of claims 11 to 15, wherein: The demodulation circuit comprises: The charge and discharge circuit is configured to receive the level output by the output terminal of the communication chip and to increase the level of the output signal of the communication chip from low to high. When the level changes to a high level, the first time of delaying the high level begins; a first switch control circuit connected to the charge-discharge circuit; the charge-discharge circuit is further configured to: output a level to control the on / off of the first switch control circuit; The second switch control circuit is connected to the first switch control circuit; the output end of the second switch control circuit is connected to the signal receiving end of the main controller; the output end of the first switch control circuit is configured to control the on and off of the second switch control circuit.

17. The multi-split air conditioning system according to any one of claims 11 to 16, wherein: The multi-connected air conditioning system further comprises: a receiving-side AC coupling circuit connected to the receiving side of the communication chip and configured to receive signals from the home bus and send them to the communication chip; and The transmitting-side AC coupling circuit is connected to the transmitting side of the communication chip and is configured to receive signals from the communication chip and output communication signals to the home bus.

18. The multi-split air conditioning system according to any one of claims 11 to 17, wherein: The multi-split air conditioning system further includes a bus driving circuit, which is configured to drive and amplify the signal output by the communication chip through the signal output terminal.

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