MMC hardware-in-the-loop fault wave simulation method and device based on high-low frequency separation

Abstract

This invention provides a method and apparatus for simulating hardware-in-the-loop fault waveforms in MMC based on high- and low-frequency separation. The method includes: S1, determining the reference voltages of the low-frequency module group and the high-frequency module group in the upper and lower bridge arms, respectively, based on the output reference voltage and the DC bus voltage. S2, for each bridge arm, determining the engagement mode of the high-frequency module group, obtaining the corrected reference voltages of the low-frequency module group and the high-frequency module group, performing voltage modulation on each low-frequency submodule in the low-frequency module group, performing voltage modulation on each high-frequency submodule in the high-frequency module group, and performing fault waveform simulation. According to the embodiments of this invention, while ensuring the high-power main output capability, the reconstruction accuracy of local high-frequency disturbances can be improved, thus balancing output capability and fault waveform simulation fidelity.

Description

Technical Field

[0001] This invention relates to the field of power electronic converter technology, and to a method and apparatus for simulating MMC hardware-in-the-loop fault waveforms based on high- and low-frequency separation. Background Technology

[0002] With the large-scale grid connection of new energy power generation and energy storage devices, the dynamic characteristics of power systems are becoming increasingly complex. System-level empirical testing, fault disturbance simulation, and power hardware-in-the-loop verification place higher demands on grid connection interface devices. These devices not only need to have high-power energy interaction capabilities but also need to consider low latency, high fidelity, and strong stability dynamic response characteristics to support grid connection performance evaluation and fault characteristic reproduction in scenarios with a high proportion of new energy and energy storage. Therefore, developing high-power controllable grid connection interface devices for complex grid environments has become an important foundation for building high-fidelity testing platforms and improving system-level empirical capabilities.

[0003] Existing grid-connected interface device topologies mainly include low-level converters with transformers, cascaded / parallel multilevel converters, and other supplementary implementation methods. The low-level converter with transformer solution has high engineering maturity and a clear implementation path, but the system size is large, and its dynamic response capability and high-fidelity disturbance reproduction capability are limited. Cascaded / parallel multilevel topologies have good modular expansion capabilities and output waveform quality, and have been widely used in multi-megawatt scenarios, but their operating performance is highly dependent on the consistency and coordinated control of the DC side of each power unit. While linear power amplifiers and four-quadrant programmable AC sources possess good dynamic performance, their power rating and scalability are limited, making it difficult to meet the requirements of high-power grid-connected interfaces.

[0004] In contrast, the Modular Multilevel Converter (MMC) topology achieves medium- to high-voltage output through cascading submodules, offering advantages such as voltage stress dispersion, high output waveform quality, and strong modular scalability, especially in back-to-back MMC architectures (such as...). Figure 1 As shown, it can decouple the grid side from the measured side through the DC side, making it more suitable for the design of high-power grid-connected interface devices under complex operating conditions.

[0005] However, in MMC grid-connected interface devices, the modulation strategy directly affects the output waveform quality, dynamic response capability, and fault disturbance reproduction accuracy. Existing MMC modulation methods mainly rely on nearest-level approximation and carrier phase-shift modulation, which can achieve good results in main voltage synthesis and steady-state waveform control. However, in fault transient simulation scenarios, a single modulation method often cannot simultaneously take into account both high-power main output and high-frequency detail reconstruction. Summary of the Invention

[0006] To address the problems in the prior art, this invention provides a hardware-in-the-loop fault waveform simulation method and apparatus based on high- and low-frequency separation, wherein the low-frequency module is responsible for generating the main contour of the fault waveform, and the high-frequency module is responsible for correcting local transient details, thereby balancing high-power output capability, dynamic response speed, and fault waveform simulation fidelity.

[0007] In a first aspect, the present invention provides a hardware-in-the-loop fault waveform simulation method for MMC based on high-low frequency separation, comprising: S1, determining reference voltages for the low-frequency module group and the high-frequency module group in the upper and lower bridge arms, respectively, based on the output reference voltage and the DC bus voltage. S2, for each bridge arm, determining the connection mode of the high-frequency module group based on the capacitor voltage of each low-frequency submodule in the low-frequency module group, the capacitor voltage of each high-frequency submodule in the high-frequency module group, and the direction of bridge arm current flow. Correcting the reference voltages of the low-frequency module group and the high-frequency module group according to the connection mode of the high-frequency module group to obtain corrected reference voltages for the low-frequency module group and the high-frequency module group. Voltage modulation of each low-frequency submodule in the low-frequency module group based on the corrected reference voltages of the low-frequency module group. Voltage modulation of each high-frequency submodule in the high-frequency module group based on the corrected reference voltages of the high-frequency module group, and performing fault waveform simulation. The upper and lower bridge arms are symmetrically arranged. Each bridge arm in the upper and lower bridge arms includes a low-frequency module group and a high-frequency module group connected in series. The low-frequency module group consists of n cascaded low-frequency sub-modules. Each low-frequency sub-module has a half-bridge structure, comprising two first switching devices, their anti-parallel diodes, and a first DC support capacitor. The high-frequency module group consists of x cascaded high-frequency sub-modules. Each high-frequency sub-module has a full-bridge structure, comprising four second switching devices, their anti-parallel diodes, and a second DC support capacitor. x and n are positive integers.

[0008] In some embodiments, S1 includes: S11, determining the capacitor voltage of each low-frequency submodule in the low-frequency module group and the capacitor voltage of each high-frequency submodule in the high-frequency module group based on the DC bus voltage. S12, determining the target modulation voltage of the upper bridge arm and the target modulation voltage of the lower bridge arm based on the output reference voltage and the DC bus voltage. S13, determining the reference voltages of the low-frequency module group and the high-frequency module group in the upper and lower bridge arms, respectively, based on the target modulation voltages of the upper and lower bridge arms.

[0009] In some embodiments, S13 includes: S131, for each bridge arm, normalizing the target modulation voltage of the bridge arm according to the capacitor voltage of each low-frequency submodule in the low-frequency module group, and calculating the number of step voltage levels undertaken by the low-frequency module group in combination with the floor function to obtain the reference voltage of the low-frequency module group in each bridge arm. S132, for each bridge arm, extracting the remaining part between the target modulation voltage of the bridge arm and the reference voltage of the low-frequency module group in each bridge arm as the reference voltage of the high-frequency module group in each bridge arm.

[0010] In some embodiments, S2 includes: S21, for each bridge arm, comparing the average value of the capacitor voltage of each low-frequency submodule in the low-frequency module group with the sum of the capacitor voltages of each high-frequency submodule in the high-frequency module group, and determining the activation mode of the high-frequency module group based on the comparison result and the direction of the bridge arm current. S22, for each bridge arm, determining a correction voltage based on the activation mode of the high-frequency module group, and correcting the reference voltage of the low-frequency module group and the reference voltage of the high-frequency module group based on the correction voltage to obtain the corrected reference voltage of the low-frequency module group and the corrected reference voltage of the high-frequency module group. S23, for each bridge arm, performing voltage modulation on each low-frequency submodule in the low-frequency module group based on the corrected reference voltage of the low-frequency module group. Performing voltage modulation on each high-frequency submodule in the high-frequency module group based on the corrected reference voltage of the high-frequency module group.

[0011] In some embodiments, S21 includes: if the comparison result shows that the average capacitor voltage of each low-frequency submodule in the low-frequency module group is greater than the sum of the capacitor voltages of each high-frequency submodule in the high-frequency module group, then the high-frequency module group adopts a positive connection mode when the bridge arm current is greater than 0. When the bridge arm current is less than or greater than 0, the high-frequency module group adopts a negative connection mode. If the comparison result shows that the average capacitor voltage of each low-frequency submodule in the low-frequency module group is less than the sum of the capacitor voltages of each high-frequency submodule in the high-frequency module group, then the high-frequency module group adopts a negative connection mode when the bridge arm current is greater than 0. When the bridge arm current is less than or greater than 0, the high-frequency module group adopts a positive connection mode.

[0012] In some embodiments, S22 includes: S221, according to formula Determine the correction voltage .in, This is the DC bus voltage. S222, according to formula... Obtain the corrected reference voltage for the low-frequency module group. and the corrected high-frequency module group reference voltage ,in, This is the reference voltage for the low-frequency module group. This is the reference voltage for the high-frequency module group.

[0013] In some embodiments, in S23, voltage modulation is performed on each low-frequency submodule in the low-frequency module group according to the corrected low-frequency module group reference voltage, including: performing bubble sorting on each low-frequency submodule in the low-frequency module group. When the bridge arm current is greater than 0, low-frequency submodules are connected according to the input with the smallest capacitor voltage in ascending order. When the bridge arm current is less than 0, low-frequency submodules are connected according to the input with the largest capacitor voltage in descending order. The number of low-frequency submodules connected is related to the corrected low-frequency module group reference voltage.

[0014] In some embodiments, when the high-frequency module group is engaged in a positive engagement mode, in step S23, voltage modulation is performed on each high-frequency submodule in the high-frequency module group according to the corrected high-frequency module group reference voltage, including: S231, comparing the corrected high-frequency module group reference voltage with x stacked carriers, where the voltage range of the x stacked carriers is the interval [0,1]. S232, determining the number of high-frequency submodules in the high-frequency module group that are engaged in positive engagement, bypass engagement, and PWM engagement modes respectively, based on the comparison results. S233, sorting the capacitor voltages of each high-frequency submodule in the high-frequency module group using a bubble sort method. When the bridge arm current is greater than 0, the engagement mode of each high-frequency submodule is set to positive engagement, bypass engagement, and PWM engagement mode respectively, according to the capacitor voltage of each high-frequency submodule in the high-frequency module group from smallest to largest. When the bridge arm current is less than or greater than 0, the engagement mode of each high-frequency submodule is set to positive engagement, bypass engagement, and PWM engagement mode respectively, according to the capacitor voltage of each high-frequency submodule in the high-frequency module group from largest to smallest. If the corrected instantaneous reference voltage value of the high-frequency module group is greater than the instantaneous values ​​of x stacked carriers, the high-frequency submodule using PWM is in positive input mode. If the corrected instantaneous reference voltage value of the high-frequency module group is less than the instantaneous values ​​of x stacked carriers, the high-frequency submodule using PWM is in bypass mode.

[0015] In some embodiments, when the high-frequency module group is connected in a negative connection mode, in step S23, voltage modulation is performed on each high-frequency sub-module in the high-frequency module group according to the corrected high-frequency module group reference voltage, including: S234, comparing the corrected high-frequency module group reference voltage with x stacked carriers, where the voltage range of the x stacked carriers is the interval [-1, 0]. S235, determining the number of high-frequency sub-modules in the high-frequency module group that adopt negative connection mode, bypass mode, and PWM mode respectively based on the comparison results. S236, sorting the capacitor voltages of each high-frequency sub-module in the high-frequency module group using a bubble sort method. When the bridge arm current is greater than 0, the connection mode of each high-frequency sub-module is set to positive connection mode, bypass mode, and PWM mode respectively according to the capacitor voltage of each high-frequency sub-module in the high-frequency module group from largest to smallest. When the bridge arm current is less than or greater than 0, the connection mode of each high-frequency sub-module is set to positive connection mode, bypass mode, and PWM mode respectively according to the capacitor voltage of each high-frequency sub-module in the high-frequency module group from smallest to largest. If the corrected instantaneous reference voltage value of the high-frequency module group is greater than the instantaneous values ​​of x stacked carriers, the high-frequency submodule using PWM adopts a bypass mode. If the corrected instantaneous reference voltage value of the high-frequency module group is less than the instantaneous values ​​of x stacked carriers, the high-frequency submodule using PWM adopts a negative input mode.

[0016] Secondly, the present invention provides a hardware-in-the-loop fault waveform simulation device based on high-low frequency separation (MMC), comprising an MMC device. The MMC device includes an upper bridge arm, a lower bridge arm, and a controller. The upper and lower bridge arms are symmetrically arranged. Each bridge arm includes a low-frequency module group and a high-frequency module group connected in series. The low-frequency module group includes n cascaded low-frequency sub-modules. The low-frequency sub-modules are half-bridge structures, including two first switching devices and their anti-parallel diodes and a first DC support capacitor. The high-frequency module group includes x cascaded high-frequency sub-modules. The high-frequency sub-modules are full-bridge structures, including four second switching devices and their anti-parallel diodes and a second DC support capacitor. x and n are positive integers. The controller is used to execute the hardware-in-the-loop fault waveform simulation method based on high-low frequency separation in any of the above embodiments.

[0017] This invention provides a hardware-in-the-loop (MMC) fault waveform simulation method and apparatus based on high- and low-frequency separation. By configuring a low-frequency module and a high-frequency module in the same bridge arm, it achieves layered output of the main component and detail components of the fault waveform. The low-frequency module is used for main voltage synthesis, while the high-frequency module is used for local transient detail correction. Compared with traditional single-modulation or single-module output methods, this invention can improve the reconstruction accuracy of local high-frequency disturbances while ensuring high-power main output capability, thus balancing output capability and fault waveform simulation fidelity.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0019] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which: The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which: Figure 1 This is a back-to-back MMC converter topology in the prior art; Figure 2 A flowchart illustrating a hardware-in-the-loop fault waveform simulation method for MMC based on high-low frequency separation, provided in an embodiment of the present invention; Figure 3 A topology diagram of an MMC device in a loop fault waveform simulation device based on high-low frequency separation, provided for an embodiment of the present invention; Figure 4 A circuit diagram of the low-frequency submodule in an MMC device in a loop fault waveform simulation device based on high and low frequency separation, provided for an embodiment of the present invention; Figure 5 A circuit diagram of the high-frequency submodule in an MMC device based on high- and low-frequency separation is provided for an embodiment of the present invention. Figure 6 A flowchart of another MMC hardware-in-the-loop fault waveform simulation method based on high-low frequency separation provided in an embodiment of the present invention; Figure 7 A flowchart illustrating another method for simulating MMC hardware-in-the-loop fault waveforms based on high-low frequency separation, provided in an embodiment of the present invention; Figure 8 A block diagram illustrating the generation of high-frequency module group reference voltage and low-frequency module group reference voltage in a hardware-in-the-loop fault waveform simulation method for MMC based on high- and low-frequency separation, provided in an embodiment of the present invention. Figure 9This is an example of waveform diagrams of the reference voltage of the high-frequency module group and the reference voltage of the low-frequency module group in a hardware-in-the-loop fault waveform simulation method for MMC based on high- and low-frequency separation, provided in an embodiment of the present invention. Figure 10 A flowchart of another method for simulating MMC hardware-in-the-loop fault waveforms based on high-low frequency separation provided in an embodiment of the present invention; Figure 11 This invention provides a schematic diagram of the relationship between the high-frequency module group's engagement state and capacitor voltage when the upper arm current is greater than 0 in a hardware-in-the-loop fault waveform simulation method for MMC based on high- and low-frequency separation; wherein, (a) is a schematic diagram of the relationship between the positive engagement state of the high-frequency module group and capacitor voltage; and (b) is a schematic diagram of the relationship between the negative engagement state of the high-frequency module group and capacitor voltage. Figure 12 A flowchart of another method for simulating MMC hardware-in-the-loop fault waveforms based on high-low frequency separation provided in an embodiment of the present invention; Figure 13 This is a schematic diagram illustrating the correction of the reference voltage of the high- and low-frequency module group under different modes in a high- and low-frequency separation-based MMC hardware-in-the-loop fault waveform simulation method provided in an embodiment of the present invention; wherein, (a) is a schematic diagram illustrating the correction of the reference voltage of the high- and low-frequency module group under the positive input mode; and (b) is a schematic diagram illustrating the correction of the reference voltage of the high- and low-frequency module group under the negative input mode. Figure 14 A flowchart of another method for simulating MMC hardware-in-the-loop fault waveforms based on high-low frequency separation provided in an embodiment of the present invention; Figure 15 A schematic diagram illustrating the carrier comparison of a high-frequency module in an MMC hardware-in-the-loop fault waveform simulation method based on high- and low-frequency separation, provided in an embodiment of the present invention. Figure 16 A flowchart of another method for simulating MMC hardware-in-the-loop fault waveforms based on high-low frequency separation provided in an embodiment of the present invention; Figure 17 This is a schematic diagram illustrating the simulation of normal operating conditions in an MMC hardware-in-the-loop fault waveform simulation method based on high-low frequency separation, provided in an embodiment of the present invention. Figure 18 This is a schematic diagram illustrating the simulation of high-frequency oscillation conditions in an MMC hardware-in-the-loop fault wave simulation method based on high- and low-frequency separation, as provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of the present invention, exemplary embodiments of the present invention are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present invention to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0021] Where there is no conflict, the various embodiments of the present invention and the features thereof may be combined with each other.

[0022] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Terms such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0024] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant art and the invention, and will not be interpreted as having an idealized or overly formal meaning unless expressly so defined herein.

[0025] Embodiments of the present invention provide a method for simulating hardware-in-the-loop fault waveforms in MMC based on high- and low-frequency separation, such as... Figure 2 As shown, the method includes steps S1 and S2.

[0026] Step S1: Determine the reference voltages of the low-frequency module group and the high-frequency module group in the upper and lower bridge arms, respectively, based on the output reference voltage and the DC bus voltage.

[0027] In step S1, the upper and lower bridge arms are symmetrically arranged. Each bridge arm includes a low-frequency module group and a high-frequency module group connected in series. The low-frequency module group includes n cascaded low-frequency sub-modules. The low-frequency sub-modules have a half-bridge structure, including two first switching devices, their anti-parallel diodes, and a first DC supporting capacitor. The high-frequency module group includes x cascaded high-frequency sub-modules. The high-frequency sub-modules have a full-bridge structure, including four second switching devices, their anti-parallel diodes, and a second DC supporting capacitor. x and n are positive integers.

[0028] Understandably, Figure 2 The method shown can be applied to, for example Figure 3 The MMC device shown is as follows: Figure 3 As shown, the MMC device topology adopts a symmetrical structure, consisting of a DC bus, bridge arm inductors, low-frequency module group, high-frequency module group, and the device under test. The DC side voltage is... The potentials of the upper and lower busbars are respectively and The upper and lower bridge arms are connected in series with bridge arm inductors respectively. L The corresponding currents are respectively and The output current is The output voltage across the device under test is The positive direction of current flow is as follows: Figure 3 As shown in the diagram. Each bridge arm is composed of a series connection of high-frequency and low-frequency module groups. The high-frequency modules utilize high-frequency submodules HSM1~HSM. x Cascaded configuration; the low-frequency module uses low-frequency sub-modules LSM1~LSM n Cascaded structure.

[0029] like Figure 4 As shown, the low-frequency submodule consists of two switching devices. S 1 and S The 2 and its anti-parallel diodes form a half-bridge structure, and the DC support capacitor is C L The output ports of the low-frequency submodule are denoted as 1 and 1'. The low-frequency submodule mainly undertakes the main task of step voltage synthesis and features high output power and low switching frequency.

[0030] In the low-frequency submodule, the switch S 1 and switch S 2. Complementary, define the switching function S x As shown in equation (1): (1) In equation (3), S x =1 indicates a switchS 1. Conduction, switch S 2. Turn off S x =0 indicates a switch. S 2 conduction, switch S 1. Turn off.

[0031] like Figure 5 As shown, the high-frequency submodule consists of four switching devices. T 1~ T 4 and its anti-parallel diodes form a full-bridge structure, and the DC support capacitor is C H The output ports of the high-frequency submodule are denoted as 2 and 2'. The high-frequency submodule is mainly used to output high-frequency transient regulation components, and uses a high switching frequency to achieve rapid reconstruction of local details of the fault wave.

[0032] In the high-frequency submodule, the switch T 1 and T 2. Complementary, switch T 3 and T 4. Complementary, define their switching functions T x As shown in equation (2): (2) In equation (2), T x =1 indicates a switch T 1 and T 4 conduction, switch T 2 and T 3. Shutdown, high-frequency submodule is in operation; T x =-1 indicates a switch T 2 and T 3 conduction, switch T 1 and T 4. Shutdown, negative input of high-frequency submodule; T x =0 indicates a switch. T 1 and T 3 conduction, switch T 2 and T 4. Turn off or T 2 and T 4 conduction, switch T 1 and T 3. Shutdown, bypassing the high-frequency submodule.

[0033] Generally, as the number of low-frequency sub-modules in the low-frequency module group increases, the number of steps in the output main waveform increases, and the approximation error of the main fault wave decreases. As the number of high-frequency sub-modules in the high-frequency module group increases, the degree of freedom of high-frequency local adjustment increases, and the tracking error of transient oscillation details decreases. Both factors together determine the overall reconstruction accuracy of the target reference wave.

[0034] In some embodiments, such as Figure 6 As shown, step S1 includes steps S11 to S13.

[0035] Step S11: Determine the capacitor voltage of each low-frequency submodule in the low-frequency module group and the capacitor voltage of each high-frequency submodule in the high-frequency module group based on the DC bus voltage.

[0036] For example, the capacitor voltage of the low-frequency submodule in the low-frequency module group and the capacitor voltage of each high-frequency submodule in the high-frequency module group can be calculated according to equations (3) and (4), respectively: (3) (4) In equations (3) and (4), denoted as , where is the capacitor voltage of the low-frequency submodule in the low-frequency module group, and n is the number of low-frequency submodules in the low-frequency module group. denoted as , where is the capacitor voltage of each high-frequency submodule in the high-frequency module group, and x is the number of high-frequency submodules in the high-frequency module group.

[0037] Understandably, since the capacitor voltage of the high-frequency submodule is lower, its capacitors and power devices can be selected and designed according to the lower voltage level, while the low-frequency submodule is configured according to the voltage level required by the main output. Therefore, parameter design and device selection can be carried out separately according to the voltage tolerance level of different modules, which can reduce system cost and improve the flexibility of engineering implementation while ensuring fault waveform simulation performance.

[0038] Step S12: Determine the target modulation voltage of the upper bridge arm and the target modulation voltage of the lower bridge arm based on the output reference voltage and the DC bus voltage, respectively.

[0039] Understandably, based on the output reference voltage and DC bus voltage The target modulation voltage of the upper bridge arm can be determined separately as follows: The target modulation voltage of the lower bridge arm is This corresponds to the voltage distribution relationship of the upper and lower bridge arms under the symmetrical structure of the DC bus, respectively.

[0040] Step S13: Determine the reference voltages of the low-frequency module group and the high-frequency module group in the upper and lower bridge arms respectively, based on the target modulation voltage of the upper bridge arm and the target modulation voltage of the lower bridge arm.

[0041] In some embodiments, such as Figure 7 As shown, step S13 includes steps S131 to S132.

[0042] Step S131: For each bridge arm, the target modulation voltage of the bridge arm is normalized according to the capacitor voltage of each low-frequency submodule in the low-frequency module group, and the number of step voltage levels undertaken by the low-frequency module group is calculated by combining the floor function to obtain the reference voltage of the low-frequency module group in each bridge arm.

[0043] For example, such as Figure 8 As shown, the above bridge arm reference values ​​are calculated based on the capacitor voltage of the low-frequency submodule. Normalization is performed, and the number of voltage levels that the low-frequency module should bear is calculated using the floor function, thereby obtaining the reference voltage for the low-frequency module group. and .in, This indicates the reference voltage of the low-frequency module group in the upper arm. This indicates the reference voltage of the low-frequency module group in the lower bridge arm.

[0044] Step S132: For each bridge arm, extract the remaining portion between the target modulation voltage of the bridge arm and the reference voltage of the low-frequency module group in each bridge arm as the reference voltage of the high-frequency module group in each bridge arm.

[0045] Understandably, after the output of the low-frequency module group is determined, the remaining portion between the target voltage of the bridge arm and the voltage already allocated by the low-frequency module group is extracted and used as the reference voltage of the high-frequency module group, thus obtaining the reference voltage of the high-frequency module group of the upper bridge arm. and the reference voltage of the lower bridge arm high frequency module group .

[0046] For example, the reference voltage of the upper bridge arm high-frequency module group Equal to the target modulation voltage of the upper bridge arm Reference voltage of the low-frequency module group in the upper bridge arm The difference. Lower bridge arm high-frequency module group reference voltage. Equal to the target modulation voltage of the lower bridge arm Reference voltage of the low-frequency module group in the lower bridge arm difference.

[0047] Understandably, step S1 achieves a hierarchical distribution of the bridge arm's reference voltage between the low-frequency module group and the high-frequency module group: the low-frequency module is responsible for the main stepped voltage synthesis, and the high-frequency module is responsible for the remaining detailed voltage correction, such as... Figure 9 As shown.

[0048] Step S2: For each bridge arm, determine the activation method of the high-frequency module group based on the capacitor voltage of each low-frequency submodule in the low-frequency module group, the capacitor voltage of each high-frequency submodule in the high-frequency module group, and the current flow direction of the bridge arm. Correct the reference voltages of the low-frequency and high-frequency module groups according to the activation method, obtaining corrected reference voltages for the low-frequency and high-frequency module groups. Apply voltage modulation to each low-frequency submodule in the low-frequency module group based on the corrected reference voltage. Apply voltage modulation to each high-frequency submodule in the high-frequency module group based on the corrected reference voltage, and perform fault wave simulation.

[0049] In some embodiments, such as Figure 10 As shown, step S2 includes steps S21 to S23.

[0050] Step S21: For each bridge arm, compare the average value of the capacitor voltage of each low-frequency submodule in the low-frequency module group with the sum of the capacitor voltages of each high-frequency submodule in the high-frequency module group, and determine the activation method of the high-frequency module group based on the comparison result and the direction of the bridge arm current.

[0051] like Figure 11 As shown, taking the upper bridge arm as an example, the charging and discharging state of the high-frequency submodule is related to the direction of the bridge arm current and the polarity of the module's input. When the bridge arm current... When the value is greater than 0, the high-frequency submodule is in a positive charging state, and in a negative state, it is in a discharging state. When the bridge arm current... When the value is less than 0, the situation is reversed: a positive input corresponds to the discharge state, and a negative input corresponds to the charging state. If the high-frequency submodule is in bypass mode, the capacitor of that high-frequency submodule does not participate in energy exchange, and the capacitor voltage remains unchanged.

[0052] To achieve voltage balance control between the low-frequency module group and the high-frequency module group, the average value of the capacitor voltage of each low-frequency submodule in the low-frequency module group is calculated. The sum of the capacitor voltages of each high-frequency submodule in the high-frequency module group The comparison is made, and the high-frequency module group is determined accordingly to be in a charging or discharging state.

[0053] In some embodiments, step S21 includes: if the comparison result shows that the average capacitor voltage of each low-frequency submodule in the low-frequency module group is greater than the sum of the capacitor voltages of each high-frequency submodule in the high-frequency module group, then the high-frequency module group adopts a positive connection mode when the bridge arm current is greater than 0. When the bridge arm current is less than or greater than 0, the high-frequency module group adopts a negative connection mode. If the comparison result shows that the average capacitor voltage of each low-frequency submodule in the low-frequency module group is less than the sum of the capacitor voltages of each high-frequency submodule in the high-frequency module group, then the high-frequency module group adopts a negative connection mode when the bridge arm current is greater than 0. When the bridge arm current is less than or greater than 0, the high-frequency module group adopts a positive connection mode.

[0054] Understandably, when When this occurs, it indicates that the capacitor voltages of each high-frequency submodule in the high-frequency module group are relatively low. At this time, the high-frequency module group should be controlled to enter the charging state. If the bridge arm current... If the current is greater than 0, the high-frequency module group adopts the positive connection mode. If the bridge arm current is... If the value is less than 0, the high-frequency module group adopts a negative input mode.

[0055] Understandably, when When this occurs, it indicates that the capacitor voltage of each high-frequency submodule in the high-frequency module group is relatively high. At this time, the high-frequency module should be controlled to enter a discharge state. If the bridge arm current... If the current is greater than 0, the high-frequency module group adopts a negative input method. If the bridge arm current... If the value is less than 0, the high-frequency module group adopts the positive input mode.

[0056] Therefore, through the control logic of "voltage comparison - charging and discharging determination - input polarity selection", the input mode of the high-frequency module group can be adaptively adjusted according to the direction of the bridge arm current, so that the capacitor voltage of each high-frequency sub-module in the high-frequency module group always fluctuates around the target value, and the voltage coordination and balance between the high-frequency module group and the low-frequency module group can be achieved.

[0057] Step S22: For each bridge arm, determine the correction voltage according to the connection method of the high-frequency module group, and correct the reference voltage of the low-frequency module group and the reference voltage of the high-frequency module group according to the correction voltage to obtain the corrected reference voltage of the low-frequency module group and the corrected reference voltage of the high-frequency module group.

[0058] In some embodiments, such as Figure 12 As shown, step S22 includes steps S221 to S222.

[0059] Step S221, determine the correction voltage according to equation (5) : (5) In equation (5), This is the DC bus voltage.

[0060] Step S222: Obtain the corrected low-frequency module group reference voltage according to equation (6). and the corrected high-frequency module group reference voltage : (6) In equation (6), The reference voltage for the low-frequency module group is obtained according to equation (3). The reference voltage for the high-frequency module group is obtained according to equation (4).

[0061] like Figure 13 As shown, voltage balancing between the high-frequency module group and the low-frequency module group can be achieved by switching between positive and negative input methods.

[0062] Step S23: For each bridge arm, voltage modulation is performed on each low-frequency submodule in the low-frequency module group according to the corrected low-frequency module group reference voltage. Voltage modulation is performed on each high-frequency submodule in the high-frequency module group according to the corrected high-frequency module group reference voltage.

[0063] In some embodiments, step S23, voltage modulation of each low-frequency submodule in the low-frequency module group according to the corrected low-frequency module group reference voltage, includes: performing bubble sorting on each low-frequency submodule in the low-frequency module group. When the bridge arm current is greater than 0, low-frequency submodules are connected according to the input capacitor voltage from smallest to largest. When the bridge arm current is less than 0, low-frequency submodules are connected according to the input capacitor voltage from largest to smallest. The number of low-frequency submodules connected is related to the corrected low-frequency module group reference voltage.

[0064] Understandably, for the low-frequency module group: first, the capacitor voltages of each low-frequency submodule are sorted using a bubble sort method. When the bridge arm current... When the voltage is greater than 0, priority is given to activating low-frequency sub-modules with lower capacitor voltages; when the bridge arm current is greater than 0, priority is given to activating low-frequency sub-modules with lower capacitor voltages. When the voltage is less than 0, priority is given to activating low-frequency sub-modules with larger capacitor voltages. The specific number of low-frequency sub-modules activated is determined by the corrected reference voltage of the low-frequency module group. The decision was made. Through the above method, while achieving low-frequency main reference voltage tracking, the capacitor voltage balance of each low-frequency module can be maintained.

[0065] In some embodiments, such as Figure 14 As shown, when the high-frequency module group is in the positive input mode, step S23, the method of voltage modulation of each high-frequency sub-module in the high-frequency module group according to the corrected high-frequency module group reference voltage, includes steps S231 to S233.

[0066] Step S231: Compare the corrected high-frequency module group reference voltage with x stacked carriers.

[0067] In step S231, the voltage range of the x stacked carriers is the interval [0,1].

[0068] Step S232: Determine the number of high-frequency sub-modules in the high-frequency module group that adopt positive input mode, bypass mode and PWM mode respectively based on the comparison results.

[0069] Step S233: The capacitor voltages of each high-frequency submodule in the high-frequency module group are sorted using the bubble sort method. When the bridge arm current is greater than 0, the connection mode of each high-frequency submodule is set to positive connection mode, bypass mode, and PWM mode respectively, according to the capacitor voltage of each high-frequency submodule in the high-frequency module group from smallest to largest. When the bridge arm current is less than or greater than 0, the connection mode of each high-frequency submodule is set to positive connection mode, bypass mode, and PWM mode respectively, according to the capacitor voltage of each high-frequency submodule in the high-frequency module group from largest to smallest.

[0070] In step S233, if the corrected instantaneous value of the high-frequency module group reference voltage is greater than the instantaneous values ​​of x stacked carriers, the high-frequency submodule using PWM is in the positive input mode. If the corrected instantaneous value of the high-frequency module group reference voltage is less than the instantaneous values ​​of x stacked carriers, the high-frequency submodule using PWM is in the bypass mode.

[0071] For example, the voltage range of the x stacked carriers is the interval [0,1], and the amplitude of each carrier is... ,by And taking the converter operating in positive input mode as an example. Figure 15 As shown, Compare with 7 stacked carriers. When When the value falls within the interval [4 / 7, 5 / 7], it indicates that 4 high-frequency sub-modules in the high-frequency module group are operating in the active state, 2 high-frequency sub-modules are operating in the bypass state, and another high-frequency sub-module is operating in PWM state. That is, the high-frequency sub-module corresponding to the 5th carrier has entered PWM modulation mode. Figure 15 The carrier wave is shown in the figure. Its PWM switching state is shown in equation (7): (7) In equation (7), For the carrier wave within the corresponding interval.

[0072] Subsequently, the capacitor voltages of each high-frequency submodule were sorted using the bubble sort method, and the bridge arm current was... When the current is greater than 0, the following modes are used from smallest to largest: positive input mode, PWM mode, and bypass mode; when the bridge arm current is greater than 0... When <0, the following modes are used from largest to smallest: positive input mode, PWM mode, and bypass mode.

[0073] In some embodiments, when the high-frequency module group is supplied in a negative supply mode, such as Figure 16 As shown, in step S23, the method of voltage modulation of each high-frequency submodule in the high-frequency module group according to the corrected high-frequency module group reference voltage includes steps S234 to S236.

[0074] Step S234: Compare the corrected high-frequency module group reference voltage with x stacked carriers.

[0075] In step S234, the voltage range of the x stacked carriers is the interval [-1, 0].

[0076] Step S235: Determine the number of high-frequency sub-modules in the high-frequency module group that adopt negative input mode, bypass mode and PWM mode respectively based on the comparison results.

[0077] Step S236: The capacitor voltages of each high-frequency submodule in the high-frequency module group are sorted using the bubble sort method. When the bridge arm current is greater than 0, the connection mode of each high-frequency submodule is set to negative connection mode, bypass mode, and PWM mode respectively, according to the capacitor voltage of each high-frequency submodule in the high-frequency module group from largest to smallest. When the bridge arm current is less than or greater than 0, the connection mode of each high-frequency submodule is set to negative connection mode, bypass mode, and PWM mode respectively, according to the capacitor voltage of each high-frequency submodule in the high-frequency module group from smallest to largest.

[0078] In step S236, if the corrected instantaneous value of the high-frequency module group reference voltage is greater than the instantaneous values ​​of x stacked carriers, the high-frequency submodule using PWM mode adopts a bypass mode. If the corrected instantaneous value of the high-frequency module group reference voltage is less than the instantaneous values ​​of x stacked carriers, the high-frequency submodule using PWM mode adopts a negative input mode.

[0079] Understandably, the situation is similar in negative input mode to positive input mode, where the corrected high-frequency reference voltage will be used. Between [-1,0] The stacked carrier waves are compared, and then the capacitor voltages of each high-frequency module are sorted using a bubble sort method. When the bridge arm current... When the current is greater than 0, the negative input mode, PWM mode, and bypass mode are used respectively from large to small; when the bridge arm current is greater than 0, the negative input mode, PWM mode, and bypass mode are used respectively. When <0, the negative input mode, PWM mode, and bypass mode are used respectively from small to large. The PWM state is shown in equation (8): (8) In equation (8), For the carrier wave within the corresponding interval.

[0080] Step S23 enables the realization of the high-frequency module group reference voltage. While tracking, the capacitor voltage of each high-frequency submodule is kept balanced, thereby ensuring the long-term stable operation of the high-frequency module group and improving the ability to simulate high-frequency oscillations and transient details.

[0081] This invention provides a hardware-in-the-loop (MMC) fault waveform simulation method based on high-low frequency separation. By configuring a low-frequency module and a high-frequency module in the same bridge arm, it achieves layered output of the main fault waveform components and detail components. The low-frequency module is used for main voltage synthesis, while the high-frequency module is used for local transient detail correction. Compared with traditional single modulation or single-module output methods, this invention can improve the reconstruction accuracy of local high-frequency disturbances while ensuring high-power main output capability, thus balancing output capability and fault waveform simulation fidelity. Furthermore, by decomposing the output reference voltage into low-frequency main components and high-frequency correction components, and assigning them to the low-frequency and high-frequency modules respectively, it achieves coordinated modulation of "low-frequency for layering, high-frequency for fine-graining." Compared with traditional modulation methods, this invention improves the simulation capability of transient fault characteristics such as high-frequency oscillations without excessively increasing system losses and control complexity, enhancing the device's adaptability under complex operating conditions and its ability to generate high-fidelity fault waveforms.

[0082] The simulation results of an MMC hardware-in-the-loop fault waveform simulation method based on high-low frequency separation provided by an embodiment of the present invention are as follows: A simulation model of a single-phase modular multilevel converter based on high- and low-frequency separation was built in MATLAB / Simulink. The proposed control and modulation method was used to simulate fault waves under normal operating conditions and high-frequency oscillation conditions to verify the performance of the proposed topology and method. Specific circuit simulation parameters are shown in Table 1. Table 1. Main Circuit Simulation Parameters ; like Figure 17 As shown, under normal operating conditions, the converter's total output voltage can track the reference output voltage well, and the voltage at the terminal of the device under test... Waveform and target sine reference The results are largely consistent, with a distortion rate (THD) of 1.35%, indicating that the proposed device can achieve stable simulation of normal operating voltage. Furthermore, the outputs of the low-frequency and high-frequency modules in the upper bridge arm of the figure show that the synergistic effect of the high and low frequency modules improves the approximation accuracy of the output voltage to the reference waveform, verifying the effectiveness of the improved low-frequency separation structure and modulation method.

[0083] like Figure 18As shown, under high-frequency oscillation conditions, the reference output voltage Local high-frequency oscillation components are superimposed on the fundamental frequency. Simulation results show that the total output voltage of the converter... and the voltage at the terminals of the device under test The ability to track the reference waveform well indicates that the proposed device can simulate high-frequency oscillating fault waves, and the voltage of the high and low frequency modules in the upper bridge arm is also demonstrated. and As can be seen from the waveform, in the high-frequency oscillation stage, the low-frequency module makes small adjustments, while the high-frequency module makes rapid and accurate corrections, thereby achieving precise tracking of the oscillation waveform and verifying the proposed method's ability to reconstruct details of transient disturbances.

[0084] It is understood that the various method embodiments mentioned above in this invention can be combined with each other to form combined embodiments without violating the underlying principles and logic. Due to space limitations, these will not be elaborated upon further. Those skilled in the art will understand that the specific execution order of each step in the above methods of specific implementation should be determined by its function and possible internal logic.

[0085] Embodiments of the present invention also provide a hardware-in-the-loop fault waveform simulation device based on high- and low-frequency separation of MMC, the device including an MMC device.

[0086] like Figure 3 As shown, the MMC device includes an upper bridge arm, a lower bridge arm, and a controller (not shown in the figure). The upper and lower bridge arms are symmetrically arranged. Each bridge arm includes a low-frequency module group and a high-frequency module group connected in series. The low-frequency module group includes n cascaded low-frequency sub-modules, which are half-bridge structures, including two first switching devices, their anti-parallel diodes, and a first DC support capacitor. The high-frequency module group includes x cascaded high-frequency sub-modules, which are full-bridge structures, including four second switching devices, their anti-parallel diodes, and a second DC support capacitor. x and n are positive integers. The controller is used to execute the MMC hardware-in-the-loop fault waveform simulation method based on high-low frequency separation described in any of the above embodiments.

[0087] For details and beneficial effects of the MMC hardware-in-the-loop fault waveform simulation device based on high-low frequency separation provided in the embodiments of the present invention, please refer to the relevant description of the MMC hardware-in-the-loop fault waveform simulation method based on high-low frequency separation provided in the embodiments of the present invention, which will not be repeated here.

Claims

1. A method for simulating hardware-in-the-loop fault waveforms in MMC based on high- and low-frequency separation, characterized in that, include: S1, determine the reference voltages of the low-frequency module group and the high-frequency module group in the upper and lower bridge arms respectively based on the output reference voltage and the DC bus voltage; wherein, the upper and lower bridge arms are symmetrically arranged; each bridge arm of the upper and lower bridge arms includes a low-frequency module group and a high-frequency module group connected in series; the low-frequency module group includes n cascaded low-frequency sub-modules; the low-frequency sub-module is a half-bridge structure, including two first switching devices and their anti-parallel diodes and a first DC support capacitor; the high-frequency module group includes x cascaded high-frequency sub-modules; the high-frequency sub-module is a full-bridge structure, including four second switching devices and their anti-parallel diodes and a second DC support capacitor; x and n are positive integers; S2, for each bridge arm, the activation method of the high-frequency module group is determined based on the capacitor voltage of each low-frequency submodule in the low-frequency module group, the capacitor voltage of each high-frequency submodule in the high-frequency module group, and the current flow direction of the bridge arm. The reference voltages of the low-frequency module group and the high-frequency module group are corrected according to the activation method of the high-frequency module group to obtain corrected reference voltages for the low-frequency module group and the high-frequency module group. Voltage modulation is applied to each low-frequency submodule in the low-frequency module group based on the corrected reference voltages of the low-frequency module group. Voltage modulation is also applied to each high-frequency submodule in the high-frequency module group based on the corrected reference voltages of the high-frequency module group, and fault wave simulation is performed.

2. The method for simulating MMC hardware-in-the-loop fault waveforms based on high-low frequency separation according to claim 1, characterized in that, S1 includes: S11, determine the capacitor voltage of each low-frequency submodule in the low-frequency module group and the capacitor voltage of each high-frequency submodule in the high-frequency module group according to the DC bus voltage. S12, determine the target modulation voltage of the upper bridge arm and the target modulation voltage of the lower bridge arm according to the output reference voltage and the DC bus voltage, respectively; S13, determine the reference voltages of the low-frequency module group and the high-frequency module group in the upper and lower bridge arms respectively based on the target modulation voltage of the upper bridge arm and the target modulation voltage of the lower bridge arm.

3. The method for simulating MMC hardware-in-the-loop fault waveforms based on high-low frequency separation according to claim 2, characterized in that, S13 includes: S131, For each bridge arm, the target modulation voltage of the bridge arm is normalized according to the capacitor voltage of each low-frequency sub-module in the low-frequency module group, and the number of step voltage levels undertaken by the low-frequency module group is calculated by combining the floor function to obtain the reference voltage of the low-frequency module group in each bridge arm. S132, for each bridge arm, extract the remaining portion between the target modulation voltage of the bridge arm and the reference voltage of the low-frequency module group in each bridge arm as the reference voltage of the high-frequency module group in each bridge arm.

4. The method for simulating MMC hardware-in-the-loop fault waveforms based on high-low frequency separation according to claim 1, characterized in that, S2 include: S21, For each bridge arm, compare the average value of the capacitor voltage of each low-frequency submodule in the low-frequency module group with the sum of the capacitor voltage of each high-frequency submodule in the high-frequency module group, and determine the activation method of the high-frequency module group based on the comparison result and the direction of the bridge arm current. S22, For each bridge arm, a correction voltage is determined according to the engagement method of the high-frequency module group, and the reference voltage of the low-frequency module group and the reference voltage of the high-frequency module group are corrected according to the correction voltage to obtain the corrected reference voltage of the low-frequency module group and the corrected reference voltage of the high-frequency module group. S23, for each bridge arm, voltage modulation is performed on each low-frequency submodule in the low-frequency module group according to the corrected low-frequency module group reference voltage; voltage modulation is performed on each high-frequency submodule in the high-frequency module group according to the corrected high-frequency module group reference voltage.

5. The method for simulating MMC hardware-in-the-loop fault waveforms based on high-low frequency separation according to claim 4, characterized in that, S21 includes: If the comparison result shows that the average capacitor voltage of each low-frequency submodule in the low-frequency module group is greater than the sum of the capacitor voltages of each high-frequency submodule in the high-frequency module group, then the high-frequency module group adopts positive connection mode when the bridge arm current is greater than 0; and adopts negative connection mode when the bridge arm current is less than or greater than 0. If the comparison result shows that the average capacitor voltage of each low-frequency submodule in the low-frequency module group is less than the sum of the capacitor voltages of each high-frequency submodule in the high-frequency module group, then the high-frequency module group adopts the negative connection method when the bridge arm current is greater than 0; and adopts the positive connection method when the bridge arm current is less than or greater than 0.

6. The method for simulating MMC hardware-in-the-loop fault waveforms based on high-low frequency separation according to claim 4, characterized in that, S22 includes: S221, according to formula Determine the correction voltage ;in, This is the DC bus voltage; S222, according to formula Obtain the corrected reference voltage for the low-frequency module group. and the corrected high-frequency module group reference voltage ,in, This is the reference voltage for the low-frequency module group. This is the reference voltage for the high-frequency module group.

7. The method for simulating MMC hardware-in-the-loop fault waveforms based on high-low frequency separation according to claim 4, characterized in that, In S23, voltage modulation is performed on each low-frequency submodule in the low-frequency module group according to the corrected low-frequency module group reference voltage, including: The low-frequency sub-modules in the low-frequency module group are sorted by bubble sort. When the bridge arm current is greater than 0, the low-frequency sub-modules are connected according to the input of the capacitor voltage from small to large. When the bridge arm current is less than 0, the low-frequency sub-modules are connected according to the input of the capacitor voltage from large to small. The number of low-frequency sub-modules connected is related to the corrected reference voltage of the low-frequency module group.

8. The method for simulating MMC hardware-in-the-loop fault waveforms based on high-low frequency separation according to claim 4, characterized in that, When the high-frequency module group is in positive input mode, in step S23, voltage modulation is performed on each high-frequency sub-module in the high-frequency module group according to the corrected high-frequency module group reference voltage, including: S231, compare the corrected high-frequency module group reference voltage with x stacked carriers, wherein the voltage range of the x stacked carriers is the interval [0,1]; S232, determine the number of high-frequency sub-modules in the high-frequency module group that adopt positive input mode, bypass mode and PWM mode respectively according to the comparison results; S233, the bubble sort method is used to sort the capacitor voltages of each high-frequency submodule in the high-frequency module group; when the bridge arm current is greater than 0, the connection mode of each high-frequency submodule is set to positive connection mode, bypass mode, and PWM mode respectively according to the capacitor voltage of each high-frequency submodule in the high-frequency module group from small to large; when the bridge arm current is less than or greater than 0, the connection mode of each high-frequency submodule is set to positive connection mode, bypass mode, and PWM mode respectively according to the capacitor voltage of each high-frequency submodule in the high-frequency module group from large to small; wherein, if the instantaneous value of the corrected reference voltage of the high-frequency module group is greater than the instantaneous value of x stacked carriers, the high-frequency submodule using the PWM mode uses the positive connection mode; if the instantaneous value of the corrected reference voltage of the high-frequency module group is less than the instantaneous value of x stacked carriers, the high-frequency submodule using the PWM mode uses the bypass mode.

9. The method for simulating MMC hardware-in-the-loop fault waveforms based on high-low frequency separation according to claim 4, characterized in that, When the high-frequency module group is connected in a negative connection mode, step S23, which modulates the voltage of each high-frequency sub-module in the high-frequency module group according to the corrected reference voltage of the high-frequency module group, further includes: S234, compare the corrected high-frequency module group reference voltage with x stacked carriers, wherein the voltage range of the x stacked carriers is the interval [-1, 0]; S235, determine the number of high-frequency sub-modules in the high-frequency module group that adopt negative input mode, bypass mode and PWM mode respectively according to the comparison results; S236, the bubble sort method is used to sort the capacitor voltages of each high-frequency submodule in the high-frequency module group; when the bridge arm current is greater than 0, the connection mode of each high-frequency submodule is set to negative connection mode, bypass mode, and PWM mode respectively according to the capacitor voltage of each high-frequency submodule in the high-frequency module group from large to small; when the bridge arm current is less than or greater than 0, the connection mode of each high-frequency submodule is set to negative connection mode, bypass mode, and PWM mode respectively according to the capacitor voltage of each high-frequency submodule in the high-frequency module group from small to large; wherein, if the instantaneous value of the corrected reference voltage of the high-frequency module group is greater than the instantaneous value of x stacked carriers, the high-frequency submodule using the PWM mode uses the bypass mode; if the instantaneous value of the corrected reference voltage of the high-frequency module group is less than the instantaneous value of x stacked carriers, the high-frequency submodule using the PWM mode uses the negative connection mode.

10. A hardware-in-the-loop fault waveform simulation device based on high-low frequency separation (MMC), characterized in that, Includes an MMC device; the MMC device includes an upper bridge arm, a lower bridge arm, and a controller; The upper bridge arm and the lower bridge arm are symmetrically arranged; each bridge arm of the upper bridge arm and the lower bridge arm respectively includes a low-frequency module group and a high-frequency module group connected in series; the low-frequency module group includes n cascaded low-frequency sub-modules; the low-frequency sub-module is a half-bridge structure, including two first switching devices and their anti-parallel diodes and a first DC support capacitor; the high-frequency module group includes x cascaded high-frequency sub-modules; the high-frequency sub-module is a full-bridge structure, including four second switching devices and their anti-parallel diodes and a second DC support capacitor; x and n are positive integers; The controller is used to execute the MMC hardware-in-the-loop fault waveform simulation method based on high-low frequency separation as described in any one of claims 1 to 8.

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