A capacitance detection system and method

Abstract

This invention belongs to the field of detection circuit technology, specifically relating to a capacitance detection method and system. It includes an oscillation excitation unit, a micro-capacitor coupling amplification unit, a true RMS conversion unit, and a filter buffer output unit. The oscillation excitation unit generates a fixed-frequency, stable-amplitude sinusoidal AC excitation signal through an RC series-parallel frequency selection network. The micro-capacitor under test converts its capacitance change into an AC signal amplitude change, which is amplified by a non-inverting amplifier circuit and input to a true RMS chip, converting it into a DC voltage proportional to the capacitance. A three-stage RC low-pass filter network filters out high-frequency noise, and the non-inverting buffer isolates the load and outputs a stable detection voltage. The detection method achieves accurate micro-capacitor detection through a closed-loop process of excitation generation, capacitance coupling, RMS conversion, and filtering output. The voltage-capacitance linear correlation coefficient is ≥0.99. It features a simple structure, strong anti-interference capability, and is suitable for high-precision micro-capacitor detection scenarios.

Description

Technical Field

[0001] This invention belongs to the field of detection circuit technology, specifically relating to a capacitance detection system and method. Background Technology

[0002] Microcapacitance sensing technology is the core supporting technology for miniature capacitive pressure, humidity, and acceleration sensors. Its detection accuracy and stability directly determine the output reliability of the sensor, playing an irreplaceable role in industrial process monitoring, biomedical detection, and consumer electronics sensing. With the rapid popularization of the Internet of Things and portable smart devices, the demand for microcapacitance sensing in the 1pF~50pF range continues to grow, placing increasingly stringent requirements on the accuracy, cost, anti-interference capability, and integration of detection circuits.

[0003] Current microcapacitance detection technologies still have many shortcomings: the charge integration method relies on high-precision analog-to-digital converter chips and precision integrating devices, resulting in high hardware costs and susceptibility to power supply noise interference; the resonance method derives capacitance values ​​through LC resonant frequencies, but is sensitive to ambient temperature and parasitic parameters, making miniaturization and integration difficult; while the impedance analysis method has a simple structure, it is easily affected by distributed capacitance in small-capacity capacitance detection, failing to meet the requirements of high-precision scenarios. Furthermore, most solutions rely on dedicated chips or inductor components, which not only increases hardware costs but also expands circuit size and increases the risk of electromagnetic interference, limiting their application in portable devices and complex industrial environments. Summary of the Invention

[0004] This invention provides a capacitance detection system and method to solve the technical problems of existing micro-capacitance detection schemes, such as high hardware cost, weak anti-interference ability, low integration, and susceptibility to temperature and parasitic parameters, making it difficult to meet the requirements of high precision and miniaturization.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A capacitance detection system includes an oscillation excitation unit, a micro-capacitor coupling amplification unit, a true RMS conversion unit, and a filter buffer output unit, wherein the oscillation excitation unit, the micro-capacitor coupling amplification unit, the true RMS conversion unit, and the filter buffer output unit are sequentially connected in signal configuration. The oscillation excitation unit includes a first operational amplifier U1.1, which is connected to an RC series-parallel frequency selection network composed of resistors and capacitors connected in series and parallel. The RC series-parallel frequency selection network provides a positive feedback signal to the first operational amplifier U1.1 to generate a sinusoidal AC excitation signal with a fixed frequency. The microcapacitor coupling amplification unit is connected to the output terminal of the oscillation excitation unit. The microcapacitor coupling amplification unit includes a second operational amplifier U3.1. The non-inverting input terminal of the second operational amplifier U3.1 is connected to the microcapacitor to be tested. The inverting input terminal of the second operational amplifier U3.1 is connected to the second grounding resistor R8 and the second feedback resistor R9 in series. The output terminal of the second operational amplifier U3.1 is connected to the second feedback resistor R9, thus forming a non-inverting amplification circuit. The true RMS conversion unit includes a true RMS chip U2. The signal input terminal of the true RMS chip U2 is connected to the output terminal of the micro-capacitor-coupled amplifier unit, which is used to convert the AC signal into a DC voltage that is proportional to the RMS value of the signal. The filter buffer output unit includes a three-stage filter network and a non-inverting buffer. The three-stage filter network consists of three capacitors connected in series and grounded. A third operational amplifier U3.2 is used to form a non-inverting buffer. The non-inverting input terminal of the non-inverting buffer is connected to the output terminal of the three-stage filter network, and the inverting input terminal of the non-inverting buffer is connected to its own output terminal.

[0006] The RC series-parallel frequency selection network composed of series and parallel resistors and capacitors specifically includes a first resistor R1, a first capacitor C1, a second capacitor C2, and a fourth resistor. The first resistor R1 and the first capacitor C1 are connected in parallel. The non-inverting input terminal of the first operational amplifier U1.1 is connected to one end of the parallel line of the first resistor R1 and the first capacitor C1, and the other end of the parallel line of the first resistor R1 and the first capacitor C1 is grounded. The non-inverting input terminal of the first operational amplifier U1.1 is also connected to the series node of the second capacitor C2 and the fourth resistor R4. The first resistor R1 and the first capacitor C1 are connected in parallel, and the second capacitor C2 and the fourth resistor R4 are connected in series. After the first resistor R1 and the first capacitor C1 are connected in parallel, they are connected in series to one end of the series line of the second capacitor C2 and the fourth resistor R4, which together constitute the RC series-parallel frequency selection network.

[0007] The inverting input terminal of the first operational amplifier U1.1 is grounded through the first grounding resistor R2 and connected to the output terminal of the first operational amplifier U1.1 through the first bias resistor R3, forming a basic negative feedback branch.

[0008] The first bias resistor R3 and the first feedback resistor R5 are connected in series. The output terminal of the first operational amplifier U1.1 is also connected to one end of the first feedback resistor R5 in the series circuit of the first bias resistor R3 and the first feedback resistor R5. One end of the first bias resistor R3 in the series circuit of the first bias resistor R3 and the first feedback resistor R5 is connected in series with the first grounding resistor R2 to divide the voltage. The RC series-parallel frequency selection network, the first operational amplifier U1.1, the first grounding resistor R2, the first bias resistor R3, and the first feedback resistor R5 together constitute the RC series-parallel frequency selection oscillation circuit.

[0009] The non-inverting input of the second operational amplifier U3.1 is connected to the micro-capacitor under test. Specifically, the micro-capacitor coupling amplification unit also includes a buffer resistor R6 and a second bias resistor R7. One end of the buffer resistor R6 is connected to the output of the first operational amplifier U1.1, and the other end of the buffer resistor R6 is connected in series with the micro-capacitor under test C3 and the second bias resistor R7 and then grounded. The non-inverting input of the second operational amplifier U3.1 is connected to the series node of the micro-capacitor under test C3 and the second bias resistor R7.

[0010] The grounded end of the second bias resistor R7 is also connected to a second grounding resistor R8 and a second feedback resistor R9 in series. The inverting input terminal of the second operational amplifier U3.1 is connected to the series node of the second grounding resistor R8 and the second feedback resistor R9. The output terminal of the second operational amplifier U3.1 is connected to the second feedback resistor R9, forming a non-inverting amplifier circuit.

[0011] The VIN pin of the true RMS chip U2 is connected to the output terminal of the microcapacitor-coupled amplifier unit. The CS pin of the true RMS chip U2 is connected to one end of the third feedback resistor R10. The other end of the third feedback resistor R10 is connected to the +VS pin of the true RMS chip U2. The DEN_INPUT pin of the true RMS chip U2 is connected to one end of the compensation capacitor C4. The other end of the compensation capacitor C4 is connected to the CAV pin of the true RMS chip U2.

[0012] The three-stage filtering network includes a first-order RC low-pass filter, a higher-order RC filter, and a non-inverting buffer. The first-order RC low-pass filter includes a seventh capacitor C7, one end of which is connected to the series connection of resistors R11 and R12, and the other end is grounded, forming a first-order RC low-pass filter. The higher-order RC filter is as follows: the output signal of the true RMS chip U2 is input to the filter buffer output unit through resistor R11. The other end of resistor R11 is connected in series with the third grounding resistor R12 and resistor R13, and then connected to the non-inverting input of the third operational amplifier U3.2. The fifth capacitor C5 and the sixth capacitor C6 are connected in parallel, one end of which is connected to the series connection of resistors R11 and R12, and the other end is connected to the output of the third operational amplifier U3.2, together with resistors R12 and R13, forming a higher-order RC filter.

[0013] A capacitance detection method includes the following steps: The oscillation excitation unit filters a specific frequency signal through an RC series-parallel frequency selection network, and generates a fixed frequency sinusoidal AC excitation signal through positive feedback oscillation of the first operational amplifier U1.1; The sinusoidal AC excitation signal is transmitted to the microcapacitor under test through the buffer resistor of the microcapacitor coupling amplifier unit. The microcapacitor under test converts its capacitance change into an AC signal amplitude change, and the in-phase amplifier circuit amplifies the amplitude of the AC signal. The true RMS chip in the true RMS conversion unit receives the amplified AC signal and converts it into a DC voltage proportional to the signal's RMS value through internal calculations. The three-stage filtering network of the filter buffer output unit performs multi-stage low-pass filtering on the DC voltage to remove high-frequency noise and residual excitation signals. Then, the load is isolated by the in-phase buffer to output a stable capacitor detection signal.

[0014] When no microcapacitor under test is connected, the input signal amplitude of the microcapacitor coupling amplifier unit approaches 0, and the output voltage of the filter buffer output unit approaches 0, so the influence of parasitic capacitance can be ignored. When the microcapacitor under test C3 is connected, the output voltage is linearly proportional to the capacitance of the microcapacitor under test C3, and the capacitance value of the microcapacitor under test C3 can be directly obtained by voltage detection.

[0015] Compared with the prior art, the present invention has the following beneficial effects: This invention proposes an oscillation circuit that utilizes an RC series-parallel frequency selection network in the oscillation excitation unit in conjunction with a first operational amplifier. This eliminates the need for dedicated oscillation chips or inductors, significantly reducing hardware costs. Furthermore, it leverages the characteristic of capacitance impedance changing with frequency to achieve stable generation of a fixed-frequency sinusoidal excitation signal, minimizing the impact of ambient temperature variations on the excitation signal and improving circuit environmental adaptability. The micro-capacitor coupling amplification unit employs a buffer resistor coupled in series with the micro-capacitor under test, along with a second bias resistor to provide a stable DC bias. This effectively suppresses interference from parasitic and distributed capacitances on weak signals. A non-inverting amplifier circuit then precisely amplifies the AC signal converted from capacitance changes, ensuring that signal changes from small-capacity micro-capacitors are effectively captured and guaranteeing detection accuracy. The true RMS conversion unit directly converts the AC signal into a DC voltage proportional to the capacitance using a true RMS chip, avoiding noise and errors introduced in traditional analog-to-digital conversion. Combined with a third feedback resistor and a compensation capacitor, this further enhances conversion stability and dynamic response speed, ensuring that the converted DC voltage accurately reflects changes in the micro-capacitor's capacitance. The filter buffer output unit adopts a three-stage filter network formed by combining a first-order RC low-pass filter and a high-order RC filter to deeply filter out high-frequency noise and residual excitation signals in the DC voltage. Then, the influence of the subsequent load on the filter network is isolated by the in-phase buffer to ensure the stability of the output detection signal. At the same time, the overall circuit adopts a modular design, and each unit has a simple structure and is easy to integrate, effectively reducing the circuit size and meeting the application requirements of portable devices and complex industrial environments, achieving a balance between high precision and miniaturization. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a capacitance detection system module in an embodiment of the present invention; Figure 2This is a schematic diagram of the circuit structure of a capacitance detection system according to an embodiment of the present invention. Detailed Implementation

[0017] To further understand the content of this invention, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments are merely illustrative and not limiting of the invention.

[0018] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0019] Example 1 This embodiment proposes a capacitance detection system, such as Figure 1 As shown, it includes an oscillation excitation unit, a micro-capacitor-coupled amplification unit, a true RMS conversion unit, and a filter buffer output unit. By combining series-parallel frequency-selective oscillation with a high-precision true RMS conversion chip, the detection accuracy and signal stability are greatly improved. It adopts general-purpose dual operational amplifiers and standard resistor-capacitor components, which significantly reduces hardware costs. At the same time, it has excellent anti-interference capabilities and does not require inductors. The circuit topology is simplified, making it easier to miniaturize and integrate, and it is suitable for the application needs of portable devices and complex industrial scenarios.

[0020] Specifically, such as Figure 2 As shown, the oscillation excitation unit includes a first operational amplifier U1.1, a first resistor R1, a first capacitor C1, a second capacitor C2, a first bidirectional limiting diode D1, and a second bidirectional limiting diode D2. The oscillation excitation unit uses the first operational amplifier U1.1 as the core amplification device, and together with the first resistor R1, the first capacitor C1, and the second capacitor C2, it forms the main circuit of the oscillation excitation unit. Specifically, the first resistor R1 and the first capacitor C1 are connected in parallel. The non-inverting input terminal (pin 3) of the first operational amplifier U1.1 is connected to one end of the parallel line of the first resistor R1 and the first capacitor C1, and the other end of the parallel line of the first resistor R1 and the first capacitor C1 is grounded. At the same time, the non-inverting input terminal (pin 3) of the first operational amplifier U1.1 is connected to the series node of the second capacitor C2 and the fourth resistor R4. The first resistor R1 and the first capacitor C1 are connected in parallel, and the second capacitor C2 and the fourth resistor R4 are connected in series. After the first resistor R1 and the first capacitor C1 are connected in parallel, they are connected in series to one end of the series line of the second capacitor C2 and the fourth resistor R4, which together form an RC series-parallel frequency selection network. Since the capacitor impedance changes with the frequency, the RC series-parallel frequency selection network exhibits different transmission characteristics for input signals of different frequencies.

[0021] The other end of the series circuit of the second capacitor C2 and the fourth resistor R4 is connected to the output terminal (pin 1) of the first operational amplifier U1.1. The RC series-parallel frequency selection network obtains the signal through the output terminal (pin 1) of the first operational amplifier U1.1, selects the frequency, and feeds it back to the non-inverting input terminal of the first operational amplifier U1.1, providing a positive feedback signal that satisfies the sinusoidal oscillation phase condition for the first operational amplifier U1.1. The inverting input terminal (pin 2) of the first operational amplifier U1.1 is grounded through the first grounding resistor R2 and connected to the output terminal of the first operational amplifier U1.1 through the first bias resistor R3, forming the basic negative feedback branch. The first bias resistor R3 and the first feedback resistor R5 are connected in series. The output terminal of the first operational amplifier U1.1 is also connected to one end of the first feedback resistor R5 in the series circuit of the first bias resistor R3 and the first feedback resistor R5. One end of the first bias resistor R3 in the series circuit of the first bias resistor R3 and the first feedback resistor R5 is connected in series with the first grounding resistor R2 to divide the voltage. The RC series-parallel frequency selection network, the first operational amplifier U1.1, the first grounding resistor R2, the first bias resistor R3, and the first feedback resistor R5 together constitute an RC series-parallel frequency selection oscillation circuit, which has frequency selection characteristics and can filter and output a sinusoidal AC excitation signal of a fixed frequency.

[0022] The first bidirectional limiting diode D1 and the second bidirectional limiting diode D2 are connected in reverse parallel, then in parallel with the first feedback resistor R5, and connected between the output terminal of the first operational amplifier U1.1 and the first bias resistor R3. Utilizing the forward conduction characteristics of the first bidirectional limiting diode D1 and the second bidirectional limiting diode D2, the amplitude of the excitation signal is clamped to approximately ±0.7V. Amplitude stabilization is achieved by dynamically adjusting the negative feedback depth, ensuring the amplitude stability and waveform quality of the output signal. In this embodiment, the first operational amplifier U1.1 is powered by a dual ±15V power supply. Its negative power supply terminal (pin 4) is connected to a -15V voltage, and its positive power supply terminal (pin 8) is connected to a +15V voltage, providing operating power for the entire oscillation excitation unit.

[0023] The microcapacitor coupling amplification unit includes a microcapacitor under test (C3), a buffer resistor R6, a second bias resistor R7, a second grounding resistor R8, a second feedback resistor R9, and a second operational amplifier U3.1. One end of the buffer resistor R6 is connected to the output terminal of the first operational amplifier U1.1, and the other end of the buffer resistor R6 is connected in series with the microcapacitor under test (C3) and the second bias resistor R7 and then grounded. The buffer resistor R6 is connected in series between the output terminal of the oscillation excitation unit and the microcapacitor under test (C3), and the resistance value of the buffer resistor R6 is conjugate matched with the output impedance of the excitation unit. To reduce reflection loss during signal transmission, the non-inverting input (pin 3) of the second operational amplifier U3.1 is connected to the series connection of the micro-capacitor C3 under test and the second bias resistor R7. The micro-capacitor C3 can convert its capacitive reactance change into an AC signal amplitude change and couple this signal to the non-inverting input of the second operational amplifier U3.1. Simultaneously, one end of the second bias resistor R7 is connected to the non-inverting input of the second operational amplifier U3.1, and the other end is grounded, providing a stable 0V DC bias potential for the second operational amplifier U3.1 and preventing signal distortion. The grounded end of the second bias resistor R7 is also connected to a second grounding resistor R8 and a second feedback resistor R9 in series. The inverting input (pin 2) of the second operational amplifier U3.1 is connected to the series connection of the second grounding resistor R8 and the second feedback resistor R9. The output of the second operational amplifier U3.1 is connected to the second feedback resistor R9, forming a non-inverting amplifier circuit.

[0024] The true RMS conversion unit includes a true RMS chip U2, a third feedback resistor R10, and a compensation capacitor C4. The VIN pin of the true RMS chip U2 is connected to the output terminal of the micro-capacitor-coupled amplifier unit, serving as a signal input interface. The true RMS chip U2 converts the amplified AC signal output from the micro-capacitor-coupled amplifier unit into a DC voltage proportional to the signal's RMS value, thus eliminating the influence of AC signal fluctuations. One end of the third feedback resistor R10 is connected to the CS pin of the true RMS chip U2, and the other end is connected to the +VS pin of the true RMS chip U2. The third feedback resistor R10 provides a stable bias voltage to the CS pin, ensuring the stability of the internal operational circuitry of the true RMS chip U2. One end of the compensation capacitor C4 is connected to the DEN_INPUT pin of the true RMS chip U2, and the other end of the compensation capacitor C4 is connected to the CAV pin of the true RMS chip U2. The compensation capacitor C4 participates in the calculation of the internal integration stage of the true RMS chip U2 to ensure the dynamic response characteristics of the RMS conversion, and also suppresses the high-frequency noise generated during the chip operation.

[0025] The filter buffer output unit consists of a three-stage filter network and a non-inverting buffer, mainly including resistor R11, third grounding resistor R12, resistor R13, fifth capacitor C5, sixth capacitor C6, seventh capacitor C7, and third operational amplifier U3.2, which is connected as a non-inverting buffer; one end of resistor R11 is connected to the RMS_OUT pin of the true RMS chip U2, and the output signal of the true RMS chip U2 is input to the filter buffer output unit through resistor R11. The other end of resistor R11 is connected in series with the third grounding resistor R12 and resistor R13, and then connected to the non-inverting input (pin 5) of the third operational amplifier U3.2. The fifth capacitor C5 and the sixth capacitor C6 are connected in parallel, with one end connected to the series node of resistors R11 and R12 and the other end connected to the output of the third operational amplifier U3.2. Together with resistors R12 and R13, they form a high-order RC filter to further smooth the signal, suppress high-frequency noise, and purify the DC component. One end of the seventh capacitor C7 is connected to the series node of resistors R11 and R12, and the other end is connected to ground, forming a first-order RC low-pass filter. The non-inverting input of the third operational amplifier U3.2 is connected to resistor R13, and the inverting input of the third operational amplifier U3.2 is shorted to its own output to isolate the filter network from the subsequent load, further smooth the output signal, and finally output a stable detection signal from the VO port. The first-order RC low-pass filter, the higher-order RC filter, and the third operational amplifier U3.2 connected as a non-inverting buffer constitute a three-stage filtering network. The cutoff frequency of the three-stage low-pass filter network is designed to be much lower than the output frequency of the oscillation excitation unit, so as to achieve ≥40dB attenuation of the residual excitation signal and filter out high-frequency noise.

[0026] Example 2 Based on the capacitance detection system proposed in Embodiment 1, this embodiment proposes a capacitance detection method for detecting the micro capacitance C3 to be tested, specifically including the following steps: First, the oscillation excitation unit, micro-capacitor coupled amplification unit, true RMS conversion unit, and filter buffer output unit are connected to preset power supplies. The first operational amplifier U1.1 is connected to a dual ±15V power supply (pin 4 is connected to -15V and pin 8 is connected to +15V). The true RMS chip U2, the second operational amplifier U3.1, and the third operational amplifier U3.2 are all connected to their respective operating power supplies. The grounding resistors and bias resistors in each unit are in preset connection states to ensure that each chip is initialized to a ready-to-work state without any abnormal level drift.

[0027] In the oscillation excitation unit, the RC series-parallel frequency selection network composed of the first operational amplifier U1.1, the first resistor R1 (100Ω), the first capacitor C1 (22nF), the fourth resistor R4 (10kΩ), and the second capacitor C2 (22nF) starts working. It filters out a sinusoidal signal of a specific frequency by utilizing the characteristic of the capacitor impedance changing with frequency. The RC series-parallel frequency selection network obtains the signal from the output terminal of the first operational amplifier U1.1, and after frequency selection, feeds it back to the non-inverting input terminal of the first operational amplifier U1.1 to meet the phase condition of sinusoidal oscillation and form continuous oscillation. The first bidirectional limiting diode D1 and the second bidirectional limiting diode D2 connected in reverse parallel dynamically adjust the negative feedback depth to clamp the amplitude of the excitation signal to ±0.7V to avoid signal clipping distortion. Finally, a sinusoidal AC excitation signal with fixed frequency and stable amplitude is output from the output terminal of the first operational amplifier U1.1.

[0028] The microcapacitor C3 under test is connected in series between the buffer resistor R6 (100Ω) and the second bias resistor R7 (15kΩ). The sinusoidal AC excitation signal output by the oscillation excitation unit is transmitted to the microcapacitor C3 under test through the buffer resistor R6. Since the capacitive reactance of the microcapacitor C3 under test is inversely proportional to its capacitance, the microcapacitor C3 under test converts its capacitance change into an AC signal amplitude change. At the same time, the second bias resistor R7 provides a stable 0V DC bias for the second operational amplifier U3.1, avoiding distortion of the AC signal due to bias drift, and ensuring that the amplitude change of the coupled signal is determined only by the capacitance of the microcapacitor C3 under test.

[0029] The inverting input (pin 2) of the second operational amplifier U3.1 is connected to the series connection of the second grounding resistor R8 and the second feedback resistor R9. The second operational amplifier U3.1, the second grounding resistor R8, and the second feedback resistor R9 form a non-inverting amplifier circuit. In this embodiment, the amplification factor is preset to 11 times. The non-inverting input of the second operational amplifier U3.1 receives the AC signal coupled to the micro capacitor C3 under test. After internal amplification, the AC signal amplified by 11 times is output from the output of the second operational amplifier U3.1. The amplitude of this signal is linearly related to the capacitance of the micro capacitor C3 under test, providing a signal basis with sufficient amplitude for subsequent effective value conversion.

[0030] The VIN pin of the true RMS chip U2 receives the AC signal amplified 11 times from the output of the second operational amplifier U3.1. The true RMS chip U2 internally converts the amplified AC signal into a DC voltage proportional to the signal's effective value through integration and RMS calculation circuits. The third feedback resistor R10 (10kΩ) provides a stable bias voltage to the CS pin of the true RMS chip U2, preventing the internal operation circuit from being affected by power supply fluctuations in conversion accuracy. The compensation capacitor C4 (10nF) participates in the internal integration stage to suppress high-frequency noise and ensure that the converted DC voltage is smooth and without fluctuations. The DC voltage output from the RMS_OUT pin of the true RMS chip U2 is transmitted to the filter branch via resistor R11. One end of the seventh capacitor C7 (100nF) is connected to the series node of resistors R11 and R12, and the other end of the seventh capacitor C7 (100nF) is grounded, forming a first-order RC low-pass filter to initially filter out the high-frequency noise remaining during the conversion process. The fifth capacitor C5 (10nF) and the sixth capacitor C6 (10nF) are connected in parallel, with one end connected to the series node of resistors R11 and R12 (12kΩ), and the other end connected to the output of the third operational amplifier U3.2. Together with resistors R12 and R13 (1kΩ), they form a high-order RC low-pass filter to filter out the residual excitation signal and further purify the DC component. The third operational amplifier U3.2 is configured as a non-inverting voltage buffer to receive the DC voltage after three stages of filtering. Through its high input impedance and low output impedance characteristics, it isolates the influence of the downstream load on the filter network and finally outputs a stable DC detection voltage from the VO port.

[0031] In a preferred embodiment of the present invention, when no microcapacitor C3 is connected, the amplitude of the input signal of the microcapacitor coupling amplification unit approaches 0, and the output voltage of the filter buffer output unit approaches 0, so the influence of parasitic capacitance can be ignored; when the microcapacitor C3 is connected, the output voltage is linearly proportional to the capacitance of the microcapacitor C3, and the capacitance value of the microcapacitor C3 can be directly obtained by voltage detection.

[0032] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be appropriately combined to form other embodiments that can be understood by those skilled in the art. The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A capacitance detection system, characterized in that, It includes an oscillation excitation unit, a micro-capacitor coupled amplification unit, a true RMS conversion unit, and a filter buffer output unit, which are sequentially connected in signal configuration. The oscillation excitation unit includes a first operational amplifier U1.1, which is connected to an RC series-parallel frequency selection network composed of resistors and capacitors connected in series and parallel. The RC series-parallel frequency selection network provides a positive feedback signal to the first operational amplifier U1.1 to generate a sinusoidal AC excitation signal with a fixed frequency. The microcapacitor coupling amplification unit is connected to the output terminal of the oscillation excitation unit. The microcapacitor coupling amplification unit includes a second operational amplifier U3.

1. The non-inverting input terminal of the second operational amplifier U3.1 is connected to the microcapacitor to be tested. The inverting input terminal of the second operational amplifier U3.1 is connected to the second grounding resistor R8 and the second feedback resistor R9 in series. The output terminal of the second operational amplifier U3.1 is connected to the second feedback resistor R9, thus forming a non-inverting amplification circuit. The true RMS conversion unit includes a true RMS chip U2. The signal input terminal of the true RMS chip U2 is connected to the output terminal of the micro-capacitor-coupled amplifier unit, which is used to convert the AC signal into a DC voltage that is proportional to the RMS value of the signal. The filter buffer output unit includes a three-stage filter network and a non-inverting buffer. The three-stage filter network consists of three capacitors connected in series and grounded. A third operational amplifier U3.2 is used to form a non-inverting buffer. The non-inverting input terminal of the non-inverting buffer is connected to the output terminal of the three-stage filter network, and the inverting input terminal of the non-inverting buffer is connected to its own output terminal.

2. The capacitance detection system according to claim 1, characterized in that, The RC series-parallel frequency selection network composed of series and parallel resistors and capacitors specifically includes a first resistor R1, a first capacitor C1, a second capacitor C2, and a fourth resistor R4. The first resistor R1 and the first capacitor C1 are connected in parallel. The non-inverting input terminal of the first operational amplifier U1.1 is connected to one end of the parallel line of the first resistor R1 and the first capacitor C1, and the other end of the parallel line of the first resistor R1 and the first capacitor C1 is grounded. The non-inverting input terminal of the first operational amplifier U1.1 is also connected to the series node of the second capacitor C2 and the fourth resistor R4. The first resistor R1 and the first capacitor C1 are connected in parallel, and the second capacitor C2 and the fourth resistor R4 are connected in series. After the first resistor R1 and the first capacitor C1 are connected in parallel, they are connected in series to one end of the series line of the second capacitor C2 and the fourth resistor R4, which together constitute the RC series-parallel frequency selection network.

3. The capacitance detection system according to claim 2, characterized in that, The inverting input terminal of the first operational amplifier U1.1 is grounded through the first grounding resistor R2 and connected to the output terminal of the first operational amplifier U1.1 through the first bias resistor R3, forming a basic negative feedback branch.

4. The capacitance detection system according to claim 3, characterized in that, The first bias resistor R3 and the first feedback resistor R5 are connected in series. The output terminal of the first operational amplifier U1.1 is also connected to one end of the first feedback resistor R5 in the series circuit of the first bias resistor R3 and the first feedback resistor R5. One end of the first bias resistor R3 in the series circuit of the first bias resistor R3 and the first feedback resistor R5 is connected in series with the first grounding resistor R2 to divide the voltage. The RC series-parallel frequency selection network, the first operational amplifier U1.1, the first grounding resistor R2, the first bias resistor R3, and the first feedback resistor R5 together constitute the RC series-parallel frequency selection oscillation circuit.

5. The capacitance detection system according to claim 1, characterized in that, The non-inverting input of the second operational amplifier U3.1 is connected to the micro-capacitor under test. Specifically, the micro-capacitor coupling amplification unit also includes a buffer resistor R6 and a second bias resistor R7. One end of the buffer resistor R6 is connected to the output of the first operational amplifier U1.1, and the other end of the buffer resistor R6 is connected in series with the micro-capacitor under test C3 and the second bias resistor R7 and then grounded. The non-inverting input of the second operational amplifier U3.1 is connected to the series node of the micro-capacitor under test C3 and the second bias resistor R7.

6. The capacitance detection system according to claim 5, characterized in that, The grounded end of the second bias resistor R7 is also connected to a second grounding resistor R8 and a second feedback resistor R9 in series. The inverting input terminal of the second operational amplifier U3.1 is connected to the series node of the second grounding resistor R8 and the second feedback resistor R9. The output terminal of the second operational amplifier U3.1 is connected to the second feedback resistor R9, forming a non-inverting amplifier circuit.

7. The capacitance detection system according to claim 1, characterized in that, The VIN pin of the true RMS chip U2 is connected to the output terminal of the microcapacitor-coupled amplifier unit. The CS pin of the true RMS chip U2 is connected to one end of the third feedback resistor R10. The other end of the third feedback resistor R10 is connected to the +VS pin of the true RMS chip U2. The DEN_INPUT pin of the true RMS chip U2 is connected to one end of the compensation capacitor C4. The other end of the compensation capacitor C4 is connected to the CAV pin of the true RMS chip U2.

8. The capacitance detection system according to claim 1, characterized in that, The three-stage filtering network includes a first-order RC low-pass filter, a higher-order RC filter, and a non-inverting buffer. The first-order RC low-pass filter includes a seventh capacitor C7. One end of the seventh capacitor C7 is connected to the series node of resistors R11 and R12, and the other end is connected to ground, thus forming a first-order RC low-pass filter. The higher-order RC filter is as follows: the output signal of the true RMS chip U2 is input to the filter buffer output unit through resistor R11. The other end of resistor R11 is connected in series with the third grounding resistor R12 and resistor R13, and then connected to the non-inverting input terminal of the third operational amplifier U3.

2. The fifth capacitor C5 and the sixth capacitor C6 are connected in parallel, with one end connected to the series node of resistors R11 and R12, and the other end connected to the output terminal of the third operational amplifier U3.2, together with resistors R12 and R13, forming a higher-order RC filter.

9. A capacitance detection method, based on a capacitance detection system according to any one of claims 1 to 8, characterized in that, Includes the following steps: The oscillation excitation unit filters a specific frequency signal through an RC series-parallel frequency selection network, and generates a fixed frequency sinusoidal AC excitation signal through positive feedback oscillation of the first operational amplifier U1.1; The sinusoidal AC excitation signal is transmitted to the microcapacitor under test through the buffer resistor of the microcapacitor coupling amplifier unit. The microcapacitor under test converts its capacitance change into an AC signal amplitude change, and the in-phase amplifier circuit amplifies the amplitude of the AC signal. The true RMS chip in the true RMS conversion unit receives the amplified AC signal and converts it into a DC voltage proportional to the signal's RMS value through internal calculations. The three-stage filtering network of the filter buffer output unit performs multi-stage low-pass filtering on the DC voltage to remove high-frequency noise and residual excitation signals. Then, the load is isolated by the in-phase buffer to output a stable capacitor detection signal.

10. A capacitance detection method according to claim 9, characterized in that, When no microcapacitor under test is connected, the input signal amplitude of the microcapacitor coupling amplifier unit approaches 0, and the output voltage of the filter buffer output unit approaches 0, so the influence of parasitic capacitance can be ignored. When the microcapacitor under test C3 is connected, the output voltage is linearly proportional to the capacitance of the microcapacitor under test C3, and the capacitance value of the microcapacitor under test C3 can be directly obtained by voltage detection.

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