Fpga prototype platform fifo buffer mapping method, device, equipment and medium
By optimizing FIFO mapping based on clock frequency ratio and resource planning information in the FPGA prototyping platform, the problem of resource, timing and layout separation in the prior art is solved, and efficient FPGA prototyping is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
- Filing Date
- 2026-03-20
- Publication Date
- 2026-06-19
AI Technical Summary
In existing technologies, ASIC design requires extensive manual code modification in FPGA prototypes to iterate repeatedly on FIFO resources, timing, and layout, which prolongs the FPGA prototype production cycle.
By determining the basic information of the first-in-first-out (FIFO) buffer based on the preset clock frequency ratio and register transfer level source file, the buffers to be mapped are selected. By combining the FPGA mapping relationship dynamic programming component and the preset dynamic programming algorithm, resource planning and layout priority are optimized to achieve automated mapping.
This avoids repeated iterations of resources, timing, and layout, improves mapping efficiency, and shortens the FPGA prototype production cycle.
Smart Images
Figure CN122240180A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and in particular to a first-in-first-out (FIFO) buffer mapping method, apparatus, device, and medium for FPGA prototyping platforms. Background Technology
[0002] Currently, due to the different structural principles of ASIC chips (Application Specific Integrated Circuits) and FPGA chips (Field Programmable Gate Arrays), porting ASIC designs to FPGA prototypes still requires corresponding adaptation work to the RTL (Register Transfer Level) code. This process mainly involves mapping the ASIC code to the corresponding underlying resources in the FPGA.
[0003] However, existing solutions often involve fragmented iterations of resources, timing, and layout. For cases where multiple FIFOs (First In First Out) in an ASIC are not mapped to a single resource, manual modification of the corresponding code is required to differentiate them. Furthermore, the process of adapting and modifying the FIFO's RTL underlying code for the FPGA prototype requires extensive manual intervention, consuming a significant amount of time and increasing uncontrollable risks to the FPGA prototype production cycle. This can easily cause delays for subsequent prototype verification work.
[0004] It is evident that how to avoid the iterative problems of separating resources, timing, and layout in existing related solutions, thereby improving mapping efficiency and shortening the FPGA prototype production cycle, is a problem that needs to be solved by those skilled in the art. Summary of the Invention
[0005] The purpose of this invention is to provide a first-in, first-out (FIFO) buffer mapping method, apparatus, device, and medium for FPGA prototyping platforms. This addresses the problem of avoiding the iterative issues of separating resources, timing, and layout in existing solutions, thereby improving mapping efficiency and shortening the FPGA prototype manufacturing cycle. The specific solution is as follows: In a first aspect, the present invention provides a first-in-first-out (FIFO) buffer mapping method for an FPGA prototype platform, comprising: Based on the preset clock frequency ratio and the register transfer level source file corresponding to the application-specific integrated circuit (ASIC), the basic information of the FIFO buffer corresponding to the ASIC is determined; the basic information of the FIFO buffer includes the clock frequency coefficient. Use the basic information of the first-in-first-out (FIFO) buffer to determine the FIFO buffer to be mapped; Based on the preset storage resource usage information, determine the resource planning information and layout priority of each first-in-first-out cache to be mapped; The FPGA mapping relationship is used to dynamically plan components, and the mapping allocation result of the first-in-first-out buffer is determined based on the preset dynamic planning algorithm, the resource planning information and layout priority of each first-in-first-out buffer to be mapped; Based on the first-in-first-out (FIFO) buffer mapping allocation results, resource mapping is performed on the FPGA prototype platform so as to update the register transfer level source file using the corresponding resource mapping results.
[0006] Optionally, based on a preset clock frequency ratio and the register transfer level source file corresponding to the application-specific integrated circuit (ASIC), the basic information of the FIFO (First-In-First-Out) buffer corresponding to the ASIC is determined, including: After completing the compilation of the register transfer level source file corresponding to the application-specific integrated circuit, the preset clock frequency ratio and the register transfer level source file are obtained; wherein, the preset clock frequency ratio is the expected ratio of each clock in the FPGA prototype version; Extract code from the register transfer level source file to determine the first-in-first-out buffer code; Based on the FIFO buffer code, determine the size, depth, and width information of the FIFO buffer; Based on the FIFO buffer code and the preset clock frequency ratio, timing analysis of the FIFO buffer is performed to determine the clock domain and clock frequency coefficient corresponding to each FIFO buffer. Based on the clock domain, clock frequency coefficient, size information, depth information, and width information corresponding to each FIFO buffer, the basic information of the FIFO buffer corresponding to the application-specific integrated circuit is determined.
[0007] Optionally, using the basic information of the first-in-first-out (FIFO) cache, determine the FIFO cache to be mapped, including: For any first-in-first-out buffer, based on the number of URAMs available, determine whether the current size information is greater than the first preset size data to determine the first size determination result; If the result of the first size determination is greater than the first preset size data, then the current first-in-first-out buffer is determined as the first first-in-first-out buffer; If the first size determination result is not greater than the first preset size data, then determine whether the current size information is less than the second preset size data to determine the second size determination result; If the result of the second size determination is less than the second preset size data, then the current first-in-first-out buffer is determined as the second first-in-first-out buffer; If the result of the second size determination is not less than the second preset size data, then the current first-in-first-out buffer is determined as the first-in-first-out buffer to be mapped. Based on the number of URAMs available, several first-in-first-out (FIFO) caches are selected to obtain the selected third-in-first-out (FIFO) cache. Map the third first-in-first-out buffer to the corresponding URAM; Map the second FIFO buffer to the corresponding LUTRAM or flip-flop.
[0008] Optionally, based on preset storage resource usage information, determine the resource planning information and layout priority corresponding to each first-in-first-out cache to be mapped, including: Based on the size information, width information, and the number of BRAMs to be used, determine the target number of BRAMs corresponding to each first-in-first-out buffer to be mapped. Based on the target number of BRAMs, determine the BRAM occupancy size information corresponding to each first-in-first-out (FIFO) cache to be mapped; Based on the BRAM occupancy size information, preset weight value, and size information of each unmapped FIFO cache, the layout priority of each unmapped FIFO cache is determined.
[0009] Optionally, the FPGA mapping relationship dynamic programming component is used, and based on a preset dynamic programming algorithm, the resource planning information and layout priority of each FIFO buffer to be mapped, the FIFO buffer mapping allocation result is determined, including: Based on the preset dynamic programming algorithm, the resource planning information and layout priority of each first-in-first-out cache to be mapped, the target dynamic programming function is determined. Based on the FPGA mapping relationship dynamic programming component, the number of BRAMs to be used, the target dynamic programming function, resource planning information, layout priority, and FIFO buffer basic information, the target FIFO buffer to be mapped as BRAM is determined from the FIFO buffers to be mapped. The statistical results of the caches are determined by identifying the FIFO caches other than the target FIFO cache among the FIFO caches to be mapped.
[0010] Optionally, based on the first-in-first-out (FIFO) buffer mapping allocation results, resource mapping for the FPGA prototype platform is performed, including: Map the target first-in-first-out buffer to the corresponding BRAM; Map the first-in-first-out (FIFO) caches in the cache statistics to the corresponding LUTRAMs.
[0011] Optionally, the FIFO buffer mapping method for the FPGA prototyping platform also includes: After updating the register transfer level source file, obtain the corresponding updated source file; The updated source files are logically synthesized using a tool to determine the logical synthesis result. Based on the results of tool and logic synthesis, the implementation process is executed, and an attempt is made to achieve timing convergence; If, after implementation, a corresponding first-in-first-out (FIFO) cache layout and routing congestion report and / or timing violation report are obtained, the preset storage resource occupancy information is updated, and the new preset storage resource occupancy information is used to jump back to the step of determining the resource planning information and layout priority of each FIFO cache to be mapped based on the preset storage resource occupancy information. If no FIFO buffer placement and routing congestion report or timing violation report is obtained after implementation, the bit file corresponding to the FPGA prototype platform is determined based on the updated source file.
[0012] Secondly, the present invention provides a first-in-first-out (FIFO) buffer mapping device for an FPGA prototyping platform, comprising: The basic information determination module is used to determine the basic information of the first-in-first-out (FIFO) buffer corresponding to the application-specific integrated circuit (ASIC) based on a preset clock frequency ratio and the register transfer level source file corresponding to the ASIC; wherein, the basic information of the FIFO buffer includes the clock frequency coefficient; The module for determining the cache to be mapped is used to determine the FIFO cache to be mapped by utilizing the basic information of the FIFO cache. The planning information determination module is used to determine the resource planning information and layout priority of each first-in-first-out cache to be mapped based on the preset storage resource occupancy information. The mapping and allocation module is used to dynamically plan components using FPGA mapping relationships, and to determine the first-in-first-out (FIFO) buffer mapping and allocation results based on a preset dynamic planning algorithm, resource planning information and layout priority of each FIFO buffer to be mapped; The mapping result determination module is used to perform resource mapping on the FPGA prototype platform based on the first-in-first-out buffer mapping allocation result, so as to update the register transfer level source file using the corresponding resource mapping result.
[0013] Thirdly, the present invention provides an electronic device, comprising: Memory, used to store computer programs; A processor is used to execute computer programs to implement the steps of the aforementioned FPGA prototype platform's first-in-first-out cache mapping method.
[0014] Fourthly, the present invention provides a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the aforementioned FPGA prototype platform first-in-first-out cache mapping method.
[0015] As can be seen, in this invention, based on a preset clock frequency ratio and the register transfer level source file corresponding to the application-specific integrated circuit (ASIC), the basic information of the FIFO buffer corresponding to the ASIC is determined; wherein, the basic information of the FIFO buffer includes a clock frequency coefficient; using the basic information of the FIFO buffer, the FIFO buffer to be mapped is determined; based on preset storage resource occupancy information, the resource planning information and layout priority corresponding to each FIFO buffer to be mapped are determined; using FPGA mapping relationship dynamic planning components, and based on a preset dynamic planning algorithm, the resource planning information and layout priority corresponding to each FIFO buffer to be mapped, the FIFO buffer mapping allocation result is determined; based on the FIFO buffer mapping allocation result, resource mapping of the FPGA prototype platform is performed, so as to update the register transfer level source file using the corresponding resource mapping result.
[0016] As can be seen from the above technical solution, in this invention, firstly, the basic information of the FIFO buffer, including the clock frequency coefficient, is determined using a preset clock frequency ratio relationship and the register transfer level source file corresponding to the application-specific integrated circuit (ASIC). Then, using this basic information, FIFO buffers to be mapped are selected. Next, based on preset storage resource occupancy information, the resource planning information and layout priority of the FIFO buffers to be mapped are determined, and combined with the FPGA mapping dynamic programming component and a preset dynamic programming algorithm, the FIFO buffer mapping allocation result is determined. Finally, based on the FIFO buffer mapping allocation result, resource mapping is performed on the FPGA prototype platform, and the obtained resource mapping result is used to update the register transfer level source file. The beneficial effect of this invention is that it avoids the iterative problem of separating resources, timing, and layout in existing related solutions, thereby improving mapping efficiency and shortening the FPGA prototype version manufacturing cycle. Attached Figure Description
[0017] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A flowchart of a first-in-first-out (FIFO) buffer mapping method for an FPGA prototype platform provided by the present invention; Figure 2A flowchart of a specific FPGA prototype platform first-in-first-out buffer mapping method provided by the present invention; Figure 3 A schematic diagram of a first-in-first-out (FIFO) buffer mapping device for an FPGA prototype platform provided by the present invention. Figure 4 This invention provides a structural diagram of an electronic device. Detailed Implementation
[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.
[0020] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.
[0021] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0022] Existing solutions often involve fragmented iterations of resources, timing, and layout. For cases where multiple FIFOs (First In First Out) in an ASIC are not mapped to a single resource, manual modification of the corresponding code is required to differentiate them. Furthermore, the process of adapting and modifying the FIFO's RTL underlying code for the FPGA prototype requires extensive manual intervention, consuming a significant amount of time and increasing uncontrollable risks to the FPGA prototype production cycle. This can easily cause delays for subsequent prototype verification work.
[0023] To address this, the present invention provides a first-in-first-out (FIFO) buffer mapping scheme for FPGA prototyping platforms, which avoids the repeated iteration problems of separating resources, timing, and layout in existing related schemes, thereby improving mapping efficiency and shortening the FPGA prototype production cycle.
[0024] See Figure 1 As shown, this embodiment of the invention discloses a first-in-first-out (FIFO) buffer mapping method for an FPGA prototype platform, including: Step S11: Based on the preset clock frequency ratio and the register transfer level source file corresponding to the application-specific integrated circuit (ASIC), determine the basic information of the FIFO buffer corresponding to the ASIC; wherein, the basic information of the FIFO buffer includes the clock frequency coefficient.
[0025] In this embodiment, the basic information of the required first-in-first-out (FIFO) buffer must first be determined, which may include, but is not limited to, the actual size of the FIFO. (Unit: Kb) Depth ,width The clock frequency coefficient is In other words, after compiling the register-transfer level source file corresponding to the application-specific integrated circuit (ASIC), the preset clock frequency ratio and the register-transfer level source file are obtained. The preset clock frequency ratio is the expected ratio of each clock in the FPGA prototype version. Code extraction is performed on the register-transfer level source file to determine the FIFO (First-In-First-Out) buffer code. Based on the FIFO buffer code, the size, depth, and width information of the FIFO buffer are determined. Timing analysis of the FIFO buffer is performed based on the FIFO buffer code and the preset clock frequency ratio to determine the clock domain and clock frequency coefficient corresponding to each FIFO buffer. Based on the clock domain, clock frequency coefficient, size, depth, and width information corresponding to each FIFO buffer, the basic information of the FIFO buffer corresponding to the ASIC is determined.
[0026] It is important to understand that, in combination Figure 2 As shown, in this embodiment, a FIFO size and clock domain scanning component, i.e., a first-in-first-out (FIFO) buffer size and clock domain scanning component, is used to extract the FIFO code from the RTL source file by analyzing and identifying it, and to identify the actual size of the FIFO within it. ,depth ,width Furthermore, the clock domain of each FIFO was analyzed, and the timing information was mapped to the FIFOs according to the clock frequency ratio (the lowest clock frequency is 1, and the remaining clock frequencies are multiples of it). Finally, the clock frequency coefficient of each FIFO was determined. For asynchronous FIFOs, the two clock frequencies with the highest frequencies are selected for the values.
[0027] Understandably, before determining the basic information of the first-in-first-out (FIFO) buffer, some processing is required on the register transfer level source file corresponding to the application-specific integrated circuit (ASIC). Specifically, the RTL source file is imported into the EDA (Electronic Design Automation) tool, and the design file is diagnosed after compilation to complete the compilation of the design circuit.
[0028] At the same time, combined Figure 2 As shown, the RTL source file and clock frequency ratio (i.e., the ratio of each clock in the FPGA prototype version) also need to be imported into the FIFO size and clock domain scanning component. The user's upper limit settings for the number of BRAM and URAM that the FIFO can occupy are provided to the dynamic programming array and value range construction component and the FIFO pre-screening component. The FIFO user weight settings are input to the FIFO layout priority calculation component. These FIFO weight settings are parameters that FPGA developers want to introduce when certain critical FIFOs are preferentially mapped to BRAM / URAM. BRAM (Block Random Access Memory) is an important storage resource in FPGAs. For example, in a certain type of FPGA, a single BRAM can store up to 36Kb of data with a bit width less than 72 bits. It can be split into two independent BRAMs with a bit width of 36 bits and a size of 18Kb each. URAM (UltraRAM) is a larger storage resource than BRAM in a certain type of FPGA. A single URAM can store 288Kb of data, with a maximum bit width of 72 bits.
[0029] Furthermore, if the clock domain in the ASIC design is complex (e.g., with gated clocks, asynchronous FIFOs, or multi-level frequency multiplication / division), relying solely on preset clock frequency ratios may not accurately reflect the actual timing pressure across clock domains, leading to distortion of basic information. Therefore, in this embodiment, an asynchronous clock domain cross-analysis step can be added to the step of determining the basic information of the FIFO buffer. This step can be encapsulated as a dedicated engine. This engine not only reads the preset clock frequency ratio but also performs static timing analysis (STA-like scan) on the ASIC's RTL code, automatically extracting the actual clock topology. For asynchronous FIFOs, the basic information can be dynamically corrected based on the actual frequency difference and phase relationship between the two clocks. This allows subsequent resource planning to reserve more timing margin or additional synchronization register resources for asynchronous FIFOs, avoiding mapping failures caused by clock domain misjudgments.
[0030] Step S12: Use the basic information of the first-in-first-out (FIFO) buffer to determine the FIFO buffer to be mapped.
[0031] In this embodiment, combined with Figure 2As shown, after determining the basic information of the FIFO buffer, it is necessary to filter out the FIFO buffers that require further processing in subsequent steps based on the obtained basic information. That is: for the size information corresponding to any FIFO buffer, based on the number of URAMs to be used, it is determined whether the current size information is greater than a first preset size data to determine the first size judgment result; if the first size judgment result is greater than the first preset size data, then the current FIFO buffer is determined as the first FIFO buffer; if the first size judgment result is not greater than the first preset size data, then it is determined whether the current size information is less than a second preset size data. The size data is used to determine the second size judgment result; if the second size judgment result is smaller than the second preset size data, then the current FIFO buffer is determined as the second FIFO buffer; if the second size judgment result is not smaller than the second preset size data, then the current FIFO buffer is determined as the FIFO buffer to be mapped; based on the number of URAMs to be used, several first FIFO buffers are selected to obtain the selected third FIFO buffer; the third FIFO buffer is mapped to the corresponding URAM; the second FIFO buffer is mapped to the corresponding LUTRAM or trigger. It is understood that the first and second preset size data can be configured or updated based on actual needs.
[0032] LUTRAM (Look-Up-Table Random Access Memory) is a special type of LUT (Look-Up-Table) that can be used to implement logical functions with memory capabilities, such as memory or RAM (Random Access Memory). Its advantages are that it is more flexible in size and location and does not cause waste of resources. However, using it to build larger memory can cause congestion and wiring problems.
[0033] Understandably, in combination Figure 2As shown, regarding the selection of FIFO buffers to be mapped, this embodiment utilizes a FIFO pre-screening component. The FIFO pre-screening component selects buffers based on the analyzed FIFO size. When the size is less than 1Kb, LUTs and FFs (Flip-Flops) are used for construction. Furthermore, based on the available URAM quantity, the FIFOs with the largest quantity are selected and constructed using URAM. The remaining FIFOs are retained for subsequent processes. This process eliminates smaller FIFOs (i.e., those with large bit width but small depth) that would result in significant resource waste when constructed using BRAM, and it also improves URAM resource utilization. In other words, by using the FIFO pre-screening component, larger FIFOs are allocated according to the available URAM quantity, and very small FIFOs are constructed using LUTRAM, avoiding the introduction of low resource utilization in subsequent algorithms. The remaining FIFOs serve as FIFO buffers to be mapped.
[0034] Step S13: Based on the preset storage resource occupancy information, determine the resource planning information and layout priority corresponding to each first-in-first-out cache to be mapped.
[0035] In this embodiment, combined with Figure 2 As shown, after determining the layout and routing of the mixed FIFO cache to be mapped, for each FIFO cache to be mapped, it is necessary not only to determine the layout priority, but also to determine the construction of the dynamic programming array and value range. That is: based on the size information, width information, and number of BRAMs to be used, determine the target number of BRAMs corresponding to each FIFO cache to be mapped; based on the target number of BRAMs, determine the BRAM size information corresponding to each FIFO cache to be mapped; based on the BRAM size information, preset weight value, and size information corresponding to each FIFO cache to be mapped, determine the layout priority corresponding to each FIFO cache to be mapped.
[0036] It's important to understand that regarding the construction of the dynamic programming array and value range, this embodiment utilizes the dynamic programming array and value range to construct components. Mathematical abstraction is performed based on the number of available BRAMs in the FIFO and the characteristics of the FPGA. Taking a specific type of FPGA as an example, the minimum independent size of the BRAM is 18Kb, and the number of BRAMs is counted. The result is used... This variable represents the additional BRAM size required for each FIFO. The calculation formula is as follows, where ceil is the floor function. Since the maximum width of an 18Kb BRAM is 36, the first ceil function represents the number of BRAMs required for FIFO bit width splicing, and the second ceil function represents the number of BRAMs required for mapping the actual size of the FIFO. The maximum value of the two results is taken to obtain the number of BRAMs required for the FIFO. The final BRAM size is obtained, in Kb: ; .
[0037] Meanwhile, regarding the determination of layout priority, in this embodiment, based on the FIFOs to be processed obtained from the filtering component, the layout priority of each FIFO is calculated. This process will incorporate the user's FIFO weights. Taking into account, its value range is (0,1), and the calculation formula is as follows. Priority coefficient: .
[0038] Step S14: Utilize the FPGA mapping relationship dynamic planning component, and based on the preset dynamic planning algorithm, the resource planning information and layout priority of each first-in-first-out (FIFO) buffer to be mapped, determine the FIFO buffer mapping allocation result.
[0039] In this embodiment, the parameters and variables required for the DP algorithm of the FIFO FPGA mapping relationship have already been constructed. Therefore, this stage can proceed with the construction of... The calculation formula and implementation process are as follows: Based on the preset dynamic programming algorithm, the resource planning information and layout priority of each FIFO buffer to be mapped, determine the target dynamic programming function; based on the FPGA mapping relationship dynamic programming components, the number of BRAMs to be used, the target dynamic programming function, resource planning information, layout priority, and basic information of the FIFO buffer, determine the target FIFO buffer to be mapped as BRAM from the FIFO buffers to be mapped; count the FIFO buffers other than the target FIFO buffer among the FIFO buffers to be mapped to determine the buffer statistics results.
[0040] It is important to understand that, in combination Figure 2 As shown, after determining the layout priority, dynamic programming array, and value range, dynamic programming will be performed based on the data obtained in the preceding steps. First, the target dynamic programming function... This represents the FIFO of each resource to be mapped, in the formula. Indicates the number of BRAMs to be mapped: .
[0041] Based on the optimal FIFO mapping solution derived from the dynamic programming algorithm above, which is based on timing and the number of BRAMs, each selected FIFO mapped to BRAM is counted and mapped to the RTL instantiation position. The remaining FIFOs not mapped to BRAM are counted, and finally LUTRAM is used to build the system.
[0042] Step S15: Based on the first-in-first-out buffer mapping allocation result, perform resource mapping on the FPGA prototype platform, so as to update the register transfer level source file using the corresponding resource mapping result.
[0043] In this embodiment, after determining the FIFO buffer mapping allocation result, the resource mapping of the FPGA prototype platform is performed using this mapping allocation result. That is, the target FIFO buffer is mapped to the corresponding BRAM; and the FIFO buffers in the buffer statistics are mapped to the corresponding LUTRAM. It can be understood that after mapping the FIFOs to BRAM, URAM, LUTRAM, etc., according to the above allocation result, the RTL of each FIFO is automatically adapted and modified based on the mapping result, and corresponding synthesis attributes are added to complete the update.
[0044] In addition, combined Figure 2 As shown, this embodiment includes a corresponding verification process after updating the source file. Specifically: after updating the register transfer level source file, the updated source file is obtained; logic synthesis is performed on the updated source file using a tool to determine the synthesis result; based on the tool and the synthesis result, the implementation process is executed, and timing closure is attempted; if a corresponding FIFO buffer placement and routing congestion report and / or timing violation report are obtained after implementation, the preset memory resource occupancy information is updated, and the new preset memory resource occupancy information is used to jump back to the step of determining the resource planning information and placement priority corresponding to each FIFO buffer to be mapped based on the preset memory resource occupancy information; if no FIFO buffer placement and routing congestion report and timing violation report are obtained after implementation, the bit file corresponding to the FPGA prototype platform is determined based on the updated source file.
[0045] Understandably, the process involves using EDA tools to synthesize the updated RTL source file (with added synthesis attributes) to obtain the synthesized netlist. Next, the EDA tools are used to execute the implementation process, attempting timing closure and obtaining congestion and timing reports after implementation. These reports are then analyzed to check for FIFO-related issues. If problems are found, the FIFO weights and the amount of BRAM and URAM occupied by the FIFO need to be appropriately modified for further iteration. If no problems are found, the subsequent process continues. Finally, the bit file is generated, completing the FPGA prototype.
[0046] In summary, this embodiment discloses a first-in-first-out (FIFO) automatic mapping scheme for an FPGA prototyping platform based on dynamic programming (i.e., Figure 2 The process (highlighted by the dashed box) introduces three input parameters in the early stages: clock frequency ratio, FIFO weight, and the amount of BRAM and URAM occupied by the FIFO. After automatically acquiring FIFO information from the RTL, a dynamic programming algorithm considering FIFO placement priority is constructed. This approach avoids resource waste caused by small-sized FIFOs occupying BRAM or URAM, and also avoids situations where placement and timing factors are not considered when manually selecting BRAM, LUTRAM, LUT, FF, and other resources. It achieves the optimal mapping result that balances FPGA utilization and FIFO timing. This solution uses the most efficient and optimal method to automatically map FIFOs in the FPGA prototype. In summary, compared to existing related solutions, this solution introduces timing and available FPGA resources into the FIFO mapping process in the FPGA prototype to obtain the optimal solution, avoiding repeated iterations caused by congestion, unreasonable resource allocation, timing violations, etc., and significantly shortening the process time, improving the efficiency of FIFO resource mapping in the FPGA, and accelerating the prototype production cycle.
[0047] Therefore, in this embodiment of the invention, firstly, the basic information of the FIFO buffer, including the clock frequency coefficient, is determined using a preset clock frequency ratio relationship and the register transfer level source file corresponding to the application-specific integrated circuit (ASIC). Then, the FIFO buffers to be mapped are selected using this basic information. Next, the resource planning information and layout priority of the FIFO buffers to be mapped are determined based on preset storage resource occupancy information, and the FIFO buffer mapping allocation result is determined by combining the FPGA mapping relationship dynamic programming component and a preset dynamic programming algorithm. Finally, resource mapping is performed on the FPGA prototype platform according to the FIFO buffer mapping allocation result, so that the obtained resource mapping result is used to update the register transfer level source file. The beneficial effect of this invention is that it avoids the iterative problem of separating resources, timing, and layout in existing related solutions, thereby improving mapping efficiency and shortening the FPGA prototype version manufacturing cycle.
[0048] See Figure 3 As shown, this embodiment of the invention also discloses a first-in-first-out (FIFO) buffer mapping device for an FPGA prototype platform, comprising: The basic information determination module 11 is used to determine the basic information of the first-in-first-out (FIFO) buffer corresponding to the application-specific integrated circuit (ASIC) based on a preset clock frequency ratio and the register transfer level source file corresponding to the ASIC; wherein, the basic information of the FIFO buffer includes the clock frequency coefficient. The module 12 for determining the cache to be mapped is used to determine the first-in-first-out cache to be mapped using the basic information of the first-in-first-out cache. The planning information determination module 13 is used to determine the resource planning information and layout priority of each first-in-first-out cache to be mapped based on the preset storage resource occupancy information. The mapping and allocation module 14 is used to dynamically plan components using FPGA mapping relationships, and to determine the first-in-first-out (FIFO) cache mapping and allocation results based on a preset dynamic planning algorithm, resource planning information and layout priority of each FIFO cache to be mapped. The mapping result determination module 15 is used to perform resource mapping of the FPGA prototype platform based on the first-in-first-out buffer mapping allocation result, so as to update the register transfer level source file using the corresponding resource mapping result.
[0049] For more detailed information on the working process of each of the above modules, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.
[0050] Furthermore, embodiments of the present invention also disclose an electronic device, Figure 4This is a structural diagram of an electronic device according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of the invention. Specifically, the electronic device may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the FIFO buffer mapping method of the FPGA prototype platform disclosed in any of the foregoing embodiments. Alternatively, the electronic device in this embodiment may specifically be an electronic computer.
[0051] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this invention, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.
[0052] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.
[0053] The operating system 221 is used to manage and control the various hardware devices on the electronic device and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the FIFO buffer mapping method of the FPGA prototype platform executed by the electronic device as disclosed in any of the foregoing embodiments, the computer program 222 may further include computer programs capable of performing other specific tasks.
[0054] Furthermore, the present invention also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned first-in-first-out (FIFO) buffer mapping method for the FPGA prototype platform. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.
[0055] Furthermore, this invention also discloses a computer program product, including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, they implement the aforementioned FIFO cache mapping method for the FPGA prototype platform. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.
[0056] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0057] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0058] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0059] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.
[0060] The technical solution provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A first-in-first-out (FIFO) buffer mapping method for an FPGA prototype platform, characterized in that, include: Based on a preset clock frequency ratio and the register transfer level source file corresponding to the application-specific integrated circuit (ASIC), the basic information of the first-in-first-out (FIFO) buffer corresponding to the ASIC is determined; wherein, the basic information of the FIFO buffer includes a clock frequency coefficient. Using the aforementioned FIFO buffer basic information, determine the FIFO buffer to be mapped; Based on the preset storage resource occupancy information, determine the resource planning information and layout priority of each of the first-in-first-out caches to be mapped; The FPGA mapping relationship dynamic planning component is used, and the FIFO buffer mapping allocation result is determined based on the preset dynamic planning algorithm, the resource planning information corresponding to each of the FIFO buffers to be mapped, and the layout priority. Based on the first-in-first-out buffer mapping allocation result, resource mapping is performed on the FPGA prototype platform so as to update the register transfer level source file using the corresponding resource mapping result.
2. The FIFO buffer mapping method for an FPGA prototype platform according to claim 1, characterized in that, The process of determining the basic information of the first-in-first-out (FIFO) buffer corresponding to the ASIC based on a preset clock frequency ratio and the register transfer level source file corresponding to the ASIC includes: After completing the compilation of the register transfer level source file corresponding to the application-specific integrated circuit, the preset clock frequency ratio and the register transfer level source file are obtained; wherein, the preset clock frequency ratio is the expected ratio of each clock in the FPGA prototype version; The source file of the register transfer level is extracted to determine the first-in-first-out buffer code; Based on the first-in-first-out (FIFO) buffer code, determine the size, depth, and width information of the FIFO buffer; Based on the first-in-first-out (FIFO) buffer code and the preset clock frequency ratio, timing analysis of the FIFO buffer is performed to determine the clock domain and clock frequency coefficient corresponding to each FIFO buffer. Based on the clock domain, clock frequency coefficient, size information, depth information, and width information corresponding to each of the first-in-first-out (FIFO) buffers, the basic information of the FIFO buffer corresponding to the application-specific integrated circuit (ASIC) is determined.
3. The FPGA prototype platform first-in-first-out buffer mapping method according to claim 2, characterized in that, The step of determining the FIFO buffer to be mapped using the basic information of the FIFO buffer includes: For any of the aforementioned first-in-first-out buffers, based on the number of URAMs available, it is determined whether the current size information is greater than a first preset size data, so as to determine the first size determination result; If the first size determination result is greater than the first preset size data, then the current first-in-first-out buffer is determined as the first first-in-first-out buffer; If the first size determination result is not greater than the first preset size data, then determine whether the current size information is less than the second preset size data to determine the second size determination result; If the result of the second size determination is smaller than the second preset size data, then the current first-in-first-out buffer is determined as the second first-in-first-out buffer; If the result of the second size determination is not less than the second preset size data, then the current first-in-first-out buffer is determined as the first-in-first-out buffer to be mapped; Based on the number of URAMs to be used, several first first-in-first-out (FIFO) caches are selected to obtain a selected third FIFO cache. Map the third first-in-first-out buffer to the corresponding URAM; The second FIFO buffer is mapped to the corresponding LUTRAM or flip-flop.
4. The FPGA prototype platform first-in-first-out buffer mapping method according to claim 2, characterized in that, The step of determining the resource planning information and layout priority corresponding to each of the first-in-first-out caches to be mapped based on preset storage resource occupancy information includes: Based on the size information, the width information, and the number of BRAMs to be used, determine the target number of BRAMs corresponding to each of the first-in-first-out buffers to be mapped. Based on the target number of BRAMs, determine the BRAM occupancy size information corresponding to each of the first-in-first-out (FIFO) caches to be mapped; Based on the BRAM occupancy size information, preset weight value, and size information corresponding to each of the first-in-first-out (FIFO) caches to be mapped, the layout priority corresponding to each of the first-in-first-out (FIFO) caches to be mapped is determined.
5. The FIFO buffer mapping method for an FPGA prototype platform according to claim 1, characterized in that, The method of using the FPGA mapping relationship dynamic planning component, and determining the FIFO buffer mapping allocation result based on the preset dynamic planning algorithm, the resource planning information corresponding to each of the FIFO buffers to be mapped, and the layout priority, includes: Based on the preset dynamic programming algorithm, the resource planning information corresponding to each of the first-in-first-out caches to be mapped, and the layout priority, the target dynamic programming function is determined; Based on the FPGA mapping relationship dynamic programming component, the number of BRAMs to be used, the target dynamic programming function, the resource planning information, the layout priority, and the basic information of the first-in-first-out (FIFO) buffer, the target FIFO buffer to be mapped as BRAM is determined from the FIFO buffers to be mapped. The first-in-first-out (FIFO) buffers other than the target FIFO buffer are counted among the FIFO buffers to be mapped, in order to determine the buffer statistics results.
6. The FPGA prototype platform first-in-first-out buffer mapping method according to claim 5, characterized in that, The resource mapping of the FPGA prototype platform based on the first-in-first-out buffer mapping allocation result includes: Map the target first-in-first-out buffer to the corresponding BRAM; The first-in-first-out (FIFO) cache in the cache statistics is mapped to the corresponding LUTRAM.
7. The FIFO buffer mapping method for an FPGA prototyping platform according to any one of claims 1 to 6, characterized in that, Also includes: After updating the register transfer level source file, obtain the corresponding updated source file; The updated source file is logically synthesized using the tool to determine the logical synthesis result. Based on the tools and the results of the logic synthesis, the implementation process is executed, and an attempt is made to achieve timing convergence. If, after implementation, a corresponding first-in-first-out (FIFO) cache layout and routing congestion report and / or timing violation report are obtained, the preset storage resource occupancy information is updated, and the new preset storage resource occupancy information is used to jump back to the step of determining the resource planning information and layout priority of each FIFO cache to be mapped based on the preset storage resource occupancy information. If the first-in-first-out buffer placement and routing congestion report and the timing violation report are not obtained after implementation, the bit file corresponding to the FPGA prototype platform is determined based on the updated source file.
8. A first-in-first-out (FIFO) buffer mapping device for an FPGA prototyping platform, characterized in that, include: The basic information determination module is used to determine the basic information of the first-in-first-out (FIFO) buffer corresponding to the ASIC based on a preset clock frequency ratio and the register transfer level source file corresponding to the ASIC; wherein, the basic information of the FIFO buffer includes a clock frequency coefficient; The module for determining the cache to be mapped is used to determine the first-in-first-out cache to be mapped using the basic information of the first-in-first-out cache. The planning information determination module is used to determine the resource planning information and layout priority of each of the first-in-first-out caches to be mapped based on the preset storage resource occupancy information; The mapping and allocation module is used to dynamically plan components using FPGA mapping relationships, and determine the first-in-first-out (FIFO) buffer mapping and allocation results based on a preset dynamic planning algorithm, the resource planning information corresponding to each of the FIFO buffers to be mapped, and the layout priority. The mapping result determination module is used to perform resource mapping of the FPGA prototype platform based on the first-in-first-out buffer mapping allocation result, so as to update the register transfer level source file using the corresponding resource mapping result.
9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the first-in-first-out cache mapping method for the FPGA prototype platform as described in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the first-in-first-out cache mapping method for the FPGA prototype platform as described in any one of claims 1 to 7.