Adaptive priority arbitration system, method, soc system, electronic device, and storage medium

Abstract

This invention discloses an adaptive priority arbitration system, method, SOC system, electronic device, and storage medium. The adaptive priority arbitration system includes a bus monitoring module, a priority adjustment module, and an arbitration module. The bus monitoring module monitors the bus usage of each device in real time and feeds back the bus occupancy rate to the priority adjustment module. The priority adjustment module dynamically adjusts the priority of each device based on set targets. The arbitration module determines the device that will gain bus control first when multiple devices simultaneously initiate bus requests, based on the priority adjusted by the priority adjustment module. This dynamic priority adjustment ensures that the system bandwidth resource allocation is as close as possible to the actual application scenario requirements. This invention can dynamically adjust the priority of each device according to the real-time bus transmission situation, allowing the same SOC chip to better adapt to the application needs of different customers.

Description

Technical Field

[0001] This invention belongs to the technical field of chip SOC system, and relates to an SOC system, and more particularly to an adaptive priority arbitration system, method, SOC system, electronic device and storage medium. Background Technology

[0002] With the increasing maturity of semiconductor technology and the advancement of integrated circuit design capabilities, SoC systems often contain multiple functional modules such as CPU, graphics processor, DMA, and various peripherals. As the integration level of SoC systems increases, system performance is no longer solely determined by the CPU's operating speed; the balanced allocation of bus bandwidth also has a significant impact.

[0003] A shared bus is a common architecture in System-on-a-Chip (SoC) systems, where multiple devices on the bus share address lines, data lines, and control lines. When a device wants to use the bus for data transmission, it needs to send a request (req) to the arbitrator. Only after receiving permission (gnt) from the arbitrator does the device gain access to the bus for a single time; devices without permission cannot initiate data transmission. The bus arbitrator is responsible for coordinating access to the shared bus among multiple devices.

[0004] When the bus is idle, if only one device initiates a request, it will gain the right to use the bus until it completes a transmission and releases the bus, which will then be idle. If multiple devices initiate requests, the bus arbiter will determine which device can gain the right to use the bus based on a specific algorithm and priority, thus ensuring the stability and correctness of data transmission on the bus. Requests from devices that do not gain bus access will continue until the current transmission ends, initiating the next bus contention until the request is responded to.

[0005] Bus arbitrator priority rules have a significant impact on bandwidth allocation. Bus arbitrators typically employ different algorithms and priority rules. Common arbitrator architectures include fixed-priority arbitrators, round-robin arbitrators, and random-priority arbitrators. In a fixed-priority arbitrator, the priorities of each device are fixed and cannot be changed. A round-robin arbitrator processes requests from each device sequentially in a loop; the priority of the device currently granted bus access becomes the lowest after its request is granted, and the priority of each device is not fixed but adjusted according to the granting status. A random-priority arbitrator randomly generates a priority each time a bus request is made to ensure fairness.

[0006] Fixed-priority arbitrators are relatively simple in circuit design because they do not require dynamic adjustment of the priorities of each device. However, high-priority devices always gain bus access when contention occurs, which may cause requests from low-priority devices to go unanswered for extended periods. Round-robin arbitrators ensure that each device receives the highest priority within a certain timeframe, making them suitable for situations requiring fair resource allocation. However, this may result in high-priority devices requesting responses less frequently. Random-priority arbitrators, while preventing low-priority devices from going unanswered for extended periods, may also lead to high-priority devices requesting responses less frequently.

[0007] exist Figure 1 In the fixed-priority arbitration timing diagram, the priorities from high to low are ms1, ms2, and ms3.

[0008] At time T1, the three master devices simultaneously initiate bus access requests. Since the priority is ms1>ms2>ms3, ms1 wins the right to use the bus this time.

[0009] At time T2, ms1 releases bus control. At this time, ms2 and ms3 request bus access. Since the priority is ms1>ms2>ms3, ms2 wins the bus access this time.

[0010] At time T3, ms2 releases bus control. At this time, ms1 and ms3 request bus access. Since the priority is ms1>ms2>ms3, ms1 gets the bus access this time.

[0011] At time T4, ms1 releases bus control. At this time, ms2 and ms3 request bus access. Since the priority is ms1>ms2>ms3, ms2 wins the bus access this time.

[0012] At time T5, ms2 releases bus control. At this time, only ms3 is requesting the right to use the bus, so ms3 gains the right to use the bus this time.

[0013] This shows that a low-priority device, ms3, initiates a request at time T1, but only truly gains control of the bus at time T5. With this fixed-priority arbitrator, during periods of frequent requests from high-priority devices, low-priority devices must wait until all requests from devices with higher priorities have been responded to before gaining bus access. This design may result in low-priority devices being unable to gain bus control for extended periods.

[0014] Figure 2 This is the timing diagram of the polling arbitrator. The initial priorities from high to low are ms1, ms2, and ms3.

[0015] At time T1, three master devices simultaneously initiate bus access requests. Since the priority is ms1 > ms2 > ms3, ms1 gains the right to use the bus this time. After ms1 releases bus control, the priorities are updated, from high to low: ms2, ms3, ms1.

[0016] At time T2, ms2 and ms3 request bus access. Since the priority is ms2 > ms3 > ms1, ms2 wins the bus access this time. After ms2 releases bus control, the priorities are updated, from high to low: ms3, ms1, ms2.

[0017] At time T3, only ms3 requests bus access, so ms3 gains access to the bus this time. After ms3 releases bus control, the priorities are updated, from high to low: ms1, ms2, ms3.

[0018] At time T4, only ms2 is requesting bus access, so ms2 gains access to the bus this time. After ms2 releases bus control, the priorities are updated, from high to low: ms3, ms1, ms2.

[0019] At time T5, ms1 and ms3 request bus access. Since the priority is ms3 > ms1 > ms2, ms3 wins the bus access this time. After ms3 releases bus control, the priority is updated, from high to low: ms1, ms2, ms3.

[0020] At time T6, only ms1 is requesting bus access, so ms1 gains access to the bus this time. After ms1 releases bus control, the priorities are updated, from highest to lowest: ms2, ms3, ms1.

[0021] This shows that the polling arbiter ensures that requests initiated by each master device receive a response within a certain time, avoiding the problem of low-priority device requests not responding for a long time. However, the polling arbiter is more suitable for situations where fair resource allocation is required. If the bus occupancy rate of device 1 is three times that of device 3 in a real-world application scenario, then this arbiter may affect the speed at which device 1's requests are responded to.

[0022] In view of this, there is an urgent need to design a new priority arbitration method for SOC systems in order to overcome at least some of the aforementioned defects in the existing priority arbitration methods for SOC systems. Summary of the Invention

[0023] This invention provides an adaptive priority arbitration system, method, SOC system, electronic device, and storage medium, which can dynamically adjust the priority of each device according to the real-time situation of bus transmission, so that the same SOC chip can better adapt to the application needs of different customers.

[0024] To solve the above-mentioned technical problems, according to one aspect of the present invention, the following technical solution is adopted:

[0025] An adaptive priority arbitration system, the adaptive priority arbitration system comprising:

[0026] The bus monitoring module is used to monitor the bus usage of each device in real time and feed back the bus usage rate to the priority adjustment module.

[0027] The priority adjustment module is used to dynamically adjust the priority of each device based on the set target.

[0028] The arbitration module is used to determine the device that will first obtain bus control when multiple devices simultaneously initiate bus requests, based on the priority adjusted by the priority adjustment module. This dynamic priority adjustment allows the allocation of system bandwidth resources to be as close as possible to the actual application scenario requirements.

[0029] As one embodiment of the present invention, the bus protocol in the SOC system includes three types: APB, AHB, and AXI.

[0030] As one embodiment of the present invention, during the data transmission process on the AHB bus, the master device first initiates a request, and only after obtaining permission does it begin a burst data transmission, sending address and control signals, and providing address information, transmission direction, data size and burst type.

[0031] A master device will release the bus only after it has completed a full burst transfer; the process of a master device occupying the bus once is the process of completing a full burst transfer.

[0032] The AHB bus protocol has various burst types, and different burst types occupy different bus bandwidths; the bus bandwidth occupied by each burst transmission type is determined by the data bit width and the amount of data transmitted.

[0033] The bus monitoring module monitors the burst type and data size (s ize) of data transmission on the bus in real time. Combined with the device number of the current control bus provided by the arbitration module, it continuously calculates the bus occupancy information of all master devices within a time cycle. This information is represented by the data transmission volume of each device or by the number of times each device occupies the bus. The number of times the bus is occupied and the data transmission volume are not necessarily proportional. The burst transmission type initiated by the same device each time may not be the same, and the data volume transmitted by different devices each time may also be different. After the current time cycle ends, the data transmission information of the previous time cycle is cleared, and the bus monitoring module enters a new cycle, repeating the previous process.

[0034] According to another aspect of the present invention, the following technical solution is adopted: an adaptive priority arbitration method, the adaptive priority arbitration method comprising:

[0035] Bus monitoring steps: Monitor the bus usage of each device in real time and feed back the bus usage rate to the priority adjustment module;

[0036] Priority adjustment steps: Dynamically adjust the priority of each device based on the set goals;

[0037] Arbitration steps: Based on the priority adjustment steps, when multiple devices simultaneously initiate bus requests, the device that first obtains bus control is given priority. The system bandwidth resource allocation is dynamically adjusted to be as close as possible to the actual application scenario requirements.

[0038] As one embodiment of the present invention, the bus protocol in the SOC system includes three types: APB, AHB, and AXI.

[0039] As one embodiment of the present invention, during the data transmission process on the AHB bus, the master device first initiates a request, and only after obtaining permission does it begin a burst data transmission, sending address and control signals, and providing address information, transmission direction, data size and burst type.

[0040] A master device will release the bus only after it has completed a full burst transfer; the process of a master device occupying the bus once is the process of completing a full burst transfer.

[0041] The AHB bus protocol has various burst types, and different burst types occupy different bus bandwidths; the bus bandwidth occupied by each burst transmission type is determined by the data bit width and the amount of data transmitted.

[0042] The bus monitoring module monitors the burst type and data size (s ize) of data transmission on the bus in real time. Combined with the device number of the current control bus provided by the arbitration module, it continuously calculates the bus occupancy information of all master devices within a time cycle. This information is represented by the data transmission volume of each device or by the number of times each device occupies the bus. The number of times the bus is occupied and the data transmission volume are not necessarily proportional. The burst transmission type initiated by the same device each time may not be the same, and the data volume transmitted by different devices each time may also be different. After the current time cycle ends, the data transmission information of the previous time cycle is cleared, and the bus monitoring module enters a new cycle, repeating the previous process.

[0043] According to another aspect of the present invention, the following technical solution is adopted: a SOC system, the SOC system including the above-mentioned adaptive priority arbitration system.

[0044] According to another aspect of the present invention, the following technical solution is adopted: an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above method.

[0045] According to another aspect of the present invention, the following technical solution is adopted: a storage medium storing computer program instructions thereon, which, when executed by a processor, implement the steps of the above-described method.

[0046] The beneficial effects of the present invention are as follows: The adaptive priority arbitration system, method, SOC system, electronic device and storage medium proposed in the present invention can dynamically adjust the priority of each device according to the real-time situation of bus transmission, so that the same SOC chip can better adapt to the application needs of different customers.

[0047] In one application scenario of this invention, this adaptive priority arbitration structure adjusts the priority of each device based on the real-time bus situation after each data transmission. The priority of this arbitration structure is not fixed; the priority changes dynamically based on the real-time bus transmission situation, and this dynamic adjustment strives to reach certain goals. When a master device occupies too much bus resources, its priority is reduced; when a master device occupies too little bus resources, its priority is increased. The proportion of bus resources occupied by different devices is configurable. This variability allows the same SoC chip to better adapt to the application needs of different customers.

[0048] Because the priority order is updated based on certain objectives and bus occupancy information, the new arbitration result is related to the previous arbitration result. The new arbitration result takes into account the proportion of bus occupancy by each device and tries to achieve certain bus allocation objectives as much as possible. This can prevent high-priority devices from occupying the bus for a long time and also prevent low-priority devices from having their bus requests unanswered for a long time. This adaptive priority arbitration structure can make bus occupancy tend towards certain "targets". By setting certain "targets", bus bandwidth can be better allocated, thus improving performance. Attached Figure Description

[0049] Figure 1 This is a timing diagram for the existing fixed-priority arbitration method.

[0050] Figure 2 This is a timing diagram of the existing polling arbitrator arbitration method.

[0051] Figure 3 This is a schematic diagram of the composition of an adaptive priority arbitration system in one embodiment of the present invention.

[0052] Figure 4 This is a flowchart of an adaptive priority arbitration method in one embodiment of the present invention.

[0053] Figure 5 This is a timing diagram of an adaptive priority arbitration method in one embodiment of the present invention.

[0054] Figure 6 This is a timing diagram of an adaptive priority arbitration method in one embodiment of the present invention.

[0055] Figure 7 This is a schematic diagram of the composition of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0056] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0057] To further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, and not for limiting the scope of the claims of the present invention.

[0058] The description in this section pertains to only a few typical embodiments, and the present invention is not limited to the scope of the embodiments described. Substitution of identical or similar prior art methods with some technical features in the embodiments is also within the scope of the description and protection of this invention.

[0059] The steps described in the various embodiments in the specification are for illustrative purposes only, and the implementation of this application is not limited by the order of the steps.

[0060] The term "connection" in the specification includes both direct and indirect connections, such as connections made through active devices, passive devices, or electrical conduction media; it may also include connections made by other active or passive devices that are known to those skilled in the art and can achieve the same or similar functional purpose, such as connections made through circuits or components such as switches or follower circuits.

[0061] This invention discloses an adaptive priority arbitration system. Figure 3 This is a schematic diagram of the composition of an adaptive priority arbitration system according to an embodiment of the present invention; please refer to [link / reference]. Figure 3 The adaptive priority arbitration system includes: a bus monitoring module 1, a priority adjustment module 2, and an arbitration module 3.

[0062] The bus monitoring module 1 monitors the bus usage of each device in real time and feeds back the bus usage rate to the priority adjustment module. The priority adjustment module 2 dynamically adjusts the priority of each device based on the set target. The arbitration module 3 determines the device that will gain bus control first when multiple devices simultaneously initiate bus requests, based on the priority adjusted by the priority adjustment module 2, so that the allocation of system bandwidth resources is as close as possible to the actual application scenario requirements by dynamically adjusting the priority.

[0063] In one embodiment of the present invention, the commonly used bus protocols in a SOC system may include at least one of three types: APB, AHB, and AXI. In one embodiment, during data transmission on the AHB bus, the master device first initiates a request, and only after obtaining permission does it begin a burst data transmission, issuing address and control signals, providing address information, transmission direction, data size (s ize), and burst type (where s ize belongs to the control information of the AHB protocol). The bus is released only after a master device completes a full burst transmission; the process of a master device occupying the bus once is the process of completing a full burst transmission. The AHB bus protocol has multiple burst types, each occupying different bus bandwidths; the bus bandwidth occupied by each burst transmission type is determined by its transmitted data bit width and the amount of data transmitted.

[0064] The bus monitoring module 1 monitors the burst type and data size (s ize) of data transmission on the bus in real time. Combined with the device number of the current control bus provided by the arbitration module 3, it continuously calculates the bus occupancy information of all master devices within a time period. This information is represented by the data transmission volume of each device or by the number of times each device occupies the bus. The number of bus occupancy times and data transmission volume are not necessarily proportional. The burst transmission type initiated by the same device each time may not be the same, and the data volume transmitted by different devices each time may also vary. After the current time period ends, the data transmission information from the previous time period is cleared, and the bus monitoring module enters a new period, repeating the previous process.

[0065] The present invention also discloses a SOC system, which includes the above-described adaptive priority arbitration system.

[0066] This invention further discloses an adaptive priority arbitration method. Figure 4 This is a flowchart of an adaptive priority arbitration method in one embodiment of the present invention; please refer to [link / reference]. Figure 4 The adaptive priority arbitration method includes:

[0067]

Step S1

[0068]

Step S2

[0069]

Step S3

[0070] Commonly used bus protocols in SOC systems include APB, AHB, and AXI. In one embodiment of this invention, during data transmission on the AHB bus, the master device first initiates a request. Only after obtaining permission does it begin a burst data transmission, issuing address and control signals, providing address information, transmission direction, size, and burst type. The bus is released only after a master device completes a full burst transmission; the process of a master device occupying the bus once constitutes the completion of a full burst transmission. The AHB bus protocol has multiple burst types, each occupying different bus bandwidths; the bus bandwidth occupied by each burst transmission type is determined by its data bit width and the amount of data transmitted.

[0071] The bus monitoring module monitors the burst type and size value of data transmission on the bus in real time. Combined with the device number of the current control bus provided by the arbitration module, it continuously calculates the bus occupancy information of all master devices on the bus within a time period. This information is represented by the data transmission volume of each device or by the number of times each device occupies the bus. The number of times the bus is occupied and the data transmission volume are not necessarily proportional. The burst transmission type initiated by the same device each time may not be the same, and the data transmission volume of different devices each time may also be different. After the current time period ends, the data transmission information of the previous time period is cleared, and the bus monitoring module enters a new period and repeats the previous process.

[0072] In the priority adjustment module, the target may include at least one of the following conditions:

[0073] (1) The priority of master device 2 is always higher than that of master device 3;

[0074] (2) The priority of master device 4 is the same as that of master device 5;

[0075] (3) The bus occupancy rate of master device 1 is three times that of master device 3;

[0076] (4) The data transmission volume of master device 5 and master device 6 is roughly the same;

[0077] (5) When device 1 and device 2 compete for the right to use the bus, device 1 usually has priority over device 2.

[0078] (6) Adjust the priority of the next cycle based on the data transmission volume ratio calculated by the priority adjustment method of the previous cycle.

[0079] The above conditions must not contradict each other. The objectives described above will vary depending on the actual application scenario of the chip, and the objectives will be adapted to the needs of different scenarios by software configuration.

[0080] Initially, a desired bus resource allocation value is set for each device in a four-way arbitrator: a1 for device 1, a2 for device 2, a3 for device 3, and a4 for device 4. The bus monitoring module monitors the actual bus usage (number of uses or data transfer volume) of each device in real time, which are A1, A2, A3, and A4, respectively. In the priority adjustment module, the actual bus usage rate of each device is divided by the desired bus usage rate (note that the result is rounded to the nearest integer), resulting in b1, b2, b3, and b4. Larger values ​​of b1, b2, b3, and b4 indicate more frequent bus usage, requiring a lower priority for the corresponding device; smaller values ​​indicate less frequent bus usage, requiring a higher priority for the corresponding device. Sorting b1, b2, b3, and b4 in ascending order determines the arbitration priority of the corresponding devices from high to low. Because only one device occupies the bus and its actual value Ax changes after each transmission, the priority order of the devices not occupying the bus remains unchanged, except for the current priority order of the devices occupying the bus. The recalculated bx value is then inserted into the priority order of the unoccupied devices using insertion sort, resulting in a new priority order, which is then passed to arbitration module 3. The basic idea of ​​insertion sort is to insert an element to be sorted into the appropriate position in an already sorted sequence according to its value, thus obtaining a new sequence.

[0081] Figure 5 This is a timing diagram of an adaptive priority arbitration method in one embodiment of the present invention; please refer to [link / reference]. Figure 5 In one embodiment of the present invention, the target is that the bus occupancy rate of master device 1 is 3 times that of master device 2, and the burst transmission type initiated by device 1 and device 2 is set to be the same each time; the initial priority ms1 is higher than ms2.

[0082] At time T1, both ms1 and ms2 initiate bus access requests simultaneously. Since the priority is ms1 > ms2, ms1 gains the right to use the bus this time. After ms1 releases bus control, ms1 has 100% bus occupancy, and ms2 has 0% bus occupancy. The priority is then adjusted to ms2 > ms1.

[0083] At time T2, only the ms2 master device requests bus access, so ms2 gains access to the bus this time. After ms2 releases bus control, ms1 has 50% bus occupancy and ms2 has 50% bus occupancy, so the priority is adjusted to ms1 > ms2.

[0084] At time T3, only the ms1 master device is requesting bus access, so ms1 gains access to the bus this time. After ms1 releases bus control, ms1 has a bus utilization rate of 67%, ms2 has a bus utilization rate of 33%, and the priority order remains ms1>ms2.

[0085] At time T4, both ms1 and ms2 initiate bus access requests simultaneously. Since the priority is ms1 > ms2, ms1 gains the right to use the bus. After ms1 releases bus control, ms1 has a bus utilization rate of 75%, and ms2 has a bus utilization rate of 25%. The priority is then adjusted to ms2 > ms1.

[0086] At time T5, only the ms2 master device is requesting bus access, so ms2 gains access to the bus this time. After ms2 releases bus control, ms1 has a bus utilization rate of 60%, and ms2 has a bus utilization rate of 40%. The priority is adjusted to ms1 > ms2.

[0087] As time goes on, the bus occupancy rates of Device 1 and Device 2 will keep changing. By using this information, the priority can be continuously adjusted to make the bus usage as close as possible to certain set targets.

[0088] Figure 6 This is a timing diagram of an adaptive priority arbitration method in one embodiment of the present invention; please refer to [link / reference]. Figure 6 In one embodiment of the present invention, the objective is to ensure that the data transmission volume of master device 1 and master device 2 is approximately the same. It is set that each device occupies the same amount of data transmitted per bus cycle; the initial priority ms1 is higher than ms2.

[0089] At time T1, both ms1 and ms2 initiate bus access requests simultaneously. Since the priority is ms1 > ms2, ms1 gains the right to use the bus this time. After ms1 releases bus control, ms1's data transfer volume is 2, and ms2's data transfer volume is 0. The priority is then adjusted to ms2 > ms1.

[0090] At time T2, only the ms2 master device requests bus access, so ms2 gains access to the bus this time. After ms2 releases bus control, ms1 transmits 2 data and ms2 transmits 5 data, adjusting the priority to ms1 > ms2.

[0091] At time T3, only the ms1 master device requests bus access, so ms1 gains access to the bus this time. After ms1 releases bus control, ms1 transmits 4 data and ms2 transmits 5 data, maintaining the priority order ms1 > ms2.

[0092] At time T4, both ms1 and ms2 initiate bus access requests simultaneously. Since the priority is ms1 > ms2, ms1 gains the right to use the bus this time. After ms1 releases bus control, ms1's data transfer volume is 6, and ms2's data transfer volume is 5. The priority is then adjusted to ms2 > ms1.

[0093] At time T5, only the ms2 master device is requesting bus access, so ms2 gains access to the bus this time. After ms2 releases bus control, ms1's data transfer volume is 6, and ms2's data transfer volume is 9. The priority is adjusted to ms1 > ms2.

[0094] This invention also discloses an electronic device, Figure 7 This is a schematic diagram of the composition of an electronic device according to an embodiment of the present invention; please refer to [link / reference]. Figure 7 At the hardware level, the electronic device includes a memory, a processor, and at least one network interface; the processor may be a microprocessor, and the memory may include main memory, such as random access memory (RAM) or non-volatile memory. Of course, the electronic device may also include other hardware as needed.

[0095] The processor, network interface, and memory are interconnected via an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. The bus may include an address bus, a data bus, a control bus, etc. The memory stores programs (including operating system programs and application programs); the programs may include program code, which may include computer operation instructions. The memory may include main memory and non-volatile memory, and provides instructions and data to the processor.

[0096] In one embodiment, the processor can read the corresponding program from non-volatile memory into memory and then run it; the processor can execute the program stored in memory and specifically perform the following operations (e.g. Figure 4 As shown):

[0097]

Step S1

[0098]

Step S2

[0099]

Step S3

[0100] This invention further discloses a storage medium storing computer program instructions, which, when executed by a processor, implement the following steps of the method of this invention (e.g., ...). Figure 4 As shown):

[0101]

Step S1

[0102]

Step S2

[0103]

Step S3

[0104] In summary, the adaptive priority arbitration system, method, SOC system, electronic device, and storage medium proposed in this invention can dynamically adjust the priority of each device according to the real-time situation of bus transmission, so that the same SOC chip can better adapt to the application needs of different customers.

[0105] In one application scenario of this invention, this adaptive priority arbitration structure adjusts the priority of each device based on the real-time bus situation after each data transmission. The priority of this arbitration structure is not fixed; the priority changes dynamically based on the real-time bus transmission situation, and this dynamic adjustment strives to reach certain goals. When a master device occupies too much bus resources, its priority is reduced; when a master device occupies too little bus resources, its priority is increased. The proportion of bus resources occupied by different devices is configurable. This variability allows the same SoC chip to better adapt to the application needs of different customers.

[0106] Because the priority order is updated based on certain objectives and bus occupancy information, the new arbitration result is related to the previous arbitration result. The new arbitration result takes into account the proportion of bus occupancy by each device and tries to achieve certain bus allocation objectives as much as possible. This can prevent high-priority devices from occupying the bus for a long time and also prevent low-priority devices from having their bus requests unanswered for a long time. This adaptive priority arbitration structure can make bus occupancy tend towards certain "targets". By setting certain "targets", bus bandwidth can be better allocated, thus improving performance.

[0107] It should be noted that this application can be implemented in software and / or a combination of software and hardware; for example, it can be implemented using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In some embodiments, the software program of this application can be executed by a processor to implement the steps or functions described above. Similarly, the software program of this application (including related data structures) can be stored in a computer-readable recording medium; for example, RAM memory, magnetic or optical drives, floppy disks, and similar devices. In addition, some steps or functions of this application can be implemented in hardware; for example, as circuitry that cooperates with a processor to perform the various steps or functions.

[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The description and application of the present invention herein are illustrative and not intended to limit the scope of the invention to the embodiments described above. Effects or advantages involved in the embodiments may not be apparent due to various factors, and the description of effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and various substitutions and equivalents of the components in the embodiments are well known to those skilled in the art. It should be apparent to those skilled in the art that the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the invention. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of the invention.

Claims

1. An adaptive priority arbitration system, characterized in that, The adaptive priority arbitration system includes: The bus monitoring module is used to monitor the bus usage of each device in real time and feed back the bus usage rate to the priority adjustment module. The priority adjustment module is used to dynamically adjust the priority of each device based on the set target. The arbitration module is used to determine the device that will first obtain bus control when multiple devices simultaneously initiate bus requests, based on the priority adjusted by the priority adjustment module. This dynamic priority adjustment allows the allocation of system bandwidth resources to be as close as possible to the actual application scenario requirements.

2. The adaptive priority arbitration system according to claim 1, characterized in that: The bus protocols in a SoC system include three types: APB, AHB, and AXI.

3. The adaptive priority arbitration system according to claim 1, characterized in that: During data transmission on the AHB bus, the master device first initiates a request, and after obtaining permission, it begins a burst data transmission, sending address and control signals, and providing address information, transmission direction, data size, and burst type. Once a master device completes a full burst transfer, it releases the bus. A complete burst transfer is completed when a master device occupies the bus once. The AHB bus protocol has various burst types, and different burst types occupy different bus bandwidths; the bus bandwidth occupied by each burst transmission type is determined by the data bit width and the amount of data transmitted. The bus monitoring module monitors the burst type and size of data transmission on the bus in real time, and combines this with the device number of the current control bus given by the arbitration module to continuously calculate the bus occupancy information of all master devices on the bus within a time period. The information is represented by the amount of data transmitted by each device, or by the number of times each device occupies the bus; The number of times the bus is occupied is directly proportional to or disproportionate to the amount of data transmitted. The same device may initiate the same or different burst transmission types each time, and different devices may transmit the same or different amounts of data each time. After the current time period ends, the data transmission information from the previous time period is cleared, and the bus monitoring module enters a new period; the previous process is repeated.

4. An adaptive priority arbitration method, characterized in that, The adaptive priority arbitration method includes: Bus monitoring steps: Monitor the bus usage of each device in real time and feed back the bus usage rate to the priority adjustment module; Priority adjustment steps: Dynamically adjust the priority of each device based on the set goals; Arbitration steps: Based on the priority adjustment steps, when multiple devices simultaneously initiate bus requests, the device that first obtains bus control is given priority. The system bandwidth resource allocation is dynamically adjusted to be as close as possible to the actual application scenario requirements.

5. The adaptive priority arbitration method according to claim 4, characterized in that: The bus protocols in a SoC system include three types: APB, AHB, and AXI.

6. The adaptive priority arbitration method according to claim 4, characterized in that: During data transmission on the AHB bus, the master device first initiates a request, and after obtaining permission, it begins a burst data transmission, sending address and control signals, and providing address information, transmission direction, data size, and burst type. Once a master device completes a full burst transfer, it releases the bus. A complete burst transfer is completed when a master device occupies the bus once. The AHB bus protocol has various burst types, and different burst types occupy different bus bandwidths; the bus bandwidth occupied by each burst transmission type is determined by the data bit width and the amount of data transmitted. The bus monitoring module monitors the burst type and size of data transmission on the bus in real time, and combines this with the device number of the current control bus given by the arbitration module to continuously calculate the bus occupancy information of all master devices on the bus within a time period. The information is represented by the amount of data transmitted by each device, or by the number of times each device occupies the bus; The number of times the bus is occupied is directly proportional to or disproportionate to the amount of data transmitted. The same device may initiate the same or different burst transmission types each time, and different devices may transmit the same or different amounts of data each time. After the current time period ends, the data transmission information from the previous time period is cleared, and the bus monitoring module enters a new period, repeating the previous process.

7. A SOC system, characterized in that: The SOC system includes the adaptive priority arbitration system as described in any one of claims 1 to 3.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 4 to 6.

9. A storage medium storing computer program instructions thereon, characterized in that, When executed by a processor, the computer program instructions implement the steps of the method according to any one of claims 4 to 6.

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