A processor, a processor resource configuration method, a storage medium and a program product

Abstract

This invention discloses a processor, a processor resource allocation method, a storage medium, and a program product, relating to the field of computer technology. By adding a load integration control module connected to multiple computing cores to the processor, it acquires the priority information of software processes and the task execution status of each computing core. Based on the priority, the processes are divided into critical processes and non-critical processes. Critical processes are allocated to the first computing core that meets the preset idle state, and non-critical processes are centrally allocated to the second computing core. The remaining at least one third computing core is controlled to enter a low-power state. This can solve the technical problem of low energy efficiency caused by all cores being in a working state in traditional load balancing strategies. It achieves the technical effect of significantly improving the energy efficiency of multi-core open instruction set architecture processors by enabling some cores to enter a low-power mode through load integration while ensuring the real-time requirements of critical processes.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a processor, a processor resource allocation method, a storage medium, and a program product. Background Technology

[0002] With the development of Reduced Instruction Set Computing V (RISC-V) processors, they have been widely used in high-performance computing. RISC-V processors often employ a multi-core architecture. Using traditional load balancing strategies, the operating system distributes software processes and tasks evenly across multiple processor cores based on scheduling algorithms. This often results in all processor cores being active, but each core running only a small number of tasks, leading to high power consumption and low energy efficiency in multi-core RISC-V processors. Summary of the Invention

[0003] This invention provides a processor, a processor resource allocation method, a storage medium, and a program product to at least solve the problems of wasted processor power consumption and low energy efficiency caused by multi-core open instruction set architecture processors using load balancing strategies to allocate software process tasks.

[0004] This invention provides a processor, comprising: multiple computing cores and a load integration control module; The load integration control module is connected to multiple computing cores and is used to obtain the priority information of the software processes to be executed by the computing cores and the task execution status of the computing cores. Based on the priority information, it divides the processes into critical processes and non-critical processes, assigns the critical processes to the first computing core, assigns the non-critical processes to the second computing core, and controls at least one third computing core other than the first computing core and the second computing core to enter a low-power state. The first computing core is the computing core that satisfies a preset idle state.

[0005] The present invention also provides a processor resource allocation method, based on the above-mentioned processor, comprising: Obtain the priority information of the software process to be executed in the computing core of the processor; Obtain the task execution status of the computing core; Based on the priority information, critical processes and non-critical processes are divided, and the critical processes are assigned to the first computing core, while the non-critical processes are assigned to the second computing core. Control at least one third computing core among the plurality of computing cores, excluding the first computing core and the second computing core, to enter a low-power state; The first computing core is the computing core that satisfies a preset idle state.

[0006] The present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the processor resource allocation methods described above.

[0007] The present invention also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of any of the processor resource configuration methods described above.

[0008] This invention addresses the technical problem of low energy efficiency caused by traditional load balancing strategies where all cores are in operation. By adding a load integration control module connected to multiple computing cores on the processor, which acquires priority information of software processes and the task execution status of each computing core, processes are divided into critical and non-critical processes based on priority. Critical processes are assigned to the first computing core that meets a preset idle state, while non-critical processes are centrally assigned to the second computing core. At least one remaining third computing core is controlled to enter a low-power state. This solves the problem of low energy efficiency caused by traditional load balancing strategies where all cores are in operation. The invention achieves the technical effect of significantly improving the energy efficiency of multi-core open instruction set architecture processors by enabling some cores to enter a low-power mode through load integration while ensuring the real-time requirements of critical processes. Attached Figure Description

[0009] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a diagram of a traditional multi-core processor architecture; Figure 2 An architecture diagram of a processor provided for an embodiment of the present invention; Figure 3 An architecture diagram of a load integration control module provided in an embodiment of the present invention; Figure 4 An architecture diagram of a microarchitecture adjustment module provided in an embodiment of the present invention; Figure 5 This is a flowchart of a processor resource configuration method provided in an embodiment of the present invention. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0012] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0013] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0014] Here, we will first explain some key terms used in the embodiments of the present invention.

[0015] The Reduced Instruction Set Computing V (RISC-V) architecture is an open-source instruction set architecture based on the principle of reduced instruction set computing. Its features include modularity and extensibility, allowing users to customize instructions according to application scenarios.

[0016] Figure 1 This is a diagram of a traditional multi-core processor architecture.

[0017] like Figure 1 As shown, traditional multi-core open instruction set architecture (RISC-VCore) processors consist of multiple computing cores, each with its own Level 1 cache (L1 Cache). These cores share a Level 2 cache (L2 Cache), and the microarchitecture of each core remains consistent. In traditional solutions, the operating system runs a software task scheduling algorithm in multi-core RISC-VCore processors, employing a load balancing strategy to distribute tasks evenly across the multiple computing cores, ensuring all cores operate under balanced load. However, this scheduling method often results in all cores in the RISC-VCore processor being active, but each core running only one or a few non-urgent software tasks. This leads to high power consumption and low energy efficiency in multi-core RISC-VCore processors.

[0018] To address the issues of wasted power consumption and low energy efficiency in multi-core open instruction set architecture processors that use load balancing strategies to allocate software process tasks, this invention provides a processor, a processor resource configuration method, a storage medium, and a program product. By adding a load integration control module connected to multiple computing cores to the processor, the module acquires the priority information of software processes and the task execution status of each computing core. Based on priority, processes are divided into critical and non-critical processes. Critical processes are allocated to a first computing core that meets a preset idle state, while non-critical processes are centrally allocated to a second computing core. At least one third computing core is controlled to enter a low-power state. This solves the technical problem of low energy efficiency caused by traditional load balancing strategies where all cores are in operation. It achieves the technical effect of significantly improving the energy efficiency of multi-core open instruction set architecture processors by enabling some cores to enter a low-power mode through load integration, while ensuring the real-time requirements of critical processes.

[0019] Figure 2 This is an architecture diagram of a processor provided for an embodiment of the present invention.

[0020] like Figure 2 As shown, the processor provided in this embodiment of the invention may include: multiple computing cores and a load integration control module. The load integration control module is connected to the multiple computing cores and is used to obtain the priority information of the software processes to be executed by the computing cores and the task execution status of the computing cores. Based on the priority information, it divides the processes into critical and non-critical processes, assigns critical processes to a first computing core, assigns non-critical processes to a second computing core, and controls at least one third computing core (excluding the first and second computing cores) to enter a low-power state. The first computing core is a computing core that satisfies a preset idle state.

[0021] In this embodiment of the invention, the preset idle state can be either a completely idle state or the computing core that performs the fewest tasks among all computing cores.

[0022] In some alternative embodiments of the present invention, the first computing core can be a computing core where the number of waiting software processes is less than or equal to a first threshold. By allocating critical processes to nearly idle cores, the real-time requirements of critical processes can be guaranteed, and delays caused by waiting for other processes to execute can be avoided.

[0023] The load integration control module allocates and adjusts the computing cores of the running software process based on the software process information and the hardware information of the computing cores, thereby integrating and comprehensively controlling the software load and avoiding the load balancing strategy in traditional software task scheduling algorithms. This embodiment of the invention assigns a separate computing core (i.e., the first computing core) to critical tasks, while centrally processing multiple non-critical tasks on one or more computing cores (i.e., the second computing core). While ensuring software task execution performance, more computing cores (i.e., the third computing core) are placed in low-power mode, thus greatly improving the power utilization of multi-core open instruction set architecture processors.

[0024] In this embodiment of the invention, the load integration control module can also be used to wake up at least one third computing core to share the non-critical processes of the second computing core when the task execution state of the second computing core meets the preset busy state, and to control the synchronization of cached data between the source computing core and the destination computing core when performing task migration.

[0025] In this embodiment of the invention, the load integration control module can also be configured with an adjustment feedback mechanism. If a risk of failing to meet performance requirements occurs during the centralized operation of non-critical tasks, corresponding computing cores will be added again for operation, i.e., a secondary allocation of computing cores mechanism. This ensures that non-critical tasks are processed centrally to reduce power consumption, while dynamically expanding the cores through the feedback mechanism to ensure that the performance of the software process is not affected.

[0026] The processor provided in this embodiment of the invention, by adding a load integration control module connected to multiple computing cores on the processor, is used to obtain the priority information of software processes and the task execution status of each computing core. According to the priority, the processes are divided into critical processes and non-critical processes. The critical processes are allocated to the first computing core that meets the preset idle state, and the non-critical processes are centrally allocated to the second computing core. The remaining at least one third computing core is controlled to enter a low-power state. This can solve the technical problem of low energy efficiency caused by all cores being in a working state in traditional load balancing strategies. It achieves the technical effect of significantly improving the energy efficiency of multi-core open instruction set architecture processors by enabling some cores to enter a low-power mode through load integration while ensuring the real-time requirements of critical processes.

[0027] Figure 3 This is an architecture diagram of a load integration control module provided in an embodiment of the present invention.

[0028] Based on the above embodiments, such as Figure 3As shown, the load integration control module may include: a software process information statistics submodule, used to collect statistics on the information of the software processes to be executed issued by the operating system and create a software process information statistics table; a computing core hardware information statistics submodule, used to collect statistics on the hardware information of the computing core and create a computing core hardware information table; a computing core pre-allocation and adjustment submodule, used to determine the target computing cores for critical processes and non-critical processes based on the software process information statistics table and the computing core hardware information table; and a cache data synchronization submodule, used to synchronize the L1 cache data in the source computing core to the L1 cache of the destination computing core after the computing core pre-allocation and adjustment submodule has completed process allocation.

[0029] In practical implementation, the software process information statistics module submodule is used to collect statistics on all software processes to be executed by the operating system and create a software process information statistics table. The software process information statistics table can include the process identifier, priority identifier, and time constraint information of the software processes to be executed. The software process information statistics table can be as shown in Table 1. Table 1

[0030] The compute core hardware information statistics submodule is used to collect statistics on the hardware information of the RISC-V Core and create a compute core hardware information table. This table can include the number of waiting software processes on the compute core (queue_process_cnt), the estimated execution time of these waiting processes (time_queue_process), and the estimated execution time of the currently running software processes on the compute core (time_cur_process). The compute core hardware information table can be shown in Table 2. Table 2

[0031] The computing core pre-allocation and adjustment submodule is used to classify software processes into critical processes and non-critical processes based on priority information in the software process information statistics table, and to determine the target core allocation for each process based on hardware information in the computing core hardware information table.

[0032] In this embodiment of the invention, the computing core pre-allocation and adjustment submodule allocates critical processes to the first computing core. This can include: allocating critical processes to computing cores where the number of waiting software processes (queue_process_cnt) is zero or one, based on the computing core hardware information table. This avoids the direct allocation of important / urgent tasks to idle computing cores, as is common in traditional solutions, reducing the occupancy of idle computing cores and allowing more computing cores to operate in a low-power state.

[0033] In the embodiment of the present invention, the computing core pre-allocation and adjustment sub-module allocating non-critical processes to the second computing core may include: for non-critical processes without time constraints, allocating the non-critical processes to the computing core with the largest number (queue_process_cnt) of software processes waiting to run; for non-critical processes with time constraints, determining to allocate the non-critical processes to the second computing core according to the sum of the estimated execution time (time_cur_process) of the currently running software process of the second computing core, the estimated execution time (time_queue_process) of the software processes waiting to run of the second computing core, and the average processing time (T_average) of the processes executed by the second computing core being less than the maximum allowable time (time_max) of the non-critical processes.

[0034] Specifically, the computing core pre-allocation and adjustment sub-module is used for: (1) First, according to the software process information statistical table created by the software process information statistical module sub-module, for important / urgent software processes, find the Core with queue_process_cnt = 0 or 1 in the computing core hardware information table created by the computing core hardware information statistical sub-module, and preferentially allocate the important / urgent processes to run on the Core that meets the above conditions. Thus, it is possible to avoid directly allocating important / urgent tasks to idle computing cores in the traditional solution, reducing the occupation of idle computing cores, and enabling more computing cores to be in a low-power state.

[0035] (2) Then, for non-important / non-urgent processes, if the process has no maximum allowable time time_max for software tasks, allocate the process to the computing core with the largest queue_process_cnt.

[0036] (3) For non-important / non-urgent processes and the process has a maximum allowable time time_max for software tasks, allocate the process to the computing core that is the closest according to the principle of time_cur_process + time_queue_process + T_average < time_max for each computing core.

[0037] For example, there are 3 new processes, and the maximum allowed times (time_max) for these three processes are 20ms, 17ms, and 12ms respectively. The computational core pre-allocation and adjustment submodule determines the estimated total time (T_need) required for all currently running processes within the multi-core open instruction set architecture processor to complete all existing tasks: T_need = time_cur_process + time_queue_process + T_average. For example: Computational core 0: time_cur_process = 0.5ms, time_queue_process = 12ms, T_average = 3ms; Computational core 1: time_cur_process = 0.7ms, time_queue_process = 10ms, T_average = 3.5ms; Computational core 2: time_cur_process = 1.2ms, time_queue_process = 15ms, T_average = 2ms…; Computational core 15: time_cur_process = 1ms, time_queue_process = 8ms, T_average = 2.5ms.

[0038] The computing cores are allocated based on the principle of closest time difference: First, the maximum allowed time_max of process 0 is closest to the T_need of Core 2 among all computing cores (the difference is the smallest), so process 0 is allocated to run in Core 2.

[0039] Again, the maximum allowed time_max of process 1 is closest to the T_need of Core 0 (with the smallest difference) among all the computing cores' T_needs. Therefore, process 1 is assigned to run in Core 0.

[0040] Again, the maximum allowed time_max of process 2 is closest to the T_need of Core 15 (with the smallest difference) among all computing cores' T_needs. Therefore, process 1 is assigned to run on Core 15.

[0041] The processor provided in this embodiment of the invention ensures that as many processes as possible can be allocated to the already running computing cores while meeting performance requirements, without having to be reallocated to new computing cores in low-power mode. This can greatly improve the hardware resource utilization and power consumption utilization of a single computing core. The load integration is achieved through a hardware method using an added load integration control module.

[0042] As described in the above embodiments, the load integration control module is further configured to wake up at least one third computing core to share the non-critical processes of the second computing core when the task execution state of the second computing core meets a preset busy state, and to control the synchronization of cached data between the source computing core and the destination computing core during task migration. The task can then be executed by the computing core pre-allocation and adjustment submodule. That is, the computing core pre-allocation and adjustment submodule can also be used to wake up at least one third computing core to share the non-critical processes of the second computing core when the task execution state of the second computing core meets a preset busy state, and to control the synchronization of cached data between the source computing core and the destination computing core during task migration.

[0043] Specifically, after the above steps are completed and each new process is assigned to a specific computing core, the computing core pre-allocation and adjustment submodule will monitor the program execution status of each process on each computing core in real time. Every T time interval, it will again use the following inequality to make a judgment (N is the number of judgments), where time_cur_process, time_queue_process, and T_average change in real time: time_cur_process + time_queue_process + T_average <time_max-T×N。

[0044] If, during a certain determination, the above inequality is found to no longer hold (i.e., the left side of the inequality is greater than or equal to the right side), the computational core allocation for that process needs to be updated promptly. The process should be treated as a new process and reallocated according to the computational core allocation steps described above.

[0045] If it is found that in the above computing core allocation, the T_max of a certain process is less than the T_need of all computing cores, then the process needs to be allocated to a new computing core to run on (such as selecting one from the third computing core). This computing core was previously in low-power mode and will be woken up at this time.

[0046] It should be noted that, in this embodiment of the invention, if a certain computing core has queue_process_cnt=0 and there are no new important / urgent processes to be allocated at this time, the computing core is promptly set to low power mode to reduce the power consumption of the multi-core open instruction set architecture processor.

[0047] The above describes the dynamic low-power and dynamic wake-up mechanism of the computing core in the embodiments of the present invention. While ensuring that the performance requirements of the software process on the processor are met, the power consumption of the processor is reduced as much as possible, which maximizes the energy efficiency ratio of the multi-core open instruction set architecture processor.

[0048] The cache data synchronization submodule synchronizes the L1 cache of the previously default-allocated computing cores to the L1 cache of the computing cores configured by the computing core pre-allocation and adjustment submodule after the computing core pre-allocation and adjustment submodule has completed the allocation of computing cores for the new process. This is because the operating system considers the principle of cache locality during allocation, prioritizing the allocation of processes to the computing cores from the previous run. Through the cache data synchronization submodule, the L1 cache hit rate of the new software process is improved, reducing performance loss caused by cache misses due to core switching, while the preceding modules enhance the energy efficiency of the open instruction set architecture processor.

[0049] Figure 4 This is an architecture diagram of a microarchitecture adjustment module provided in an embodiment of the present invention.

[0050] In traditional solutions, the microarchitecture of the computing cores of open instruction set architecture processors is fixed. That is, regardless of whether the task is complex or simple, urgent or non-urgent, the microarchitecture of each computing core in the processor remains unchanged, including (instruction prefetching enabled, multiple issue enabled, out-of-order execution enabled, compressed instruction parsing enabled, etc.). However, for simple or non-urgent tasks, the energy efficiency of the above-mentioned complex microarchitecture is very low, that is, a lot of power consumption is used but the effect on improving workload is not high.

[0051] Based on the above embodiments, such as Figure 2 As shown, the processor provided in this embodiment of the invention may further include a microarchitecture adjustment module; the microarchitecture adjustment module is connected to multiple computing cores and is used to control the on / off state of the microarchitecture function modules of the computing cores according to the performance requirement parameters of the processes running by the computing cores.

[0052] In this embodiment of the invention, the microarchitecture functional module may include at least one of the following: instruction prefetching functional module, branch prediction functional module, multiple issue functional module, and out-of-order execution functional module, and may also be other types of microarchitecture functional modules.

[0053] The microarchitecture adjustment module is used to adaptively adjust or trim the microarchitecture of the computing core, in order to simplify the actual microarchitecture scale of the computing core as much as possible while meeting the performance requirements of the software process, thereby further reducing the power consumption of the computing core and improving the energy efficiency of multi-core open instruction set architecture processors.

[0054] In this embodiment of the invention, the on / off state of the microarchitecture functional modules controlling the computing core can be executed only when the number of processes running on the computing core is one.

[0055] In embodiments of the present invention, such as Figure 4As shown, the microarchitecture adjustment module may include: a microarchitecture statistics submodule, used to determine the composition of the microarchitecture functional modules included in the computing core; a microarchitecture performance impact analysis submodule, used to determine the performance impact parameters of multiple microarchitecture functional modules of the computing core in the on and off states, and create a microarchitecture performance impact analysis table; a time slack calculation submodule, used to determine the time slack of the computing core for running the currently running software process based on the performance requirement parameters of the currently running software process of the computing core and the processing time of the currently running software process of the computing core; and a microarchitecture adjustment submodule, used to select a matching microarchitecture combination mode from the microarchitecture performance impact analysis table based on the time slack, and configure the computing core according to the selected microarchitecture combination mode.

[0056] In practical implementation, the microarchitecture statistics submodule is used to perform statistics on the composition of the hardware microarchitecture within the computing core.

[0057] The microarchitecture performance impact analysis submodule analyzes the impact of enabling and disabling the instruction prefetching module, branch prediction module, multi-issue module, and out-of-order execution module on the computing core processing software. Specifically, based on a test program (a test program that runs before the multi-core open instruction set architecture processor officially starts working), it sequentially tests the performance impact ratio of enabling or disabling the above functions on the computing core, creating a microarchitecture performance impact analysis table. The microarchitecture performance impact analysis table can include microarchitecture combination mode identifiers, the on / off status of each microarchitecture functional module under the microarchitecture combination mode, and the performance impact ratio of the microarchitecture combination mode relative to the state where all microarchitecture functional modules are enabled. By pre-quantifying the performance impact of each microarchitecture configuration, it provides data support for dynamic adjustments at runtime.

[0058] The performance impact analysis of microarchitecture can be shown in Table 3. Table 3

[0059] In Table 3, 1 indicates that the corresponding functional unit is enabled or turned on, and 0 indicates that the corresponding functional unit is disabled or turned off. The performance impact ratio represents the percentage decrease in performance of this microarchitecture composition pattern relative to the state where all functional modules are enabled (Scenario 1).

[0060] In this embodiment of the invention, the microarchitecture adjustment submodule determines a matching microarchitecture combination pattern based on time slack and performance impact parameters. This can include selecting a matching microarchitecture combination pattern from a microarchitecture performance impact analysis table based on the time slack. That is, by converting the time slack of the currently running software process into an allowable performance degradation percentage, and then matching it with the performance impact percentages of each scenario in the table, the most suitable microarchitecture combination is selected.

[0061] The time buffer calculation submodule calculates the time buffer t_buffer = time_max - time_cur_process based on the time_cur_process of each computing core and the time_max of the process. It then calculates the maximum allowable processing time reduction ratio for that process on the current computing core: t_buffer / time_max. It should be noted that microarchitecture dynamic adaptive adjustment is suitable for scenarios where the number of processes on a computing core is equal to 1, a scenario frequently encountered in multi-core open instruction set architecture processors.

[0062] The microarchitecture adjustment submodule selects a matching microarchitecture combination pattern from the microarchitecture performance impact analysis table based on the time slack. This can include: calculating the ratio of the time slack to the maximum allowed processing time of the currently running software process to obtain the maximum allowed processing time reduction ratio; and selecting the microarchitecture combination pattern corresponding to the performance impact ratio closest to the maximum allowed processing time reduction ratio from the microarchitecture performance impact analysis table.

[0063] Specifically, the microarchitecture tuning submodule is used to select the microarchitecture combination pattern that is closest to the maximum processing time reduction ratio (t_buffer / time_max) for each core and its corresponding process, based on Table 3, as the final tuned microarchitecture. In other words, the microarchitecture tuning for each computing core can be different, determined specifically based on the actual running conditions of the process and the allowed maximum processing time reduction ratio.

[0064] For example, in compute core 0, time_max = 10ms and time_cur_process = 5ms, then the maximum allowable processing time reduction ratio = (10-5) / 10 = 50%. Looking up the table in Table 3, scenario 6 (performance impact ratio of 50%) is closest to 50%. Therefore, the corresponding optimal energy efficiency microarchitecture combination is: enable instruction prefetching module, disable branch prediction module, disable multi-issue module, and enable out-of-order execution module.

[0065] In compute core 1, time_max=10ms and time_cur_process=8ms, so the maximum allowable processing time reduction ratio is (10-8) / 10=20%. Looking up the table in Table 3, the closest to 20% are scenario 3 (performance impact ratio of 30%) or scenario 7 (performance impact ratio of 20%). If scenario 7 is selected, the corresponding optimal energy efficiency microarchitecture combination is: disable instruction prefetching module, enable branch prediction module, enable multi-issue module, and enable out-of-order execution module.

[0066] After the above process, the optimal energy efficiency ratio of each computing core under the current running software process can be obtained by the microarchitecture combination, and dynamic adjustments can be made to maximize the energy efficiency ratio of the multi-core open instruction set architecture processor while meeting the performance requirements of the software process.

[0067] The embodiments of the present invention provide a processor resource configuration method. The method is described in detail below in conjunction with the execution flow of the processor resource configuration method.

[0068] Figure 5 This is a flowchart of a processor resource configuration method provided in an embodiment of the present invention.

[0069] The processor resource configuration method provided in this embodiment of the invention can be implemented based on the processor provided in any of the above embodiments. For example... Figure 5 As shown, the processor resource configuration method provided in this embodiment of the invention may include: S501: obtaining the priority information of the software process to be executed in the processor's computing core.

[0070] S502: Obtain the task execution status of the computing core.

[0071] S503: Based on priority information, critical processes and non-critical processes are divided, critical processes are assigned to the first computing core, and non-critical processes are assigned to the second computing core.

[0072] S504: Controls at least one third computing core (other than the first and second computing cores) to enter a low-power state.

[0073] The first computing core is a computing core that satisfies a preset idle state.

[0074] In practice, the preset idle state can be either completely idle or the computing core with the fewest tasks executed among all computing cores.

[0075] In some alternative embodiments of the present invention, the first computing core can be a computing core where the number of waiting software processes is less than or equal to a first threshold. By allocating critical processes to nearly idle cores, the real-time requirements of critical processes can be guaranteed, and delays caused by waiting for other processes to execute can be avoided.

[0076] For S501, the priority information of the software process to be executed can be obtained from the operating system through the software process information statistics submodule in the load integration control module.

[0077] For S502, the task execution status, such as the current task queue depth and the remaining execution time of the currently running process, can be obtained through the computing core hardware information statistics submodule in the load integration control module.

[0078] For S503, the compute core pre-allocation and adjustment submodule in the load integration control module can divide processes into critical and non-critical processes based on priority information, and determine the target allocation core based on the hardware information in the compute core hardware information table. Allocating critical processes to compute cores with zero or one waiting software processes can avoid the problem of directly allocating critical tasks to idle cores, which would consume too much idle resources, as is the case in traditional solutions.

[0079] For the S504, the load integration control module controls the third computing core that is not assigned to a process to enter a low-power state (such as hibernation or frequency reduction), which can minimize the static and dynamic power consumption of the multi-core processor.

[0080] The processor resource configuration method provided in this invention adds a load integration control module connected to multiple computing cores on the processor. This module acquires the priority information of software processes and the task execution status of each computing core. Based on the priority, the processes are divided into critical processes and non-critical processes. Critical processes are allocated to the first computing core that meets the preset idle state, while non-critical processes are centrally allocated to the second computing core. The remaining at least one third computing core is controlled to enter a low-power state. This method can solve the technical problem of low energy efficiency caused by all cores being in a working state in traditional load balancing strategies. It achieves the technical effect of significantly improving the energy efficiency of multi-core open instruction set architecture processors by enabling some cores to enter a low-power mode through load integration while ensuring the real-time requirements of critical processes.

[0081] Based on the above embodiments, the processor resource configuration method provided by the embodiments of the present invention may further include: creating a software process information statistics table; wherein, the software process information statistics table includes the process identifier, priority identifier and time constraint information of the software process to be executed.

[0082] In practical implementation, the software process information statistics submodule in the load integration control module can be used to collect statistics on all software processes to be executed issued by the operating system, and create a software process information statistics table according to the format of Table 1, so as to provide a data basis for subsequent process allocation decisions.

[0083] The processor resource configuration method provided in this embodiment of the invention may further include: creating a computing core hardware information table; wherein, the computing core hardware information table includes the number of waiting software processes of the computing core (queue_process_cnt), the estimated execution time of the waiting software processes (time_queue_process), and the estimated execution time of the currently running software processes of the computing core (time_cur_process).

[0084] In practical implementation, the hardware operating status of each computing core can be statistically analyzed through the computing core hardware information statistics submodule in the load integration control module, and a computing core hardware information table can be created according to the format of Table 2 to provide real-time hardware status data for subsequent core selection decisions.

[0085] In this embodiment of the invention, the allocation of non-critical processes to the second computing core in S503 may include: for non-critical processes without time constraints, allocating the non-critical processes to the computing core with the largest number of waiting software processes; for non-critical processes with time constraints, determining the second computing core to which the non-critical processes will be allocated based on the sum of the estimated execution time of the currently running software processes on the second computing core, the estimated execution time of the waiting software processes on the second computing core, and the average processing time of the processes executed on the second computing core, which is less than the maximum allowed time for the non-critical processes.

[0086] In other words, for non-critical processes with time constraints, the estimated completion time of each computing core is calculated according to T_need = time_cur_process + time_queue_process + T_average. The core with T_need closest to time_max is selected for allocation, ensuring that as many processes as possible can be allocated to already running cores while meeting performance requirements, without waking up new cores in low-power mode. This greatly improves the hardware resource utilization of individual computing cores and the overall power consumption utilization.

[0087] The processor resource configuration method provided in this embodiment of the invention may further include: when the task execution state of the second computing core meets the preset busy state, waking up at least one third computing core to share the non-critical processes of the second computing core; and controlling the synchronization of cache data between the source computing core and the destination computing core during task migration.

[0088] Specifically, the computing core pre-allocation and adjustment submodule can monitor the process execution status of each computing core in real time after the process is allocated to a specific core. Every preset time period T, it uses the following formula to determine the process execution status: time_cur_process + time_queue_process + T_average <time_max-T×N。

[0089] Where N represents the number of judgments. When the above formula no longer holds (i.e., the left side of the inequality is greater than or equal to the right side), it indicates that the current computing core may be at risk of failing to meet the process time constraints. In this case, the computing core allocation for the process needs to be updated promptly, and the process should be reassigned as a new process. If the time_max of a process is less than the T_need of all computing cores, the process needs to be assigned to a new core to run on. This computing core was previously in low-power mode and will be woken up at this time. Through a feedback monitoring mechanism, cores are dynamically expanded when performance is insufficient due to concentrated processing of non-critical tasks, minimizing power consumption while ensuring performance. At the same time, by synchronizing the L1 cache of the source core to the L1 cache of the destination core through the cache data synchronization submodule, the cache hit rate of the new software process can be improved, reducing the performance loss caused by computing core switching.

[0090] Based on the above embodiments, the processor resource configuration method provided by the embodiments of the present invention may further include: controlling the on / off state of the microarchitecture functional modules of the computing core according to the performance requirement parameters of the process running by the computing core.

[0091] In other words, by adjusting the microarchitecture module, various microarchitecture function modules in the computing core can be dynamically enabled or disabled according to the actual computing performance requirements of the currently running software process. This simplifies the actual microarchitecture scale used by the computing core while meeting the process performance requirements, further reducing the power consumption of the computing core and improving the energy efficiency of multi-core open instruction set architecture processors.

[0092] In specific implementations, microarchitecture functional modules may include at least one of the following: instruction prefetching functional module, branch prediction functional module, multiple issue functional module, and out-of-order execution functional module, or other types of microarchitecture functional modules.

[0093] The on / off state of the microarchitecture functional modules that control the computing core can be executed only when the number of processes running on the computing core is one, thereby avoiding additional overhead and uncertainty caused by frequent microarchitecture switching when multiple processes share the computing core.

[0094] In this embodiment of the invention, controlling the on / off state of the microarchitecture functional modules of the computing core according to the performance requirement parameters of the process running by the computing core may include: determining the composition of the microarchitecture functional modules included in the computing core; determining the performance impact parameters of multiple microarchitecture functional modules of the computing core in the on and off states; determining the time margin for the computing core to run the currently running software process based on the performance requirement parameters of the currently running software process and the processing time of the currently running software process; determining a matching microarchitecture combination mode based on the time margin and the performance impact parameters; and configuring the computing core according to the selected microarchitecture combination mode.

[0095] Specifically, the microarchitecture statistics submodule can be used to first calculate the core microarchitecture components, then the microarchitecture performance impact analysis submodule can be used to pre-test the performance impact ratio of each functional module's on / off state, then the time margin calculation submodule can be used to calculate the allowable performance degradation space of the currently running software process, and finally the microarchitecture adjustment submodule can be used to select the most suitable microarchitecture combination mode for configuration.

[0096] The processor resource configuration method provided in this embodiment of the invention may further include: creating a microarchitecture performance impact analysis table based on the performance impact parameters of multiple microarchitecture functional modules of the computing core in the on and off states; wherein, the microarchitecture performance impact analysis table includes a microarchitecture combination mode identifier, the on / off state of each microarchitecture functional module in the microarchitecture combination mode, and the performance impact ratio of the microarchitecture combination mode relative to the on state of all microarchitecture functional modules.

[0097] In other words, a test program is run before the multi-core open instruction set architecture processor officially starts working. This program sequentially tests the impact of enabling or disabling various functional modules, such as instruction prefetching, branch prediction, multiple issuance, and out-of-order execution, on the performance of the computing cores. A microarchitecture performance impact analysis table is then created according to the format in Table 3. By pre-quantifying the performance impact of each microarchitecture configuration, data support is provided for dynamic adjustments at runtime, avoiding the additional overhead of online measurements.

[0098] In this embodiment of the invention, determining a matching microarchitecture combination pattern based on time margin and performance impact parameters may include: selecting a matching microarchitecture combination pattern from a microarchitecture performance impact analysis table based on the time margin. That is, the time margin of the currently running software process is converted into an allowable performance degradation percentage, and then matched with the performance impact percentages of each scenario in the microarchitecture performance impact analysis table to select the most suitable microarchitecture combination.

[0099] In this embodiment of the invention, selecting a matching microarchitecture combination pattern from the microarchitecture performance impact analysis table based on the time slack may include: calculating the ratio of the time slack to the maximum allowed processing time of the currently running software process to obtain the maximum allowed processing time reduction ratio; and selecting the microarchitecture combination pattern corresponding to the performance impact ratio closest to the maximum allowed processing time reduction ratio from the microarchitecture performance impact analysis table.

[0100] In other words, for each computing core and the unique process running on it, the time buffer t_buffer = time_max - time_cur_process is first calculated, followed by the maximum allowable processing time reduction ratio = t_buffer / time_max. Then, the microarchitecture combination mode that is closest to the performance impact ratio and the maximum allowable processing time reduction ratio is selected from the microarchitecture performance impact analysis table. Since different processes run on different computing cores, the microarchitecture adjustments of each core can be independent of each other, thereby maximizing the energy efficiency of each computing core while meeting the performance requirements of each process, thus improving the overall energy efficiency of multi-core open instruction set architecture processors.

[0101] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Since the processor resource configuration method provided in the embodiments of the present invention corresponds to the processor provided in the embodiments of the present invention, the parts not described in the method embodiments can be referred to the description of the processor embodiments.

[0102] Embodiments of the present invention also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the processor resource configuration method embodiments described above.

[0103] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the processor resource configuration method embodiments described above when running.

[0104] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0105] Embodiments of the present invention also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the processor resource configuration method embodiments described above.

[0106] Embodiments of the present invention also provide another computer program product, including a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the processor resource configuration method embodiments described above.

[0107] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be performed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0108] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0109] The present invention has been described in detail above, including a processor, a processor resource configuration method, a storage medium, and a program product. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of these embodiments are only intended to aid in understanding the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A processor, comprising: include: Multiple computing cores and load integration control modules; The load integration control module is connected to multiple computing cores and is used to obtain the priority information of the software processes to be executed by the computing cores and the task execution status of the computing cores. Based on the priority information, it divides the processes into critical processes and non-critical processes, assigns the critical processes to the first computing core, assigns the non-critical processes to the second computing core, and controls at least one third computing core other than the first computing core and the second computing core to enter a low-power state. The first computing core is the computing core that satisfies a preset idle state.

2. The processor of claim 1, wherein, The load integration control module is also used to wake up at least one of the third computing cores to share the non-critical processes of the second computing core when the task execution state of the second computing core meets the preset busy state, and to control the synchronization of cached data between the source computing core and the destination computing core when performing task migration.

3. The processor of claim 1, wherein, The load integration control module includes: The software process information statistics submodule is used to collect statistics on the software processes to be executed issued by the operating system and create a software process information statistics table. The computing core hardware information statistics submodule is used to collect statistics on the hardware information of the computing core and create a computing core hardware information table. The computing core pre-allocation and adjustment submodule is used to determine the target computing cores of the critical processes and the target computing cores of the non-critical processes based on the software process information statistics table and the computing core hardware information table. The cache data synchronization submodule is used to synchronize the level 1 cache data in the source computing core to the level 1 cache of the destination computing core after the computing core pre-allocation and adjustment submodule has completed the process allocation.

4. The processor of claim 1, wherein, It also includes a microarchitecture tuning module; The microarchitecture adjustment module is connected to multiple computing cores and is used to control the on / off state of the microarchitecture function modules of the computing cores according to the performance requirement parameters of the processes running on the computing cores.

5. The processor of claim 4, wherein, The microarchitecture tuning module includes: The microarchitecture statistics submodule is used to determine the composition of the microarchitecture functional modules included in the computing core; The microarchitecture performance impact analysis submodule is used to determine the performance impact parameters of multiple microarchitecture functional modules of the computing core in the on and off states, and to create a microarchitecture performance impact analysis table. The time margin calculation submodule is used to determine the time margin for the computing core to run the currently running software process based on the performance requirement parameters of the currently running software process of the computing core and the processing time of the computing core running the currently running software process. The microarchitecture adjustment submodule is used to select a matching microarchitecture combination pattern from the microarchitecture performance impact analysis table according to the time margin, and configure the computing core according to the selected microarchitecture combination pattern.

6. A processor resource configuration method, characterized by, The processor based on any one of claims 1 to 5 includes: Obtain the priority information of the software process to be executed in the computing core of the processor; Obtain the task execution status of the computing core; Based on the priority information, critical processes and non-critical processes are divided, and the critical processes are assigned to the first computing core, while the non-critical processes are assigned to the second computing core. Control at least one third computing core among the plurality of computing cores, excluding the first computing core and the second computing core, to enter a low-power state; The first computing core is the computing core that satisfies a preset idle state.

7. The processor resource configuration method of claim 6, wherein, Also includes: Create a software process information statistics table; The software process information statistics table includes the process identifier, priority identifier, and time constraint information of the software process to be executed.

8. The processor resource configuration method of claim 6, wherein, Also includes: Create a computing core hardware information table; The computing core hardware information table includes the number of waiting software processes on the computing core, the estimated execution time of the waiting software processes, and the estimated execution time of the currently running software processes on the computing core.

9. The processor resource configuration method of claim 6, wherein, The first computing core is the computing core whose number of waiting software processes is less than or equal to a first threshold.

10. The processor resource configuration method of claim 6, wherein, Assigning the non-critical processes to the second computing core includes: For non-critical processes without time constraints, the non-critical processes are assigned to the computing core with the largest number of waiting software processes. For the non-critical process with time constraints, the second computing core to which the non-critical process will be allocated is determined based on the sum of the estimated execution time of the currently running software process of the second computing core, the estimated execution time of the waiting software process of the second computing core, and the average processing time of the executing process of the second computing core being less than the maximum allowed time of the non-critical process.

11. The processor resource configuration method of claim 6, wherein, Also includes: When the task execution state of the second computing core meets the preset busy state, at least one of the third computing cores is woken up to share the non-critical processes of the second computing core. Control the synchronization of cached data between the source compute core and the destination compute core during task migration.

12. The processor resource configuration method of claim 6, wherein, Also includes: Based on the performance requirements of the processes running in the computing core, the on / off states of the microarchitecture functional modules of the computing core are controlled.

13. The processor resource allocation method according to claim 12, characterized in that, Based on the performance requirements of the processes running on the computing core, the on / off states of the microarchitecture functional modules of the computing core are controlled, including: Determine the composition of the microarchitecture functional modules included in the computing core; Determine the performance impact parameters of multiple microarchitectural functional modules of the computing core in the on and off states; Based on the performance requirements parameters of the currently running software process of the computing core and the processing time already completed by the computing core in running the currently running software process, determine the time margin for the computing core to run the currently running software process. Based on the time margin and the performance impact parameters, determine the matching microarchitecture combination pattern; Configure the computing cores according to the selected microarchitecture combination pattern.

14. The processor resource allocation method according to claim 13, characterized in that, Also includes: Based on the performance impact parameters of multiple microarchitecture functional modules of the computing core in the on and off states, a microarchitecture performance impact analysis table is created; The microarchitecture performance impact analysis table includes a microarchitecture combination mode identifier, the on / off status of each microarchitecture functional module under the microarchitecture combination mode, and the performance impact ratio of the microarchitecture combination mode relative to the on / off state of all the microarchitecture functional modules.

15. The processor resource allocation method according to claim 14, characterized in that, Based on the time margin and the performance impact parameters, a matching microarchitecture composition pattern is determined, including: Select a matching microarchitecture combination pattern from the microarchitecture performance impact analysis table based on the time slack.

16. The processor resource allocation method according to claim 15, characterized in that, Based on the time slack, select a matching microarchitecture combination pattern from the microarchitecture performance impact analysis table, including: Calculate the ratio of the time slack to the maximum allowed processing time of the currently running software process to obtain the maximum allowed processing time reduction ratio; Select the microarchitecture combination pattern from the microarchitecture performance impact analysis table that corresponds to the performance impact ratio closest to the maximum allowable processing time reduction ratio.

17. The processor resource allocation method according to claim 12, characterized in that, The on / off state of the microarchitecture functional modules of the computing core is controlled and is executed only when the number of processes running on the computing core is one.

18. The processor resource allocation method according to claim 12, characterized in that, The microarchitecture functional modules include at least one of the following: instruction prefetching module, branch prediction module, multiple issue module, and out-of-order execution module.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the processor resource allocation method as described in any one of claims 6 to 18.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the processor resource allocation method as described in any one of claims 6 to 18.

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