Chip, chip module, chip verification method and device, computer equipment and program product

Abstract

This application relates to a chip, a chip module, a chip verification method, an apparatus, a computer device, and a program product. The method includes: the chip comprising a bus module, a control and adjustment module, multiple data processing modules, and cache modules corresponding to each data processing module, with each cache module deployed adjacent to each other in the same chip region; the bus module is connected to each data processing module and also to each cache module; the control and adjustment module is connected to each cache module. This method can improve the chip verification effect.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip, chip module, chip verification method, apparatus, computer equipment, and software product. Background Technology

[0002] With the continuous development of chip technology, chips are carrying more and more functions, and chips can be applied to a variety of devices to achieve corresponding functions.

[0003] Currently, to ensure high-speed read and write of the data processing module in the chip, the chip is equipped with multiple DDR (Double Data Rate Synchronous Dynamic Random Access Memory).

[0004] However, the configuration of multiple DDRs results in low resource utilization during chip use and verification. Summary of the Invention

[0005] Therefore, it is necessary to provide a chip, chip module, chip verification method, apparatus, computer equipment, and program product that can improve the resource utilization of chip use and verification in order to address the above-mentioned technical problems.

[0006] In a first aspect, this application provides a chip, including a bus module, a control and adjustment module, multiple data processing modules, and cache modules corresponding to each data processing module. The cache modules are deployed adjacently in the same chip area. The bus module is connected to each data processing module and also to each cache module. The bus module is used to transmit data between the data processing modules and the corresponding cache modules, and the cache modules are used to store the data transmitted by the data processing modules. The control and adjustment module is connected to each cache module and is used for one or more of the following: adjusting the clock frequency of the cache module, adjusting the power consumption of the cache module, and monitoring the performance of the cache module.

[0007] In one embodiment, the bus module includes a bus interface and a routing unit connected to the bus interface. The bus interface is connected to each data processing module, and the routing unit is connected to each cache module. The bus interface is used to receive data sent by each data processing module. The routing unit is used to determine the target cache module that matches the data based on the identifier carried in the data for each data processing module, and to transmit the data to the target cache module.

[0008] In one embodiment, the control and adjustment module includes at least one of a dynamic frequency adjustment module, a performance monitoring module, and a low-power control module. The dynamic frequency adjustment module is connected to each cache module, the performance monitoring module is connected to each cache module, and the low-power control module is connected to each cache module. The dynamic frequency adjustment module is used to adjust the clock frequency of the cache module, the performance monitoring module is used to monitor the performance of the cache module, and the low-power control module is used to adjust the power of the cache module.

[0009] Secondly, this application also provides a chip module, including a communication module, a power module, a storage module, and the chip mentioned in the first aspect, wherein: the power module is used to provide power to the chip module; the storage module is used to store data and instructions; and the communication module is used for internal communication within the chip module or for communication between the chip module and external devices.

[0010] Thirdly, this application also provides a chip verification method applied to the chip described in the first aspect. The method includes: receiving a first verification stimulus sent by a verification device through a bus module, and transmitting the first verification stimulus to each cache module through the bus module; obtaining first response data corresponding to each cache module by having each cache module respond to the first verification stimulus; wherein each first response data determines the verification result of each cache module, and the verification result of each cache module is used to determine the verification result of the chip.

[0011] Fourthly, this application also provides a chip verification apparatus, comprising: a first verification stimulus acquisition module, configured to receive a first verification stimulus sent by a verification device via a bus module, and transmit the first verification stimulus to each cache module via the bus module; and a first response data acquisition module, configured to obtain first response data corresponding to each cache module by responding to the first verification stimulus through each cache module; wherein each first response data determines the verification result of each cache module, and the verification result of each cache module is used to determine the verification result of the chip.

[0012] Fifthly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method provided in the third aspect above.

[0013] Sixthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method provided in the third aspect above.

[0014] In a seventh aspect, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method provided in the third aspect.

[0015] The aforementioned chip, chip module, chip verification method, apparatus, computer equipment, and program product include a bus module, a control and adjustment module, multiple data processing modules, and cache modules deployed adjacent to each other in the same chip area. This reduces redundant bus deployments and improves the bus resource utilization and area utilization of the chip. The bus module is connected to each data processing module and also to each cache module. The bus module is used to transmit data between the data processing modules and the corresponding cache modules. The cache modules are used to store the data transmitted by the data processing modules. The bus module manages the bus resources of the cache modules uniformly. The control and adjustment module is connected to each cache module and is used for one or more of the following: adjusting the clock frequency of the cache module, adjusting the power consumption of the cache module, monitoring the performance of the cache module, and setting a unified / identical control and adjustment module for multiple cache modules, further improving the resource utilization of the chip. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of the first type of chip in one embodiment;

[0018] Figure 2 This is a schematic diagram of the structure of the second type of chip in one embodiment;

[0019] Figure 3 This is a schematic diagram of the structure of the third type of chip in one embodiment;

[0020] Figure 4 This is a schematic diagram of the structure of the fourth type of chip in one embodiment;

[0021] Figure 5 This is a schematic diagram illustrating the application environment of a chip verification method in one embodiment;

[0022] Figure 6 This is a flowchart illustrating a chip verification method in one embodiment;

[0023] Figure 7 This is a flowchart illustrating the second verification process in one embodiment;

[0024] Figure 8 This is a flowchart illustrating the read / write verification process in one embodiment;

[0025] Figure 9 This is a structural block diagram of a chip verification device in one embodiment;

[0026] Figure 10 This is an internal structural diagram of a computer device in one embodiment;

[0027] Figure 11 This is an internal structure diagram of a chip module in one embodiment. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0029] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0030] In practical applications, for SoC chips with multiple DDR subsystems, existing technologies design the bus, clock, power management, clock frequency switching, and performance monitoring modules of each subsystem separately. Since most systems access multiple DDRs, individual subsystem designs cannot achieve signal sharing and module multiplexing for clock, power, and other modules, leading to a significant increase in the number of bus signals. This makes backend Place and Route (PR) difficult and increases area. Furthermore, clock frequency switching (DFS), power (PMU and LPC), and performance monitoring modules (PTM) are difficult to control uniformly, resulting in poor performance and significantly increased costs. From DDR to DDR5, each generation of DDR memory has brought higher data transfer rates, lower power consumption, and higher storage density. In data centers and cloud computing, the required memory capacity has increased exponentially. In mobile devices and embedded systems, low power consumption and smaller area are required while maintaining performance. These demands indicate the need for multiple DDRs to meet the ever-increasing memory capacity requirements. However, multiple DDRs inevitably increase the difficulty of clock, power, and performance monitoring on the SoC, and also make the design of DDR controllers and PHYs more complex. Complex modular designs ultimately lead to increased area and greater routing complexity, making a well-designed architecture particularly important. Similarly, with the changing and increasingly complex design architectures, traditional single-DDR verification environment architectures are no longer sufficient to meet the verification needs of multiple DDR systems. A multi-DDR verification environment architecture that adapts to more accurate simulations and more reasonable testing procedures has become an inevitable requirement.

[0031] Traditional SoC designs with multiple DDR subsystems tend to place DDR0~DDRX in different locations on the chip, with common architectures such as... Figure 1 As shown, the PMU module manages the LPCs of each DDR subsystem, and the PTM module collects real-time performance data for each DDR subsystem and sends the data back to the CPU. In addition, the DDR subsystems require the integration of DFS, CLK, and AXI ports. The introduction of these modules not only increases the area of ​​each DDR subsystem but also adds to the number of interconnect signals between the LPC and PMU, and between the PTM and the CPU. Furthermore, each DDR system requires separate routing, necessitating a large number of routing channels on the SoC, significantly increasing the SoC area. The complexity of the routing also makes performance optimization (PR) difficult, thus increasing the overall chip cost. Moreover, the bus trace lengths for different DDR systems vary, requiring standardized handling for different routing channels when timing issues arise, further increasing development complexity. Additionally, the bus transmission distances for different DDR subsystems are not consistently maintained, leading to performance loss when the system interleaves accesses multiple DDR systems.

[0032] To address this, this application combines multiple DDR subsystems into the same chip area, unifies the buses of each DDR subsystem, manages the buses of each DDR subsystem through a unified bus module, and sets up a unified control and adjustment module for each DDR subsystem, thereby reducing implementation difficulty and saving chip area costs.

[0033] In one exemplary embodiment, such as Figure 1 As shown, a chip 101 is provided, which includes a bus module 102, a control and adjustment module 103, multiple data processing modules 104, and cache modules 105 corresponding to each data processing module. The bus module 102 is connected to each data processing module 104, and the bus module 102 is also connected to each cache module 105. The control and adjustment module 103 is connected to each cache module 105.

[0034] During implementation, the bus module 102 is used to transmit data between the data processing module 104 and the corresponding cache module 105, and the cache module 105 is used to store the data transmitted by the data processing module 104. The control and adjustment module 103 is used for one or more of the following: adjusting the clock frequency of the cache module, adjusting the power consumption of the cache module, and monitoring the performance of the cache module.

[0035] The cache module 105 can be a DDR subsystem, and each cache module 105 may include a DDR memory cell, a DDRC (DDR controller), and a PHY (physical layer interface module). Each cache module 105 can be deployed adjacently in the same chip area. The data processing module 104 can be at least one of a central processing unit, a graphics processor, a UART / Timer, or other peripherals or subsystems. The control and adjustment module 103 is used to monitor and adjust the usage status of the cache modules 105.

[0036] The aforementioned chip includes a bus module, a control and adjustment module, multiple data processing modules, and cache modules. Each cache module is deployed adjacently within the same chip area, reducing redundant bus deployments and improving bus resource utilization and area utilization. The bus module is connected to each data processing module and each cache module. The bus module transmits data between the data processing modules and their corresponding cache modules, while the cache modules store the data transmitted by the data processing modules. The bus module centrally manages the bus resources of the cache modules. The control and adjustment module is connected to each cache module and is used for one or more of the following: adjusting the clock frequency of the cache modules, adjusting the power consumption of the cache modules, monitoring the performance of the cache modules, and setting a unified / identical control and adjustment module for multiple cache modules, further improving the chip's resource utilization.

[0037] Based on the above exemplary embodiment, a chip is provided in one or more exemplary embodiments, specifically including the following contents.

[0038] In practical scenarios, the bus module 102 may include a bus interface and a routing unit connected to the bus interface for efficient bus management; in one optional embodiment provided in this application, such as Figure 2 As shown, the bus module 102 includes a bus interface 201 and a routing unit 202, with the bus interface 201 connected to the routing unit 202.

[0039] The bus interface 201 is connected to each data processing module 104, and the routing unit 202 is connected to each cache module 105. The bus interface 201 is used to receive data sent by each data processing module 104. The routing unit 202 is used to determine the target cache module that matches the data for each data processing module 104 based on the identifier carried by the data, and to transmit the data to the target cache module.

[0040] One optional implementation provided in this application uses a bus module to implement bus management for the DDR subsystem, eliminating redundant buses and area occupation, and improving chip area and bus utilization.

[0041] In practical scenarios, a chip may include multiple control and adjustment modules to implement different control and adjustment functions; in one optional embodiment provided in this application, such as Figure 3 As shown, the control and adjustment module 103 includes at least one of a dynamic frequency adjustment module 301, a performance monitoring module 302, and a low-power control module 303. The dynamic frequency adjustment module 301 is connected to each cache module 105, the performance monitoring module 302 is connected to each cache module 105, and the low-power control module 303 is connected to each cache module 105. The dynamic frequency adjustment module 301 is used to adjust the clock frequency of the cache module, the performance monitoring module 302 is used to monitor the performance of the cache module, and the low-power control module 303 is used to adjust the power of the cache module.

[0042] Among them, the dynamic frequency scaling module 301 can be DFS (Dynamic Frequency Scaling); the performance monitoring module 302 can be PTM (Performance Trace Monitor); and the low power control module 303 can be LPC (low power control module).

[0043] One optional implementation provided in this application improves the utilization rate of the power regulation module by having multiple DDR subsystems of the chip share the power regulation module, thereby saving chip area and computing resources.

[0044] In one embodiment, see Figure 4 This illustrates a chip provided in an embodiment of this application. For example... Figure 4 As shown, chip 101 includes a bus module 102, a control and adjustment module 103, multiple data processing modules 104, and cache modules 105 corresponding to each data processing module. The bus module 102 is connected to each data processing module 104 and also to each cache module 105. The control and adjustment module 103 is connected to each cache module 105. The bus module 102 includes a bus interface 201 and a routing unit 202, with the bus interface 201 connected to the routing unit 202. The control and adjustment module 103 includes a dynamic frequency adjustment module 301, a performance monitoring module 302, and a low-power control module 303.

[0045] The bus module 102 is used to transmit data between the data processing module 104 and the corresponding cache module 105, and the cache module 105 is used to store the data transmitted by the data processing module 104. The control and adjustment module 103 is used for one or more of the following: adjusting the clock frequency of the cache module, adjusting the power consumption of the cache module, and monitoring the performance of the cache module.

[0046] The bus interface 201 is connected to each data processing module 104 respectively, and the routing unit 202 is connected to each cache module 105 respectively. The bus interface 201 is used to receive data sent by each data processing module 104. The routing unit 202 is used to determine the target cache module that matches the data according to the identifier carried by the data for each data processing module 104, and to transmit the data to the target cache module.

[0047] The dynamic frequency adjustment module 301 is connected to each cache module 105, the performance monitoring module 302 is connected to each cache module 105, and the low power control module 303 is connected to each cache module 105. The dynamic frequency adjustment module 301 is used to adjust the clock frequency of the cache module, the performance monitoring module 302 is used to monitor the performance of the cache module, and the low power control module 303 is used to adjust the power of the cache module.

[0048] This chip integrates multiple DDRC / PHY components into a single DDR subsystem. This system primarily consists of an AXI PORT, bus matrix, LPC, DFS, PTM, and multiple DDRC and PHY components. The LPC, in conjunction with the PMU, provides individual low-power control for each DDR and supports unified multi-DDR collaborative power management control. Secondly, the PTM's signal transmission back to the CPU has been eliminated. Instead, the PTM directly obtains the performance status of each DDR from the bus signals, summarizes the results, and writes them back to a specific DDR chip. The CPU then reads the results, saving wiring between the PTM and CPU and enabling unified processing and analysis of performance monitoring results from multiple DDRs to adjust the performance of the entire DDR subsystem. Other subsystems only need a single set of bus signals to interact with each DDR chip, and the bus matrix ensures that external subsystems can access different DDRs according to their actual needs.

[0049] Based on the same inventive concept, this application also provides a chip verification method applied to the aforementioned chip. The solution provided by this chip verification method is similar to the implementation scheme described in the aforementioned chip; therefore, the specific limitations in one or more chip verification method embodiments provided below can be found in the chip limitations described above, and will not be repeated here.

[0050] The chip verification method provided in this application can be applied to, for example... Figure 5 The application environment shown includes at least chip 101 and verification device 502.

[0051] The chip 101 is used to receive the first verification stimulus sent by the verification device through the bus module, and transmit the first verification stimulus to each cache module through the bus module. Each cache module responds to the first verification stimulus to obtain the first response data corresponding to each cache module.

[0052] Verification device 502 can be used to send verification stimuli to chip 101 and obtain the chip's response data. Verification device 502 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, drones, low-altitude aircraft, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, projection devices, etc. Portable wearable devices can include smartwatches, smart bracelets, head-mounted devices, etc. Head-mounted devices can be virtual reality (VR) devices, augmented reality (AR) devices, smart glasses, etc. Verification device 502 can also be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services.

[0053] In real-world scenarios, traditional verification environments are only suitable for verifying single DDR subsystems. They are ill-suited for verifying clock, bus, system security, power management, and performance monitoring modules within the SoC process, and verification is impossible in these areas. Furthermore, repeatedly building multiple separate environments is unsuitable for verification scenarios where multiple DDRs operate simultaneously, making it difficult to ensure sufficient verification. Moreover, building repetitive environments significantly reduces verification efficiency and increases the need for writing repetitive verification code.

[0054] Traditionally, subsystem verification for DDR0 to DDRX has been based on independent DDR architectures. Figure 2 Each DDR chip requires a separate UVM verification environment and its own chip model (DRAM_WRAP0~X). For LPC, DFS, CLK, PTM, etc. in the DDR subsystem, separate testbench (test platform layer), environment (verification environment), agent (verification component layer), and driver (stimulus driver module) need to be set up. This requires verification personnel to set up more than 4X sets of environments, which requires a huge workload (testbench, environment, agent, driver, dram_wrap, etc. are repeatedly instantiated, 4X is a simple example). This greatly affects the verification efficiency and makes it difficult to construct collaborative verification scenarios such as multiple DDR buses and low power consumption. It is also difficult to simulate the real chip working behavior, resulting in missing verification scenarios and risks of problems after the chip is returned.

[0055] To address this, this application establishes a cyclical and reusable verification architecture that centralizes the verification of each DDR subsystem in one place, performs verification of each DDR subsystem simultaneously, and obtains verification results, which greatly reduces redundant components and improves the utilization rate of chip verification resources.

[0056] In one exemplary embodiment, such as Figure 6 As shown, a chip verification method is provided, which is applied to... Figure 5 The chip in the process includes the following steps 601 and 602.

[0057] Step 601: Receive the first verification stimulus sent by the verification device through the bus module, and transmit the first verification stimulus to each cache module through the bus module respectively.

[0058] During implementation, the chip receives the first verification stimulus sent by the verification device through the bus module, and transmits the first verification stimulus to each cache module through the bus module.

[0059] Verification stimuli are signals or data sequences applied to the inputs of the design under test (DUT) to drive circuit behavior and trigger specific functional paths. They can be categorized by function: Directed Stimulus, manually constructed for known scenarios to verify critical functions; Random Stimulus, randomly generated through constraints to cover more boundary and anomaly situations; and Scenario / protocol-based stimuli to simulate real system interactions (such as AXI and PCIe transactions) to ensure interface and protocol compliance. A reasonable combination of these stimuli can effectively improve functional coverage and defect detection rates.

[0060] Step 602: Obtain the first response data corresponding to each cache module by responding to the first verification stimulus.

[0061] In this application, each first response data determines the verification result of each cache module, and the verification result of each cache module is used to determine the verification result of the chip. In this application, response data refers to the output signal or internal state change generated by the design under test (DUT) after receiving verification stimuli. Based on the type of function, it can be divided into: Expected Response, predefined by the reference model or specification sheet, used for functional correctness comparison; Observed Response, i.e., the actual output of the DUT, used for automatic verification with expected results; and Coverage-oriented Response, whose triggered internal signals or states are used to update functional coverage and guide subsequent stimulus generation. Accurately capturing and analyzing responses is the core basis for judging whether a design conforms to specifications.

[0062] During implementation, the chip responds to the first verification stimulus through each cache module, obtaining the first response data corresponding to each cache module. Here, the verification device can actively collect the first response data of each cache module and compare it with the first reference response data to obtain the verification result.

[0063] For example, based on a multi-DDR subsystem architecture, a UVM component is built with a Testbench as the top layer, a Diver, a Monitor, a Reference model, and a Scorboard as verification modules. The Diver can issue corresponding stimuli to the entire subsystem's bus, LPC, PTM, DFS, and CLK. The Monitor monitors at the terminal of the corresponding component, and after detecting data, sends it to the Reference model and Scorboard for comparison and verification. In the DUT, multiple DDR chips are built into a DRAM_WRAP component, including DDR0 to DDRX within the wrapper. This architecture avoids the drawback of traditional architectures that require building UVM environments one by one for each DDR chip component and its modules, reducing the number of verification environments from 4X to 1, and enabling large-scale scenarios of multi-component, multi-module, and multi-chip collaborative verification. For example, scenarios where LPC stimuli are issued simultaneously to control the power-on and power-off of the DDR subsystem, and clock frequency switching stimuli are issued simultaneously to control the frequency switching of DDR0 to DDRX.

[0064] The specific verification process may include: mounting and instantiating UVM components to build drivers and monitors for DDR0~DDRX granular model environments; performing parallel initialization of DDR0~DDRX, performing ZQC verification, selecting an appropriate clock frequency for the DDR granular particles, and adjusting the clock sampling for DQ and DQS through register configuration; performing basic read / write verification after DDR initialization is completed to ensure that the granular particles can read and write normally; and verifying the bus, clock, reset, low power, and system security components of multiple DDRs. Since the verification environment includes DDR0~DDRX, it can meet the complex scenario of multiple DDRs working in parallel.

[0065] In the aforementioned chip verification method, the chip includes a bus module, a control and adjustment module, multiple data processing modules, and cache modules deployed adjacently in the same chip area. This reduces redundant bus deployments and improves the chip's bus resource utilization and area utilization. The bus module is connected to each data processing module and each cache module. The bus module is used to transmit data between the data processing modules and their corresponding cache modules, while the cache modules store the data transmitted by the data processing modules. The bus module centrally manages the bus resources of the cache modules. The control and adjustment module is connected to each cache module and is used for one or more of the following: adjusting the clock frequency of the cache modules, adjusting the power consumption of the cache modules, monitoring the performance of the cache modules, and setting a unified / identical control and adjustment module for multiple cache modules, further improving the chip's resource utilization. During the verification process, the bus module receives the first verification stimulus sent by the verification device and transmits the first verification stimulus to each cache module. Each cache module responds to the first verification stimulus, obtaining its corresponding first response data. By uniformly and simultaneously verifying multiple DDR subsystems, resource consumption is reduced, thereby improving resource utilization.

[0066] Based on the above exemplary embodiment, the following provides a chip verification method in one or more exemplary embodiments, which is applied to... Figure 5 Taking the chip in the example, the explanation includes the following:

[0067] In real-world scenarios, there are also situations where the control and adjustment module is verified simultaneously. A second verification stimulus can be sent to the control and adjustment module. In one optional implementation provided in this application, such as... Figure 7 As shown, the method further includes step 701:

[0068] Step 701: The control and adjustment module receives and responds to the second verification stimulus sent by the verification device to obtain the second response data corresponding to the control and adjustment module.

[0069] The second response data is used to determine the verification result of the control and adjustment module, and the verification result of the control and adjustment module is used to determine the verification result of the chip.

[0070] During implementation, the chip can receive and respond to the second verification stimulus sent by the verification device through the control and adjustment module, and obtain the second response data corresponding to the control and adjustment module.

[0071] One optional implementation method provided in this application verifies multiple control and adjustment modules simultaneously, thereby improving control efficiency and thus increasing the resource utilization rate of chip verification.

[0072] In real-world scenarios, there is also a process of first performing read / write verification on the cache module, i.e., the DDR subsystem; in one optional implementation provided in this application, such as Figure 8 As shown, steps 801 to 803 are included before step 601:

[0073] Step 801: Receive the read / write verification command sent by the verification device through the dynamic frequency adjustment module included in the control adjustment module.

[0074] During implementation, the verification device sends read / write verification commands to the chip; the chip receives the read / write verification commands sent by the verification device through the dynamic frequency adjustment module included in the control and adjustment module.

[0075] Step 802: The dynamic frequency adjustment module responds to the read / write verification command, configures the clock frequency of each cache module according to the reference clock frequency carried by the read / write verification command, and transmits the read / write verification command to each cache module respectively.

[0076] During implementation, the chip responds to read and write verification commands through a dynamic frequency adjustment module, configures the clock frequency of each cache module according to the reference clock frequency carried by the read and write verification command, and transmits the read and write verification command to each cache module respectively.

[0077] Step 803: Each cache module responds to the read / write verification command and performs read / write verification based on the reference clock frequency to obtain the read / write verification result.

[0078] During implementation, the chip responds to read / write verification commands through each cache module, performs read / write verification based on a reference clock frequency, and obtains the read / write verification result. The verification device reads the read / write verification result, and if the read / write verification result passes, executes steps 601 to 602. The read / write verification result is used to determine the chip's verification result.

[0079] One optional implementation method provided in this application is to first perform read and write verification of the DDR subsystem, so that the chip can be successfully verified, thereby improving the reliability of chip verification.

[0080] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0081] Based on the same inventive concept, this application also provides a chip verification apparatus for implementing the chip verification method described above. This apparatus can be applied to or integrated into a chip or chip module, for example. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more chip verification apparatus embodiments provided below can be found in the limitations of the chip verification method described above, and will not be repeated here.

[0082] In one exemplary embodiment, such as Figure 9 As shown, a chip verification device is provided, including: a first verification stimulus acquisition module 901 and a first response data acquisition module 902, wherein: the first verification stimulus acquisition module 901 is used to receive a first verification stimulus sent by a verification device through a bus module, and transmit the first verification stimulus to each cache module through the bus module respectively; the first response data acquisition module 902 is used to obtain first response data corresponding to each cache module by responding to the first verification stimulus through each cache module; wherein each first response data determines the verification result of each cache module, and the verification result of each cache module is used to determine the verification result of the chip.

[0083] In one embodiment, the apparatus further includes a second verification module, which is used to receive and respond to a second verification stimulus sent by the verification device through the control and adjustment module, and obtain second response data corresponding to the control and adjustment module.

[0084] In one embodiment, the device may further include a first unit, a second unit, and a third unit, wherein: the first unit is used to receive read / write verification instructions sent by the verification device through the dynamic frequency adjustment module included in the control adjustment module; the second unit is used to respond to the read / write verification instructions through the dynamic frequency adjustment module, configure the clock frequency of each cache module according to the reference clock frequency carried in the read / write verification instructions, and transmit the read / write verification instructions to each cache module respectively; the third unit is used to respond to the read / write verification instructions through each cache module, perform read / write verification based on the reference clock frequency, and obtain read / write verification results.

[0085] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0086] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 10As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores chip verification data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a chip verification method.

[0087] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0088] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the chip verification method described above.

[0089] Based on the same inventive concept, this application also provides a chip module, such as... Figure 11 As shown, the chip module includes a communication module, a power module, a storage module, and a chip. Specifically: the power module provides power to the chip module; the storage module stores data and instructions; the communication module enables internal communication within the chip module or communication between the chip module and external devices; and the chip corresponds to the chip in the aforementioned chip embodiment.

[0090] The implementation method of this chip module can be found in the relevant content of the above chip embodiment, and will not be repeated here.

[0091] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the chip verification method described above.

[0092] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the chip verification method described above.

[0093] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0094] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0095] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0096] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A chip, characterized in that, The chip includes a bus module, a control and adjustment module, multiple data processing modules, and a cache module corresponding to each of the data processing modules. The cache modules are deployed adjacent to each other in the same chip area of ​​the chip. The bus module is connected to each of the data processing modules respectively, and the bus module is also connected to each of the cache modules respectively. The bus module is used to transmit data between the data processing module and the corresponding cache module, and the cache module is used to store the data transmitted by the data processing module. The control and adjustment module is connected to each of the cache modules respectively, and the control and adjustment module is used for one or more of the following: adjusting the clock frequency of the cache module, adjusting the power consumption of the cache module, and monitoring the performance of the cache module.

2. The chip according to claim 1, characterized in that, The bus module includes a bus interface and a routing unit connected to the bus interface. The bus interface is connected to each of the data processing modules, and the routing unit is connected to each of the cache modules. The bus interface is used to receive data sent by each of the data processing modules; The routing unit is used to determine, for each data processing module, a target cache module that matches the data based on the identifier carried by the data, and then transmit the data to the target cache module.

3. The chip according to claim 1, characterized in that, The control and adjustment module includes at least one of a dynamic frequency adjustment module, a performance monitoring module, and a low-power control module. The dynamic frequency adjustment module is connected to each of the cache modules respectively, the performance monitoring module is connected to each of the cache modules respectively, and the low-power control module is connected to each of the cache modules respectively. The dynamic frequency adjustment module is used to adjust the clock frequency of the cache module, the performance monitoring module is used to monitor the performance of the cache module, and the low power control module is used to adjust the power of the cache module.

4. A chip module, characterized in that, Includes a communication module, a power module, a storage module, and the chip according to any one of claims 1-3, wherein: The power module is used to provide power to the chip module; The storage module is used to store data and instructions; The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices.

5. A chip verification method, characterized in that, Applied to the chip according to any one of claims 1-3, the method includes: The bus module receives the first verification incentive sent by the verification device and transmits the first verification incentive to each of the cache modules respectively through the bus module. By responding to the first verification stimulus by each of the aforementioned cache modules, the first response data corresponding to each of the aforementioned cache modules is obtained; The first response data determines the verification result of each cache module, and the verification result of each cache module is used to determine the verification result of the chip.

6. The method according to claim 5, characterized in that, The method further includes: The control and adjustment module receives and responds to the second verification stimulus sent by the verification device to obtain the second response data corresponding to the control and adjustment module. The second response data is used to determine the verification result of the control and adjustment module, and the verification result of the control and adjustment module is used to determine the verification result of the chip.

7. The method according to claim 5, characterized in that, The method further includes: The control and adjustment module includes a dynamic frequency adjustment module that receives read / write verification commands sent by the verification device. The dynamic frequency adjustment module responds to the read / write verification command, configures the clock frequency of each cache module according to the reference clock frequency carried by the read / write verification command, and transmits the read / write verification command to each cache module respectively. Each of the cache modules responds to the read / write verification command and performs read / write verification based on the reference clock frequency to obtain the read / write verification result, which is used to determine the verification result of the chip.

8. A chip verification device, characterized in that, The device includes: The first verification incentive acquisition module is used to receive the first verification incentive sent by the verification device through the bus module, and to transmit the first verification incentive to each cache module through the bus module respectively. The first response data acquisition module is used to obtain the first response data corresponding to each of the cache modules by responding to the first verification stimulus through each of the cache modules; The first response data determines the verification result of each cache module, and the verification result of each cache module is used to determine the verification result of the chip.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 5 to 7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 5 to 7.

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