A deep learning-based integrated circuit pre-wiring timing prediction method and device

Abstract

This invention discloses a deep learning-based method and apparatus for timing prediction before routing of integrated circuits. The method includes: converting the netlist of the circuit to be predicted into a first graph representation for a Graph Transformer and a second graph representation for a GNN model, and obtaining the layout features of the predicted circuit; inputting the first graph representation, the second graph representation, and the layout features into a trained timing prediction model to obtain the predicted arrival times of the timing endpoints of the circuit to be predicted; wherein the timing prediction model includes an autoencoder, a U-Net network, a GNN model, and an MLP. This invention employs a dual-branch structure to capture the global netlist topology, local circuit, and layout features of the circuit to be predicted, ensuring that structural and spatial factors are considered simultaneously during timing propagation, thereby enabling the prediction of the arrival times of timing endpoints.

Description

Technical Field

[0001] This invention belongs to the field of electronic design automation, and specifically relates to a method and apparatus for timing prediction before routing of integrated circuits based on deep learning. Background Technology

[0002] In the physical design flow of Very Large Scale Integration (VLSI) circuits, timing convergence is crucial for ensuring chip performance. Traditional timing analysis methods require accurate interconnect parasitic parameters and are therefore typically performed after routing. However, routing itself is very time-consuming, and if timing violations are found, repeated placement and routing iterations are necessary for optimization, significantly extending the design cycle. Given the powerful fitting capabilities of neural networks in numerous applications, applying deep learning techniques for timing prediction has become a new research hotspot. Rapidly and accurately predicting post-routing timing metrics before routing is of great significance for improving chip design convergence efficiency.

[0003] With breakthroughs in advanced technology nodes, chip design scale is growing exponentially, drastically increasing the difficulty and time cost of timing convergence iterations. Placement assigns locations to components, while routing obtains precise interconnections between pins, requiring repeated placement and routing to meet timing constraints. Timing prediction based on placement results can guide timing optimization in advance, saving routing runtime. After placement, since actual routing has not yet been performed, the resistance and capacitance (RC) parameters of the interconnects are unknown, making accurate timing analysis impossible. To assess design quality during the placement phase, Static Timing Analysis (STA) typically uses line length models (such as half-circuit line length) for rough estimation, but this deviates significantly from the actual timing after final routing. Furthermore, performing timing optimization techniques is a necessary step to meet timing constraints, including gate size adjustment, netlist reconstruction, and buffer insertion. These techniques improve timing by adjusting the netlist without changing circuit functionality, but also lead to inaccurate timing predictions. In recent years, Graph Neural Networks (GNNs) have been widely used in the field of Electronic Design Automation (EDA) because of their ability to handle non-Euclidean data. Significant progress has been made in building pre-wiring timing prediction models based on GNNs.

[0004] Existing pre-routing timing prediction methods fail to adequately consider the changes to the netlist structure caused by timing optimization, leading to a mismatch between the prediction model and the optimized actual circuit. Furthermore, most methods focus on local circuit characteristics, lacking awareness of global netlist topology information; signal attenuation and error accumulation along long paths severely impact prediction accuracy. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a method and apparatus for timing prediction before wiring of integrated circuits based on deep learning.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a deep learning-based method for timing prediction before wiring in integrated circuits, the method comprising: The netlist of the circuit to be predicted is converted into a first graph representation for a graph Transformer and a second graph representation for a GNN model, respectively, and the layout features of the predicted circuit are obtained. The first graph representation, the second graph representation, and the layout features are input into a trained temporal prediction model to obtain the predicted arrival time of the temporal endpoints of the circuit to be predicted. The temporal prediction model includes an autoencoder, a U-Net network, a GNN model, and an MLP. The encoder in the autoencoder is constructed based on a multi-layer graph Transformer with linear attention. The encoder is used to extract a global topological embedding based on the first graph representation. The U-Net network is used to extract multi-scale layout features based on the layout features. The GNN model is used to concatenate the multi-scale layout features and the second graph representation to obtain a local multimodal embedding. The MLP is used to map the concatenated result of the global topological embedding and the local multimodal embedding to obtain the predicted arrival time of the temporal endpoints.

[0007] Optionally, the operation of the encoder includes: Input the subgraph represented by the first graph into the feature embedding module to obtain the edge embedding as well as the same first branch node embedding, second branch node embedding and third branch node embedding; After embedding the second branch node into the input attention layer, it passes through the first linear layer, activation function layer, second linear layer, linear attention operation, dot product operation, and third linear layer in sequence, and is then summed with the first branch node embedding and subjected to layer normalization to obtain the global node features. The third branch node embedding and the edge embedding are input into the MPNN layer to obtain local node features and input edge features; After splicing the global node features and local node features, the same first splicing feature and second splicing feature are obtained; The first spliced ​​feature is input into the MLP and then residually connected with the second spliced ​​feature. After summation and layer normalization, the input node features are obtained. The global topology embedding is obtained by passing the input edge features and the input node features through a multi-layer graph Transformer.

[0008] Optionally, the autoencoder undergoes self-supervised training using a first loss function; the first loss function is expressed as follows: ; in, This represents the first loss function. This represents the mean squared error loss function. This represents the node features in the first graph representation. Indicates decoder, Indicates encoder, This represents the subgraph represented by the first training graph.

[0009] Optionally, the operation of the U-Net network includes: The layout features are input into a convolutional layer, then into a max pooling layer, and then into another convolutional layer to obtain downsampled features; The layout features are input into a convolutional layer and then into a max pooling layer, then into another convolutional layer and then into a max pooling layer, then through a convolutional layer and an upsampling layer in sequence, and then connected to the downsampling features in a skip connection, and then through a convolutional layer and an upsampling layer in sequence to obtain the upsampling features. The layout features are input into the convolutional layer and then connected to the upsampled features in a skip connection to obtain the spliced ​​features. The spliced ​​features are input into the convolutional layer to obtain the multi-scale layout features.

[0010] Optionally, the operation of the GNN model includes: The original position coordinates of each node are obtained according to the second diagram; The original position coordinates of each node are mapped to the corresponding position of the multi-scale layout feature, and the multi-scale layout feature at the corresponding position is concatenated with the node feature in the second graph representation to obtain the concatenated node feature; wherein, the node feature includes unit node feature and line node feature; A message passing function is constructed based on the node features in the second graph representation and the spliced ​​node features to model the time-series propagation process.

[0011] Optionally, the message passing function includes a first message passing subfunction, which is represented as follows: ; in, This represents the first message passing subfunction of the cell node. This represents a multilayer perceptron. Represents a cell node. This represents the timing information from the previous thread node. This represents the original features of the unit nodes in the second diagram. This represents the first message passing subfunction of the line node. Represents a line node. This represents the timing information from the previous unit node. The second diagram shows the original features of the midline node.

[0012] Optionally, the message passing function further includes a second message passing subfunction, which is represented as follows: ; in, This indicates the updated node timing information via the second message passing subfunction. The second graph represents the netlist characteristics of nodes after being updated by the first message passing subfunction of different nodes. This represents the layout features of nodes in a multi-scale layout feature. This is the ReLU activation function.

[0013] Secondly, the present invention provides a deep learning-based integrated circuit pre-routing timing prediction device, the device comprising: The conversion module is used to convert the netlist of the circuit to be predicted into a first graph representation for a graph Transformer and a second graph representation for a GNN model, respectively, and to obtain the layout features of the predicted circuit. A prediction module is used to input the first graph representation, the second graph representation, and the layout features into a trained temporal prediction model to obtain the predicted arrival time of the temporal endpoints of the circuit to be predicted. The temporal prediction model includes an autoencoder, a U-Net network, a GNN model, and an MLP. The encoder in the autoencoder is constructed based on a multi-layer graph Transformer with linear attention. The encoder is used to extract a global topological embedding based on the first graph representation. The U-Net network is used to extract multi-scale layout features based on the layout features. The GNN model is used to concatenate the multi-scale layout features and the second graph representation to obtain a local multimodal embedding. The MLP is used to map the concatenated result of the global topological embedding and the local multimodal embedding to obtain the predicted arrival time of the temporal endpoints.

[0014] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects: In the above technical solution, the present invention adopts a dual-branch structure to capture the global netlist topology, local circuit and layout features of the circuit to be predicted. One branch is a linear complexity graph Transformer, which is used to encode global endpoint embeddings and expand the receptive field of the model. The other branch is a customized GNN and U-Net, which are used to propagate multimodal features including netlist and layout information. The layout features are extracted by U-Net and fused into the graph representation of the netlist based on spatial alignment, ensuring that structural and spatial factors are considered simultaneously during the time-series propagation process, thereby predicting the arrival time of the time-series endpoints.

[0015] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0016] Figure 1 This is a flowchart of a deep learning-based integrated circuit pre-routing timing prediction method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram representing an embodiment of the present invention; Figure 3 This is an overall architecture diagram of a time series prediction model provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a self-encoder provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of a U-Net network provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a GNN model provided in an embodiment of the present invention; Figure 7 This is a block diagram of a deep learning-based integrated circuit pre-routing timing prediction device provided in an embodiment of the present invention. Detailed Implementation

[0017] To facilitate understanding of the present invention, a brief description of the prior art and the inventive concept of the present invention will be provided first.

[0018] Existing solutions primarily employ a time-propagation-based GNN model, inspired by the STA (Signal-Side Array) process. Following the circuit's topological order, it models the netlist as a graph structure of nodes and edges for message passing, simulating the propagation of circuit signals from input to output. Other solutions predict endpoint timing through multimodal fusion, simultaneously considering circuit layout and the netlist. They extract and fuse relevant features by constructing Convolutional Neural Networks (CNNs) and GNNs respectively, using the fused features to predict the timing-optimized endpoint arrival time.

[0019] Existing pre-routing timing prediction models primarily consider local netlist features, lacking a global representation of the netlist topology. Since endpoint arrival times are influenced by the entire fan-in cone, the receptive field size varies from tens to thousands of pins. Using a local receptive field fails to capture the global netlist topology that affects timing optimization behavior, leading to severe signal attenuation and error accumulation on long paths, thus limiting prediction accuracy. Furthermore, previous models constructed netlist and layout feature embeddings independently during feature fusion, failing to reflect the mutual influence of netlist and layout on latency, lacking fine-grained interaction modeling of topology and geometric features, and exhibiting insufficient robustness to structural changes brought about by timing optimization. Therefore, this invention proposes a deep learning-based pre-routing timing prediction method for integrated circuits to address these technical problems.

[0020] Figure 1 This is a flowchart of a deep learning-based integrated circuit pre-routing timing prediction method provided by an embodiment of the present invention, as shown below. Figure 1 As shown, the method may include the following steps: S101. Convert the netlist of the circuit to be predicted into a first graph representation for graph Transformer and a second graph representation for GNN model, respectively, and obtain the layout features of the predicted circuit.

[0021] Understandably, for the netlist of the circuit to be predicted, the circuit elements and their connections are modeled as a connection graph consisting of nodes and edges, and the modeling rules are adjusted according to different application scenarios. Figure 2 This is a schematic diagram representing an embodiment of the present invention. Figure 2 The left side shows the netlist of the circuit to be predicted, and the right side shows the conversion of the netlist into the first graph representation corresponding to the graph Transformer branch and the second graph representation corresponding to the layer-by-layer GNN branch. The dashed circles indicate the equivalent conversion between the two graph structures. Figure 2 The upper right part shows the first diagram, which represents the output pin of a circuit element as a cell node in the diagram during modeling, and the input pin of the element and the connection relationship of the input pin (the output pin from the previous circuit element points to the input pin of the current circuit element, and the input pin from the current circuit element points to the output pin of the current element) are represented as directed edges. Under this modeling rule, the entire netlist contains only a single type of node and edge, and is constructed as an isomorphic directed acyclic graph. Figure 2The lower right part shows the second diagram, where the input and output pins of the circuit elements are modeled as nodes, with the input pins called line nodes and the output pins called cell nodes. Two different types of edges are constructed according to the connection direction, where the edge from the input pin of the current circuit element to the output pin is called a cell edge, and the edge from the output pin of the current element to the input pin of the next element is called a line edge. The netlist is modeled as a heterogeneous directed acyclic graph with two node types and two edge types.

[0022] It's worth noting that the first and second graph representations are structurally equivalent. The dashed circles represent directed edges in the first graph representation, which are equivalent to line nodes and their connected incoming and outgoing edges in the second graph representation. In the first graph representation, both cell nodes and edges have features, while in the second graph representation, only cell nodes and line nodes have features; cell edges and line edges only represent connectivity and do not have features. Taking the second graph representation as an example, the original features of a node are explained. A cell node includes three features: gate type, cell drive strength, and pin capacitance. Gate type represents the logic gate type, such as AND, OR, or NOT gates, represented using one-hot encoding; cell drive strength represents the driving capability of the output pin of a standard cell to drive the connected load; and pin capacitance represents the pin capacitance value of a standard cell. A line node includes one feature: line distance, representing the Manhattan distance between the two pins connected by a line network. Since the Graph Transformer is used to extract global topology information, a homogeneous graph is used to represent the topology. Compared to heterogeneous graphs, homogeneous graphs have fewer nodes and edges, effectively alleviating memory consumption in large-scale graph structures. For layer-wise GNN models, the delay propagation mechanisms in cells and nets are different, so heterogeneous graphs with explicit representations of cells and nets should be used.

[0023] Considering that each timing endpoint is only affected by the circuit cells and nets in its fan-in cone, but the Graph Transformer captures global information from the input netlist, and the first graph representation used by the Graph Transformer represents all components and connections of the complete circuit, it is necessary to further extract relevant local subgraphs on this graph structure to limit the receptive field of the Graph Transformer to the fan-in cone of the current timing endpoint. Starting from each timing endpoint, a backward Breadth First Search (BFS) is performed to iteratively explore all upstream nodes until all relevant input nodes are reached. The resulting subgraph can capture the complete fan-in cone, ensuring that it contains all path information related to the timing endpoint.

[0024] For layout features, original features highly relevant to timing optimization and routing are selected, including three types: cell density map, rectangular uniform wire density (RUDY), and macrocell region map. The cell density map represents the distribution density of standard cells within the mesh; RUDY represents the wire density and congestion level within each mesh; and the macrocell region map represents the layout area occupied by macrocells with fixed internal structures. The layout area is divided into 512*512 meshes, and the corresponding feature images are extracted and stacked into a 3*512*512 format to serve as the input feature map for the U-Net network.

[0025] S102. Input the first graph representation, the second graph representation, and the layout features into the trained timing prediction model to obtain the predicted arrival time of the timing endpoints of the circuit to be predicted. The timing prediction model includes an autoencoder, a U-Net network, a GNN model, and an MLP. The encoder in the autoencoder is constructed based on a graph Transformer with linear attention. The encoder is used to extract the global topology embedding based on the first graph representation. The U-Net network is used to extract multi-scale layout features based on the layout features. The GNN model is used to concatenate the multi-scale layout features and the second graph representation to obtain the local multimodal embedding. The MLP is used to map the concatenation result of the global topology embedding and the local multimodal embedding to obtain the predicted arrival time of the timing endpoints.

[0026] Optionally, Figure 3 This is an overall architecture diagram of a time series prediction model provided in an embodiment of the present invention. The encoder operation process includes: Input the subgraph represented by the first graph into the feature embedding module to obtain the edge embedding as well as the same first branch node embedding, second branch node embedding and third branch node embedding; After embedding the second branch node into the input attention layer, it passes through the first linear layer, activation function layer, second linear layer, linear attention operation, dot product operation, and third linear layer in sequence, and is then summed with the first branch node embedding and subjected to layer normalization to obtain the global node features. The third branch node embedding and edge embedding are input into the MPNN layer to obtain local node features and input edge features; After splicing the global node features and local node features, the same first spliced ​​feature and second spliced ​​feature are obtained; The first spliced ​​feature is input into the MLP and then residually connected with the second spliced ​​feature. After summation and layer normalization, the input node features are obtained. The global topological embedding is obtained by passing the input edge features and input node features through a multi-layer graph Transformer.

[0027] Understandably, applying global attention in a standard Transformer would lead to... Computational complexity limits the application of Graph Transformer to small graphs with only a few hundred nodes. However, the number of upstream nodes in a subgraph can vary from tens to tens of thousands, leading to unacceptable GPU memory consumption. To ensure the scalability of Graph Transformer, the GraphGPS framework is used as the basic model architecture, and Mamba-inspired linear attention is integrated to achieve efficient modeling of large graphs. Figure 4 This is a schematic diagram of the structure of a self-encoder provided in an embodiment of the present invention, wherein, Figure 4 The upper part shows the designed autoencoder architecture, where the encoder encodes the node features of the input netlist into a d-dimensional latent space, uses linear attention to capture the latent global netlist topology, and then the decoder restores the features. Figure 4 The lower half shows the core encoder structure; the lower left shows the detailed structure of the attention layer, and the lower right shows the overall encoder structure. and The first The initial input to the layer consists of node features and edge features. First, there's the feature embedding module, which takes node features as input. Node embedding is performed through a linear layer, and the node position encoding is summed. The updated node features can be divided into identical first-branch node embeddings, second-branch node embeddings, and third-branch node embeddings. One branch is used as a residual connection and summed with the output of the attention layer for layer normalization; another branch is used as the input to the attention layer; and the third branch is used as the input node features to the message-passing neural network. (Edge features) Edge embedding is performed through a linear layer, directly serving as the input edge features for the MPNN layer. The attention layer and MPNN layer are the core components; the attention layer captures global dependencies between node features, and the MPNN layer aggregates information from neighboring nodes and edges. The detailed structure of the attention layer is shown below. Figure 4 As shown in the lower left, the input node features are divided into the same first-branch concatenated features and second-branch concatenated features, each of which passes through a linear layer and is activated. One branch is used for calculating the attention score. (Quary) and (Key) is obtained by projection through a linear layer. (Value) is directly the activated value; the calculation of linear attention is described later. The other branch is used to perform a dot product with the calculated attention score, which is then passed through a linear layer to obtain the output of the attention layer. The output of the attention layer is summed with the input of the attention layer and then normalized to obtain the result. Indicates that it will be used for the first The MPNN layer uses global node features obtained from the attention layer. It employs the standard GatedGCN network to aggregate and update local node and edge features, outputting... Indicates that it will be used for the first The local node features obtained from the MPNN layer of the layer, Indicates direct use for the first Input edge features of the layer. In a feedforward neural network, global node features are... With local node features The concatenated features are input into the MLP, and the other feature is residually connected to the MLP output. After summation and layer normalization, the result is... As the first Features of the input nodes of the layer.

[0028] The following is a detailed description of each part.

[0029] The feature embedding module first projects node and edge features into a d-dimensional embedding. Then, it uses the topological level and in-degree / out-degree of each node as positional encodings, incorporating them into the initial node embedding to reflect the timing propagation characteristics of the circuit. The feature embedding consists of multiple linear layers: the linear layer for node features has an input dimension of 36 and an output dimension of 8; the linear layer for edge features has an input dimension of 2 and an output dimension of 8; the linear layer for topological levels has an input dimension of 1 and an output dimension of 8; and the linear layer for in-degree / out-degree has an input dimension of 2 and an output dimension of 8. The projected topological level and in-degree / out-degree features are then added to the node features as input to the subsequent model.

[0030] The linear attention mechanism replaces the nonlinear Softmax function with linear normalization and provides a query ( ) and Key( The matrix introduces a kernel function mapping, utilizing the associativity of matrix multiplication to shift attention computation from... Transform into Reduce the complexity to However, previous research has shown that linear attention lacks expressive power, limiting its practical applications. Recent studies have revealed structural similarities between linear Transformer and Mamba models. By replacing the forget gate with positional encoding to provide local bias and positional information to the model, and by replacing the attention block design with a Mamba block design, the performance of linear Transformer can be significantly improved. Inspired by this, the standard attention module in the GraphGPS framework is replaced with a Mamba-inspired linear attention (…). Figure 4 (Lower left section) The nodes in each subgraph are converted into a sequence for attention computation, and edge features are extracted as local information by the MPNN layer. This combination strategy reduces memory consumption, enabling the model to handle subgraphs with tens of thousands of nodes.

[0031] The specific definition of linear attention is as follows: ; ; in, Indicates input features, The kernel function is represented by the ELU activation function. Represents the Quary matrix. Represents the Key matrix. Represents the Value matrix. express The weight matrix, express The weight matrix, express The weight matrix, The calculated attention score represents the current node. With all other nodes ( The degree of importance between ) Indicates the current node, Indicates other nodes, This indicates the transpose operation.

[0032] Example, Figure 4 The specific parameters of the linear attention layer in the lower left part are defined as follows: the input dimension of all linear layers is 8, the output dimension is 8, the first activation function is SiLU, the number of attention heads is 2, the kernel function in the attention calculation is ELU, and the residual connection is the dot product of the attention score and the activated input feature.

[0033] The MPNN module models the local neighborhood of each node, employing the standard GatedGCN network to perform weighted aggregation of neighboring nodes and edge features. It has an input dimension of 8, an output dimension of 8, and a Dropout value of 0.1. When the local MPNN encodes edge features into the node-level hidden representation, the global linear attention implicitly utilizes this information to update the node representation without explicitly injecting edge features during attention computation, further reducing memory consumption while preserving edge features.

[0034] The entire graph Transformer layer consists of three stacked layers. First, a feature embedding module projects node and edge features. Then, three graph Transformer layers extract global features. Edge features are directly used in the next layer after passing through the MPNN layer, while node features are updated jointly by the linear attention layer and the MPNN layer. After the attention layer output, the features are summed, residually connected, and normalized. This summation is then concatenated with the node features output from the MPNN layer and fed into a feedforward neural network. After passing through an MLP, residual connections and normalization are performed, and the output node features are used as input for the next layer.

[0035] The graph Transformer described above can be directly used to extract global netlist topology information. However, early experiments revealed that two branches with different graph data resulted in very long training times per round. The upper branch uses a subgraph, while the lower branch uses a complete graph containing all nodes and edges. This significant difference in data granularity led to batch imbalance in the training data for the two branches, significantly increasing training time. Therefore, the upper branch was constructed as an autoencoder to separate the training of the two branches, allowing the graph Transformer to be pre-trained independently. During the pre-training of the autoencoder, the encoder learns latent node representations through global linear attention and a local MPNN, while the decoder uses a lightweight MLP to reconstruct the original node features. The input dimension is 8, the output dimension is 36, and the activation function is GELU. The autoencoder undergoes self-supervised training using a first loss function, which is expressed as follows: ; in, Denotes the first loss function. This represents the mean squared error loss function. This represents the node features in the first graph representation. Indicates decoder, Indicates encoder, This represents the subgraph represented by the first training graph. After the autoencoder is trained, its parameters are frozen for use in subsequent downstream tasks to capture global netlist topology information.

[0036] Optionally, the operation of the U-Net network includes: The layout features are input into the convolutional layer, then into the max pooling layer, and then into the convolutional layer again to obtain the downsampled features; The layout features are input into a convolutional layer, then into a max pooling layer, then into another convolutional layer, then into another max pooling layer, then through a convolutional layer and an upsampling layer in sequence, and then connected to the downsampling features in a skip connection, and then through a convolutional layer and an upsampling layer in sequence to obtain the upsampling features. The layout features are input into the convolutional layer and then skipped over the upsampled features to obtain the concatenated features. The spliced ​​features are input into the convolutional layer to obtain multi-scale layout features.

[0037] Understandably, in order to construct a layer-by-layer GNN time-series propagation model that integrates layout features, the U-Net network must first extract the multi-scale spatial features of the layout. Figure 5 This is a schematic diagram of the structure of a U-Net network provided in an embodiment of the present invention, as shown below. Figure 5As shown, the input on the left is the original layout feature, and the output on the right is the multi-scale layout feature extracted by the network, containing two downsampled blocks and two upsampled blocks. The input layout feature size is 3*512*512, and the output multi-scale layout feature size is 32*512*512. The encoder consists of multiple 3*3 convolutional layers and 2*2 max-pooling layers. The convolutional layer padding is 1, the activation function is ReLU, and the number of channels is as follows. Figure 5 As shown in the diagram, they progressively extract spatial features while reducing the feature map size. After two downsampling blocks, the feature map size is reduced to 1 / 4 of its original size. Then, the decoder upsamples using transposed convolutions with a kernel size of 2 and a stride of 2, followed by decoding through 3x3 convolutional layers and a ReLU activation function, and then fuses them with the corresponding encoder output via skip connections. This multi-scale layout feature map is then integrated into the GNN module to model temporal propagation together under layout constraints.

[0038] Optionally, the operation of the GNN model includes: The original position coordinates of each node are obtained according to the second figure; The original position coordinates of each node are mapped to the corresponding position of the multi-scale layout feature, and the multi-scale layout feature at the corresponding position is concatenated with the node feature in the second graph representation to obtain the concatenated node feature; wherein, the node feature includes cell node feature and line node feature. Based on the node features in the second diagram and the spliced ​​node features, a message passing function is constructed to model the time-series propagation process.

[0039] Understandably, GNNs are suitable for handling non-Euclidean graph structures through message passing and neighbor aggregation. For time series prediction, nodes are sorted according to topological hierarchy, and GNNs are used to propagate netlist information with relevant layout characteristics. The message passing process strictly follows the topological order, mimicking the working principle of static time series analysis engines by passing messages layer by layer. Figure 6This is a schematic diagram of a GNN model provided in an embodiment of the present invention. To utilize the multi-scale layout features extracted by the U-Net network, the original position coordinates of each node need to be extracted and mapped to the corresponding position on the layout grid. The layout features at this position are then concatenated with the node features, and the fused node features are used in the message passing process of the GNN, enabling the model to implicitly learn layout information during time propagation. The heterogeneous graph with two edge types and two node types extracted above is used to model the time propagation process. Different message passing functions are used for different node types, thereby modeling two different types of time arcs in the time engine. Message passing starts from the node at topology level 0, and the corresponding message passing function is applied according to the edge type. Since operations are only performed on nodes at the current topology level, the model has low memory consumption and can be efficiently parallelized. The message passing function includes a first message passing subfunction, which is represented as follows: ; in, This represents the first message passing subfunction of the cell node. This represents a multilayer perceptron. Represents a cell node. This represents the timing information from the previous thread node. This represents the original features of the unit nodes in the second diagram. This represents the first message passing subfunction of the line node. Represents a line node. This represents the timing information from the previous unit node. The second diagram shows the original features of the midline node.

[0040] The message passing function also includes a second message passing subfunction, which is represented as follows: ; in, This indicates the updated node timing information via the second message passing subfunction. The second graph represents the netlist characteristics of nodes after being updated by the first message passing subfunction of different nodes. This represents the layout features of nodes in a multi-scale layout feature. This is the ReLU activation function.

[0041] For a cell node, a cell edge connects a line node (source node) to a cell node (target node), representing a connection from an input pin to an output pin of the same element. Since a single element can have multiple input pins, this constitutes a many-to-one relationship. Because the output delay is typically controlled by the slowest input signal in the actual circuit, maximum aggregation is used for the message passing function. The feature embedding of a unit node is formed by fusing the input signal with the greatest delay with its own unit node features. The input dimension is 128, and the output dimension is 128. The input dimension is 36, and the output dimension is 128. For line nodes, line edges connect cell nodes (source nodes) to line nodes (target nodes), representing connections between different component pins, forming a one-to-one relationship. Line node embedding is calculated by combining timing information from its predecessor node with its own line node characteristics. The input dimension is 2, and the output dimension is 128. After the neighbor aggregation of the node's own features is completed, the output is... This is used to concatenate netlist features and layout features, with an input dimension of 160 and an output dimension of 128. The updated node messages are then passed to subsequent nodes. The dimensions of the intermediate hidden layers are all 256, and the activation function is ReLU. Figure 6 The left side shows the multi-scale layout features, and the right side is the second diagram. A solid black arrow on each side indicates feature fusion. The fused features are pointed back to the same node in the netlist by a dashed red arrow, corresponding to the formula... The merged features are used for message passing.

[0042] It's worth noting that the global topological embedding extracted from the trained encoder is concatenated with the local multimodal embeddings obtained after propagation by the GNN model. This concatenation is then mapped to the predicted arrival times of temporal endpoints using an MLP (Multi-Level Processing). This MLP has an input dimension of 136, an output dimension of 1, a hidden layer dimension of 272, and uses ReLU as the activation function. The model is then trained using the mean squared error (MSE) between the predicted and actual values ​​as the loss function, employing the Adam optimizer with a learning rate of 0.001. The model performance is evaluated using the coefficient of determination (R²). After training, the predicted arrival times of each temporal endpoint can be output after layout completion, guiding layout optimization and temporal convergence.

[0043] This invention designs two equivalent graph structures when constructing the dataset. Different graph sizes and types are suitable for corresponding model architectures, which helps reduce memory consumption and improve model training performance. A dual-branch architecture is constructed to extract global and local information, and a linear attention mechanism suitable for large-scale graphs is designed to capture global topological information of the netlist, mitigating the impact of long-path signal attenuation. An autoencoder structure is used to train two branches with different input data granularities separately, which facilitates the convergence of the actual model. The multi-scale layout features extracted by U-Net are integrated into the layer-by-layer GNN temporal propagation model, while modeling the impact of layout and netlist information on temporal sequence, enhancing the model's expressive power and interpretability.

[0044] Figure 7This is a block diagram of a deep learning-based integrated circuit pre-routing timing prediction device provided in an embodiment of the present invention, as shown below. Figure 7 As shown, the device 700 may include: The conversion module 701 is used to convert the netlist of the circuit to be predicted into a first graph representation for graph Transformer and a second graph representation for GNN model, respectively, and to obtain the layout features of the predicted circuit. The prediction module 702 is used to input the first graph representation, the second graph representation, and the layout features into the trained temporal prediction model to obtain the predicted arrival time of the timing endpoints of the circuit to be predicted. The temporal prediction model includes an autoencoder, a U-Net network, a GNN model, and an MLP. The encoder in the autoencoder is constructed based on a graph Transformer with linear attention. The encoder is used to extract the global topology embedding based on the first graph representation. The U-Net network is used to extract multi-scale layout features based on the layout features. The GNN model is used to concatenate the multi-scale layout features and the second graph representation to obtain the local multimodal embedding. The MLP is used to map the concatenated result of the global topology embedding and the local multimodal embedding to obtain the predicted arrival time of the timing endpoints.

[0045] It is understood that the device embodiments are basically similar to the method embodiments, so the description is relatively simple, and relevant parts can be referred to in the description of the method embodiments.

[0046] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0047] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0048] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0049] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A deep learning-based method for timing prediction before integrated circuit routing, characterized in that, The method includes: The netlist of the circuit to be predicted is converted into a first graph representation for a graph Transformer and a second graph representation for a GNN model, respectively, and the layout features of the predicted circuit are obtained. The first graph representation, the second graph representation, and the layout features are input into a trained temporal prediction model to obtain the predicted arrival time of the temporal endpoints of the circuit to be predicted. The temporal prediction model includes an autoencoder, a U-Net network, a GNN model, and an MLP. The encoder in the autoencoder is constructed based on a multi-layer graph Transformer with linear attention. The encoder is used to extract a global topological embedding based on the first graph representation. The U-Net network is used to extract multi-scale layout features based on the layout features. The GNN model is used to concatenate the multi-scale layout features and the second graph representation to obtain a local multimodal embedding. The MLP is used to map the concatenated result of the global topological embedding and the local multimodal embedding to obtain the predicted arrival time of the temporal endpoints.

2. The deep learning-based integrated circuit pre-routing timing prediction method according to claim 1, characterized in that, The operation of the encoder includes: Input the subgraph represented by the first graph into the feature embedding module to obtain the edge embedding as well as the same first branch node embedding, second branch node embedding and third branch node embedding; After embedding the second branch node into the input attention layer, it passes through the first linear layer, activation function layer, second linear layer, linear attention operation, dot product operation, and third linear layer in sequence, and is then summed with the first branch node embedding and subjected to layer normalization to obtain the global node features. The third branch node embedding and the edge embedding are input into the MPNN layer to obtain local node features and input edge features; After splicing the global node features and local node features, the same first splicing feature and second splicing feature are obtained; The first spliced ​​feature is input into the MLP and then residually connected with the second spliced ​​feature. After summation and layer normalization, the input node features are obtained. The global topology embedding is obtained by passing the input edge features and the input node features through a multi-layer graph Transformer.

3. The deep learning-based integrated circuit pre-routing timing prediction method according to claim 2, characterized in that, The autoencoder undergoes self-supervised training using a first loss function; the first loss function is expressed as follows: ； in, This represents the first loss function. This represents the mean squared error loss function. This represents the node features in the first graph representation. Indicates decoder, Indicates encoder, This represents the subgraph represented by the first training graph.

4. The deep learning-based integrated circuit pre-routing timing prediction method according to claim 1, characterized in that, The operation of the U-Net network includes: The layout features are input into a convolutional layer, then into a max pooling layer, and then into another convolutional layer to obtain downsampled features; The layout features are input into a convolutional layer and then into a max pooling layer, then into another convolutional layer and then into a max pooling layer, then through a convolutional layer and an upsampling layer in sequence, and then connected to the downsampling features in a skip connection, and then through a convolutional layer and an upsampling layer in sequence to obtain the upsampling features. The layout features are input into the convolutional layer and then connected to the upsampled features in a skip connection to obtain the spliced ​​features. The spliced ​​features are input into the convolutional layer to obtain the multi-scale layout features.

5. The deep learning-based integrated circuit pre-routing timing prediction method according to claim 1, characterized in that, The operation process of the GNN model includes: The original position coordinates of each node are obtained according to the second diagram; The original position coordinates of each node are mapped to the corresponding position of the multi-scale layout feature, and the multi-scale layout feature at the corresponding position is concatenated with the node feature in the second graph representation to obtain the concatenated node feature; wherein, the node feature includes unit node feature and line node feature; A message passing function is constructed based on the node features in the second graph representation and the spliced ​​node features to model the time-series propagation process.

6. The deep learning-based integrated circuit pre-routing timing prediction method according to claim 5, characterized in that, The message passing function includes a first message passing subfunction, which is represented as follows: ； in, This represents the first message passing subfunction of the cell node. This represents a multilayer perceptron. Represents a cell node. This represents the timing information from the previous thread node. This represents the original features of the unit nodes in the second diagram. This represents the first message passing subfunction of the line node. Represents a line node. This represents the timing information from the previous unit node. The second diagram shows the original features of the midline node.

7. The deep learning-based integrated circuit pre-routing timing prediction method according to claim 6, characterized in that, The message passing function also includes a second message passing subfunction, which is represented as follows: ； in, This indicates the updated node timing information via the second message passing subfunction. The second graph represents the netlist characteristics of nodes after being updated by the first message passing subfunction of different nodes. This represents the layout features of nodes in a multi-scale layout feature. This is the ReLU activation function.

8. A deep learning-based integrated circuit pre-routing timing prediction device, characterized in that, The device includes: The conversion module is used to convert the netlist of the circuit to be predicted into a first graph representation for a graph Transformer and a second graph representation for a GNN model, respectively, and to obtain the layout features of the predicted circuit. A prediction module is used to input the first graph representation, the second graph representation, and the layout features into a trained temporal prediction model to obtain the predicted arrival time of the temporal endpoints of the circuit to be predicted. The temporal prediction model includes an autoencoder, a U-Net network, a GNN model, and an MLP. The encoder in the autoencoder is constructed based on a multi-layer graph Transformer with linear attention. The encoder is used to extract a global topological embedding based on the first graph representation. The U-Net network is used to extract multi-scale layout features based on the layout features. The GNN model is used to concatenate the multi-scale layout features and the second graph representation to obtain a local multimodal embedding. The MLP is used to map the concatenated result of the global topological embedding and the local multimodal embedding to obtain the predicted arrival time of the temporal endpoints.

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