Method, device and equipment for verifying special integrated circuit based on multi-chip FPGA prototype platform timing optimization and medium
By combining logic synthesis and hypergraph construction of ASIC designs with partitioning and static timing analysis of multi-FPGA prototype platforms, the verification process of application-specific integrated circuits was optimized, the adverse effects caused by multiple iterative partitioning were resolved, and efficiency was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
- Filing Date
- 2026-03-20
- Publication Date
- 2026-06-19
Smart Images
Figure CN122242408A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, device, and medium for verifying application-specific integrated circuits with optimal timing based on a multi-FPGA prototype platform. Background Technology
[0002] Currently, with the increasing scale and complexity of ASIC (Application Specific Integrated Circuit) designs, the resource requirements for prototype platforms are also constantly increasing. Prototype platforms, often built from multiple FPGAs (Field Programmable Gate Arrays), are needed to help hardware and software developers verify their designs.
[0003] However, in order to verify ASIC designs, existing solutions often reduce the number of timing path cross-chip operations by using multiple iterative partitioning strategies and adjusting interconnect connections. However, this increases the production cycle of the FPGA prototype. Furthermore, since the partitioning results are limited by the requirements of the partitioned interconnects and the upper limit of the partitioning resources, it increases the difficulty and uncertainty of each partitioning scheme adjustment, thereby increasing the uncertainty of the prototype production cycle time and easily causing delays for subsequent prototype verification personnel.
[0004] It is evident that avoiding the adverse effects of multiple iterative segmentation in existing related solutions, as well as the uncertainties and complexities of manual processing inherent in these solutions, thereby improving efficiency, is a problem that those skilled in the art need to solve. Summary of the Invention
[0005] The purpose of this invention is to provide a method, apparatus, device, and medium for verifying application-specific integrated circuits (ASICs) with optimal timing based on a multi-FPGA prototyping platform. This addresses the problem of avoiding the adverse effects caused by multiple iterative partitioning in existing solutions, as well as the uncertainties and complexities of manual processing present in existing solutions, thereby improving efficiency. The specific solution is as follows: In a first aspect, the present invention provides a timing-optimized application-specific integrated circuit (ASIC) verification method based on a multi-FPGA prototype platform, comprising: The register transfer level source file corresponding to the application-specific integrated circuit (ASIC) is logic synthesized to determine the netlist file corresponding to the ASIC. Based on the netlist file, preset partitioning constraint information, and preset clock constraint information, a hypergraph based on time-series information is constructed to determine the target weighted directed hypergraph. Based on the number of FPGA chips corresponding to the multi-FPGA prototype platform and the weight values of each hyperedge in the target weighted directed hypergraph, the target weighted directed hypergraph is segmented to determine the segmentation result; Based on the segmentation results, weight values, and preset hyperedge filtering strategies, static time series analysis is performed, and the corresponding time series analysis results are verified to determine the time series verification results. If the timing verification result shows that the verification is successful, then based on the segmentation result, the bit file corresponding to each FPGA in the multi-FPGA prototype platform is determined.
[0006] Optionally, logic synthesis is performed on the register-transfer level source file corresponding to the application-specific integrated circuit (ASIC) to determine the netlist file corresponding to the ASIC, including: Based on preset tools, the register transfer level source files corresponding to the application-specific integrated circuit are compiled to determine the compilation result; Based on the preset tools and compilation results, a syntax check is performed to determine the syntax check result; If the syntax check result indicates that the syntax is correct, then based on the preset tools and the compilation results, logic synthesis is performed to determine the netlist file corresponding to the application-specific integrated circuit.
[0007] Optionally, a hypergraph based on time-series information is constructed based on the netlist file, preset partitioning constraint information, and preset clock constraint information, including: Obtain the netlist file and preset segmentation constraint information; wherein, the preset segmentation constraint information includes a number of pre-specified target circuit modules and / or target circuit structures that will not be segmented; After packaging the FPGA IP core, target circuit module and / or target circuit structure into a black box, the combinational logic units on the paths between flip-flops in the netlist file are identified to determine the flip-flop information identification results. Based on the trigger information identification results, the netlist files are marked to determine the marked netlist files; Based on clock domain partitioning rules and preset clock constraint information, the netlist file is processed by boundary partitioning and cross-clock domain boundary labeling to determine the processed netlist file; wherein, the preset clock constraint information includes the proportional relationship constraint between clock sources, the synchronous and asynchronous relationship constraint between clocks, and the clock partitioning weight value. The weight table is determined based on the constraint transformation weight table rules and preset clock constraint information; Based on the weight table and the processed netlist file, determine the weight information of the hyperedges; Based on the hyperedge weight information and the labeled netlist file, the target weighted directed hypergraph is determined; the nodes in the target weighted directed hypergraph are triggers, and the hyperedges are paths between two triggers.
[0008] Optionally, based on the number of FPGAs corresponding to the multi-FPGA prototype platform and the weight values of each hyperedge in the target weighted directed hypergraph, the target weighted directed hypergraph is segmented to determine the segmentation result, including: Based on the number of FPGA chips corresponding to the multi-FPGA prototype platform, determine the number of hyperedge subsets corresponding to the target weighted directed hypergraph. The average weight of the hyperedge subset is determined based on the number of hyperedge subsets and the total weight of the hyperedges in the target weighted directed hypergraph. Based on the number of hyperedge subsets, average weight, greedy algorithm, and weight values of each hyperedge in the target weighted directed hypergraph, the hyperedges are divided to determine each hyperedge subset. Based on each hyperedge subset, the target weighted directed hypergraph is initially segmented to determine the initial segmentation result; The initial segmentation results are optimized and adjusted to determine the final segmentation result.
[0009] Optionally, based on the segmentation results, weight values, and a preset hyperedge filtering strategy, static time series analysis is performed, and the corresponding time series analysis results are verified to determine the time series verification results, including: Based on the preset superedge filtering strategy, the target superedge with the largest weight value under each clock domain is filtered out from the segmentation results. Static timing analysis is performed based on the target hyperedge to determine the timing analysis results. The timing analysis results include the highest predicted frequency corresponding to each clock domain and the timing path used for frequency estimation. Based on the timing analysis results and preset frequency values, a verification is performed to determine the timing verification result.
[0010] Optionally, if the timing verification result shows that the verification is successful, then based on the segmentation result, determine the bit file corresponding to each FPGA in the multi-FPGA prototype platform, including: If the timing verification results show that the highest estimated frequency corresponding to each clock domain is not less than the preset frequency value, then a target constraint file is constructed based on the timing analysis results. Based on FPGA synthesis tools, the allocation results are implemented to achieve timing convergence; Based on FPGA synthesis tools and allocation results, the bit file corresponding to each FPGA in the multi-FPGA prototype platform is determined.
[0011] Optionally, after determining the timing verification result, the following steps are also included: If the timing verification result shows that the verification fails, the preset clock constraint information is updated to determine the new preset clock constraint information; Based on the new preset clock constraint information, the process jumps back to the step of constructing a hypergraph based on time-series information, using the netlist file, preset partition constraint information, and preset clock constraint information.
[0012] Secondly, the present invention provides a timing-optimized application-specific integrated circuit verification device based on a multi-FPGA prototype platform, comprising: The logic synthesis module is used to perform logic synthesis on the register transfer level source file corresponding to the application-specific integrated circuit (ASIC) in order to determine the netlist file corresponding to the ASIC. The hypergraph construction module is used to construct a time-series-based hypergraph based on netlist files, preset partitioning constraint information, and preset clock constraint information, in order to determine the target weighted directed hypergraph. The segmentation module is used to segment the target weighted directed hypergraph based on the number of FPGA chips corresponding to the multi-FPGA prototype platform and the weight values of each hyperedge in the target weighted directed hypergraph, so as to determine the segmentation result. The time series verification module is used to perform static time series analysis based on the segmentation results, weight values, and preset hyperedge filtering strategies, and to verify the corresponding time series analysis results to determine the time series verification results. The verification module is used to determine the bit file corresponding to each FPGA in the multi-FPGA prototype platform based on the segmentation result if the timing verification result is successful.
[0013] Thirdly, the present invention provides an electronic device, comprising: Memory, used to store computer programs; A processor is used to execute computer programs to implement the steps of the aforementioned application-specific integrated circuit verification method with optimal timing based on a multi-FPGA prototype platform.
[0014] Fourthly, the present invention provides a computer-readable storage medium for storing a computer program, which, when executed by a processor, implements the steps of the aforementioned application-specific integrated circuit verification method based on a multi-FPGA prototype platform with optimal timing.
[0015] As can be seen, in this invention, the register transfer level source file corresponding to the application-specific integrated circuit (ASIC) is logically synthesized to determine the netlist file corresponding to the ASIC; based on the netlist file, preset segmentation constraint information, and preset clock constraint information, a hypergraph based on timing information is constructed to determine the target weighted directed hypergraph; based on the number of FPGAs corresponding to the multi-FPGA prototype platform and the weight values of each hyperedge in the target weighted directed hypergraph, the target weighted directed hypergraph is segmented to determine the segmentation result; based on the segmentation result, weight values, and preset hyperedge filtering strategy, static timing analysis is performed, and the corresponding timing analysis results are verified to determine the timing verification result; if the timing verification result shows that the verification is successful, the bit file corresponding to each FPGA in the multi-FPGA prototype platform is determined based on the segmentation result.
[0016] As can be seen from the above technical solution, in this invention, firstly, the register transfer level source file corresponding to the application-specific integrated circuit (ASIC) is subjected to logic synthesis processing to obtain a netlist file; then, based on the netlist file, preset segmentation constraint information, and preset clock constraint information, a hypergraph based on timing information is constructed to obtain the target weighted directed hypergraph corresponding to the netlist file; then, using the number of FPGAs in the multi-FPGA prototype platform and the weight values of the hyperedges in the target weighted directed hypergraph, the target weighted directed hypergraph is segmented to obtain the segmentation result; then, based on the segmentation result and the preset hyperedge filtering strategy, static timing analysis is performed, and the corresponding timing analysis results are verified. If the verification passes, the bit file corresponding to each FPGA in the multi-FPGA prototype platform is determined based on the segmentation result. The beneficial effect of this invention is that it can avoid the adverse effects caused by multiple iterative segmentation in existing related solutions, and avoid the uncertainties and complexity of manual processing in existing related solutions, thereby improving efficiency. Attached Figure Description
[0017] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A flowchart of a timing-optimized application-specific integrated circuit (ASIC) verification method based on a multi-FPGA prototype platform is provided by the present invention. Figure 2 A flowchart of a specific application-specific integrated circuit (ASIC) verification method based on a multi-FPGA prototype platform with optimal timing is provided for this invention. Figure 3 A specific time-optimal segmentation flowchart is provided for this invention; Figure 4 A schematic diagram illustrating the construction of a weighted directed supergraph provided by the present invention; Figure 5 A schematic diagram of a timing-optimized application-specific integrated circuit (ASIC) verification device based on a multi-FPGA prototype platform provided by the present invention; Figure 6 This invention provides a structural diagram of an electronic device. Detailed Implementation
[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.
[0020] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.
[0021] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0022] To verify ASIC designs, existing solutions often employ multiple iterative partitioning strategies and adjustments to interconnect connections to reduce the number of timing path cross-chip operations. However, these methods increase the FPGA prototype manufacturing cycle. Furthermore, because the partitioning results are limited by the upper limits of the partitioned interconnects and resources, each adjustment to the partitioning scheme becomes more difficult and uncertain, further increasing the uncertainty of the prototype manufacturing cycle and potentially causing delays for subsequent prototype verification personnel. Therefore, this invention provides a timing-optimized ASIC verification solution based on a multi-FPGA prototype platform. This solution avoids the adverse effects of multiple iterative partitioning in existing solutions, eliminates the uncertainties and manual complexity inherent in existing solutions, and thus improves efficiency.
[0023] See Figure 1 As shown, this embodiment of the invention discloses a timing-optimized application-specific integrated circuit (ASIC) verification method based on a multi-FPGA prototype platform, comprising: Step S11: Perform logic synthesis on the register transfer level source file corresponding to the application-specific integrated circuit (ASIC) to determine the netlist file corresponding to the ASIC.
[0024] In this embodiment, firstly, the register-transfer level source file corresponding to the application-specific integrated circuit (ASIC) is acquired and processed to obtain the netlist file. That is, based on a preset tool, the register-transfer level source file corresponding to the ASIC is compiled to determine the compilation result; based on the preset tool and the compilation result, a syntax check is performed to determine the syntax check result; if the syntax check result shows that the syntax is correct, then based on the preset tool and the compilation result, logic synthesis is performed to determine the netlist file corresponding to the ASIC.
[0025] It is understandable that, in this embodiment, in combination with Figure 2 As shown, the RTL (Register Transfer Level) source file is imported into the EDA (Electronic Design Automation) tool, and the EDA tool performs RTL compilation and syntax checking. After the checking is completed, the RTL synthesis process is performed using the corresponding EDA tool, ultimately generating a complete RTL netlist file.
[0026] Step S12: Based on the netlist file, preset partitioning constraint information, and preset clock constraint information, construct a hypergraph based on time-series information to determine the target weighted directed hypergraph.
[0027] Combination Figure 2 As shown in this embodiment, after determining the netlist file, in addition to setting the segmentation according to the netlist file, it is also necessary to pre-configure the clock constraint information, that is, the process of adding clock relationships and weight presets. In this process, it is necessary to provide the proportional relationship constraints between clock sources, give the synchronous and asynchronous relationship constraints between each clock, and provide the segmentation weight value for each clock.
[0028] Furthermore, after determining the preset clock constraint information, combined with Figure 3As shown, a hypergraph based on timing information is constructed, namely: obtaining the netlist file and preset partitioning constraint information; wherein, the preset partitioning constraint information includes several pre-specified target circuit modules and / or target circuit structures that are not to be partitioned; after packaging the FPGA IP cores, target circuit modules and / or target circuit structures into a black box, the combinational logic units on the paths between flip-flops in the netlist file are identified to determine the flip-flop information identification results; based on the flip-flop information identification results, the netlist file is marked to determine the marked netlist file; based on the clock domain partitioning rules and Preset clock constraint information is used to perform boundary partitioning and cross-clock domain boundary labeling on the netlist file to determine the processed netlist file. The preset clock constraint information includes proportional relationship constraints between clock sources, synchronous / asynchronous relationship constraints between clocks, and clock segmentation weight values. Based on the constraint transformation weight table rules and the preset clock constraint information, a weight table is determined. Based on the weight table and the processed netlist file, hyperedge weight information is determined. Based on the hyperedge weight information and the labeled netlist file, a target weighted directed hypergraph is determined. Nodes in the target weighted directed hypergraph are triggers, and hyperedges are paths between two triggers.
[0029] It is important to understand that, in the process of constructing the hypergraph, regarding the identification and labeling of triggers, this embodiment utilizes a trigger extraction component: this component acquires the netlist and preset partitioning constraint information, extracts and labels the triggers, and calculates the number of combinational logic units along the D-terminus of the triggers towards the source direction. (where N is the total number of triggers in the netlist). The process continues until a trigger is encountered. The number of combinational logic units along the path is counted and compared with the corresponding triggers, and the information is finally marked in the netlist. For user-specified modules in the preset partitioning constraints, the module is packaged as a black box in the netlist, and its internal paths are ignored during extraction. For FPGA IP (Intellectual Property) cores such as BRAM, URAM, and GT high-speed transceivers (Gigabit Transceivers), they are also packaged as black boxes. BRAM (Block Random Access Memory) is an important storage resource in FPGAs; URAM (UltraRAM) is a larger storage resource in FPGAs compared to BRAM. In other words, this embodiment extracts the netlist based on user-specified modules and IPs as black boxes, using triggers as nodes and the data paths between triggers as hyperedges.
[0030] Regarding the determination of hyperedge weights, this embodiment 2 introduces factors such as synchronous / asynchronous relationships, clock ratio relationships, user-defined clock domain segmentation weights, and algorithm adjustment parameters, and comprehensively evaluates the hyperedge weight calculation based on segmentation priority under each clock domain. Combined with... Figure 3 As shown, the process begins with the clock domain partitioning component: This component acquires the netlist file and preset clock constraint information. It first partitions the boundaries in the netlist according to the logic driven by the clock, and then marks the corresponding cross-clock domain boundaries based on the asynchronous relationships between clocks. Next, the constraint-to-weight table component is used: This component establishes the required weight table based on the preset clock constraint information and preset weight information. The clock frequency ratio setting rule is as follows: the lowest frequency clock in the netlist is set to a value of 1, and the values of the remaining clocks are multiples of the lowest frequency clock. At the same time, users need to set the clock weights. This value is used by the user to balance the partitioning of each clock domain based on RTL characteristics. The value range is [0,1], as shown in Table 1. This component establishes a synchronous / asynchronous weight table based on the constraints of clock synchronization / asynchronous relationships, as shown in Table 2. If two clock domains are synchronous, then the weights... The weight is 1 if the two clock domains are asynchronous. It is 0.
[0031] Table 1 Clock Domain Segmentation Table ; Table 2. Simultaneous and Asynchronous Weight Table ; Next, the hyperedge weight calculation component is used: the main function of this component is to calculate the weight of the hyperedge, and the weight formula is as follows. This represents the clock source for the i-th flip-flop. (Superedge) For triggers With the previous stage trigger The path between them, if there is no parent trigger. Then there is no need to calculate the hyperedge weight. This is because there is only one trigger. The node is therefore not a hyperedge by definition. (In the formula...) The parameters are used to adjust the algorithm, and their values range from (0,1).
[0032] ; in, This represents the clock source for the i-th flip-flop; .
[0033] Regarding the construction of the target weighted directed hypergraph, this embodiment utilizes a weighted directed graph construction component: the hypergraph is expressed as follows: V represents the set of nodes, which in this scheme is the set of triggers; E represents the set of hyperedges, i.e., the connection relationships between triggers; w represents the set of weights of each hyperedge, i.e., the weight set of the hyperedges between triggers. This component abstracts and extracts the nodes and hyperedges from the netlist and introduces the hyperedge weight values, ultimately obtaining a weighted directed graph. An example of this process is shown below. Figure 4 As shown.
[0034] .
[0035] Step S13: Based on the number of FPGA chips corresponding to the multi-FPGA prototype platform and the weight values of each hyperedge in the target weighted directed hypergraph, the target weighted directed hypergraph is segmented to determine the segmentation result.
[0036] In this embodiment, combined with Figure 3 As shown, after determining the target weighted directed hypergraph, an initial segmentation is performed on the hypergraph, namely: determining the number of hyperedge subsets corresponding to the target weighted directed hypergraph based on the number of FPGAs corresponding to the multi-FPGA prototype platform; determining the average weight of the hyperedge subsets based on the number of hyperedge subsets and the total weight of the hyperedges in the target weighted directed hypergraph; dividing the hyperedges based on the number of hyperedge subsets, the average weight, the greedy algorithm, and the weight of each hyperedge in the target weighted directed hypergraph to determine each hyperedge subset; performing an initial segmentation on the target weighted directed hypergraph based on each hyperedge subset to determine the initial segmentation result; and optimizing and adjusting the initial segmentation result to determine the final segmentation result.
[0037] It's important to understand that the initial segmentation process for the target weighted directed hypergraph first requires importing the netlist. Then, the netlist circuitry is modeled, extracting basic FPGA logic units such as LUTs (Look-Up Tables), MUXs (Multiplexers), FDCEs (Flip-Flop with Clock Enable and Asynchronous Clear), and BRAMs, and setting them as nodes. This process does not include modules or circuit structures specified by the user in the segmentation preset. All nodes are then constructed into a hypergraph. Using hyperedge weights as a metric, a greedy algorithm is employed to place edges with higher weights into different subsets, with the number of subsets matching the number of FPGA chips. Subsequently, the points connected to edges with higher weights in each subset are added to the corresponding subset. Then, edges with higher weights from the periphery of the subgraph are gradually introduced into the subgraph, ensuring that the hyperedge weight of each subgraph does not exceed a certain percentage of the average weight. times, of which This is an allowed imbalance factor, and eventually all nodes exist in each subgraph, completing the initial partitioning.
[0038] Step S14: Based on the segmentation results, weight values, and preset superedge filtering strategy, perform static time series analysis and verify the corresponding time series analysis results to determine the time series verification results.
[0039] In this embodiment, combined with Figure 3 As shown, after the initial segmentation of the target weighted directed hypergraph is completed, the segmentation results are filtered, static timing analysis is performed, and verification is conducted to verify the effect of the initial segmentation. Specifically, based on the preset hyperedge filtering strategy, the target hyperedge with the largest weight value in each clock domain is selected from the segmentation results; static timing analysis is performed based on the target hyperedge to determine the timing analysis results; the timing analysis results include the highest estimated frequency corresponding to each clock domain and the timing path used for frequency estimation; and verification is performed based on the timing analysis results and the preset frequency value to determine the timing verification results.
[0040] It's important to understand that optimizing the segmentation results can employ local optimization algorithms, such as the Fiduccia-Mattheyses Algorithm (FM) with single-node movement or the Kernighan-Lin Algorithm (KL) with paired-node swapping. The balance constraint remains 1 + the average value. The optimal segmentation boundary is obtained by multiplying the values by a factor of 1. Then, a worst-case cut edge path selection component is used: this component analyzes the optimized segmentation boundary and selects the worst cut edge (i.e., the hyperedge with the largest weight value) in each clock domain. Next, static timing analysis is performed: using the hyperedge with the largest segmentation weight in each clock domain as input, the highest estimated frequency in each clock domain is obtained. The highest frequency of each clock domain after segmentation, along with the timing path used for frequency estimation, is exported and output as a report for user reference, allowing users to have a performance evaluation and measurement of the segmentation results. Furthermore, combined with... Figure 2 As shown, verify whether the frequencies in the static timing analysis results meet the expected values.
[0041] Furthermore, in this embodiment, to avoid timing errors or functional malfunctions caused by improper clock domain partitioning and to improve the reliability of prototype verification, the hyperedges of different clock domains can be marked during hypergraph construction, and special weights or constraints can be set for asynchronous paths (such as cross-clock domain paths) to ensure that cross-clock domain paths are not scattered across different FPGAs during partitioning, or to automatically insert synchronizers. Moreover, during subsequent static timing analysis, each clock domain can be independently verified, and the metastability of asynchronous paths can be considered.
[0042] Step S15: If the timing verification result shows that the verification is successful, then based on the segmentation result, determine the bit file corresponding to each FPGA in the multi-FPGA prototype platform.
[0043] In this embodiment, combined with Figure 2 As shown, if the effect of this segmentation meets the expectations, a bit file is generated. That is, if the timing verification results show that the highest estimated frequency corresponding to each clock domain is not less than the preset frequency value, then a target constraint file is constructed based on the timing analysis results; the allocation results are implemented based on the FPGA synthesis tool to complete timing convergence; and the bit file corresponding to each FPGA in the multi-FPGA prototype platform is determined based on the FPGA synthesis tool and the allocation results.
[0044] Furthermore, such as Figure 2 As shown, if the effect of this segmentation does not meet expectations, the process of missing relations and weight preset is repeated, and the time-optimal segmentation is performed again. That is, if the time-series verification result shows that the verification fails, the preset clock constraint information is updated to determine the new preset clock constraint information. Based on the new preset clock constraint information, the process jumps back to the step of constructing a hypergraph based on time-series information based on the netlist file, preset segmentation constraint information, and preset clock constraint information.
[0045] In summary, the timing-optimal partitioning scheme proposed in this embodiment incorporates timing information during the partitioning stage, prioritizing the performance of the FPGA prototype version to achieve the best possible partitioning result. This scheme introduces the frequency ratios of each clock domain before partitioning. Simultaneous and asynchronous weights between clocks User-defined clock weights This approach obtains basic information about each clock domain by using parameters such as [parameter name missing], and allows users to intervene in the segmentation weights of certain clock domains, increasing the applicability and compatibility of the solution. During the segmentation phase, this solution uses triggers as nodes and employs timing-oriented hyperedge weights to ultimately construct a weighted directed hypergraph. Compared to the undirected graph constructed from each basic FPGA logic unit in the netlist in traditional solutions, the hypergraph size is exponentially reduced, and the hypergraph coarsening clustering step is eliminated, reducing the possibility of local optima introduced during coarsening clustering. Compared to the traditional approach that aims for the minimum number of cut edges, this solution directly improves the performance of the FPGA prototype version, avoiding the need for multiple iterative segmentations without specific targeting required in traditional solutions. It achieves the best performance for the FPGA prototype version, and derives the estimated frequency after segmentation, allowing FPGA prototype developers to measure timing results during the segmentation phase.
[0046] In summary, compared to existing solutions, this approach meets the performance requirements of multi-FPGA prototyping platforms, avoiding the difficulty of achieving optimal performance despite multiple partitioning and iterations in traditional solutions. It also accelerates the prototype production cycle.
[0047] Therefore, in this embodiment of the invention, firstly, the register transfer level source file corresponding to the application-specific integrated circuit (ASIC) is subjected to logic synthesis processing to obtain a netlist file; then, based on the netlist file, preset segmentation constraint information, and preset clock constraint information, a hypergraph based on timing information is constructed to obtain the target weighted directed hypergraph corresponding to the netlist file; then, using the number of FPGAs in the multi-FPGA prototype platform and the weight values of the hyperedges in the target weighted directed hypergraph, the target weighted directed hypergraph is segmented to obtain the segmentation result; then, based on the segmentation result and the preset hyperedge filtering strategy, static timing analysis is performed, and the corresponding timing analysis results are verified. If the verification passes, the bit file corresponding to each FPGA in the multi-FPGA prototype platform is determined based on the segmentation result. This avoids the adverse effects caused by multiple iterative segmentation in existing related solutions, and avoids the uncertainties and manual processing complexity present in existing related solutions, thereby improving efficiency.
[0048] See Figure 5 As shown, this embodiment of the invention also discloses a timing-optimized application-specific integrated circuit (ASIC) verification device based on a multi-FPGA prototype platform, comprising: The logic synthesis module 11 is used to perform logic synthesis on the register transfer level source file corresponding to the application-specific integrated circuit (ASIC) to determine the netlist file corresponding to the ASIC. The hypergraph construction module 12 is used to construct a hypergraph based on time-series information, based on the netlist file, preset partitioning constraint information and preset clock constraint information, so as to determine the target weighted directed hypergraph. The segmentation module 13 is used to segment the target weighted directed hypergraph based on the number of FPGA chips corresponding to the multi-FPGA prototype platform and the weight value of each hyperedge in the target weighted directed hypergraph, so as to determine the segmentation result. The time series verification module 14 is used to perform static time series analysis based on the segmentation results, weight values and preset hyperedge filtering strategies, and to verify the corresponding time series analysis results to determine the time series verification results. The verification module 15 is used to determine the bit file corresponding to each FPGA in the multi-FPGA prototype platform based on the segmentation result if the timing verification result is successful.
[0049] For more detailed information on the working process of each of the above modules, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.
[0050] Furthermore, embodiments of the present invention also disclose an electronic device, Figure 6 This is a structural diagram of an electronic device according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of the invention. Specifically, the electronic device may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the timing-optimized application-specific integrated circuit verification method based on a multi-FPGA prototype platform disclosed in any of the foregoing embodiments. Alternatively, the electronic device in this embodiment may specifically be a computer.
[0051] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this invention, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.
[0052] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.
[0053] The operating system 221 is used to manage and control the various hardware devices on the electronic device and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the timing-optimized application-specific integrated circuit verification method based on a multi-FPGA prototype platform disclosed in any of the foregoing embodiments, the computer program 222 may further include computer programs capable of performing other specific tasks.
[0054] Furthermore, this invention also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned time-optimized application-specific integrated circuit verification method based on a multi-FPGA prototype platform. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.
[0055] Furthermore, this invention also discloses a computer program product, including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, they implement the aforementioned disclosed method for timing-optimized application-specific integrated circuit verification based on a multi-FPGA prototype platform. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.
[0056] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0057] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0058] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0059] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.
[0060] The technical solution provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A timing-optimized application-specific integrated circuit (ASIC) verification method based on a multi-FPGA prototype platform, characterized in that, include: The register transfer level source file corresponding to the application-specific integrated circuit (ASIC) is subjected to logic synthesis to determine the netlist file corresponding to the ASIC. Based on the netlist file, preset segmentation constraint information, and preset clock constraint information, a hypergraph based on time-series information is constructed to determine the target weighted directed hypergraph. Based on the number of FPGA chips corresponding to the multi-FPGA prototype platform and the weight values of each hyperedge in the target weighted directed hypergraph, the target weighted directed hypergraph is segmented to determine the segmentation result; Based on the segmentation results, the weight values, and the preset hyperedge filtering strategy, static time series analysis is performed, and the corresponding time series analysis results are verified to determine the time series verification results. If the timing verification result shows that the verification is successful, then based on the segmentation result, the bit file corresponding to each FPGA in the multi-FPGA prototype platform is determined.
2. The application-specific integrated circuit (ASIC) verification method based on a multi-FPGA prototype platform with optimal timing, as described in claim 1, is characterized in that... The step of performing logic synthesis on the register transfer level source file corresponding to the application-specific integrated circuit (ASIC) to determine the netlist file corresponding to the ASIC includes: Based on preset tools, the register transfer level source files corresponding to the application-specific integrated circuit are compiled to determine the compilation result; Based on the preset tool and the compilation result, a syntax check is performed to determine the syntax check result; If the syntax check result indicates that the syntax is correct, then based on the preset tool and the compilation result, logical synthesis processing is performed to determine the netlist file corresponding to the application-specific integrated circuit.
3. The application-specific integrated circuit (ASIC) verification method based on a multi-FPGA prototype platform with optimal timing, as described in claim 1, is characterized in that... The construction of a hypergraph based on time-series information, based on the netlist file, preset segmentation constraint information, and preset clock constraint information, includes: Obtain the netlist file and preset segmentation constraint information; wherein, the preset segmentation constraint information includes a number of pre-specified target circuit modules and / or target circuit structures that will not be segmented; After packaging the FPGA IP core, the target circuit module, and / or the target circuit structure into a black box, the combinational logic units on the paths between the flip-flops in the netlist file are identified to determine the flip-flop information identification result. Based on the trigger information identification results, the netlist file is marked to determine the marked netlist file; Based on clock domain partitioning rules and preset clock constraint information, the netlist file is processed by boundary partitioning and cross-clock domain boundary labeling to determine the processed netlist file; wherein, the preset clock constraint information includes proportional relationship constraints between clock sources, synchronous and asynchronous relationship constraints between clocks, and clock partitioning weight values; The weight table is determined based on the constraint transformation weight table rules and the preset clock constraint information; Based on the weight table and the processed netlist file, determine the hyperedge weight information; Based on the hyperedge weight information and the labeled netlist file, a target weighted directed hypergraph is determined; the nodes in the target weighted directed hypergraph are the triggers, and the hyperedges are the paths between two triggers.
4. The application-specific integrated circuit (ASIC) verification method based on a multi-FPGA prototype platform with optimal timing, as described in claim 1, is characterized in that... The target weighted directed hypergraph is segmented based on the number of FPGAs corresponding to the multi-FPGA prototype platform and the weight values of each hyperedge in the target weighted directed hypergraph to determine the segmentation result, including: Based on the number of FPGA chips corresponding to the multi-FPGA prototype platform, the number of hyperedge subsets corresponding to the target weighted directed hypergraph is determined. Based on the number of the hyperedge subsets and the total weight of the hyperedges in the target weighted directed hypergraph, the average weight of the hyperedge subsets is determined. Based on the number of hyperedge subsets, the average weight, the greedy algorithm, and the weight values of each hyperedge in the target weighted directed hypergraph, the hyperedges are divided to determine each hyperedge subset. Based on each of the aforementioned hyperedge subsets, the target weighted directed hypergraph is initially segmented to determine the initial segmentation result; The initial segmentation results are optimized and adjusted to determine the final segmentation result.
5. The application-specific integrated circuit (ASIC) verification method based on a multi-FPGA prototype platform with optimal timing, as described in claim 4, is characterized in that... The step involves performing static time series analysis based on the segmentation results, the weight values, and a preset hyperedge filtering strategy, and verifying the corresponding time series analysis results to determine the time series verification results, including: Based on a preset superedge filtering strategy, the target superedge with the largest weight value in each clock domain is filtered out from the segmentation results. Based on the target hyperedge, static timing analysis is performed to determine the timing analysis results; the timing analysis results include the highest estimated frequency corresponding to each clock domain and the timing path used for frequency estimation. Based on the timing analysis results and the preset frequency value, a verification is performed to determine the timing verification result.
6. The application-specific integrated circuit (ASIC) verification method based on a multi-FPGA prototype platform with optimal timing, as described in claim 5, is characterized in that... If the timing verification result shows that the verification is successful, then based on the segmentation result, the bit file corresponding to each FPGA in the multi-FPGA prototype platform is determined, including: If the timing verification results show that the highest estimated frequency corresponding to each clock domain is not less than the preset frequency value, then a target constraint file is constructed based on the timing analysis results. Based on FPGA synthesis tools, the allocation result is implemented to achieve timing convergence; Based on the FPGA synthesis tool and the allocation results, the bit file corresponding to each FPGA in the multi-FPGA prototype platform is determined.
7. The application-specific integrated circuit (ASIC) verification method based on a multi-FPGA prototype platform with optimal timing, as described in any one of claims 1 to 6, is characterized in that... After determining the timing verification result, the process also includes: If the timing verification result shows that the verification fails, the preset clock constraint information is updated to determine the new preset clock constraint information. Based on the new preset clock constraint information, the process jumps back to the step of constructing a hypergraph based on time-series information, using the netlist file, preset partition constraint information, and preset clock constraint information.
8. A timing-optimized application-specific integrated circuit (ASIC) verification device based on a multi-FPGA prototyping platform, characterized in that, include: The logic synthesis module is used to perform logic synthesis on the register transfer level source file corresponding to the application-specific integrated circuit (ASIC) to determine the netlist file corresponding to the ASIC. The hypergraph construction module is used to construct a hypergraph based on time-series information based on the netlist file, preset segmentation constraint information, and preset clock constraint information, so as to determine the target weighted directed hypergraph. The segmentation module is used to segment the target weighted directed hypergraph based on the number of FPGA chips corresponding to the multi-FPGA prototype platform and the weight value of each hyperedge in the target weighted directed hypergraph, so as to determine the segmentation result. The time series verification module is used to perform static time series analysis based on the segmentation results, the weight values and the preset superedge filtering strategy, and to verify the corresponding time series analysis results to determine the time series verification results. The verification module is used to determine the bit file corresponding to each FPGA in the multi-FPGA prototype platform based on the segmentation result if the timing verification result shows that the verification is successful.
9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the application-specific integrated circuit verification method based on a multi-FPGA prototype platform with optimal timing as described in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the application-specific integrated circuit verification method based on a multi-FPGA prototype platform with optimal timing as described in any one of claims 1 to 7.