A millimeter wave integrated circuit automated design system and method

Abstract

This invention proposes an automated design system and method for millimeter-wave integrated circuits, belonging to the field of millimeter-wave circuit design. In the system, an active circuit design unit generates active device models according to predetermined process rules based on the performance parameter requirements and design constraints of the millimeter-wave integrated circuit to be designed; a passive matching network design unit generates passive device models and corresponding layouts and performs simulations based on set impedance matching targets and frequency band requirements to obtain the corresponding SNP file; a circuit co-simulation unit embeds the SNP file into the circuit schematic and completes port interfacing with the active device models to construct a complete millimeter-wave integrated circuit; then, the millimeter-wave integrated circuit is simulated, and closed-loop iterative optimization is used to ensure that all performance indicators meet the performance parameter requirements, outputting the final millimeter-wave integrated circuit design result. This invention can effectively improve design efficiency and ensure the design accuracy and reliability of millimeter-wave integrated circuits.

Description

Technical Field

[0001] This invention belongs to the field of circuit design and automation technology, and specifically relates to an automated design system and method for millimeter-wave integrated circuits. Background Technology

[0002] Millimeter waves are strictly defined in the frequency range of 30 GHz to 300 GHz (corresponding to wavelengths of 1 mm to 10 mm), which falls precisely in the critical frequency band between microwaves (300 MHz - 30 GHz) and terahertz radiation (300 GHz - 10 THz). This is a special region in the electromagnetic spectrum that combines the engineering feasibility of microwaves with the performance advantages of high-frequency bands. This unique positioning makes it stand out in multiple fields such as radio frequency and microwave engineering, communication technology, and sensing, forming an irreplaceable technological value.

[0003] Compared to traditional microwave technology, the core advantage of millimeter waves stems from their higher carrier frequency: On the one hand, spatial resolution is positively correlated with frequency (according to the Rayleigh criterion, resolution is approximately half the wavelength). The short wavelength of millimeter waves enables imaging systems or sensing devices to capture minute features at the millimeter level. For example, in radar imaging, the resolution of a 30 GHz millimeter-wave radar can reach 5 mm, while the resolution of a 10 GHz microwave radar is only about 15 mm. This gives millimeter waves a natural advantage in scenarios such as precise detection and close-range imaging. On the other hand, the 30 GHz-300 GHz band can be divided into multiple continuous ultra-wideband channels, and the bandwidth of a single channel can easily exceed 1 GHz (far exceeding the bandwidth of hundreds of MHz in the microwave band). According to Shannon's formula, greater bandwidth means higher information transmission rates, providing a physical basis for Gbps-level broadband communication.

[0004] However, the design of millimeter-wave integrated circuits still faces many severe challenges, among which two core issues are particularly prominent:

[0005] First, impedance matching involves long iteration times and high electromagnetic costs, making theoretical analysis of millimeter-wave integrated circuits more difficult compared to radio frequency circuits. Second, it requires full-layout simulation optimization design, which directly leads to extended design cycles and significantly increased R&D costs. Due to the substantial increase in frequency (30 GHz - 300 GHz), the parasitic parameters of transmission lines, device packaging parasitic effects, and electromagnetic coupling phenomena in millimeter-wave integrated circuits are exceptionally significant. Impedance mismatch can directly cause signal reflection, gain attenuation, noise figure deterioration, and even circuit oscillation. Furthermore, even minute dimensional deviations (such as micrometer-level linewidth and spacing changes) can disrupt the preset impedance matching state, posing a significant challenge to the design and debugging of the matching network. Simultaneously, the drastic amplification of distributed parameter effects means that even small changes in layout size can severely deviate from the design objectives. Therefore, millimeter-wave integrated circuits must undergo multiple full-layout iterative optimization designs. However, full-layout iterative optimization not only requires repeated adjustments to the impedance matching network but also consumes a significant amount of simulation time, resulting in extremely high R&D and time costs. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of existing technologies and propose an automated design system and method for millimeter-wave integrated circuits. This invention enables a closed-loop design process in millimeter-wave chip design, encompassing "parameter setting - automated simulation - index matching - iterative optimization," effectively improving design efficiency while ensuring design accuracy and reliability.

[0007] This invention proposes an automated design system for millimeter-wave integrated circuits, comprising: an active circuit design unit, a passive matching network design unit, and a circuit co-simulation unit; wherein the active circuit design unit and the passive matching network design unit are respectively connected to the circuit co-simulation unit;

[0008] The active circuit design unit is used to generate active device models of the millimeter-wave integrated circuit according to the performance parameter requirements and design constraints of the millimeter-wave integrated circuit to be designed, and in accordance with predetermined process rules.

[0009] The passive matching network design unit is used to generate a passive device model in the millimeter-wave integrated circuit according to the set impedance matching target and frequency band requirements; then, based on the passive device model, a corresponding layout is generated and simulated to obtain the corresponding SNP file.

[0010] The circuit co-simulation unit is used to embed the SNP file output by the passive matching network design unit into a preset circuit schematic and to complete port docking with the active device model output by the active circuit design unit to construct a complete millimeter-wave integrated circuit. Then, the generated millimeter-wave integrated circuit is simulated, and the model or layout size generated by the passive matching network design unit is adjusted according to the simulation results until all performance indicators meet the performance parameter requirements, and the final millimeter-wave integrated circuit design result is output.

[0011] In one specific embodiment of the present invention, it further includes:

[0012] The active device model reserves an interface for a passive matching network.

[0013] In one specific embodiment of the present invention, it further includes:

[0014] The circuit co-simulation unit configures the simulation type according to the design objectives during simulation;

[0015] The simulation types include: DC operating point analysis, AC small-signal analysis, load traction analysis, and harmonic balance analysis.

[0016] In a specific embodiment of the present invention, the workflow of the passive matching network design unit includes:

[0017] 1) The passive matching network design unit uses the impedance circle diagram algorithm to select the optimal matching network topology for passive devices based on the set impedance matching target and frequency band requirements, and obtains the passive device model.

[0018] 2) Based on the network topology results and according to the preset process library rules, the passive matching network design unit generates the matching network layout and simultaneously completes the metal layer allocation, grounding structure design and electromagnetic compatibility optimization.

[0019] 3) By calling the EMX electromagnetic simulation tool, setting the simulation frequency point and mesh generation accuracy, full-wave electromagnetic simulation is performed on the matching network layout to extract port S-parameters, parasitic capacitance or inductance and electromagnetic coupling parameters.

[0020] 4) After the simulation is completed, an SNP file is generated, which contains port network parameters at each frequency point in the wideband.

[0021] In one specific embodiment of the present invention, it further includes:

[0022] The passive matching network design unit will generate passive device models to form a model library.

[0023] In one specific embodiment of the present invention, it further includes:

[0024] After the circuit co-simulation unit completes the simulation, it compares the simulation results with the performance parameter requirements stored in the active circuit design unit. If there is a deviation, the deviation is fed back to the passive matching network design unit. The passive matching network design unit adjusts the topology or layout size of the passive devices, or retrieves a new model from the model library. The passive matching network design unit re-executes the simulation and outputs an updated SNP file. The circuit co-simulation unit uses the updated SNP file to perform the simulation again until all performance indicators in the simulation results meet the performance parameter requirements, and the millimeter-wave integrated circuit design is completed.

[0025] This invention also proposes an automated design method for millimeter-wave integrated circuits based on the above system, comprising:

[0026] Based on the performance parameter requirements and design constraints of the millimeter-wave integrated circuit to be designed, the active device model of the millimeter-wave integrated circuit is generated according to the predetermined process rules.

[0027] Based on the set impedance matching target and frequency band requirements, a passive device model in the millimeter-wave integrated circuit is generated; then, based on the passive device model, a corresponding layout is generated and simulation is performed to obtain the corresponding SNP file;

[0028] The SNP file is embedded into a preset circuit schematic and port-connected with the active device model to construct a complete millimeter-wave integrated circuit. Then, the generated millimeter-wave integrated circuit is simulated, and the passive device model or layout size is adjusted according to the simulation results until all performance indicators meet the performance parameter requirements, and the final millimeter-wave integrated circuit design result is output.

[0029] The features and beneficial effects of this invention are as follows:

[0030] 1) Design efficiency has increased by orders of magnitude.

[0031] Traditional millimeter-wave design requires engineers to manually complete iterative processes of impedance matching topology selection, layout drawing, electromagnetic simulation, and circuit co-simulation. Optimization of passive matching networks alone can take 1-2 weeks, and the entire design cycle typically lasts 4-8 weeks. The more iterations, the higher the labor costs. This invention, through Skill script automation and algorithm integration, compresses the entire closed-loop cycle of "topology optimization - layout drawing - EM simulation - circuit integration - performance iteration" to 3-7 days, improving design efficiency by over 60%. Manual operations are reduced by 80%, eliminating the need for engineers to engage in repetitive drawing and simulation parameter configuration. Engineers can focus their energy on optimizing core performance indicators and innovative topology design, significantly reducing both labor and time costs.

[0032] 2) Design accuracy and reliability are significantly improved.

[0033] The short wavelength characteristics of the millimeter-wave band (30 GHz-300 GHz) lead to parasitic effects (such as line coupling, via parasitics, and metal loss) that have a significant impact on circuit performance. Manual design often results in layout size deviations and unreasonable electromagnetic simulation parameter settings, frequently leading to performance discrepancies exceeding 10% between the fabricated and simulation results. In severe cases, this can result in fatal defects such as insufficient gain and excessive VSWR, with a fabrication failure rate exceeding 30%. This invention addresses these issues by automating layout creation to strictly adhere to process library rules, using micrometer-level mesh EMX simulation to accurately capture parasitic effects, employing a closed-loop iterative algorithm to automatically correct performance deviations, and standardizing parameter import and simulation configuration processes to avoid random errors from manual operation. This ensures consistency in design results across different engineers and batches, improving product quality stability.

[0034] 3) Achieve large-scale, standardized design and mass production.

[0035] Traditional manual design relies on the accumulated experience of engineers. Differences in impedance matching topology and simulation strategies among engineers lead to fragmented design solutions for similar products, making it difficult to quickly adapt to mass production requirements across different frequency bands (e.g., 24 GHz-28 GHz, 37 GHz-43 GHz) and process nodes (GaAs / InP / CMOS). Furthermore, product iterations require rebuilding the design flow, resulting in long adaptation cycles. This invention, through a parametric design framework, automatically generates corresponding design solutions by simply modifying performance parameters and process constraints, achieving "one tool, multiple scenarios." Simultaneously, standardized SNP file output and simulation report generation processes enable rapid reuse and portability of design results, supporting batch design of multi-frequency band and multi-specification circuits on the same platform. This meets the mass production needs of large-scale applications such as 5G / 6G base stations and millimeter-wave radar, shortening product iteration cycles by more than 50%.

[0036] 4) Optimize resource utilization and lower design threshold.

[0037] Millimeter-wave circuit design requires a balance between chip area, power consumption, and performance. Traditional manual design struggles to accurately weigh multiple constraints, often resulting in chip area redundancy (20%-30% larger than the optimal solution) or excessive power consumption. This invention's automated topology optimization algorithm automatically selects the matching network scheme with the smallest area and lowest power consumption while meeting performance requirements. This reduces chip area by an average of 15%-25% and thermal power consumption by 10%-20%, improving product integration and battery life (especially for portable devices). Furthermore, this invention encapsulates the complex millimeter-wave design process into an automated tool, reducing reliance on engineer experience. Novice engineers can complete high-quality designs with minimal training, addressing the industry's shortage of millimeter-wave design talent and promoting technology adoption and industrial upgrading.

[0038] 5) Strong cross-process compatibility, adapting to technological evolution.

[0039] The design framework of this invention can be flexibly adapted to mainstream millimeter-wave process nodes (0.15 μm GaAs, 0.1 μm InP, 65 nm CMOS, etc.). Different process rules can be imported through a standardized process library interface, enabling process migration without refactoring automated workflows. With the maturation of third-generation semiconductor (such as GaN) processes, only process parameters and device models need to be updated to quickly extend to GaN-based millimeter-wave circuit design, demonstrating excellent technical scalability. This feature allows it to keep pace with the technological evolution needs of the communication and sensing fields, providing efficient design support for emerging scenarios such as 6G terahertz communication and high-resolution millimeter-wave imaging, and facilitating the commercialization of related technologies. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of an automated design system for millimeter-wave integrated circuits according to an embodiment of the present invention.

[0041] Figure 2 This is a schematic diagram illustrating the working principle of a millimeter-wave integrated circuit automated design system in a specific embodiment of the present invention. Detailed Implementation

[0042] This invention proposes an automated design system and method for millimeter-wave integrated circuits, which will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] This embodiment proposes an automated design system for millimeter-wave integrated circuits, innovatively constructing a full-link automated system encompassing "automatic layout generation - precise schematic rendering - multi-dimensional indicator output - high-quality dataset construction - closed-loop iterative optimization," completely breaking away from the inefficient "manual drawing - distributed simulation - manual iteration" model in traditional millimeter-wave integrated circuit design. The system uses Cadence Skill scripts as its core driving engine, deeply integrating the EMX electromagnetic simulation tool and the Cadence Virtuoso design platform to achieve end-to-end automated connection from performance parameter input to final design iteration.

[0044] In this embodiment, the structure of the millimeter-wave integrated circuit automated design system is as follows: Figure 1 As shown, it includes: an active circuit design unit, a passive matching network design unit, and a circuit co-simulation unit; wherein, the active circuit design unit and the passive matching network design unit are respectively connected to the circuit co-simulation unit.

[0045] Furthermore, the working principle of the millimeter-wave integrated circuit automated design system is as follows: Figure 2 As shown, it includes:

[0046] The active circuit design unit is used to generate active device models of the millimeter-wave integrated circuit according to the performance parameter requirements and design constraints of the millimeter-wave integrated circuit to be designed, and in accordance with predetermined process rules.

[0047] In one specific embodiment of the present invention, taking the design of a differential capacitor power amplifier circuit as an example, the performance parameters of the millimeter-wave power amplifier need to cover the key indicators of millimeter-wave power amplifiers: output power (typical value 10-30 dBm, peak value up to 40 dBm or more), operating bandwidth (such as mainstream frequency bands such as 24 GHz-28 GHz, 37 GHz-43 GHz, etc.), power-added efficiency (PAE ≥ 30%, high-end application scenarios require ≥ 40%), small-signal gain (≥ 15 dB, fluctuation ≤ ± 1 dB), noise figure (≤ 3 dB), input / output standing wave ratio (VSWR ≤ 1.5:1); design constraints include: upper limit of chip area, supply voltage range (0.6V-5 V), thermal dissipation threshold (≤ 10 W), and process node parameters (such as 28 nm CMOS or 65 nm CMOS process rules). In this embodiment, the above performance parameter requirements and design constraints are imported into the EDA design platform through a standardized interface and stored in the design target database.

[0048] It should be noted that active circuits are the core of millimeter-wave circuits, and their design quality directly determines the gain, efficiency, and stability of millimeter-wave integrated circuit designs. The construction process must be closely integrated with device characteristics and process rules.

[0049] In one specific embodiment of the present invention, the active circuit design unit performs the following process of power amplifier design:

[0050] 1) Set the performance parameter requirements for the millimeter-wave integrated circuit to be designed.

[0051] In this embodiment, the core S-parameters are set (including input / output VSWR ≤ 1.5:1, small signal gain fluctuation ≤ ±1 dB), power-added efficiency (PAE ≥ 15%), output power (≥ 15 dBm), and 3 dB bandwidth, etc.

[0052] 2) Component selection and size determination.

[0053] In this embodiment, based on the design frequency band (40 GHz-80 GHz) and output power requirements, high-performance NMOS transistors are selected from the TSMC 65 nm CMOS process library to determine the die size of each stage of the three-stage amplification structure: the first stage is 24 μm / 60um (small size, low noise, responsible for initial signal amplification), the second stage is 48 μm / 60um (medium size, balancing gain and efficiency), and the third stage is 96 μm / 60um (large size, improving output power). Each stage adopts a multi-finger parallel structure.

[0054] 3) Interconnect design optimization.

[0055] In the millimeter-wave band, the parasitic effects (inductance, capacitance) of interconnects have a significant impact on circuit performance. The interconnect parameters need to be determined according to the die size and process rules. In this embodiment, the key signal path uses the top metal M9.

[0056] 4) Neutralization capacitor matching.

[0057] In this embodiment, to suppress the severe Miller capacitance effect in the millimeter-wave band (which leads to gain roll-off and decreased stability), the neutralization capacitance value is calculated based on the gate-drain capacitance Cgd of each die stage: C neutralization = 16 fF for the first stage, 20 fF for the second stage, and 24 fF for the third stage. MIM capacitors (metal-insulator-metal capacitors) from the process library are selected to ensure capacitance accuracy and high-frequency stability.

[0058] 5) Generation of active circuit structure.

[0059] In this embodiment, a three-level structure of "common source + neutralizing capacitor + interstage matching" is finally determined, and it is encapsulated as a standardized active model, with an interface (50Ω standard port) reserved for passive matching network to facilitate subsequent automated integration.

[0060] The passive matching network design unit is used to generate passive device models in millimeter-wave integrated circuits according to the set impedance matching target and frequency band requirements; then, based on the passive device models, the corresponding layout is generated and simulated to obtain the corresponding SNP file.

[0061] Specifically, the workflow of the passive matching network design unit is as follows:

[0062] 1) The passive matching network design unit uses the impedance circle diagram algorithm to automatically select the optimal matching network topology for passive devices based on the set impedance matching target and frequency band requirements. The optimal matching network topology needs to take into account bandwidth, insertion loss and area requirements, thereby generating a passive device model.

[0063] 2) Based on the network topology results, according to the preset process library rules (line width, line length, spacing, via size, etc.), the passive matching network design unit automatically generates the matching network layout and simultaneously completes the metal layer allocation, grounding structure design and electromagnetic compatibility optimization.

[0064] 3) By calling the EMX electromagnetic simulation tool, setting the simulation frequency points and mesh subdivision accuracy (micrometer-level subdivision to capture parasitic effects in the millimeter-wave band), full-wave electromagnetic simulation is performed on the matching network layout to extract port S-parameters, parasitic capacitance / inductance, and electromagnetic coupling parameters.

[0065] 4) After the simulation is completed, a standard SNP file (such as S6P or S8P file) is automatically generated, which contains the port network parameters of each frequency point in the wide frequency band, providing an accurate passive network model for subsequent circuit co-simulation.

[0066] Furthermore, the passive matching network design unit can also assemble the generated passive device models into a model library.

[0067] In one specific embodiment of the present invention, the passive matching network design unit constructs a diverse transformer model library and an automated simulation process as follows:

[0068] 1) The passive matching network design unit designs and implements multiple types of transformer models to meet different impedance transformation requirements, covering all combinations of input-side (single-turn, double-turn, three-turn) and output-side (single-turn, double-turn, three-turn) topologies (a total of 3×3=9 basic topologies). The number of turns, line width, spacing, inner diameter, and other parameters of each model can be flexibly adjusted via scripts to adapt to different frequency bands and impedance matching targets (e.g., single-turn models are suitable for low impedance transformation ratios, while double-turn and three-turn models are suitable for high impedance transformation ratios). All transformer models constitute a transformer model library.

[0069] 2) Initialization configuration: Call the internal function of Skill to define the working area coordinates (e.g., 0,0 to 1000 μm,1000 μm) and import the design rules (DRC rules) of the TSMC 65 nm process library.

[0070] 3) Parametric drawing: Based on the transformer type set by the user (such as input two-turn, output three-turn), the script automatically calculates the coordinates and bending angles of each metal wire, selects the M8 metal layer (the second-to-top metal, with high conductivity and low loss) to draw the windings, and the winding spacing strictly follows the minimum spacing requirement of the process library (0.5 μm) to avoid DRC errors.

[0071] 4) EMX High-Precision Electromagnetic Simulation: The script automatically calls the EMX simulation tool and completes the following configuration: Simulation parameter settings: frequency range 40 GHz-80 GHz, frequency step 1 GHz (to ensure full bandwidth coverage), mesh subdivision accuracy set to 0.1 μm (micrometer-level subdivision to accurately capture skin effect, proximity effect and electromagnetic coupling in the millimeter wave band).

[0072] 5) Dataset Construction and SNP File Output: After all simulations are completed, the script automatically organizes the results into a high-quality database and generates standard SNP files (such as S6P and S8P, corresponding to the number of ports of different windings). The files contain parameters such as S11, S21, S12, and S22 for each frequency point, providing an accurate passive network model for subsequent schematic integration. At the same time, the database can be called repeatedly to avoid repeated simulations of similar designs.

[0073] The circuit co-simulation unit is used to automatically embed the SNP file output by the passive matching network design unit into the circuit schematic and to complete the port docking with the active device model output by the active circuit design unit to build a complete millimeter-wave integrated circuit. The circuit co-simulation unit is also used to simulate the generated millimeter-wave integrated circuit and adjust the model or layout size generated by the passive matching network design unit according to the simulation results until all performance indicators meet the design requirements, and output the final millimeter-wave integrated circuit design result.

[0074] In this embodiment, the circuit co-simulation unit automatically calls the ADE (Analog Design Environment) simulation environment during simulation and configures the simulation type according to the design goals, including DC operating point analysis (determining device bias voltage / current), AC small signal analysis (verifying gain and bandwidth), load traction analysis (optimizing output power and efficiency), and harmonic balance analysis (evaluating nonlinear distortion).

[0075] After the circuit co-simulation unit completes the simulation, it compares the simulation results with the performance parameter requirements stored in the active circuit design unit. If there are deviations in the indicators (such as insufficient gain, excessive VSWR, or low efficiency), the results are automatically fed back to the passive matching network design unit. The passive matching network design unit adjusts the topology or layout size of the passive devices (or retrieves a new model from the model library), re-executes the simulation, and outputs an updated SNP file. The circuit co-simulation unit uses the updated SNP file to perform the simulation again until all performance indicators in the simulation results meet the design requirements, ultimately achieving closed-loop iterative optimization.

[0076] In one specific embodiment of the present invention, the circuit co-simulation unit operates as follows:

[0077] 1) Initialization preparation: Build the schematic diagram and the parameterized model of passive components. The interface impedance is strictly matched (50Ω). At the same time, set the key parameters in the circuit (such as transformer model, neutralizing capacitor value, and die size) as variables to facilitate batch modification and parameter scanning by the script.

[0078] 2) Fault tolerance mechanism design.

[0079] In this embodiment, the compatibility of the port number and frequency range of the SNP file with the schematic diagram is automatically checked during the integration process. If a port mismatch or file corruption occurs, the script will automatically issue an alarm and call a backup model to avoid simulation interruption.

[0080] 3) Ocean script automated simulation configuration.

[0081] In this embodiment, the script generates a customized Ocean script, covering the following core steps:

[0082] Cell Selection: Specify the schematic cell to be simulated, and automatically load the corresponding technology and model libraries. Simulation Type Configuration: Select simulation types in batches according to design goals: DC operating point analysis (determine the bias voltage / current at each stage), AC small-signal analysis (e.g., verifying gain and bandwidth from 40 GHz to 80 GHz), load pull analysis (optimize output power and PAE), and harmonic balance analysis (evaluate second / third harmonic distortion and ensure harmonic rejection ratio ≥30 dB). Result Output Settings: Select the performance index curves to be exported (e.g., gain-frequency curve, PAE-output power curve, VSWR-frequency curve), and save the numerical results as a CSV file with fields including "frequency (GHz), gain (dB), PAE (%), output power (dBm), VSWR" for subsequent data processing. Batch Execution of Simulation Tasks: The script automatically submits simulation tasks, supports multi-threaded parallel processing (simulating multiple transformer models of integrated circuits simultaneously), and automatically generates a simulation report after simulation completion, marking whether the design specifications are met.

[0083] 4) Data feedback and iterative optimization.

[0084] In this embodiment, the CSV file exported from the ADE simulation is visualized using a Python script (or Origin tool) to obtain curves and graphs of various performance indicators. Engineers use the feedback from these graphs for iterative optimization: if the gain is insufficient (e.g., the gain at a certain frequency point is only 18 dB, failing to reach the 20 dB target), a transformer model with higher coupling is selected from the model library generated by the passive matching network design unit (e.g., changing the input single-turn to double-turn), and the simulation is re-executed. The iterative process is automatically driven by the script until the performance indicators at all frequency points meet the performance parameter requirements, forming a closed-loop optimization.

[0085] This invention also proposes an automated design method for millimeter-wave integrated circuits based on the above system, comprising:

[0086] Based on the performance parameter requirements and design constraints of the millimeter-wave integrated circuit to be designed, the active device model of the millimeter-wave integrated circuit is generated according to the predetermined process rules.

[0087] Based on the set impedance matching target and frequency band requirements, a passive device model in the millimeter-wave integrated circuit is generated; then, based on the passive device model, a corresponding layout is generated and simulation is performed to obtain the corresponding SNP file;

[0088] The SNP file is embedded into a preset circuit schematic and port-connected with the active device model to construct a complete millimeter-wave integrated circuit. Then, the generated millimeter-wave integrated circuit is simulated, and the passive device model or layout size is adjusted according to the simulation results until all performance indicators meet the performance parameter requirements, and the final millimeter-wave integrated circuit design result is output.

[0089] Furthermore, the method described in this embodiment will be further explained below with reference to a specific example (based on TSMC 65 nm CMOS process).

[0090] In this embodiment, the millimeter-wave integrated circuit automated design method includes the following steps:

[0091] 1) Performance index setting.

[0092] In this embodiment, the application scenario of the millimeter-wave power amplifier to be designed is defined as an ultra-wideband communication system. The core indicators are set as follows: operating frequency band 40 GHz-80 GHz, small signal gain ≥20 dB (fluctuation ≤±1 dB) across the entire bandwidth, power-added efficiency (PAE) ≥15%, saturated output power ≥15 dBm, input / output standing wave ratio (VSWR) ≤1.5:1, supply voltage 1.8 V, and chip area ≤1.5 mm × 1 mm.

[0093] 2) Construction of active circuits.

[0094] In this embodiment, a three-stage common-source amplification structure is adopted, and the die size and parameters of each stage are determined:

[0095] First stage (driver stage): gate width 24 μm / 60 um, neutralization capacitor 16 fF, bias voltage Vgs=0.6 V, responsible for low noise amplification, providing about 8 dB gain;

[0096] Second stage (intermediate stage): gate width 48 μm / 60 um, neutralization capacitor 20 fF, bias voltage Vgs=0.6 V, balancing gain and efficiency, providing approximately 7 dB gain;

[0097] Third stage (output stage): gate width 96 μm / 60 um, neutralization capacitor 25 fF, bias voltage Vgs=0.6 V, maximizes output power, and provides approximately 5 dB gain;

[0098] Short-distance interconnects (0.8 μm width, ≤8 μm length) are used between each level, with M9 metal wiring on the top layer.

[0099] 3) Construction of electromagnetic simulation files for passive matching networks.

[0100] In this embodiment, electromagnetic simulation files for various transformer models are constructed based on the M8 and M9 metal layers of TSMC's 65 nm process, specifically including:

[0101] Input side: Single-turn transformer. Output side: Single-turn transformer. All transformer layouts are automatically drawn using Skill scripts, submitted for EMX simulation (frequency 10 GHz-100 GHz), and a passive network simulation database is built.

[0102] 4) Automatic schematic integration and ADE co-simulation, specifically including:

[0103] Schematic parameterization: Create a schematic cell “PA_40-80 GHz”, and integrate the SNP files of the active circuit model and the transformer model respectively to form multiple candidate schemes.

[0104] Ocean script configuration: Select simulation type (DC, AC small signal, load traction, harmonic balance), set output parameters (gain, PAE, output power, VSWR), and export CSV file.

[0105] 5) Iterative optimization and result verification.

[0106] In this embodiment, the exported performance curve is plotted using a Python script to select the optimal solution (input double-turn transformer + output single-turn transformer):

[0107] The gain across the entire bandwidth is 20.5-21.8 dB (fluctuation ≤ ±0.65 dB), PAE is 15.8%-17.2%, output power is 15.3-16.1 dBm, and VSWR is ≤ 1.4:1. All indicators meet the design requirements, and the design is finally completed.

[0108] This embodiment fully verifies the feasibility and efficiency of the method of the present invention. By automating the process, the design cycle of ultra-wideband millimeter-wave power amplifiers is shortened from the traditional 4-6 weeks to less than 1 week, and the consistency and reliability of the design results are significantly improved, providing a practical solution for the large-scale design and mass production of millimeter-wave power amplifiers.

Claims

1. A millimeter-wave integrated circuit automated design system, characterized in that, include: The system includes an active circuit design unit, a passive matching network design unit, and a circuit co-simulation unit; wherein the active circuit design unit and the passive matching network design unit are respectively connected to the circuit co-simulation unit. The active circuit design unit is used to generate active device models of the millimeter-wave integrated circuit according to the performance parameter requirements and design constraints of the millimeter-wave integrated circuit to be designed, and in accordance with predetermined process rules. The passive matching network design unit is used to generate a passive device model in the millimeter-wave integrated circuit according to the set impedance matching target and frequency band requirements; then, based on the passive device model, a corresponding layout is generated and simulated to obtain the corresponding SNP file. The circuit co-simulation unit is used to embed the SNP file output by the passive matching network design unit into a preset circuit schematic and to complete port docking with the active device model output by the active circuit design unit to construct a complete millimeter-wave integrated circuit. Then, the generated millimeter-wave integrated circuit is simulated, and the model or layout size generated by the passive matching network design unit is adjusted according to the simulation results until all performance indicators meet the performance parameter requirements, and the final millimeter-wave integrated circuit design result is output.

2. The system according to claim 1, characterized in that, Also includes: The active device model reserves an interface for a passive matching network.

3. The system according to claim 1, characterized in that, Also includes: The circuit co-simulation unit configures the simulation type according to the design objectives during simulation; The simulation types include: DC operating point analysis, AC small-signal analysis, load traction analysis, and harmonic balance analysis.

4. The system according to claim 1, characterized in that, The workflow of the passive matching network design unit includes: 1) The passive matching network design unit uses the impedance circle diagram algorithm to select the optimal matching network topology for passive devices based on the set impedance matching target and frequency band requirements, and obtains the passive device model. 2) Based on the network topology results and according to the preset process library rules, the passive matching network design unit generates the matching network layout and simultaneously completes the metal layer allocation, grounding structure design and electromagnetic compatibility optimization. 3) By calling the EMX electromagnetic simulation tool, setting the simulation frequency point and mesh generation accuracy, full-wave electromagnetic simulation is performed on the matching network layout to extract port S-parameters, parasitic capacitance or inductance and electromagnetic coupling parameters. 4) After the simulation is completed, an SNP file is generated, which contains port network parameters at each frequency point in the wideband.

5. The system according to claim 4, characterized in that, Also includes: The passive matching network design unit will generate passive device models to form a model library.

6. The system according to claim 5, characterized in that, Also includes: After the circuit co-simulation unit completes the simulation, it compares the simulation results with the performance parameter requirements stored in the active circuit design unit. If there is a deviation in the performance indicators, the deviation is fed back to the passive matching network design unit; the passive matching network design unit adjusts the topology or layout size of the passive device, or retrieves a new model from the model library; the passive matching network design unit re-executes the simulation and outputs an updated SNP file. The circuit co-simulation unit uses the updated SNP file to perform simulation again until all performance indicators in the simulation results meet the performance parameter requirements, and the millimeter-wave integrated circuit design is completed.

7. A method for automated design of millimeter-wave integrated circuits based on the system described in any one of claims 1-6, characterized in that, include: Based on the performance parameter requirements and design constraints of the millimeter-wave integrated circuit to be designed, the active device model of the millimeter-wave integrated circuit is generated according to the predetermined process rules. Based on the set impedance matching target and frequency band requirements, a passive device model in the millimeter-wave integrated circuit is generated; then, based on the passive device model, a corresponding layout is generated and simulation is performed to obtain the corresponding SNP file; The SNP file is embedded into a preset circuit schematic and port-connected with the active device model to construct a complete millimeter-wave integrated circuit. Then, the generated millimeter-wave integrated circuit is simulated, and the passive device model or layout size is adjusted according to the simulation results until all performance indicators meet the performance parameter requirements, and the final millimeter-wave integrated circuit design result is output.

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