A deep sequence inference engine dynamic computing power allocation architecture and acceleration method

Abstract

This invention discloses a dynamic computing power allocation architecture and acceleration method for a deep sequence inference engine, belonging to the interdisciplinary field of integrated circuit design and artificial intelligence hardware accelerators. It is used for bioelectrical signal detection and includes an off-chip analog front-end, a multi-scale coarse-grained entropy sentinel circuit, a programmable adaptive threshold register, a main deep sequence inference engine, an adaptive learning engine, a five-state finite state automaton, a fixed-priority interrupt arbitrator, a multi-voltage domain hierarchical clock gating network, a host computer configuration bus, a diagnostic output bus, and a host computer. This invention achieves signal complexity prediction at the physical layer by placing an independent entropy sensing circuit before the main deep inference engine; and by combining a programmable adaptive threshold register and a shadow caching mechanism, it achieves nonlinear allocation and dynamic precision switching of computing resources while ensuring medical-grade computational accuracy, fundamentally solving the energy efficiency and safety contradiction of high-performance deep sequence models in biosignal processing.

Description

Technical Field

[0001] This invention discloses a dynamic computing power allocation architecture and acceleration method for a deep sequence inference engine, belonging to the interdisciplinary technical field of integrated circuit design and artificial intelligence hardware accelerators. Background Technology

[0002] In recent years, deep sequence inference models (such as Transformer, state space models like Mamba, and higher-order RNNs) have demonstrated superior long-range dependency modeling capabilities, showcasing accuracy far exceeding that of traditional local processing models (such as CNNs) in pathological detection, motor intent recognition, and rehabilitation training based on bioelectrical signals (such as EEG and EMG). However, deploying these high-performance deep models in implantable or wearable edge devices faces three major challenges.

[0003] To ensure the preservation of crucial pathological features (such as neuronal firing pulses), bioelectrical signals typically require sampling rates as high as 1 kHz or even 10 kHz. However, for most of the monitoring time, the signal remains in a stable baseline state or contains only environmental noise, resulting in extremely sparse effective physiological information over time. Existing hardware accelerators (such as GPUs and NPUs) typically employ static computation, performing full matrix operations regardless of whether the input signal contains valuable information. This leads to significant wasted power consumption during signal stationary periods, severely limiting the battery life of battery-powered devices.

[0004] Software pruning, by discarding certain feature units or data nodes in early layers, cannot be recalled in subsequent layers. In medical diagnosis, mistakenly pruning crucial prodromal features (such as weak arrhythmias before epileptic seizures) due to weak signals can lead to serious misdiagnosis. Most dynamic mechanisms require waking up the main computation pipeline to run the first few layers (pre-computation) before determining the importance of the current data frame. During this time, the power consumption of data movement and preliminary computation has already occurred, making "zero-power standby" impossible. The bioelectrical signal baselines differ significantly among individuals, and the entropy features of the same patient are dynamically changing at different pathological stages (such as fatigue levels or drug interventions). Current hardware accelerators lack a physical triggering mechanism that can adaptively adjust based on individual characteristics. Existing hard-wired logic often only allows for static optimization for specific datasets and cannot achieve non-linear, adaptive allocation of computing power in complex clinical environments.

[0005] To reduce power consumption, edge devices widely employ quantization techniques with a bit width of 4 or lower. However, at critical characteristic points of biological signals (such as sudden changes in muscle explosive power or arrhythmia points), low-bit-width calculations often produce large rounding errors due to insufficient dynamic range, leading to a collapse in the confidence of the output results. Existing technologies lack a closed-loop protection logic implemented at the hardware level that possesses "prediction-evaluation-backtracking" capabilities. Summary of the Invention

[0006] The purpose of this invention is to provide a dynamic computing power allocation architecture and acceleration method for a deep sequence reasoning engine, in order to solve the problems in the prior art, such as the imbalance between the high sampling rate of bioelectric signals and the extreme sparsity of information, data irreversibility, prediction lag, low accuracy, and insufficient adaptability of hardware architecture to individual physiological differences.

[0007] A dynamic computing power allocation architecture for a deep sequence reasoning engine includes: Off-chip analog front-end, multi-scale coarse-grained entropy sentinel circuit, programmable adaptive threshold register, main deep sequence inference engine, adaptive learning engine, five-state finite state automaton, fixed priority interrupt arbiter, multi-voltage domain hierarchical clock gating network, host computer configuration bus, diagnostic output bus and host computer.

[0008] The safety redundancy subsystem includes a calibration module, a shadow statistics unit, a multi-library threshold register group, an automatic state switching controller, an asymmetric precision dual-path distributor, a shadow FIFO, a pipeline embedded confidence extractor, and a confidence-driven backtracking interrupt controller. The multi-scale coarse-grained entropy sentinel circuit includes a successive approximation ADC, a ring buffer register, a multi-scale coarse-grained engine, a multi-phase shift register network, a symbol dynamics comparator array, a sliding window Popcount entropy approximation estimator, a nonlinear threshold trigger controller, and a clock gating unit. The multiphase shift register network includes a divider clock tap, a depth-accumulating shift register, and an arithmetic right shifter; The sign dynamics comparator array includes digital comparators, single-stage D flip-flops, and XOR gates; The sliding window Popcount entropy approximation estimator includes a bit counter and a shift adder; The nonlinear threshold trigger controller and clock gating unit include a hysteresis comparator and an integrated clock gating unit; The calibration module includes an EWMA filter, an adder, and a shifter; The shadow statistics unit includes a fixed-point accumulator and a maximum value comparator; The automatic state selection controller includes a subtractor, a priority comparison tree, and a hysteresis counter; The pipeline's embedded confidence extractor includes a maximum value comparison tree and a fixed-point comparator; The main deep sequence reasoning engine includes reconfigurable matrix computation units; The reconfigurable matrix computation unit includes a data path multiplexer and a multiply-accumulate unit.

[0009] The bioelectrical signal is amplified and anti-aliasing filtered by an off-chip analog front-end. The result is then sampled using a successive approximation ADC at a fixed sampling frequency to obtain the original sampled signal sequence. , This is a discrete-time index for the global sampling time. Let the ADC quantization bit width be... , for: ; In the formula, For the first Digital bioelectric sampling values ​​at each moment, For ADC sampling frequency, This is a continuous voltage signal output from an external analog front-end. For successive approximation analog-to-digital converters; Based on the number of sampling points Construct a circular buffer to write pointer address The original sampled signal sequence is written into the ring buffer register; The multi-scale coarsening engine reads data from the ring buffer register. ,definition Parallel coarse-grained channels, setting time scale factor , , , To achieve parallel coarse-grained channel indexing, an arithmetic right shifter combined with a time scaling factor is used to approximate coarse-grainedness of the original sampled signal sequence: ; In the formula, For scale The coarse-grained subsequence below, For indexing coarse-grained subsequences, For each coarse-grained channel, a discrete-time index of the sampling time. , This is an arithmetic right shift operation. This is the floor symbol.

[0010] Will A digital comparator is used to map the data into a binary symbol bit stream. The XOR gate is used to calculate the change of adjacent symbols bit by bit to obtain the direction flipping flag sequence. Set the half length of the sliding window A sliding window is constructed, and a bit counter is used to count the flip rate within the sliding window. The flip rate is then normalized using a normalization formula, and this normalization is used as the current value. The entropy approximation, using Weighting coefficients Calculate multi-scale fusion index ; Define the double-threshold hysteresis comparison logic in the hysteresis comparator to obtain the wake-up or sleep state flag. : ; In the formula, The wake-up threshold, The sleep threshold, In the wake-up state, In hibernation mode; right Perform glitch-free processing to output a standard signal, and simultaneously set the minimum wake-up duration. Define the wake-up extension counter : ; In the formula, To find the maximum value; Output final gating enable signal : ; In the formula, For logical OR symbols.

[0011] Upon initial startup, the main deep sequence inference engine remains forcibly enabled. The multi-scale coarse-grained entropy sentinel circuit operates but does not participate in gating decisions, and continuously outputs... The calibration module expands the EWMA recursive formula into a shift-addition form using an EWMA filter, shifter, and adder, and calculates the EWMA estimate of the baseline complexity mean. The mean absolute deviation (MAD) is used to calculate the baseline complexity of variance estimation. : ; ; In the formula, The number of shifts for the smoothing factor; When calibration is complete, output a calibration completion flag. and utilize and Calculate the wake-up threshold after initial calibration and the sleep threshold after initial calibration And write it to the programmable adaptive threshold register; The shadow statistical unit is used to maintain the entropy mean of the current active frame. and peak At the end of each frame inference cycle Calculate the threshold margin metric for the current frame: ; The shadow statistics unit will be the current frame's , and Save to the programmable adaptive threshold register, then save the data in the shadow statistics unit. , and Reset to zero, prepare for the next frame.

[0012] The classification confidence score output after inference is based on the main deep sequence inference engine. and category tags , , , In the diagram, 0 represents normal and 1 represents pathological. This is the moment when the current frame inference cycle ends; Adaptive learning engine defines feedback signals : ; In the formula, To motivate, 0 represents punishment, and 0 represents neutrality. This is a near-loss event. For high confidence threshold; A simplified LMS algorithm is used to adjust the threshold by incrementing or decrementing it with a fixed step size. ; ; In the formula, The wake-up threshold at the end of the current frame inference cycle. The sleep threshold at the end of the current frame inference cycle. The learning rate; The absolute safety clamping lower boundary is set by the threshold preset by the host computer. and upper boundary By introducing hardware clamping logic, the updated wake-up threshold is obtained. and lower wake-up threshold And write it to the programmable adaptive threshold register: ; ; Set a fixed hysteresis bandwidth ,satisfy: ; It has A set of multi-library threshold registers is formed, and each set of multi-library threshold registers stores a pair of thresholds and corresponding benchmark statistics. The benchmark statistics include the reference benchmark mean and reference benchmark deviation corresponding to the current threshold. ; In the formula, For the first The complete parameter set of the group multi-library threshold register, For the first The wake-up threshold of the group multi-library threshold register, For the first The sleep threshold of the group multi-library threshold register. For the first The reference baseline mean corresponding to the group threshold. For the first The reference baseline deviation corresponding to the group threshold This is the index for the multi-library threshold register; Through the Perform EWMA filtering to extract The changing trend of low-frequency signal energy is used as an indicator of low-frequency signal energy. ,calculate In each group of multi-library threshold registers The distance is used to select the multi-library threshold register with the smallest distance as the current active library, and the hysteresis counter is used. Set the threshold for library switching hysteresis counting. When the new candidate pool wins consecutively After one cycle, the state automatic switching controller switches scenes, outputs the index of the currently active threshold library, and sets the wake-up threshold of the currently active library. and sleep threshold Write and update the wake-up threshold in the programmable adaptive threshold register. and sleep threshold : ; .

[0013] If the output is The value is equal to 1, so The process is divided into two branches. The first branch uses symmetrical uniform quantization. Perform quantization compression, setting the original sampled signal to Bit width, set the target quantization bit width of the first branch path to be... : ; ; In the formula, This is the quantized, low-precision signal. This is the quantization scaling factor. Round to the nearest integer; The second branch utilizes shadow FIFO storage. The depth of the shadow FIFO is : ; In the formula, The signal length for a single frame of inference. Main inference engine pipeline delay margin; like Shadow FIFO is not written to; Synchronous write to a shallow FIFO with a depth at the frame level, writing once per frame: ; In the formula, The end time of the current frame inference cycle , Input data for a shallow FIFO.

[0014] By utilizing the maximum comparison tree in the pipeline's embedded confidence extractor, the probability normalization vector output by the main deep sequence inference engine is extracted. Maximum confidence level, as the maximum probability value , , The total number of categories; Extract the second-largest confidence level as the second-largest probability value, and calculate... The difference between the second-highest probability value and the second-highest probability value is used as the certainty of the classification result. Set the security confidence threshold. Alertness confidence threshold and safety margin threshold A three-level confidence state flag is defined using a fixed-point comparator. The three confidence levels include safe, alert, and dangerous: ; In the formula, For safety, As a warning, It is dangerous; Set the count threshold for continuous alert triggering interruption. When the confidence level is dangerous or continuous When the frame is alert, the confidence-driven backtracking interrupt controller generates a backtracking interrupt signal. It also sends a precision mode switching command to the main deep sequence inference engine. If a backtracking interrupt signal is generated, If no backtracking interrupt signal is generated, ; when At that time, the data path multiplexer of the reconfigurable matrix computation unit is based on The mode of the multiply-accumulate unit is changed within a single clock cycle by... Switch to At the same time, the read pointer of the shadow FIFO rewinds to the beginning of the current frame and reads out sequentially. Corresponding raw data ,Will Input data path multiplexer replacement The reconfigurable matrix calculation unit is re-entered, and the calculation result is input into the pipeline's embedded confidence extractor to re-evaluate the confidence level. The number of consecutive safe frames required for accuracy recovery is then set. If the reassessed confidence level does not meet the interruption condition, the pipeline-embedded confidence extractor inputs an interrupt clear signal to the confidence-driven backtracking interrupt controller. The confidence-driven backtracking interrupt controller clears the interrupt flag, and the main deep sequence inference engine resumes operation. If the reassessed confidence level reaches the interruption condition, the main deep sequence inference engine will continue to be used. Process subsequent frames until continuous Since none of the frame confidence scores meet the interruption criteria, the main deep sequence inference engine resumes operation. ; Define a soft drop buffer, which is a circular FIFO with a depth of [value missing]. ,when At this time, the original data is still written to the soft discard buffer. When the soft discard buffer is full, the oldest data is overwritten, and only the original data is retained. One sampling point; when the confidence-driven backtracking interrupt controller generates a backtracking interrupt signal, and And the confidence level is lower than the special recall threshold. Triggering delayed recall interruption Delayed recall interruption includes setting the maximum backtracking frame. The read pointer of the soft-discard buffer starts back from the most recent data. Frames, the data read is in The precision input is used for supplementary inference by the main deep sequence inference engine. The inference result of the current frame and the supplementary inference result are jointly evaluated using a logical OR operation to obtain the final classification result after joint evaluation. Complete the delayed recall interruption and output the recall reasoning completion flag. Clear backtracked data from the soft discard buffer. Frame data.

[0015] Five global states of the system are defined using a five-state finite state automaton, including deep sleep. Initial calibration Low-precision inference High-precision rollback and delayed recall ; Define the input signal vector, including , , , , and ; Define state transition function : ; ; ; ; ; In the formula, For precision recovery counter; Define the set of interrupt sources and their corresponding priorities using a fixed-priority interrupt arbitrator, and output the highest-priority interrupt currently in effect. Use a cascaded priority encoder to output the arbitration output code. When a high-priority interrupt is in progress, low-priority interrupts are suspended in the fixed-priority interrupt arbiter and are processed sequentially. A multi-voltage domain hierarchical clock gating network is used to partition the power domain, dividing it into... , and , This includes a multi-scale coarse-grained entropy sentinel circuit, a soft drop buffer, a five-state finite state automaton, and a fixed-priority interrupt arbiter; Includes Tensor Core, Shadow FIFO, and asymmetric precision dual-path distributor; This includes a shadow statistics unit, an adaptive learning engine, a multi-library threshold register group, and an automatic state switching controller; Define power domain enable functions. Each power domain includes an independent voltage regulator interface and a clock gating tree. Each power domain is gated through the clock gating tree. Define signal routing function ,include , , , , , , , , and frame completion signal The transmission is controlled by a five-state finite state automaton. ; Communicate with the host computer via the SPI or I²C host computer configuration bus. Configuration parameters include wake-up threshold sensitivity coefficient. Dormancy threshold sensitivity coefficient , , , , , , , , , , , , Calculation unit down-division ratio , , Shift bits of active intra-frame EWMA Shift bits of slow-varying EWMA , All configuration parameters are mapped to programmable registers; The current status is reported to the host computer in real time via the diagnostic output bus, including... , , , , , , Cumulative count of backtracking events Cumulative count of recall events .

[0016] A dynamic acceleration method for a deep sequence inference engine, employing a dynamic computing power allocation architecture for the deep sequence inference engine, includes: S1. The equipment is calibrated to establish a benchmark. , will benchmark Write to a programmable adaptive threshold register; a multi-scale coarse-grained entropy sentinel circuit continuously monitors bioelectrical signals; when... The main deep sequence reasoning engine remains off; S2, when Multi-scale coarse-grained entropy sentinel circuit output To the main deep sequence reasoning engine, the main deep sequence reasoning engine uses Standard operation, shadow FIFO synchronous writing ; S3. When a backtracking interrupt signal is generated, the shadow FIFO reads out. The main deep sequence reasoning engine is Recalculate the confidence level. Feedback is sent to the adaptive learning engine until the confidence-driven backtracking interrupt controller is triggered. Calculate the final classification result; S4, Main Deep Sequence Inference Engine Resumes Operation Later, when At this point, the multi-library threshold register group stores all the thresholds for the entire process, and returns to step S1.

[0017] Compared with existing technologies, the present invention has the following advantages: The present invention achieves prediction of signal complexity at the physical layer by placing an independent entropy sensing circuit in front of the main deep inference engine; and by combining a programmable adaptive threshold register and a shadow caching mechanism, it achieves nonlinear allocation of computing resources and dynamic precision switching while ensuring medical-grade computing accuracy, fundamentally solving the contradiction between energy efficiency and safety of high-performance deep sequence models in biological signal processing. Attached Figure Description

[0018] Figure 1 This is a flowchart of the technology of this invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention are described clearly and completely below. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0020] A dynamic computing power allocation architecture for a deep sequence reasoning engine includes: Off-chip analog front-end, multi-scale coarse-grained entropy sentinel circuit, programmable adaptive threshold register, main deep sequence inference engine, adaptive learning engine, five-state finite state automaton, fixed priority interrupt arbiter, multi-voltage domain hierarchical clock gating network, host computer configuration bus, diagnostic output bus and host computer.

[0021] The safety redundancy subsystem includes a calibration module, a shadow statistics unit, a multi-library threshold register group, an automatic state switching controller, an asymmetric precision dual-path distributor, a shadow FIFO, a pipeline embedded confidence extractor, and a confidence-driven backtracking interrupt controller. The multi-scale coarse-grained entropy sentinel circuit includes a successive approximation ADC, a ring buffer register, a multi-scale coarse-grained engine, a multi-phase shift register network, a symbol dynamics comparator array, a sliding window Popcount entropy approximation estimator, a nonlinear threshold trigger controller, and a clock gating unit. The multiphase shift register network includes a divider clock tap, a depth-accumulating shift register, and an arithmetic right shifter; The sign dynamics comparator array includes digital comparators, single-stage D flip-flops, and XOR gates; The sliding window Popcount entropy approximation estimator includes a bit counter and a shift adder; The nonlinear threshold trigger controller and clock gating unit include a hysteresis comparator and an integrated clock gating unit; The calibration module includes an EWMA filter, an adder, and a shifter; The shadow statistics unit includes a fixed-point accumulator and a maximum value comparator; The automatic state selection controller includes a subtractor, a priority comparison tree, and a hysteresis counter; The pipeline's embedded confidence extractor includes a maximum value comparison tree and a fixed-point comparator; The main deep sequence reasoning engine includes reconfigurable matrix computation units; The reconfigurable matrix computation unit includes a data path multiplexer and a multiply-accumulate unit.

[0022] The bioelectrical signal is amplified and anti-aliasing filtered by an off-chip analog front-end. The result is then sampled using a successive approximation ADC at a fixed sampling frequency to obtain the original sampled signal sequence. , This is a discrete-time index for the global sampling time. Let the ADC quantization bit width be... , for: ; In the formula, For the first Digital bioelectric sampling values ​​at each moment, For ADC sampling frequency, This is a continuous voltage signal output from an external analog front-end. For successive approximation analog-to-digital converters; Based on the number of sampling points Construct a circular buffer to write pointer address The original sampled signal sequence is written into the ring buffer register; The multi-scale coarsening engine reads data from the ring buffer register. ,definition Parallel coarse-grained channels, setting time scale factor , , , To achieve parallel coarse-grained channel indexing, an arithmetic right shifter combined with a time scaling factor is used to approximate coarse-grainedness of the original sampled signal sequence: ; In the formula, For scale The coarse-grained subsequence below, For indexing coarse-grained subsequences, For each coarse-grained channel, a discrete-time index of the sampling time. , This is an arithmetic right shift operation. This is the floor symbol.

[0023] Will A digital comparator is used to map the data into a binary symbol bit stream. The XOR gate is used to calculate the change of adjacent symbols bit by bit to obtain the direction flipping flag sequence. Set the half length of the sliding window A sliding window is constructed, and a bit counter is used to count the flip rate within the sliding window. The flip rate is then normalized using a normalization formula, and this normalization is used as the current value. The entropy approximation, using Weighting coefficients Calculate multi-scale fusion index ; Define the double-threshold hysteresis comparison logic in the hysteresis comparator to obtain the wake-up or sleep state flag. : ; In the formula, The wake-up threshold, The sleep threshold, In the wake-up state, In hibernation mode; right Perform glitch-free processing to output a standard signal, and simultaneously set the minimum wake-up duration. Define the wake-up extension counter : ; In the formula, To find the maximum value; Output final gating enable signal : ; In the formula, For logical OR symbols.

[0024] Upon initial startup, the main deep sequence inference engine remains forcibly enabled. The multi-scale coarse-grained entropy sentinel circuit operates but does not participate in gating decisions, and continuously outputs... The calibration module expands the EWMA recursive formula into a shift-addition form using an EWMA filter, shifter, and adder, and calculates the EWMA estimate of the baseline complexity mean. The mean absolute deviation (MAD) is used to calculate the baseline complexity of variance estimation. : ; ; In the formula, The number of shifts for the smoothing factor; When calibration is complete, output a calibration completion flag. and utilize and Calculate the wake-up threshold after initial calibration and the sleep threshold after initial calibration And write it to the programmable adaptive threshold register; The shadow statistical unit is used to maintain the entropy mean of the current active frame. and peak At the end of each frame inference cycle Calculate the threshold margin metric for the current frame: ; The shadow statistics unit will be the current frame's , and Save to the programmable adaptive threshold register, then save the data in the shadow statistics unit. , and Reset to zero, prepare for the next frame.

[0025] The classification confidence score output after inference is based on the main deep sequence inference engine. and category tags , , , In the diagram, 0 represents normal and 1 represents pathological. This is the moment when the current frame inference cycle ends; Adaptive learning engine defines feedback signals : ; In the formula, To motivate, 0 represents punishment, and 0 represents neutrality. This is a near-loss event. For high confidence threshold; A simplified LMS algorithm is used to adjust the threshold by incrementing or decrementing it with a fixed step size. ; ; In the formula, The wake-up threshold at the end of the current frame inference cycle. The sleep threshold at the end of the current frame inference cycle. The learning rate; The absolute safety clamping lower boundary is set by the threshold preset by the host computer. and upper boundary By introducing hardware clamping logic, the updated wake-up threshold is obtained. and lower wake-up threshold And write it to the programmable adaptive threshold register: ; ; Set a fixed hysteresis bandwidth ,satisfy: ; It has A set of multi-library threshold registers is formed, and each set of multi-library threshold registers stores a pair of thresholds and corresponding benchmark statistics. The benchmark statistics include the reference benchmark mean and reference benchmark deviation corresponding to the current threshold. ; In the formula, For the first The complete parameter set of the group multi-library threshold register, For the first The wake-up threshold of the group multi-library threshold register, For the first The sleep threshold of the group multi-library threshold register. For the first The reference baseline mean corresponding to the group threshold. For the first The reference baseline deviation corresponding to the group threshold This is the index for the multi-library threshold register; Through the Perform EWMA filtering to extract The changing trend of low-frequency signal energy is used as an indicator of low-frequency signal energy. ,calculate In each group of multi-library threshold registers The distance is used to select the multi-library threshold register with the smallest distance as the current active library, and the hysteresis counter is used. Set the threshold for library switching hysteresis counting. When the new candidate pool wins consecutively After one cycle, the state automatic switching controller switches scenes, outputs the index of the currently active threshold library, and sets the wake-up threshold of the currently active library. and sleep threshold Write and update the wake-up threshold in the programmable adaptive threshold register. and sleep threshold : ; .

[0026] If the output is The value is equal to 1, so The process is divided into two branches. The first branch uses symmetrical uniform quantization. Perform quantization compression, setting the original sampled signal to Bit width, set the target quantization bit width of the first branch path to be... : ; ; In the formula, This is the quantized, low-precision signal. This is the quantization scaling factor. Round to the nearest integer; The second branch utilizes shadow FIFO storage. The depth of the shadow FIFO is : ; In the formula, The signal length for a single frame of inference. Main inference engine pipeline delay margin; like Shadow FIFO is not written to; Synchronous write to a shallow FIFO with a depth at the frame level, writing once per frame: ; In the formula, The end time of the current frame inference cycle , Input data for a shallow FIFO.

[0027] By utilizing the maximum comparison tree in the pipeline's embedded confidence extractor, the probability normalization vector output by the main deep sequence inference engine is extracted. Maximum confidence level, as the maximum probability value , , The total number of categories; Extract the second-largest confidence level as the second-largest probability value, and calculate... The difference between the second-highest probability value and the second-highest probability value is used as the certainty of the classification result. Set the security confidence threshold. Alertness confidence threshold and safety margin threshold A three-level confidence state flag is defined using a fixed-point comparator. The three confidence levels include safe, alert, and dangerous: ; In the formula, For safety, As a warning, It is dangerous; Set the count threshold for continuous alert triggering interruption. When the confidence level is dangerous or continuous When the frame is alert, the confidence-driven backtracking interrupt controller generates a backtracking interrupt signal. It also sends a precision mode switching command to the main deep sequence inference engine. If a backtracking interrupt signal is generated, If no backtracking interrupt signal is generated, ; when At that time, the data path multiplexer of the reconfigurable matrix computation unit is based on The mode of the multiply-accumulate unit is changed within a single clock cycle by... Switch to At the same time, the read pointer of the shadow FIFO rewinds to the beginning of the current frame and reads out sequentially. Corresponding raw data ,Will Input data path multiplexer replacement The reconfigurable matrix calculation unit is re-entered, and the calculation result is input into the pipeline's embedded confidence extractor to re-evaluate the confidence level. The number of consecutive safe frames required for accuracy recovery is then set. If the reassessed confidence level does not meet the interruption condition, the pipeline-embedded confidence extractor inputs an interrupt clear signal to the confidence-driven backtracking interrupt controller. The confidence-driven backtracking interrupt controller clears the interrupt flag, and the main deep sequence inference engine resumes operation. If the reassessed confidence level reaches the interruption condition, the main deep sequence inference engine will continue to be used. Process subsequent frames until continuous Since none of the frame confidence scores meet the interruption criteria, the main deep sequence inference engine resumes operation. ; Define a soft drop buffer, which is a circular FIFO with a depth of [value missing]. ,when At this time, the original data is still written to the soft discard buffer. When the soft discard buffer is full, the oldest data is overwritten, and only the original data is retained. One sampling point; when the confidence-driven backtracking interrupt controller generates a backtracking interrupt signal, and And the confidence level is lower than the special recall threshold. Triggering delayed recall interruption Delayed recall interruption includes setting the maximum backtracking frame. The read pointer of the soft-discard buffer starts back from the most recent data. Frames, the data read is in The precision input is used for supplementary inference by the main deep sequence inference engine. The inference result of the current frame and the supplementary inference result are jointly evaluated using a logical OR operation to obtain the final classification result after joint evaluation. Complete the delayed recall interruption and output the recall reasoning completion flag. Clear backtracked data from the soft discard buffer. Frame data.

[0028] Five global states of the system are defined using a five-state finite state automaton, including deep sleep. Initial calibration Low-precision inference High-precision rollback and delayed recall ; Define the input signal vector, including , , , , and ; Define state transition function : ; ; ; ; ; In the formula, For precision recovery counter; Define the set of interrupt sources and their corresponding priorities using a fixed-priority interrupt arbitrator, and output the highest-priority interrupt currently in effect. Use a cascaded priority encoder to output the arbitration output code. When a high-priority interrupt is in progress, low-priority interrupts are suspended in the fixed-priority interrupt arbiter and are processed sequentially. A multi-voltage domain hierarchical clock gating network is used to partition the power domain, dividing it into... , and , This includes a multi-scale coarse-grained entropy sentinel circuit, a soft drop buffer, a five-state finite state automaton, and a fixed-priority interrupt arbiter; Includes Tensor Core, Shadow FIFO, and asymmetric precision dual-path distributor; This includes a shadow statistics unit, an adaptive learning engine, a multi-library threshold register group, and an automatic state switching controller; Define power domain enable functions. Each power domain includes an independent voltage regulator interface and a clock gating tree. Each power domain is gated through the clock gating tree. Define signal routing function ,include , , , , , , , , and frame completion signal The transmission is controlled by a five-state finite state automaton. ; Communicate with the host computer via the SPI or I²C host computer configuration bus. Configuration parameters include wake-up threshold sensitivity coefficient. Dormancy threshold sensitivity coefficient , , , , , , , , , , , , Calculation unit down-division ratio , , Shift bits of active intra-frame EWMA Shift bits of slow-varying EWMA , All configuration parameters are mapped to programmable registers; The current status is reported to the host computer in real time via the diagnostic output bus, including... , , , , , , Cumulative count of backtracking events Cumulative count of recall events .

[0029] A dynamic acceleration method for a deep sequence inference engine, employing a dynamic computing power allocation architecture for the deep sequence inference engine, includes: S1. The equipment is calibrated to establish a benchmark. , will benchmark Write to a programmable adaptive threshold register; a multi-scale coarse-grained entropy sentinel circuit continuously monitors bioelectrical signals; when... The main deep sequence reasoning engine remains off; S2, when Multi-scale coarse-grained entropy sentinel circuit output To the main deep sequence reasoning engine, the main deep sequence reasoning engine uses Standard operation, shadow FIFO synchronous writing ; S3. When a backtracking interrupt signal is generated, the shadow FIFO reads out. The main deep sequence reasoning engine is Recalculate the confidence level. Feedback is sent to the adaptive learning engine until the confidence-driven backtracking interrupt controller is triggered. Calculate the final classification result; S4, Main Deep Sequence Inference Engine Resumes Operation Later, when At this point, the multi-library threshold register group stores all the thresholds for the entire process, and returns to step S1.

[0030] like Figure 1As shown, the process of this invention is as follows: First, the device is calibrated to establish a personal baseline entropy. The personal baseline entropy is written into a programmable adaptive threshold register. A multi-scale coarse-grained entropy sentinel circuit continuously monitors bioelectrical signals. When the personal baseline entropy is less than the dormancy threshold, the main deep sequence inference engine remains off. When the personal baseline entropy is greater than or equal to the dormancy threshold, the multi-scale coarse-grained entropy sentinel circuit outputs a final gating enable signal (wake-up signal) to the main deep sequence inference engine. The main deep sequence inference engine operates at a 4-bit standard, and the shadow FIFO synchronously writes 16-bit data. When a backtracking interrupt signal is generated, the shadow FIFO reads out 16-bit data, the main deep sequence inference engine recalculates the confidence with the 16-bit data, and the backtracking interrupt signal is fed back to the adaptive learning engine until the confidence-driven backtracking interrupt controller triggers a delayed recall interrupt and calculates the final classification result. After the main deep sequence inference engine resumes using 4-bit data, when the final gating enable signal is a dormancy signal, the multi-library threshold register group stores all the thresholds of the entire process and returns to the initial step.

[0031] The processing steps of each module in this invention are as follows: The bioelectrical signal is input to an off-chip analog front-end for amplification and anti-aliasing filtering. The result is then sampled using a successive approximation ADC at a fixed sampling frequency to obtain the original sampled signal sequence. , This is a discrete-time index for the global sampling time. Let the ADC quantization bit width be... , for: ; In the formula, For the first Digital bioelectric sampling values ​​at each moment, For ADC sampling frequency, This is a continuous voltage signal output from an external analog front-end. For successive approximation analog-to-digital converters; Based on the number of sampling points Construct a circular buffer to write pointer address Write the original sampled signal sequence into the ring buffer register: ; ;n In the formula, For modulo operation, To analyze the length of the time window; The multi-scale coarsening engine reads data from the ring buffer register. ,definition Parallel coarse-grained channels, setting time scale factor , , , For parallel coarse-grained channel indexing, the frequency-divided clock taps are drawn from the system sample clock. (frequency Frequency division generation The depth-accumulating shift register is in Accumulate point by point under the drive, The accumulated value is output and cleared to zero on the rising edge. An arithmetic right shifter combined with a time scaling factor is used to approximate coarsen the original sampled signal sequence: ; In the formula, For scale The coarse-grained subsequence below, For indexing coarse-grained subsequences, For each coarse-grained channel, a discrete-time index of the sampling time. , For arithmetic right shift operation, This is the floor symbol.

[0032] Will Mapped to a binary sign bit stream using a digital comparator. ; In the formula, For scale Next The binary symbol at each moment; according to Constructing a binary symbolic bitstream : ; ; In the formula, For scale Effective length of the lower-signed bitstream; Use a single-machine D trigger gate to temporarily store the previous symbol The first-order difference between adjacent symbols is calculated using XOR gates: ; In the formula, For the direction flip flag, when At that time, the signal direction is reversed. This is a logical XOR operation; Defined in scale Below, by position Centered on the window, half the length flip rate for: ; In the formula, This is a bit counting operation; Normalized flip rate for: ; denominator Constraints , Approximately: ; ; In the formula, The number of bits for right shifting the window to normalization. The rounding up symbol; Multi-scale complexity fusion index for: ; In the formula, As weighting coefficients, a shift adder is used to... The constraint is a binary decimal; Define the double-threshold hysteresis comparison logic in the hysteresis comparator to obtain the wake-up or sleep state flag. The trigger signal needs to be glitched before being output as the gated clock of the downstream deep sequence inference engine. : ; In the formula, For integrated clock gating unit; Simultaneously set the minimum wake-up duration period. Define the wake-up extension counter Output the final gating enable signal .

[0033] When the device is first worn, the main deep sequence inference engine is forcibly kept on, the multi-scale coarse-grained entropy sentinel circuit works but does not participate in gating decisions, and continuously outputs... ,right Perform EWMA estimation : ; ; In the formula, EWMA smoothing factor, The number of shifts for the smoothing factor; use Expanded into pure shift addition form: ; Recursive estimation of synchronous tracking variance: ; When calibration is complete, output a calibration completion flag. and utilize and Calculate the wake-up threshold after initial calibration and the sleep threshold after initial calibration And write it to the programmable adaptive threshold register: when When the time comes, the statistical results are written to the threshold register: ; ; In the formula, This is the sensitivity coefficient. The initial wake-up threshold after calibration. This is the initial wake-up threshold after calibration. At the end of the current frame ; The shadow statistical unit is used to maintain the entropy mean of the current active frame. and peak : ; ; At the end of each frame inference cycle , In each frame inference cycle At the end, the shadow statistics unit latches the statistics of the current frame into the output register and clears it, including when... On the rising edge, proceed sequentially: ; ; ; ; In the formula, The left assignment operator, This represents the average frame-level complexity after saving. This represents the peak frame-level complexity after saving. This represents the average instantaneous complexity within the currently active frames. This represents the peak complexity within the currently active frame. Calculate the threshold margin metric for the current frame: ; The shadow statistics unit will be the current frame's , and Save to the programmable adaptive threshold register, then save the data in the shadow statistics unit. , and Reset to zero, prepare for the next frame.

[0034] The classification confidence score output after inference is based on the main deep sequence inference engine. and category tags , , , In the diagram, 0 represents normal and 1 represents pathological. This is the moment when the current frame inference cycle ends; Adaptive learning engine defines feedback signals : ; In the formula, To motivate, 0 represents punishment, and 0 represents neutrality. This is a near-loss event. For high confidence threshold; A simplified LMS algorithm is used to adjust the threshold by incrementing or decrementing it with a fixed step size. ; ; In the formula, The wake-up threshold at the end of the current frame inference cycle. The sleep threshold at the end of the current frame inference cycle. The learning rate; Will Constraints form: ; ; The absolute safety clamping lower boundary is set by the threshold preset by the host computer. and upper boundary By introducing hardware clamping logic, the updated wake-up threshold is obtained. and lower wake-up threshold And write it to the programmable adaptive threshold register: ; ; Set a fixed hysteresis bandwidth ,satisfy: ; It has A set of multi-library threshold registers is formed, and each set of multi-library threshold registers stores a pair of thresholds and corresponding benchmark statistics. The benchmark statistics include the reference benchmark mean and reference benchmark deviation corresponding to the current threshold. ; In the formula, For the first The complete parameter set of the group multi-library threshold register, For the first The wake-up threshold of the group multi-library threshold register, For the first The sleep threshold of the group multi-library threshold register. For the first The reference baseline mean corresponding to the group threshold. For the first The reference baseline deviation corresponding to the group threshold This is the index for the multi-library threshold register; Through the Perform EWMA filtering to extract The changing trend of low-frequency signal energy is used as an indicator of low-frequency signal energy. ,calculate In each group of multi-library threshold registers Based on the distance, select the multi-library threshold register with the smallest distance as the currently active library: ; In the formula, pass This is accomplished by a parallel subtractor and a priority comparison tree.

[0035] To avoid threshold jumps caused by frequent database switching, a hysteresis counter is introduced. Hysteresis counter Set the threshold for library switching hysteresis counting. When the new candidate pool wins consecutively After one cycle, the state automatic selection controller switches scenes and outputs the currently active threshold library index: ; Set the wake-up threshold of the current activation library. and sleep threshold Write and update the wake-up threshold in the programmable adaptive threshold register. and sleep threshold : ; .

[0036] Output Afterwards, The process is divided into two branches. The first branch uses symmetrical uniform quantization to quantize and compress the wake-up signal, setting the original sampled signal as... Bit width, set the target quantization bit width of the first branch path to be... : ; ; In the formula, This is the quantized, low-precision signal. This is the quantization scaling factor. Round to the nearest integer; Second branch judgment ,like Using shadow FIFO storage The depth of the shadow FIFO is : ; In the formula, The signal length for a single frame of inference. Main inference engine pipeline delay margin; like Shadow FIFO is not written to; Write control is controlled by Gating: ; ; In the formula, To wake up the signal, Write an enable function for the shadow FIFO. Write data to the shadow FIFO; Synchronous write to a shallow FIFO with a depth at the frame level, writing once per frame: ; In the formula, The end time of the current frame inference cycle , Input data for a shallow FIFO.

[0037] By utilizing the maximum comparison tree in the pipeline's embedded confidence extractor, the probability normalization vector output by the main deep sequence inference engine is extracted. Maximum confidence level, as the maximum probability value , , The total number of categories; Extract the second-largest confidence level as the second-largest probability value, and calculate... The difference between the second-highest probability value and the second-highest probability value is used as the certainty of the classification result. Set the security confidence threshold. Alertness confidence threshold and safety margin threshold , combined and Define three-level confidence status flags The three confidence levels include safe, alert, and dangerous: ; In the formula, For safety, As a warning, It is dangerous; Set the count threshold for continuous alert triggering interruption. When the confidence level is dangerous or continuous When the frame is alert, the confidence-driven backtracking interrupt controller generates a backtracking interrupt signal. : ; ; In the formula, The threshold for counting interrupts triggered by continuous YELLOW events. A counter for continuous YELLOW states; And issue a precision mode switching command to the main deep sequence inference engine. : ; when At that time, the data path multiplexer of the reconfigurable matrix computation unit is based on The mode of the multiply-accumulate unit is changed within a single clock cycle by... Switch to At the same time, the read pointer of the shadow FIFO rewinds to the beginning of the current frame and reads out sequentially. Corresponding raw data : ; ; Will Input data path multiplexer replacement The reconfigurable matrix calculation unit is re-entered, and the calculation result is input into the pipeline's embedded confidence extractor to re-evaluate the confidence level. : ; ; In the formula, Input data to the reconfigurable matrix computation unit, The confidence level status flag is recalculated. Set the number of consecutive safe frames required for accuracy recovery. If the reassessed confidence level does not meet the interruption condition, the pipeline-embedded confidence extractor inputs an interrupt clear signal to the confidence-driven backtracking interrupt controller. The signal, confidence-driven backtracking interrupt controller clears the interrupt flag, and the main deep sequence inference engine resumes operation. If the reassessed confidence level reaches the interruption condition, the main deep sequence inference engine will continue to be used. Process subsequent frames until continuous Since none of the frame confidence scores meet the interruption criteria, the main deep sequence inference engine resumes operation. : ; ; Define a soft drop buffer, which is a circular FIFO with a depth of [value missing]. : ; ; when At this time, the original data is still written to the soft discard buffer. When the soft discard buffer is full, the oldest data is overwritten, and only the original data is retained. One sampling point; when the confidence-driven backtracking interrupt controller generates a backtracking interrupt signal, and And the confidence level is lower than the special recall threshold. Triggering delayed recall interruption : ; Delayed recall interruption includes setting the maximum backtracking frame. The read pointer of the soft-discard buffer starts back from the most recent data. frame: ; The data read is The precision input is used for supplementary inference by the main deep sequence inference engine. The inference result of the current frame and the supplementary inference result are jointly evaluated using a logical OR operation to obtain the final classification result after joint evaluation. Complete the delayed recall interruption and output the recall reasoning completion flag. Clear backtracked data from the soft discard buffer. Frame data.

[0038] Five global states of the system are defined using a five-state finite state automaton, including deep sleep. Initial calibration Low-precision inference High-precision rollback and delayed recall ; For multi-scale coarse-grained entropy sentinel circuit detection, the main deep sequence inference engine is turned off; The learning period is for first-time users of the device. For multi-scale coarse-grained entropy sentinel circuit output The main deep sequence inference engine, shadow FIFO, shadow statistical unit, and adaptive learning engine are based on... Further processing is required; Generate a backtracking interrupt signal for the confidence-driven backtracking interrupt controller, and calculate... The main deep sequence reasoning engine is Data execution; To be Input data path multiplexer replacement The reconfigurable matrix calculation unit is re-entered, and the calculation result is input into the pipeline's embedded confidence extractor to re-evaluate the confidence level until the main deep sequence inference engine is restored. The processing procedure.

[0039] Define the input signal vector, including , , , , and ; Define state transition function : ; ; ; ; ; In the formula, For precision recovery counter; Define the set of interrupt sources and their corresponding priorities using a fixed-priority interrupt arbiter: ; ; ; ; In the formula, for Rising edge detection pulse, For library switching requests; Output the highest priority interrupt currently in effect. : ; Arbitration output encoding using a cascaded priority encoder: ; When a high-priority interrupt is in progress, low-priority interrupts are suspended in the fixed-priority interrupt arbiter and proceed sequentially: ; ; A multi-voltage domain hierarchical clock gating network is used to partition the power domain, dividing it into... , and , This includes a multi-scale coarse-grained entropy sentinel circuit, a soft drop buffer, a five-state finite state automaton, and a fixed-priority interrupt arbiter; This includes Tensor Cores, Shadow FIFOs, and quantizers; This includes a shadow statistics unit, an adaptive learning engine, a multi-library threshold register group, and an automatic state switching controller; Define the power domain enable function and the power domain enable mapping for each state, including defining the power domain enable function. : ; ; ; ; ; Each power domain includes an independent voltage regulator interface and a clock gating tree. Each power domain is gated through the clock gating tree. Clock gating is implemented by gating the root clock of each power domain through an ICG unit. ; Power domain Internally, the clock frequency is further differentiated for precision modes. In this mode, the Tensor Core runs in a downclocked mode: ; In the formula, To calculate the actual operating frequency of the unit, To calculate the down-division ratio of the calculation unit, Pre-precision mode; Define signal routing function ,include , , , , , , , , and frame completion signal The transmission is controlled by a five-state finite state automaton. ; Communicate with the host computer via the SPI or I²C host computer configuration bus. Configuration parameters include wake-up threshold sensitivity coefficient. Dormancy threshold sensitivity coefficient , , , , , , , , , , , , Calculation unit down-division ratio , , Shift bits of active intra-frame EWMA Shift bits of slow-varying EWMA , All configuration parameters are mapped to programmable registers.

[0040] The current status is reported to the host computer in real time via the diagnostic output bus, including... , , , , , , Cumulative count of backtracking events Cumulative count of recall events .

[0041] The following section uses a complete work scenario to verify the closed loop of the entire system, namely, "a patient experiences a prodromal epileptic event after wearing the device".

[0042] The device is powered on and enters the calibration period (step 2.1). After 30 seconds, an individual baseline entropy is established and written to the threshold register. Sleep mode. Power consumption. .

[0043] Ongoing: The signal remained stable for the next two hours, and the sentry continued to monitor the situation. The main engine remains off. SDB temporarily stores the filtered data at microwatt-level power consumption.

[0044] At the 121st minute, the patient experienced a weak brain electrical arrhythmia. breakthrough The sentry wakes up the main engine (4-bit mode). (4-bit), shadow FIFO synchronously writes 16-bit data (i.e., 4-bit), (16-bit).

[0045] Operation: The computational unit uses 4-bit inference, confidence level , The learning engine issues a reward ( (To identify pathological conditions), the threshold is finely adjusted and lowered.

[0046] At minute 122, the signal complexity increased sharply (epilepsy aura worsened), and 4-bit quantization caused the Softmax probability to flatten. It dropped to 0.62. It dropped to 0.08. CBIC triggered FSM transfer .

[0047] Rollback: The shadow FIFO reads the 16-bit raw data, and the calculation unit switches to 16-bit recalculation. The value was restored to 0.95, accurately identifying epileptic prodromal symptoms. The feedback is simultaneously sent to the learning engine to further reduce the threshold.

[0048] CBIC detected the rollback before extremely low and ,trigger FSM transfer SDB reviewed the previous three frames and, through further reasoning, discovered a faint precursor at the 120th minute (which was filtered out by the sentry at the time). .

[0049] The recall is complete, the signal gradually returns to stable, and after 5 consecutive green frames, it returns to 4-bit mode. ), then ,return Sleep. The multi-library selector stores the current threshold experience into the corresponding library.

[0050] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dynamic computing power allocation architecture for a deep sequence reasoning engine, characterized in that, include: Off-chip analog front-end, multi-scale coarse-grained entropy sentinel circuit, programmable adaptive threshold register, main deep sequence inference engine, adaptive learning engine, five-state finite state automaton, fixed priority interrupt arbiter, multi-voltage domain hierarchical clock gating network, host computer configuration bus, diagnostic output bus and host computer.

2. The dynamic computing power allocation architecture for a deep sequence reasoning engine as described in claim 1, characterized in that, The safety redundancy subsystem includes a calibration module, a shadow statistics unit, a multi-library threshold register group, an automatic state switching controller, an asymmetric precision dual-path distributor, a shadow FIFO, a pipeline embedded confidence extractor, and a confidence-driven backtracking interrupt controller. The multi-scale coarse-grained entropy sentinel circuit includes a successive approximation ADC, a ring buffer register, a multi-scale coarse-grained engine, a multi-phase shift register network, a symbol dynamics comparator array, a sliding window Popcount entropy approximation estimator, a nonlinear threshold trigger controller, and a clock gating unit. The multiphase shift register network includes a divider clock tap, a depth-accumulating shift register, and an arithmetic right shifter; The sign dynamics comparator array includes digital comparators, single-stage D flip-flops, and XOR gates; The sliding window Popcount entropy approximation estimator includes a bit counter and a shift adder; The nonlinear threshold trigger controller and clock gating unit include a hysteresis comparator and an integrated clock gating unit; The calibration module includes an EWMA filter, an adder, and a shifter; The shadow statistics unit includes a fixed-point accumulator and a maximum value comparator; The automatic state selection controller includes a subtractor, a priority comparison tree, and a hysteresis counter; The pipeline's embedded confidence extractor includes a maximum value comparison tree and a fixed-point comparator; The main deep sequence reasoning engine includes reconfigurable matrix computation units; The reconfigurable matrix computation unit includes a data path multiplexer and a multiply-accumulate unit.

3. The dynamic computing power allocation architecture for a deep sequence reasoning engine as described in claim 2, characterized in that, The bioelectrical signal is amplified and anti-aliasing filtered by an off-chip analog front-end. The result is then sampled using a successive approximation ADC at a fixed sampling frequency to obtain the original sampled signal sequence. , This is a discrete-time index for the global sampling time. Let the ADC quantization bit width be... , for: ； In the formula, For the first Digital bioelectric sampling values ​​at each moment, For ADC sampling frequency, This is a continuous voltage signal output from an external analog front-end. For successive approximation analog-to-digital converters; Based on the number of sampling points Construct a circular buffer for writing pointer addresses The original sampled signal sequence is written into the ring buffer register; The multi-scale coarsening engine reads data from the ring buffer register. ,definition Parallel coarse-grained channels, setting time scale factor , , , To achieve parallel coarse-grained channel indexing, an arithmetic right shifter combined with a time scaling factor is used to approximate coarse-grainedness of the original sampled signal sequence: ； In the formula, For scale The coarse-grained subsequence below, For indexing coarse-grained subsequences, For each coarse-grained channel, a discrete-time index of the sampling time. , This is an arithmetic right shift operation. This is the floor symbol.

4. The dynamic computing power allocation architecture for a deep sequence reasoning engine as described in claim 3, characterized in that, Will A digital comparator is used to map the data into a binary symbol bit stream. The XOR gate is used to calculate the change of adjacent symbols bit by bit to obtain the direction flipping flag sequence. Set the half length of the sliding window A sliding window is constructed, and a bit counter is used to count the flip rate within the sliding window. The flip rate is then normalized using a normalization formula, and this normalization is used as the current value. The entropy approximation, using Weighting coefficients Calculate multi-scale fusion index ; Define the double-threshold hysteresis comparison logic in the hysteresis comparator to obtain the wake-up or sleep state flag. : ； In the formula, The wake-up threshold, The sleep threshold, In the wake-up state, In hibernation mode; right Perform glitch-free processing to output a standard signal, and simultaneously set the minimum wake-up duration. Define the wake-up extension counter : ； In the formula, To find the maximum value; Output final gating enable signal : ； In the formula, For logical OR symbols.

5. The dynamic computing power allocation architecture for a deep sequence reasoning engine as described in claim 4, characterized in that, Upon initial startup, the main deep sequence inference engine remains forcibly enabled. The multi-scale coarse-grained entropy sentinel circuit operates but does not participate in gating decisions, and continuously outputs... The calibration module expands the EWMA recursive formula into a shift-addition form using an EWMA filter, shifter, and adder, and calculates the EWMA estimate of the baseline complexity mean. The mean absolute deviation (MAD) is used to calculate the baseline complexity of variance estimation. : ； ； In the formula, The number of shifts for the smoothing factor; When calibration is complete, output a calibration completion flag. and utilize and Calculate the wake-up threshold after initial calibration and the sleep threshold after initial calibration And write it to the programmable adaptive threshold register; The shadow statistical unit is used to maintain the entropy mean of the current active frame. and peak At the end of each frame inference cycle Calculate the threshold margin metric for the current frame: ； The shadow statistics unit will be the current frame's , and Save to the programmable adaptive threshold register, then save the data in the shadow statistics unit. , and Reset to zero, prepare for the next frame.

6. The dynamic computing power allocation architecture for a deep sequence reasoning engine as described in claim 5, characterized in that, The classification confidence score output after inference is based on the main deep sequence inference engine. and category tags , , , In the diagram, 0 represents normal and 1 represents pathological. This is the moment when the current frame inference cycle ends; Adaptive learning engine defines feedback signals : ； In the formula, To motivate, 0 represents punishment, and 0 represents neutrality. This is a near-loss event. For high confidence threshold; A simplified LMS algorithm is used to adjust the threshold by increasing or decreasing it with a fixed step size: ； ； In the formula, The wake-up threshold at the end of the current frame inference cycle. The sleep threshold at the end of the current frame inference cycle. The learning rate; The absolute safety clamping lower boundary is set by the threshold preset by the host computer. and upper boundary By introducing hardware clamping logic, the updated wake-up threshold is obtained. and lower wake-up threshold And write it to the programmable adaptive threshold register: ； ； Set a fixed hysteresis bandwidth ,satisfy: ； It has A set of multi-library threshold registers is formed, and each set of multi-library threshold registers stores a pair of thresholds and corresponding benchmark statistics. The benchmark statistics include the reference benchmark mean and reference benchmark deviation corresponding to the current threshold. ； In the formula, For the first The complete parameter set of the group multi-library threshold register, For the first The wake-up threshold of the group multi-library threshold register, For the first The sleep threshold of the group multi-library threshold register. For the first The reference baseline mean corresponding to the group threshold. For the first The reference baseline deviation corresponding to the group threshold This is the index for the multi-library threshold register; Through the Perform EWMA filtering to extract The changing trend of low-frequency signal energy is used as an indicator of low-frequency signal energy. ,calculate In each group of multi-library threshold registers The distance is used to select the multi-library threshold register with the smallest distance as the current active library, and the hysteresis counter is used. Set the threshold for library switching hysteresis counting. When the new candidate pool wins consecutively After one cycle, the state automatic switching controller switches scenes, outputs the index of the currently active threshold library, and sets the wake-up threshold of the currently active library. and sleep threshold Write and update the wake-up threshold in the programmable adaptive threshold register. and sleep threshold : ； 。 7. The dynamic computing power allocation architecture for a deep sequence reasoning engine as described in claim 6, characterized in that, If the output is The value is equal to 1, so The process is divided into two branches. The first branch uses symmetrical uniform quantization. Perform quantization compression, setting the original sampled signal to Bit width, set the target quantization bit width of the first branch path to be... : ； ； In the formula, This is the quantized, low-precision signal. This is the quantization scaling factor. Round to the nearest integer; The second branch utilizes shadow FIFO storage. The depth of the shadow FIFO is : ； In the formula, The signal length for a single frame of inference. Main inference engine pipeline delay margin; like Shadow FIFO is not written to; Synchronous write to a shallow FIFO with a depth at the frame level, writing once per frame: ； In the formula, The end time of the current frame inference cycle , Input data for a shallow FIFO.

8. The dynamic computing power allocation architecture for a deep sequence reasoning engine as described in claim 7, characterized in that, By utilizing the maximum comparison tree in the pipeline's embedded confidence extractor, the probability normalization vector output by the main deep sequence inference engine is extracted. Maximum confidence level, as the maximum probability value , , The total number of categories; Extract the second-largest confidence level as the second-largest probability value, and calculate... The difference between the second-highest probability value and the second-highest probability value is used as the certainty of the classification result. ; Set a safety confidence threshold Alert confidence threshold and safety margin threshold A three-level confidence state flag is defined using a fixed-point comparator. The three confidence levels include safe, alert, and dangerous: ； In the formula, For safety, As a warning, It is dangerous; Set the count threshold for continuous alert triggering interruption. When the confidence level is dangerous or continuous When the frame is alert, the confidence-driven backtracking interrupt controller generates a backtracking interrupt signal. It also sends a precision mode switching command to the main deep sequence inference engine. If a backtracking interrupt signal is generated, If no backtracking interrupt signal is generated, ; when At that time, the data path multiplexer of the reconfigurable matrix computation unit is based on The mode of the multiply-accumulate unit is changed within a single clock cycle by... Switch to At the same time, the read pointer of the shadow FIFO rewinds to the beginning of the current frame and reads out sequentially. Corresponding raw data ,Will Input data path multiplexer replacement The reconfigurable matrix calculation unit is re-entered, and the calculation result is input into the pipeline's embedded confidence extractor to re-evaluate the confidence level. The number of consecutive safe frames required for accuracy recovery is then set. If the reassessed confidence level does not meet the interruption condition, the pipeline-embedded confidence extractor inputs an interrupt clear signal to the confidence-driven backtracking interrupt controller. The confidence-driven backtracking interrupt controller clears the interrupt flag, and the main deep sequence inference engine resumes operation. If the reassessed confidence level reaches the interruption condition, the main deep sequence inference engine will continue to be used. Process subsequent frames until continuous Since none of the frame confidence scores meet the interruption criteria, the main deep sequence inference engine resumes operation. ; Define a soft drop buffer, which is a circular FIFO with a depth of [value missing]. ,when At this time, the original data is still written to the soft discard buffer. When the soft discard buffer is full, the oldest data is overwritten, and only the original data is retained. One sampling point; when the confidence-driven backtracking interrupt controller generates a backtracking interrupt signal, and And the confidence level is lower than the special recall threshold. Triggering delayed recall interruption Delayed recall interruption includes setting the maximum backtracking frame. The read pointer of the soft-discard buffer starts back from the most recent data. Frames, the data read is in The precision input is used for supplementary inference by the main deep sequence inference engine. The inference result of the current frame and the supplementary inference result are jointly evaluated using a logical OR operation to obtain the final classification result after joint evaluation. Complete the delayed recall interruption and output the recall reasoning completion flag. Clear backtracked data from the soft discard buffer. Frame data.

9. The dynamic computing power allocation architecture for a deep sequence reasoning engine as described in claim 8, characterized in that, Five global states of the system are defined using a five-state finite state automaton, including deep sleep. Initial calibration Low-precision inference High-precision rollback and delayed recall ; Define the input signal vector, including , , , , and ; Define state transition function : ； ； ； ； ； In the formula, For precision recovery counter; Define the set of interrupt sources and their corresponding priorities using a fixed-priority interrupt arbitrator, and output the highest-priority interrupt currently in effect. Use a cascaded priority encoder to output the arbitration output code. When a high-priority interrupt is in progress, low-priority interrupts are suspended in the fixed-priority interrupt arbiter and are processed sequentially. A multi-voltage domain hierarchical clock gating network is used to partition the power domain, dividing it into... , and , This includes a multi-scale coarse-grained entropy sentinel circuit, a soft drop buffer, a five-state finite state automaton, and a fixed-priority interrupt arbiter; Includes Tensor Core, Shadow FIFO, and asymmetric precision dual-path distributor; This includes a shadow statistics unit, an adaptive learning engine, a multi-library threshold register group, and an automatic state switching controller; Define power domain enable functions. Each power domain includes an independent voltage regulator interface and a clock gating tree. Each power domain is gated through the clock gating tree. Define signal routing function ,include , , , , , , , , and frame completion signal The transmission is controlled by a five-state finite state automaton. ; Communicate with the host computer via the SPI or I²C host computer configuration bus. Configuration parameters include wake-up threshold sensitivity coefficient. dormancy threshold sensitivity coefficient , , , , , , , , , , , , Calculation unit down-division ratio , , Shift bit length of active intra-frame EWMA Shift bits of slow-varying EWMA , All configuration parameters are mapped to programmable registers; The current status is reported to the host computer in real time via the diagnostic output bus, including... , , , , , , Cumulative count of backtracking events Cumulative count of recall events .

10. A method for dynamically accelerating a deep sequence inference engine, using a dynamic computing power allocation architecture for a deep sequence inference engine as described in claim 9, characterized in that, include: S1. The equipment is calibrated to establish a benchmark. , will benchmark Write to a programmable adaptive threshold register; a multi-scale coarse-grained entropy sentinel circuit continuously monitors bioelectrical signals; when... The main deep sequence reasoning engine remains off; S2, when Multi-scale coarse-grained entropy sentinel circuit output To the main deep sequence reasoning engine, the main deep sequence reasoning engine uses Standard operation, shadow FIFO synchronous writing ; S3. When a backtracking interrupt signal is generated, the shadow FIFO reads out. The main deep sequence reasoning engine is Recalculate the confidence level. Feedback is sent to the adaptive learning engine until the confidence-driven backtracking interrupt controller is triggered. Calculate the final classification result; S4, Main Deep Sequence Inference Engine Resumes Operation Later, when At this point, the multi-library threshold register group stores all the thresholds for the entire process, and returns to step S1.

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