Quantum circuits, quantum computers, and methods for implementing quantum fourier transforms

Abstract

This application discloses a quantum circuit, quantum computer, and method for implementing quantum Fourier transform (QFT), belonging to the field of quantum computing technology. The quantum circuit includes n QFT modules and n qubits, where n is a positive integer determined by the number of bits in the quantum state data to be processed. The number of qubits operated by the n QFT modules decreases according to the execution sequence. Each QFT module is configured to load the state of all its operated qubits into the phase of a designated qubit, while simultaneously converting the state information of the remaining qubits into the state of adjacent qubits, wherein the designated qubit is the most significant qubit or the least significant qubit. The first n-1 QFT modules in the execution sequence include two-qubit gates operating on adjacent qubits, and the two-qubit gates form a chain structure according to the order of the operated qubits. Applying this application reduces the depth of the QFT quantum circuit.

Description

Technical Field

[0001] This application belongs to the field of quantum computing technology, and in particular to a quantum circuit, quantum computer and method for realizing quantum Fourier transform. Background Technology

[0002] The Quantum Fourier Transform (QFT), a core operation of quantum computing, is a crucial extension of the classical Discrete Fourier Transform (DFT) within the framework of quantum mechanics. Its core function is to map quantum states from computational bases to Fourier bases, providing underlying technical support for cutting-edge quantum algorithms such as quantum phase estimation, Shor's large number factorization, and quantum machine learning. It is a vital foundation for realizing the advantages of quantum computing.

[0003] Current mainstream QFT quantum circuit implementation schemes include Figure 1 As shown, quantum circuits are designed from a logical implementation perspective, without fully considering the topological constraints of quantum chips. However, the connections between qubits in a quantum chip are not entirely free; they are constrained by the physical layout of the hardware. Because qubits are almost never fully connected, a large number of basic logic gates, such as SWAP gates and CNOT gates, are needed for bit routing during the circuit compilation stage to achieve logical connections between non-adjacent qubits. The superposition of too many quantum gates directly leads to a significant increase in the depth of the compiled quantum circuit. Existing NISQ (Noisy Medium-Scale Quantum) computers, limited by their small number of qubits, short coherence time, and weak fault tolerance, cannot support excessively deep quantum circuits. Ultimately, this makes it difficult for such QFT circuits to run effectively on practical NISQ devices, severely restricting the practical application of quantum algorithms that rely on QFT. Summary of the Invention

[0004] The purpose of this application is to provide a quantum circuit, a quantum computer, and a method for implementing quantum Fourier transform, with the aim of reducing the depth of QFT quantum circuits.

[0005] One embodiment of this application provides a quantum circuit for implementing quantum Fourier transform, the quantum circuit including n QFT modules and n qubits, where n is a positive integer and is determined by the number of bits of the quantum state data to be processed; the number of qubits operated by the n QFT modules decreases according to the execution timing.

[0006] Each QFT module is configured to load the states of all the qubits it operates into the phase of the designated qubit it operates into, while converting the state information of the remaining qubits into the states of the adjacent qubits, wherein the designated qubit is the most significant qubit or the least significant qubit.

[0007] The first n-1 execution timing QFT modules include two-qubit gates acting on adjacent qubits, and the two-qubit gates form a chain structure according to the order of the qubits acting on them.

[0008] Optionally, the two-qubit gate includes a controlled phase gate and a swap gate;

[0009] Adjacent qubits in the same group are sequentially subjected to controlled phase gates and swap gates.

[0010] Optionally, the controlled phase gate is used to load the state of the target bit into the phase of the target bit;

[0011] The swapping gate swaps the state of the controlled phase gate bit acting on the same qubit with the state of the target bit.

[0012] Optionally, the control bit of the first controlled phase gate in all QFT modules is the same qubit.

[0013] Optionally, the rotation angle of the controlled phase gate is π / 2. m , where m is the order of the controlled phase gate among all controlled phase gates in the QFT module.

[0014] Optionally, the QFT module includes a single-qubit gate that loads the state of a specific bit into the phase of that specific bit, wherein the specific bit is the control bit of the first controlled phase gate in the QFT module.

[0015] Optionally, the single-qubit gate is located in the first execution sequence of the QFT module.

[0016] Optionally, the single-qubit gate is an H-gate.

[0017] Another embodiment of this application provides a quantum computer, which includes a quantum chip and a quantum measurement and control integrated machine. The quantum chip and the quantum measurement and control integrated machine are combined to implement the quantum circuit in any of the above embodiments.

[0018] Another embodiment of this application provides a quantum Fourier transform method, which is executed by running the quantum circuit in any of the above embodiments.

[0019] Compared to existing technologies, in this application, the two-qubit gates of the first n-1 QFT modules only operate on adjacent qubits and form a chain structure (adjacent gates share qubits). The chain structure avoids the additional depth overhead caused by spanning multiple bits, thus reducing the overall circuit depth growth rate. Attached Figure Description

[0020] Figure 1An example system block diagram of a quantum circuit for implementing quantum Fourier transform is provided in an embodiment of this application;

[0021] Figure 2 A schematic diagram of a quantum circuit for implementing quantum Fourier transform, provided as an embodiment of this application;

[0022] Figure 3 A circuit diagram of a quantum circuit for implementing quantum Fourier transform is provided for embodiments of this application;

[0023] Figure 4 A circuit diagram of a quantum circuit provided in an embodiment of this application. Detailed Implementation

[0024] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0026] Classical computers use transistors to encode information in binary data, such as bits, where each bit can represent a value of 1 or 0. These 1s and 0s act as switches to drive the functions of a classical computer. If there are n bits of data, there are 2^n possible classical states, and one state is represented at a time.

[0027] Quantum computers use quantum processors that operate on data represented by qubits, also known as quantum bits. A qubit can represent the classical binary states "0" or "1", or a superposition of "0" and "1". Because it can represent a superposition of "0" and "1", a qubit can represent both "0" and "1" states simultaneously. For example, if there are n bits of data, n quantum states can be represented simultaneously. Furthermore, qubits in a superposition can be correlated with each other, a phenomenon known as entanglement. The state of one qubit (whether it's 1, 0, or both) can depend on the state of another qubit, and more information can be encoded within two entangled qubits. Based on the principles of superposition and entanglement, qubits enable quantum computers to perform functions that might be relatively complex and time-consuming for classical computers.

[0028] Please refer to Figure 1This illustration shows an example system block diagram of a quantum circuit for implementing a quantum Fourier transform, provided in one embodiment of this application. The system can be a hybrid computing system comprising a combination of one or more quantum computers, quantum systems, and / or classical computers. Figure 1 In the example shown, the system may include quantum hardware 11 and classical hardware 12. In one implementation, quantum hardware 11 and classical hardware 12 may be configured to communicate via one or more wired and / or wireless connections (e.g., wireless networks). Quantum hardware 11 may include a quantum chipset consisting of one or more quantum chips, comprising various hardware components for processing data encoded in qubits. The quantum chipset may be a quantum computing core surrounded by infrastructure to protect the quantum chips from electromagnetic noise sources, mechanical vibration sources, heat sources, and other noise sources that can degrade the performance of the quantum chips. Classical hardware 12 may be electronically integrated with quantum hardware 11 via any suitable wired and / or wireless electronic connection.

[0029] exist Figure 1 In the example shown, quantum hardware 11 can be any suitable set of components capable of performing quantum operations on a physical system. Quantum operations, for example, can be quantum logic gate operations that manipulate the quantum states of qubits to evolve and / or become entangled. Figure 1 In the illustrated example embodiment, quantum hardware 11 may include a measurement and control unit 111, an interface 112, and a quantum chip 113. In some embodiments, all or part of each of the measurement and control unit 111, interface 112, and quantum chip 113 may be located in a cryogenic environment to facilitate the performance of quantum operations. Quantum chip 113 may be any hardware capable of processing information using quantum states. This hardware may include multiple qubits and means for coupling or entanglement of the qubits to process information using quantum states. Qubits may include, but are not limited to, charge qubits, flux qubits, phase qubits, spin qubits, and ion qubits. The quantum chip may include a set of quantum logic gates configured to perform quantum logic operations on the qubits stored in a quantum register. Quantum gates may include one or more single-qubit gates, two-qubit gates, and / or other multi-qubit gates.

[0030] The measurement and control unit 111 can be any combination of digital computing devices capable of performing quantum computing (e.g., executing quantum circuits) in conjunction with interface 112. This digital computing device may include a digital processor and memory for storing and executing quantum instructions using interface 112. The digital computing device may also include a communication protocol device for receiving instructions and sending the results of the performed quantum computing to a classical computer. Additionally, the digital computing device may include a communication interface with interface 112. In one embodiment, the measurement and control unit 111 may be configured to receive classical instructions (e.g., from classical hardware 12) and convert these classical instructions into measurement and control instructions for interface 112. The measurement and control instructions provided by the measurement and control unit 111 to interface 112 may be, for example, digital signals indicating which quantum gates in a quantum gate array need to be applied to the qubits to perform a specific function. Interface 112 may be configured to convert these digital signals into analog signals (e.g., analog pulses of microwave pulses), which can be used to apply quantum gates to the qubits to manipulate the interactions between the qubits.

[0031] Interface 112 may be a classical-quantum interface, comprising a combination of devices capable of receiving instructions from the integrated measurement and control unit 111 and converting those instructions into a means for implementing quantum operations. In one embodiment, interface 112 may convert instructions from the integrated measurement and control unit 111 into drive signals capable of driving or manipulating qubits, and / or applying quantum gates to qubits. Additionally, interface 112 may be configured to convert signals received from the quantum chip 113 into digital signals capable of being processed and transmitted by the integrated measurement and control unit 111. Devices included in interface 112 may include, but are not limited to, digital-to-analog converters, analog-to-digital converters, waveform generators, attenuators, amplifiers, optical fibers, lasers, and filters. Interface 112 may further include circuitry configured to measure multiple qubits after a quantum gate is applied, wherein the measurement may produce results represented in classical bits. Each measurement performed by interface 112 may be read out to a device connected to quantum hardware 11, such as classical hardware 12. The multiple measurement results provided by interface 112 may represent probabilistic results.

[0032] Classical hardware 12 can include hardware components such as processors and storage devices (e.g., including memory devices and classical registers) for processing data encoded in classical bits. In one embodiment, classical hardware 12 can be configured to provide quantum hardware 11 with various control signals, instructions, and data encoded in classical bits. Further, quantum states measured by quantum hardware 11 can be read out by classical hardware 12, and classical hardware 12 can store the measured quantum states as classical bits in classical registers. In one embodiment, classical hardware 12 can be any suitable combination of computer-executable hardware and / or computer-executable software capable of executing computation module 122 to perform quantum computation using data stored in storage module 121 as part of the construction and computation. Storage module 121 can be a repository of data to be analyzed using quantum computing algorithms and the results of that analysis. Computation module 122 can be a program or module capable of preparing classical data from storage module 121 as part of a quantum circuit implementation. Computation module 122 can be instantiated as part of a larger algorithm, such as a function call to an application programming interface (API), or by resolving hybrid classical-quantum computing into aspects of quantum and classical computing. For example, computing module 122 can generate instructions for creating quantum circuits using quantum gates. In an embodiment, such instructions can be stored by the measurement and control unit 111 and executed by instantiating components of interface 112, so that quantum operations of quantum gates can be performed on quantum chip 113.

[0033] Classic hardware 12 can be a laptop computer, desktop computer, vehicle-integrated computer, smart mobile device, tablet device, and / or any other suitable classic computing device. Additionally or alternatively, classic hardware 12 can also operate as part of a cloud computing service model, such as Software as a Service (SaaS), Platform as a Service (PaaS), or Infrastructure as a Service (IaaS). Classic hardware 12 can also reside in a cloud computing deployment model, such as a private cloud, community cloud, public cloud, or hybrid cloud.

[0034] See Figure 2 Taking 5 qubits as an example, Figure 2 The quantum circuit for implementing quantum Fourier transform provided in this application includes n QFT modules and n qubits, where n is a positive integer and is determined by the number of bits of the quantum state data to be processed; the number of qubits operated by the n QFT modules decreases according to the execution timing.

[0035] Each QFT module is configured to load the states of all the qubits it operates into the phase of the designated qubit it operates into, while converting the states of the remaining qubits into the states of the adjacent qubits, wherein the designated qubit is the most significant qubit or the least significant qubit.

[0036] The first n-1 execution timing QFT modules include two-qubit gates acting on adjacent qubits, and the two-qubit gates form a chain structure according to the order of the qubits acting on them.

[0037] Generally, n ≥ 2, where the specific value of n is determined by the data to be QFT'd. The data is converted into binary, with n bits. These binary data are then used as the initial states of the qubits, i.e., the quantum state data. Therefore, n qubits carrying n bits of quantum state data can be denoted as a qubit set Q = {q1, q2, ..., qn}, where q1 is the least significant qubit and qn is the most significant qubit. The first QFT module operates on all n qubits (q1 to qn); the second QFT module operates on n-1 qubits, typically q1 to qn-1; the k-th QFT module operates on n-k+1 qubits; and the n-th QFT module operates on only one qubit. The last QFT module, which executes the timing sequence, does not contain two-qubit gates because it operates on only one qubit.

[0038] A designated bit is responsible for encoding and storing the state of all qubits involved in the module in phase form; the remaining qubits then pass their own state to their neighboring qubits. The first n-1 QFT modules, since they involve ≥2 qubits, require two-qubit gates to achieve state coupling, which are cascaded in qubit order to ensure no information loss during state transfer between adjacent qubits, while maintaining the coherence of the quantum states.

[0039] This application achieves phase loading and adjacency propagation of quantum state information through the sequential and decremental interaction of n QFT modules and n qubits, while ensuring the coherence propagation of quantum states through a chained two-qubit gate. The two-qubit gate operates only on adjacent qubits, reducing coherence loss caused by cross-qubit operations and improving the accuracy of the calculation results. The two-qubit gates of the first n-1 QFT modules operate only on adjacent qubits and form a chained structure (adjacent gates share qubits). The chained structure avoids the additional depth overhead caused by crossing multiple qubits, reducing the overall circuit depth growth rate.

[0040] In this application, the two-qubit gate includes a controlled phase gate and a swapping gate; adjacent qubits in the same group are sequentially processed by the controlled phase gate and the swapping gate. For processing k bits, adjacent bits are processed sequentially from the least significant bit q0 to the most significant bit qk-1. The controlled phase gate and the swapping gate are applied sequentially to each pair of adjacent bits. After processing, the most significant bit qk-1 accumulates the states of all k bits (as phase), while the states of the remaining bits (qk-2 to q0) become the states of the adjacent higher-order bits; or after processing, the least significant bit q0 accumulates the states of all k bits (as phase), while the states of the remaining bits (q1 to qk-1) become the states of the adjacent lower-order bits.

[0041] Specifically, the controlled phase gate is used to load the initial state of the target bit into the phase of the target bit; the swap gate swaps the state of the controlled phase gate control bit acting on the same qubit with the state of the target bit.

[0042] Quantum state information flows unidirectionally from the least significant bit (or most significant bit) to the specified bit direction through a combination of phase loading via a CP gate (controlled phase gate) and state transfer via a SWAP gate (swap gate), avoiding interference caused by information backflow and ensuring the independence of each encoding step. The state of the target bit is copied into its own phase via a CP gate (non-destructive preservation); the state of the target bit is transferred to the control bit via a SWAP gate (preparing for the next level of QFT). The operation of each QFT module is based on the output state of the previous level, forming a mathematical recursive relationship.

[0043] In some embodiments of this application, the rotation angle of the controlled phase gate is π / 2. m , where m is the order of the controlled phase gate among all controlled phase gates in the QFT module.

[0044] If a QFT module operates on k qubits, then the QFT module has a total of k-1 controlled phase gates. The rotation angle of the m-th controlled phase gate in the QFT module is π / 2. m The rotation angle of the controlled phase gate decreases with the sorting exponent, ensuring that the resolution of the phase encoding is improved step by step. Through phase modulation at different resolutions, the complete quantum state encoding is finally achieved through the superposition of phases of different orders of magnitude.

[0045] The angles of the controlled phase gates with different orders differ exponentially, ensuring that the phase information of each qubit is orthogonal in the frequency domain, thus avoiding information aliasing during decoding (similar to the orthogonality of different frequency components in a Fourier transform).

[0046] In some embodiments of this application, the control bit of the first controlled phase gate in all QFT modules is the same qubit.

[0047] Once the control bit of the first controlled phase gate in each QFT module is determined, the control bits of the other controlled phase gates in that QFT module are also determined according to the execution timing. The control bits are automatically determined through a recursive relationship, ensuring that all controlled phase gates within the same module form a continuous chain structure (without breaks or crossovers). For any n or any range of QFT modules, only the first control bit and its designated bit need to be determined to automatically generate the control-target relationship for all controlled phase gates, greatly simplifying the design process for multi-module modules.

[0048] Quantum bits on quantum chips are typically arranged in a linear or two-dimensional grid, with the coupling strength between adjacent qubits being much higher than that between non-adjacent qubits. The recursive rule for controlling the bits (passing only between adjacent qubits) ensures that all controlled phase gates operate on adjacent pairs with high coupling strength, improving the fidelity of gate operations (and making it easier to implement at the hardware level).

[0049] All QFT modules use the same qubit as their first CP gate as the control core, ensuring consistency in the source of information transmission. Regardless of how the effective range of the QFT module decreases, information always converges from the edge qubits to the designated qubit through the fixed control core, avoiding link chaos caused by dynamic changes in the control bit. By fixing the control bit of the first CP gate, when phase modulation is applied to the target qubit of different QFT modules, their phase factors can be superimposed according to a uniform rule (because the control source is fixed), ensuring that the final phase is a linear combination of all quantum state information. On a quantum chip, fixing the control bit of the first CP gate reduces dynamic switching of cross-qubit connections, lowering wiring complexity and crosstalk noise.

[0050] When the control bit of the first controlled phase gate is the least significant qubit, the designated qubits for the first n-1 QFT modules are, in order, the most significant qubit, the second most significant qubit, ..., the second most significant qubit.

[0051] In this application, the QFT module includes a single-qubit gate that loads the state of a specific bit into the phase of that specific bit, wherein the specific bit is the control bit of the first controlled phase gate in the QFT module.

[0052] Single-qubit gates supplement the self-encoding stage of specific qubits, solving the problem that the controlled phase gate alone could not encode its own state (the controlled phase gate mainly encodes information from other bits), enabling the state of all qubits (including the control core) to be completely recorded in the phase. Furthermore, because the control bit of the first controlled phase gate in each QFT module is the same, all single-qubit gates operate on the same qubit.

[0053] In this application, the single-qubit gate is located in the first execution sequence of the QFT module.

[0054] The single-qubit gate is executed first, solidifying its own state as a phase. The external information phases superimposed by subsequent controlled-phase gates are then added to the self-encoded phase, forming a hierarchical structure and preventing aliasing. The control bits of the controlled-phase gates must be in a defined state to accurately determine whether to apply phase modulation to the target bit. The priority execution of the single-qubit gate allows a specific bit to be processed from an arbitrary state into a superposition state, providing a stable control ground state for subsequent controlled-phase gates and avoiding encoding errors caused by ambiguity in the control bit state.

[0055] In some embodiments of this application, the single-qubit gate is an H-gate. The H-gate provides an optimal initial basis for subsequent controlled phase gates by mapping the state of a specific bit to a uniform superposition state, while ensuring that the state of the specific bit itself can be efficiently encoded.

[0056] For example, a quantum circuit for implementing a quantum Fourier transform can be as follows: Figure 3 As shown, the controlled P gate in the figure is a CP gate. The quantum circuit is constructed iteratively, optimizing the operation order of the quantum gates, reducing the number of quantum gates and the depth of the quantum circuit. Therefore, the requirements for the topology of the quantum chip are lower during quantum circuit compilation, resulting in a quantum circuit with fewer logic gates and shallower depth. In the current NISQ era, this reduces the impact of noise. Since QFT has wide applications in many fields such as HHL algorithms, quantum machine learning, and quantum chemistry, the quantum circuit of this application can be effectively applied to other fields, contributing to the further development and application of quantum computing technology.

[0057] The following explains why the quantum circuit of this application can achieve QFT functionality:

[0058] The matrix A of the n-dimensional Fourier transform n It can be written as:

[0059]

[0060] in,

[0061] For example, when n=2, Its Fourier transform matrix A2 is:

[0062]

[0063] This is the Hadamard matrix (or Hadamard gate).

[0064] The quantum Fourier transform of a single qubit can be expressed as:

[0065]

[0066] For the quantum Fourier transform of two qubits, we have:

[0067]

[0068] Similarly, for the quantum Fourier transform of n qubits, we have:

[0069]

[0070] The above equation shows that a quantum circuit that can achieve quantum Fourier transform can be realized through recursion.

[0071] Quantum state (|0>+e) iφ |1>) can be derived from Figure 4 The quantum circuit fabrication, where the matrix of the P(φ) gate is as follows:

[0072]

[0073] use Figure 4 The quantum circuit shown can be constructed as follows: Figure 3 The quantum circuit shown.

[0074] The following is a discussion of... Figure 3 The quantum state changes in the quantum state illustrate the process of QFT:

[0075] Assumption Figure 3 The input quantum state is |x1x2x3x4x5>, which respectively correspond to Figure 3 From top to bottom, the five qubits in the middle, after the first QFT module is completed, the quantum state of the last qubit becomes:

[0076]

[0077] The quantum states of the other qubits, from top to bottom, are |x2>, |x3>, |x4>, and |x5>.

[0078] After the second QFT module is applied, the quantum state of the last qubit remains unchanged, and the quantum state of the penultimate qubit is:

[0079]

[0080] The quantum states of the other three qubits, from top to bottom, are |x3>, |x4>, and |x5>.

[0081] After the third QFT module is applied, the quantum states of the last and penultimate qubits remain unchanged, while the quantum state of the middle qubit becomes:

[0082]

[0083] The quantum states of the two qubits above, from top to bottom, are |x4> and |x5>.

[0084] After the fourth QFT module is applied, the states of the bottom three qubits remain unchanged, while the quantum state of the second qubit changes to:

[0085]

[0086] The quantum state of the topmost qubit becomes |x5>.

[0087] After the fifth QFT module is applied, the states of the following four qubits remain unchanged, while the quantum state of the first qubit becomes:

[0088]

[0089] In some embodiments, this application also provides a quantum computer, which includes a quantum chip and a quantum measurement and control integrated machine, wherein the quantum chip and the quantum measurement and control integrated machine are combined to implement the quantum circuit in any of the above embodiments.

[0090] In some embodiments, this application also provides a quantum Fourier transform method, which is executed by running a quantum circuit of any of the above embodiments.

[0091] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0092] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0093] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0094] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software sub-circuits in the decoding processor. The software sub-circuits can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0095] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0096] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0097] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0098] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0099] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0100] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0101] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A quantum circuit for implementing quantum Fourier transform, characterized in that, The quantum circuit includes n QFT modules and n qubits, where n is a positive integer and is determined by the number of bits of the quantum state data to be processed; the number of qubits operated by the n QFT modules decreases according to the execution timing. Each QFT module is configured to load the states of all the qubits it operates into the phase of the designated qubit it operates into, while converting the state information of the remaining qubits into the states of the adjacent qubits, wherein the designated qubit is the most significant qubit or the least significant qubit. The first n-1 execution timing QFT modules include two-qubit gates acting on adjacent qubits, and the two-qubit gates form a chain structure according to the order of the qubits acting on them.

2. The quantum circuit as described in claim 1, characterized in that, Two-qubit gates include controlled phase gates and swap gates; Adjacent qubits in the same group are sequentially subjected to controlled phase gates and swap gates.

3. The quantum circuit as described in claim 2, characterized in that, The controlled phase gate is used to load the state of the target bit into the phase of the target bit; The swapping gate swaps the state of the controlled phase gate bit acting on the same qubit with the state of the target bit.

4. The quantum circuit as described in claim 2, characterized in that, The control bit of the first controlled phase gate in all QFT modules is the same qubit.

5. The quantum circuit as described in claim 2, characterized in that, The rotation angle of the controlled phase gate is π / 2 m , where m is the order of the controlled phase gate among all controlled phase gates in the QFT module.

6. The quantum circuit as described in claim 2, characterized in that, A QFT module includes a single-qubit gate that loads the state of a specific bit into the phase of that specific bit, wherein the specific bit is the control bit of the first controlled phase gate in the QFT module.

7. The quantum circuit as described in claim 6, characterized in that, The single-qubit gate is located in the first execution sequence of the QFT module.

8. The quantum circuit as described in claim 6, characterized in that, The single-qubit gate is an H-gate.

9. A quantum computer, characterized in that, The quantum computer includes a quantum chip and a quantum measurement and control integrated machine, wherein the quantum chip and the quantum measurement and control integrated machine are combined to implement the quantum circuit described in any one of claims 1-8.

10. A quantum Fourier transform method, characterized in that, The method is performed by running the quantum circuit described in any one of claims 1-8.

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